®
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
FEATURES
• Complete Integrated Remote Terminal
Including:
•Dual Low-Power 3.3V or 5.0V
Transceivers
•Complete RT Protocol Logic
• Supports MIL-STD-1553A/B Notice 2,
STANAG-3838 RT, and
MIL-STD-1760 Stores Management
• World’s Smallest CQFP SSRT
• 80-Pin Ceramic Flat Pack or Gull Wing
Package
• 3.3V Logic Power
• Meets 1553A/McAir Response Time
Requirements
• Internal FIFO for Burst Mode Capability on
Receive Data
• 16-bit DMA Interface
• Auto Configuration Capability
• Comprehensive Built-In Self-Test
• Direct Interface to Simple (Processorless)
Systems
• Available with Full Military Temperature
Range and Screening
• Selectable Input Clock:
10, 12, 16, or 20 MHz
DESCRIPTION
The BU-64703 Simple System RT Mark3 (SSRT Mark3) MIL-
STD-1553 terminal provides a complete interface between a simple
system and a MIL-STD-1553 bus. The SSRT Mark3 can be powered
entirely by 3.3 volts, thus eliminating the need for a 5V power supply.
This terminal integrates dual transceiver, protocol logic, and a FIFO
memory for received messages in an extremely small, 0.88 inch
square 0.130” max height ceramic package. The gull wing package
with a “toe-to-toe” maximum dimension of 1.110 inches enables its
use in applications where PC board space is at a premium. The
SSRT Mark3 provides multi-protocol support of MIL-STD-1553A/B,
MIL-STD-1760, McAir, and STANAG-3838.
The SSRT Mark3's transceivers are completely monolithic, require
only a +3.3V supply (+5.0V available), and consume low power. The
internal architecture is identical to that of the original BU-61703/61705
Simple System RT (SSRT). There are versions of the Simple System
RT Mark3 available with transceivers trimmed for MIL-STD-1760
compliance, or compatible to McAir standards. The SSRT Mark3 can
operate with a choice of clock frequencies at 10, 12, 16, or 20 MHz.
The SSRT Mark3 incorporates a Built-In-Test (BIT). This BIT, which is
processed following power turn-on or after receipt of an Initiate Self-
Test Mode command, provides a comprehensive test of the SSRT
Mark3's encoders, decoders, protocol, transmitter watchdog timer,
and protocol section. The SSRT Mark3 also includes an auto-config-
uration feature.
The SSRT Mark3 is ideal for stores and other simple systems that do
not require a microprocessor. To streamline the interface to simple
systems, the SSRT Mark3 includes an internal 32-word FIFO for
received data words. This serves to ensure that only complete, con-
sistent blocks of validated data words are transferred to a system.
© 2003 Data Device Corporation
BU-64703
SIMPLE SYSTEM RT MARK3
(SSRT MARK3)
Make sure the next
Card you purchase
has...
2
Data Device Corporation
www.ddc-web.com
BU-64703
H-06/11-0
FIGURE 1. SSRT Mark3 BLOCK DIAGRAM
COMMAND
ADDRESS
BUS
RT
MESSAGE
STATUS
RT
WORD
INPUTS
DATA
TRANSFER
CONTROL
DMA
HANDSHAKE
CONTROL
DMA
HANDSHAKE
AND
TRANSFER
CONTROL
LOGIC
SYSTEM
DATA
DATA
BUFFERS
DTREQ
D15-D0
DTGRT
DTACK
HS FAIL
MEMOE
MEMWR
L_BRO, T/R, SA4-SA0
WC/MC/CWC4-0
ILLEGAL
SRV_RQST
SSFLAG
BUSY
RTACTIVE
INCMD
RTAD4-RTAD0
RT_AD_LAT
RT_AD_ERR
GBR
CLK_IN
CLK_SEL1
CLK_SEL0
MSG_ERR
RTFAIL
DUAL
ENCODER
DECODER
AND
RT STATE
LOGIC
BRO_ENA
AUTO_CFG
MSTCLR
CONTROL
INPUTS
RT
ADDRESS
CLOCK
FREQUENCY
SELECTION
TX/RX A
TX/RX A
TX/RX B
TX/RX B
TRANSCEIVER
A
TRANSCEIVER
B
TX_INH
RTADP
+Vcc
3
Data Device Corporation
www.ddc-web.com
BU-64703
H-06/11-0
V
V
V
V
V
V
µA
µA
µA
µA
µA
V
V
mA
mA
pF
pF
0.7
0.2•Vcc
10
-33
-33
10
10
0.4
-2.2
50
50
2.1
0.8•Vcc
0.4
1.0
-10
-350
-350
-10
-10
2.4
2.2
LOGIC
VIH
All signals except CLOCK_IN
CLOCK_IN
VIL
All signals except CLOCK_IN
CLOCK_IN
Schmidt Hysteresis
All signals except CLOCK_IN
CLOCK_IN
IIH, IIL
All signals except CLOCK_IN
IIH (Vcc=3.6V, VIN=Vcc)
IIH (Vcc=3.6V, VIH=2.7V)
IIL (Vcc=3.6V, VIH=0.4V)
CLOCK_IN
IIH
IIL
VOH (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOL (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOL=max)
IOL (Vcc = 3.0V)
IOH (Vcc = 3.0V)
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
Vp-p
Vp-p
Vp-p
mVp-p
mVpeak
nsec
nsec
9
27
27
10
250
300
300
7
20
21.5
150
250
6
18
20
-250
100
200
TRANSMITTER
Differential Output Voltage (Note 8)
• Direct Coupled Across 35 Ω,
Measured on Bus
• Transformer Coupled Across
70 Ω, Measured on Bus
BU-64703XX-XX0
BU-64703X8/3-XX2 (Note 9)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
BU-64703X8/3
BU-64703X9/4
kΩ
pF
Vp-p
Vpeak
5
0.860
10
2.5
0.200
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
V
V
V
V
V
6.0
6.0
4.5
7.0
6.0
-0.3
-0.3
-0.3
-0.3
-0.3
ABSOLUTE MAXIMUM RATING
Supply Voltage
• Logic +3.3V
• Transceivers +3.3V (Note 10)
(not during transmit)
• Transceiver +3.3V
(during transmit) (Note 10)
• Transceiver +5.0V
• +3.3V Logic Input Range
UNITSMAXTYPMINPARAMETER
TABLE 1. SSRT Mark3 SPECIFICATIONS
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
UNITSMAXTYP
MIN
PARAMETER
0.31
0.69
1.04
1.74
0.31
0.71
1.08
1.83
0.63
0.85
1.07
1.51
0.63
0.86
1.09
1.56
0.09
0.47
0.82
1.52
0.09
0.49
0.85
1.61
3.60
3.46
5.25
95
300
500
900
95
315
535
975
100
205
310
520
40
100
216
332
565
40
3.3
3.3
5.0
3.00
3.14
4.75
POWER DISSIPATION
Total Hybrid (Notes 8, 11 and 14)
• BU-64703X8/9-XX0, (1553 & McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-64703X8-XX2, (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-64703X3/4-X00, (1553 & McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-64703X3-X02, (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
• BU-64703X8/9-XX0 (1553 &McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-64703X8-XX2 (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
• +3.3V Logic
• +3.3V Transceivers (Note 10)
• +5.0V Transceivers
Current Drain(Total Hybrid)(Notes 8,14)
• BU-64703X8/9-XX0,(1553 & McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-64703X8-XX2, (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Current Drain(Total Hybrid)(Notes 8,14)
• BU-64703X3/4-X00,(1553 & McAir)
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
• BU-64703X3-X02,(1760)
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont’d)
4
Data Device Corporation
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BU-64703
H-06/11-0
oz
(g)
in.
(mm)
in.
(mm)
°C/W
°C
°C
°C
°C
°C
°C
11
+125
+85
+70
150
150
+300
9
-55
-40
0
-55
-65
Weight
80-pin Ceramic Flatpack/Gull Wing
Package
PHYSICAL CHARACTERISTICS
Size
80-pin Ceramic Flatpack / Gull Lead
Lead Toe-to-Toe Distance
80-pin Gull Wing
THERMAL
Thermal Resistance (Notes 8, 13)
Ceramic Flatpack / Gull Lead
Junction-to-Case, Hottest Die (θJC)
Operating Case Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
µs
µs
µs
19.5
7
18.5
660.5
17.5
4
1553 MESSAGE TIMING
RT-to-RT Response Timeout
(Note 12)
RT Response Time
(mid-parity to mid-sync) (Note 12)
Transmitter Watchdog Timeout
UNITSMAXTYPMINPARAMETER
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont’d)
0.353
(10)
0.88 X 0.88 X 0.13
(22.3 x 22.3 x 3.3)
1.110
(28.194)
NOTES:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Differential Capacitance Specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Impedance parameters are specified directly between pins
TX/RX A(B) and TX/RX A(B) of the SSRT Mark3 hybrid.
(3) It is assumed that all power and ground inputs to the hybrid are con-
nected.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7) Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to the pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid-
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8) An "X" in one or more of the product type fields indicates that the
reference is applicable to all available product options.
(9) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub con-
nection.
(10) External 10 µF tantalum and 0.1 µF capacitors to ground should be
located as close as possible to +3.3 Vdc input pins.
(11) Power dissipation is the input power minus the power delivered to
the 1553 fault isolation resistors, the power delivered to the bus ter-
mination resistors, and the copper losses in the transceiver isolation
transformer and the bus coupling transformer. An illustration of exter-
nal power dissipation for transformer coupled configuration (while
transmitting) is: 0.14 watts for the active isolation transformer, 0.08
watts for the active bus coupling transformer, 0.45 watts for each of
the two bus isolation resistors and 0.15 watts for each of the two bus
termination resistors.
(12) Measured from mid-parity crossing of command word to mid-sync
crossing of RT's status word.
(13) θJC is measured to bottom of ceramic case.
(14) Current drain and power dissipation specifications are based on a
small sample size and subject to change.
MHz
MHz
MHz
MHz
%
%
%
%
%
-0.01
-0.10
0.001
0.01
60
16.0
12.0
10.0
20.0
0.01
0.10
-0.001
-0.01
40
CLOCK INPUT
Frequency
• Nominal Value
• Default
• Option
• Option
• Option
• Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
• Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
• Duty Cycle
UNITSMAXTYPMINPARAMETER
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont’d)
W
W
W
W
W
W
W
W
0.25
0.47
0.69
1.13
0.25
0.48
0.71
1.18
POWER DISSIPATION (CONT’D)
• BU-64703X3/4-X00 (1553 &McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-64703X3-X02 (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
5
Data Device Corporation
www.ddc-web.com
BU-64703
H-06/11-0
The SSRT Mark3 may be operated from a 10, 12, 16, or 20 MHz
clock input. For any clock frequency, the decoder samples
incoming data on both edges of the clock input. This oversam-
pling, in effect, provides for a sampling rate of twice the input
clocks' frequency. Benefits of the higher sampling rate include a
wider tolerance for zero-crossing distortion and improved bit
error rate performance.
The SSRT Mark3 includes a hardwired RT address input. This
includes 5 address lines, an address parity input, and an address
parity error output. The RT address can also be latched by
means of a latching input signal.
The SSRT Mark3 supports command illegalization. Commands
may be illegalized by asserting the input signal ILLEGAL active
low within approximately 2 µs after the mid-parity bit zero-cross-
ing of the received command word. Command words may be
illegalized as a function of broadcast, T/R bit, subaddress, word
count, and/or mode code.
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The SSRT Mark3 provides a number of real-time output signals.
These various signals provide indications of message in prog-
ress, valid received message, message error, handshake fail,
loop-test fail or transmitter timeout.
The SSRT Mark3 includes standard DMA handshake sig-
nals (Request, Grant, and Acknowledge) as well as transfer
control outputs (MEMOE and MEMWR). The DMA interface
operates in a 16-bit mode, supporting word-wide transfers.
The SSRT Mark3's system interface allows the SSRT Mark3 to
be interfaced directly to a simple system that doesn't include a
microprocessor. This provides a low-cost 1553 interface for A/D
and D/A converters, switch closures, actuators, and other dis-
crete I/O signals.
The SSRT Mark3 has an internal FIFO for received data words.
This 32-word deep FIFO may be used to allow the SSRT Mark3 to
transfer its data words to the local system in burst mode. Burst
mode utilizes the FIFO by transferring data to the local bus at a rate
of one data word every three clock cycles. Burst mode negotiates
only once for use of the subsystem bus. Negotiation is performed
only after all 1553 data words have been received and validated. In
non-burst mode, the SSRT Mark3 will negotiate for the local bus
after every received data word. The data word transfer period is
three clock cycles for each received 1553 data word.
The SSRT Mark3 may also be used in a shared RAM interface
configuration. By means of tri-state buffers and a small amount
of "glue" logic, the SSRT Mark3 will store Command Words and
access Data Words to/from dedicated "mailbox" areas in a
shared RAM for each broadcast / T/R bit / subaddress / mode
code.
INTRODUCTION
GENERAL
The BU-64703 Simple System RT Mark3 (SSRT Mark3) is a
complete MIL-STD-1553 Remote Terminal (RT) bus interface
unit. Contained in this hybrid are a dual transceiver and
Manchester II encoder/decoder, and MIL-STD-1553 Remote
Terminal (RT) protocol logic. Also included are built-in self-test
capability and a parallel subsystem interface. The subsystem
interface includes a 12-bit address bus and a 16-bit data bus that
operates in a 16-bit DMA handshake transfer configuration. The
local bus and associated control signals are optimized for +3.3
volt logic but are +5 volt tolerant.
The transceiver front end of the SSRT Mark3 is implemented by
means of low-power monolithic technology. The transceiver
requires only a single +3.3V voltage source (+5.0V available).
The voltage source transmitters provide superior line driving
capability for long cables and heavy amounts of bus loading. In
addition, the monolithic transceivers can provide a minimum stub
voltage level of 20 volts peak-to-peak transformer coupled, mak-
ing the SSRT Mark3 suitable for MIL-STD-1760 applications. To
provide compatibility to McAir specs, the SSRT Mark3 is avail-
able with an option for transmitters with increased rise and fall
times.
Besides eliminating the demand for an additional power supply,
the use of a +3.3V only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer. This provides the
advantage of a higher terminal input impedance than is possible
for a 15V, 12V or 5V transmitter. As a result, there is a greater
margin for the input impedance test, mandated for the 1553
validation test. This allows for longer cable lengths between a
system connector and the isolation transformers of an embed-
ded 1553 terminal.
The receiver sections of the SSRT Mark3 are fully compliant with
MIL-STD-1553B in terms of front-end overvoltage protection,
threshold, and bit-error rate.
The SSRT Mark3 implements all MIL-STD-1553 message for-
mats, including all 13 MIL-STD-1553 dual redundant mode
codes. Any subset of the possible 1553 commands (broadcast,
T/R bit, subaddress, word count/mode code) may be optionally
illegalized by means of an external PROM, PLD, or RAM. An
extensive amount of message validation is performed for each
message received. Each word received is validated for correct
sync type and sync encoding, Manchester II encoding, parity,
and bit count. All messages are verified to contain a legal,
defined command word and correct word count. If the SSRT
Mark3 is the receiving RT in an RT-to-RT transfer, it verifies that
the T/R bit of the transmit command word is logic "1" and that the
transmitting RT responds in time and contains the correct RT
address in its Status Word.
6
Data Device Corporation
www.ddc-web.com
BU-64703
H-06/11-0
BU-64703E8 SSRT MARK3 (+3.3V) TRANSFORMER
EVALUATION BOARD (SEE FIGURE 2)
The BU-64703E8 board is intended to support customers who
are interested in electrically connecting and evaluating the per-
formance of the +3.3V SSRT Mark3. The user will be able to
quickly perform functional tests and run their system software
utilizing this relatively small (2.0” x 2.5”) evaluation board.
The BU-64703E8 consists of a PC board incorporating a +3.3V
SSRT Mark3 (BU-64703G8), necessary decoupling capacitors,
and associated isolation transformers. The MIL-STD-1553 outputs
have been factory configured for Stub (transformer) coupling. The
board supports the signal fan-out of the +3.3V SSRT Mark3 to 96
pins subdivided into (4) dual inline, berg type pin rows. These pins
(0.025” square max) and their row placement adhere to standard
0.100” vector board spacing.
ADDRESS MAPPING
A typical addressing scheme for the SSRT Mark3 12-bit address
bus could be as follows:
A11: BROADCAST/OWNADDRESS
A10: TRANSMIT/RECEIVE
A9-A5: SUBADDRESS 4-0
A4-A0: WORD COUNT/MODE CODE 4-0
This method of address mapping provides for a "mailbox" alloca-
tion scheme for the storage of data words. The 12 address out-
puts may be used to map into 4K words of processor address
space. The SSRT Mark3's addressing scheme maps messages
in terms of broadcast/ownaddress, transmit/receive, subaddress,
and word/count mode code. A 32-word message block is allo-
cated for each T/R-subaddress.
For non-mode code messages, the Data Words to be transmitted
or received are accessed from (to) relative locations
0 through 31 within the respective message block. For the
MIL-STD-1553B Synchronize with data, Selected transmitter
shutdown, Override selected transmitter shutdown, and Transmit
vector word mode commands which involve a single data word
transfer, the address for the data word is offset from location 0
of the message block for subaddresses 0 and 31 by the value of
the mode code field of the received command word.
The data words transmitted in response to the Transmit last com-
mand or Transmit BIT word mode commands are accessed from
a pair of internal registers.
DMA INTERFACE
A 16-bit data bus, a 12-bit address bus, and six control signals
are provided to facilitate communication with the parallel subsys-
tem. The data bus D15-D0 consists of bi-directional tri-state
signals. The address bus L_BRO, T/R, SA4-SA0, and WC/MC/
CWC4-0; along with the data transfer control signals MEMOE
and MEMWR are two-state output signals.
The control signals include the standard DMA handshake sig-
nals DTREQ, DTGRT, DTACK, as well as the transfer control
outputs MEMOE and MEMWR. HS_FAIL provides an indication
to the subsystem of a handshake failure condition.
Data transfers between the subsystem and the SSRT Mark3 are
performed by means of a DMA handshake, initiated by
the SSRT Mark3. A data read operation is defined to be the trans-
fer of data from the subsystem to the SSRT Mark3. Conversely, a
data write operation transfers data from the SSRT Mark3 to the
subsystem. Data is transferred as a single 16-bit word.
DMA READ OPERATION
In response to a transmit command, the SSRT Mark3 needs to
read data words from the external subsystem. To initiate a data
word read transfer, the SSRT Mark3 asserts the signal DTREQ
low. Assuming that the subsystem asserts DTGRT in time, the
SSRT Mark3 will then assert the appropriate values of L_BRO
(logic "0"), T/R (high), SA4-0, and MC/CWC4-0; MEMWR high,
along with DTACK low and MEMOE low to enable data to be
read from the subsystem.
After the transfer of each Data Word has been completed, the
value of the address bus outputs CWC4 through CWC0 is incre-
mented.
DMA WRITE OPERATION
In response to a receive command, the SSRT Mark3 will need to
transfer data to the subsystem. There are two options for doing
this, the burst mode and the non-burst mode. In burst mode, all
received data words are transferred from the SSRT Mark3 to the
subsystem in a contiguous burst, only following the reception of
the correct number of valid data words. In the non-burst mode,
single data words are written to the external subsystem immedi-
ately following the reception of each individual data word.
To initiate a DMA write cycle, the SSRT Mark3 asserts DTREQ
low. The subsystem must then respond with DTGRT low.
Assuming that DTGRT was asserted in time, the SSRT Mark3
will then assert DTACK low. The SSRT Mark3 will then assert the
appropriate value of L_BRO, T/R, SA4-0, and MC/CWC4-0,
MEMOE high, and MEMWR low. MEMWR will be asserted low
for one clock cycle. The subsystem may then use either the fall-
ing or rising edge of MEMWR to latch the data. Similar to the
DMA read operation, the address outputs CWC4 through CWC0
are incremented after the completion of a DMA write operation.
HANDSHAKE FAIL
Following the assertion of DTREQ low by the SSRT Mark3, the
external subsystem has 10 µs to respond by asserting DTACK to
logic "0".
7
Data Device Corporation
www.ddc-web.com
BU-64703
H-06/11-0
FIGURE 2. BU-64703E8 SSRT Mark3 (+3.3V) TRANSFORMER EVALUATION BOARD
T2 T1
P1 P3
P4
P2
112 X ∅0.025 ±.001
[∅0.64]
0.100 [2.54]
1.600 [40.64]
0.100
[2.54]
2.200 [55.88]
2.300 [58.42]
2.500 [63.50]
(MAX)
0.062 (1.57)
4X 0.230
[5.84]
4X 0.090 [2.30]
0.300 [7.62]
(MAX)
31
32
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
31
32
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
S/N
DC
0.100
[2.54]
2.000 [50.80]
1.700 [43.18]
2 X 11 EQUAL SPACES @
0.100 [2.54] = 1.100 [27.94]
(TOL NON-CUM)
0.150 [3.81]
2 X 0.300 [7.62]
2X 15 EQUAL SP @
0.100 [2.54]=
1.500 [38.10]
(TOL-NONCUM)
2X 0.600 [15.24]
U1
Dimensions are in inches
[mm]
8
Data Device Corporation
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H-06/11-0
L-BRO
T/R
A 11
A 10
A 9
A 8
A 7
A 6
A 5
A 4
A 3
A 2
A 1
PROM / RAM / PLD
(4Kx1)
SA1
WC/MC/CWC3
WC/MC/CWC2
SA0
WC/MC/CWC4
WC/MC/CWC1
SA4
SA3
SA2
WC/MC/CWC0
I L L E G A L
A 0
D 0
BU - 64703
"SSRT Mark3"
(400ns max)
FIGURE 3. SSRT Mark3 ILLEGALIZATION
If the SSRT Mark3 asserts DTREQ and the subsystem does not
respond with DTGRT in time for the SSRT Mark3 to complete a
data word transfer, the HSFAIL output will be asserted low to
inform the subsystem of the handshake failure, and bit 12 in the
internal Built-In-Test (BIT) word will be set to logic "1". If the
handshake failure occurs on a data word read transfer (for a
transmit command), the SSRT Mark3 will abort the current mes-
sage transmission. In the case of a handshake failure on a write
transfer (received command) the SSRT Mark3 will set the hand-
shake failure output and BIT word bit, and abort processing the
current message.
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
SSRT Mark3 will attempt to perform one of the following opera-
tions: (1) transfer received 1553 data to the subsystem, (2) read
data from the subsystem for transmission on the 1553 bus, (3)
transmit status (and possibly the last command word or RT BIT
word) on the 1553 bus, and/or (4) set status word conditions.
The SSRT Mark3 responds to all non-broadcast messages to its
RT address with a 1553 Status Word.
RT ADDRESS
RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity
(RT_AD_P) should be programmed for a unique RT address and
reflect an odd parity sum. The SSRT Mark3 will not respond to
any MIL-STD-1553 commands or transfer received data from
any non-broadcast messages if an odd parity sum is not pre-
sented by RT_AD_4-0 and RT_AD_P. An address parity error will
be indicated by a low output on the RT_AD_ERR pin. The input
signal RT_AD_LAT operates a transparent latch for RTAD4-
RTAD0 and RTADP. If RT_AD_LAT is low, the output of the latch
tracks the value presented on the input pins. If RT_AD_LAT is
high, the output of the internal latch becomes latched to the val-
ues presented at the time of a low-to-high transition of RT_AD_
LAT.
RT address and RT Address Parity must be presented valid
before the mid-parity crossing of the 1553 command and held, at
least, until following the first received data word.
COMMAND ILLEGALIZATION
The SSRT Mark3 includes a provision for command illegaliza-
tion. If a command is illegalized, the SSRT Mark3 will set the
Message error bit and transmit its status word to the Bus
Controller. No data words will be transmitted in response to an
illegalized transmit command. However, data words associated
with an illegalized receive command will be written to the exter-
nal subsystem (although these transfers may be blocked using
external logic).
ILLEGAL is sampled approximately 2 µs following the mid-parity
bit zero crossing of the received command word. A low on
ILLEGAL will illegalize a particular command word and cause the
SSRT Mark3 to respond with its Message error bit set in its sta-
tus word. Command illegalization based on broadcast, T/R bit,
subaddress, and/or word count/mode code may be implemented
by means of an external PROM, PLD, or RAM device, as shown
in Figure 3.
The external device may be used to define the legality of spe-
cific commands. Any subset of the possible 1553 commands
may be illegalized as a function of broadcast, T/R bit, subad-
dress, word count, and/or mode code. The output of the illegal-
ization device should be tied directly to the SSRT Mark3's
ILLEGAL signal input. The maximum access time of the external
illegalizing device is 400 ns.
If illegalization is not used, ILLEGAL should be hardwired to logic
"1".
9
Data Device Corporation
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cessfully transferred to the subsystem, a negative pulse will be
asserted on the output Good Block Received (GBR). The width
of this pulse is two clock cycles.
RT-TO-RT TRANSFER ERRORS
For the case where the SSRT Mark3 is the receiving RT of an
RT-to-RT transfer, if the transmitting RT does not respond within
the specified time period, the SSRT Mark3 will determine that a
timeout condition has occurred. The value of the SSRT Mark3's
RT-to-RT timeout timer is in the range from 17.5 to 18.5 µs, and
is specified from the mid-parity bit crossing of the transmit com-
mand word to the mid-sync crossing of the transmitting RT's
status word. In the case of an RT-to-RT timeout, the SSRT Mark3
will not respond and the RT-to-RT NO TRANSFER TIMEOUT bit
(bit 2) of the SSRT Mark3's BIT Word will be set to logic "1".
Also, if the SSRT Mark3 is the receiving RT for an RT-to-RT
transfer, and the T/R bit of the second command word is logic
"0", or the RT address field for the transmit command is the
same as for the receive command, or the subaddress for the
transmit command is 00000 or 11111, the SSRT Mark3 will not
respond, and will set the RT-to-RT SECOND COMMAND
ERROR bit (bit 1) of the RT BIT word to logic "1".
RT STATUS, ERROR HANDLING, AND MESSAGE
TIMING SIGNALS
Message transfers and transfer errors are indicated by means of
the INCMD, HS_FAIL, MSG_ERR, and RTFAIL error indication
outputs. Additional error detection and indication mechanisms
include updating of the internal command, RT status and BIT
word registers.
The SSRT Mark3 provides a number of timing signals during the
processing of 1553 messages. INCMD is asserted low when a
new command is received. At the end of a message (either valid
or invalid), INCMD transitions from low to high.
As discussed above, HS_FAIL will be asserted low if the subsys-
tem fails to respond to DTREQ within the maximum amount of
time (10 µs).
Following the last data word transfer for a valid non-mode code
receive message (for either non-burst mode or burst mode),
GBR will be asserted low for two clock cycles.
MSG_ERR is asserted as a low output level following any detect-
ed error in a received message, except for an error in the com-
mand word. If an error is detected in a received command word,
the rest of the message will be ignored.
If MSG_ERR and/or HS_FAIL have been asserted (low), they will
be cleared to logic "1" following receipt of a subsequent valid
command word.
BUSY
The external subsystem may control the SSRT Mark3's Busy RT
status word bit by means of the BUSY input signal. The SSRT
Mark3 samples BUSY approximately 2 µs following the mid-
parity bit zero crossing of the received Command Word. If BUSY
is sampled low for a particular message, the value of the busy bit
transmitted in the SSRT Mark3's status word will be logic "1". If
BUSY is sampled high for a particular message, the value of the
busy bit transmitted in the SSRT Mark3's status word will be logic
"0".
If the RT responds to a transmit command with a busy bit of logic
"1", the status word will be transmitted, but no data words will be
transmitted by the SSRT Mark3. If the SSRT Mark3 responds to
a receive command with a busy bit of logic "1", data words will
be transferred to the external subsystem (although these may be
blocked by means of external logic).
Similar to ILLEGAL, it is possible to cause the SSRT Mark3 to
respond with Busy for specific command words (only), by means
of an external PROM, RAM, or PLD device.
TRANSMIT COMMAND (RT-TO-BC TRANSFER)
If the SSRT Mark3 receives a valid Transmit command word that
the subsystem determines is legal (input signal ILLEGAL is high)
and the subsystem is not BUSY (input signal BUSY is high), the
SSRT Mark3 will initiate a transmit data response following
transmission of its status word. This entails a handshake/read
cycle for each data word transmitted, with the number of data
words to be transmitted specified by the word count field of the
transmit command word.
If ILLEGAL is sampled low, the Message Error bit will be set in
the SSRT Mark3's status word. No data words will be transmitted
following transmission of the status word to an illegalized trans-
mit command. A low on the BUSY input will set the busy bit in the
Status Word; in this instance, only the status word will be trans-
mitted, with no data words.
RECEIVE COMMAND (BC-TO-RT TRANSFER)
In non-burst mode, a DMA handshake will be initiated for each
data word received from the 1553 data bus. If successful, the
respective handshake will be followed by a corresponding write
cycle. A handshake timeout will not terminate transfer attempts
for the remaining data words, error flagging or Status Word trans-
mission. After the reception of a valid non-mode code receive
Command Word followed by the correct number of valid Data
Words and assuming that all words are successfully transferred
to the subsystem, a negative pulse will be asserted on the Good
Block Received (GBR) output. The width of this pulse is two clock
cycles.
In burst mode, a DMA handshake will not be initiated until after
all data words have been received over the 1553 data bus and
stored into the SSRT Mark3's internal FIFO. After the handshake
has been negotiated, the SSRT Mark3 will burst the contents of
the FIFO to the local bus (D0-D15). After the reception of a valid
non-mode code receive command word followed by the correct
number of valid data words and assuming that all words are suc-
10
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LOOPBACK TEST
The SSRT Mark3 performs a loopback self-test at the end of
each non-broadcast message processed. The loopback test
consists of the following verifications: (1) The received version of
every transmitted word is verified for validity (encoding, bit count,
parity) and correct sync type; and (2) The received version of the
last transmitted word is verified by means of a bit-by-bit com-
parison to the transmitted version of this word. If there is a trans-
mitter timeout (660.5 µs) and/or if the loopback test fails for one
or more transmitted words, the Terminal flag status word bit will
be set in response to the next non-broadcast message.
Note that the setting of the Terminal flag status bit following a
loop test failure may be disabled by means of the Auto-Config
feature; i.e., by setting Auto-Config bit 4 to logic "0".
STATUS WORD
The Broadcast Command Received bit is formulated internally
by the SSRT Mark3. The Message Error Status bit will be set if
the current command is a Transmit Status Word or Transmit Last
Command mode command if there was an error in the data por-
tion of the previous receive message. Message Error will also be
set if ILLEGAL has been sampled low by the SSRT Mark3 for the
current message. ILLEGAL, SRV_RQST, BUSY, and SSFLAG
(Subsystem Flag) will be sampled from their respective Status
input pins approximately 2 µs following the mid-parity bit zero
crossing of the received Command Word. This time is 400 ns
maximum following after the L_BRO, T/R, SA4-0, and WC/MC/
CWC4-0 outputs have been presented valid.
PROTOCOL SELF-TEST
The SSRT Mark3 includes a comprehensive, autonomous off-
line self-test of its internal protocol logic. The test includes a
comprehensive test of all registers, Manchester encoder and
MIL-STD-1553A/B
(-B is logic "1", or the
default).
POWER-UP SELF-
TEST ENABLE
BURST MODE
SUBADDRESS 30
WRAPAROUND
RTFAIL-to-TERMINAL
FLAG AUTO-WRAP
RT GOES ONLINE IF
SELF-TEST FAILS
FUNCTION
In MIL-STD-1553B mode, subaddress 31 is a mode code subaddress, and
mode codes are implemented in full accordance with MIL-STD-1553B. In MIL-
STD-1553A mode, subaddress 31 is a non-mode code subaddress, and no
data words are transmitted or anticipated to be received for mode code mes-
sages.
If enabled, the SSRT Mark3 will perform self-test following the rising edge of
MSTCLR.
0
Enables burst mode (using the internal FIFO) for received data words. In burst
mode, for a receive message, all data words are transferred to the external
system in a contiguous burst following reception of the last data word.
1
Subaddress 30 wraparound is enabled. That is, the data words for a receive
message to subaddress 30 are stored in the internal FIFO, and not transferred
to the external system. For a subsequent transmit message to subaddress 30,
the transmitted data words are read from the internal FIFO, rather than from
the external system.
2
If the loop test fails for a particular message, the Terminal flag bit will be set in
the SSRT Mark3's status response for the subsequent non-broadcast message.
4
If logic "0", the RT will become enabled only if the self-test passes. If auto-con-
fig is not used, or if this bit is logic "1", or if the power-up self-test passes, then
the RT will go online following self-test.
5
DESCRIPTIONBIT
3
TABLE 2. AUTO-CONFIGURATION PARAMETERS
11
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0
1
1
0
CLK_SEL_0
16 MHz1
20 MHz0
10 MHz0
CLOCK FREQUENCYCLK_SEL_1
1
TABLE 3. CLOCK FREQUENCY SELECTION
12 MHz
decoders, transmitter failsafe timer, protocol logic, and the inter-
nal FIFO.
This test is completed in approximately 32,000 clock cycles.
That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz,
2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. While the SSRT
Mark3 is performing its off-line self-test, it will ignore (and
therefore not respond to) all messages received from the
1553 bus.
Unless disabled by means of the SSRT Mark3's Auto-Config
feature, the protocol self-test will be performed following the
SSRT Mark3's power turn-on (i.e., when MSTCLR is released
high). If the Auto-Config feature is used and Auto-Config bit 5 is
set to logic "0", then a failure of the protocol self-test following
power turn-on will result in the SSRT Mark3 not going online. If
bit 5 is set to logic "0" and the protocol self-test passes following
power turn-on, the SSRT Mark3 will go online.
The protocol self-test will also be performed following receipt of
an Initiate self-test mode command from the 1553 bus. If an
Initiate self-test mode command is received by the SSRT Mark3,
and Auto-Config bit 5 is set to logic "0", then a failure of the pro-
tocol self-test following will result in the SSRT Mark3 going
offline.
If the protocol self-test fails: (1) the Terminal Flag bit will be
set to logic "1" in the SSRT Mark3 status word; (2) bit 8 in the
SSRT Mark3's BIT word, BIT Test Fail, will be set to logic "1";
(3) the SSRT Mark3's RTFAIL output will be asserted to logic
"0".
AUTO-CONFIGURATION
The SSRT Mark3 includes an auto-configuration feature, which
allows various optional features to be enabled or disabled. Auto-
configuration may be enabled or disabled by means of the input
signal AUTO_CFG. If AUTO_CFG is connected to logic "1", then
the auto-configure option is disabled, and the six configuration
parameters revert to their default values.
Note that the default condition for each configuration param-
eter is enabled (for the MIL-STD-1553A/B protocol selection,
-1553B is the default).
If AUTO_CFG is connected to logic "0", then the configuration
parameters are transferred over D5-D0 by means of a DMA read
data transfer. The transfer occurs during the time that the
RTACTIVE and DTACK outputs are logic "0", following MSTCLR
transitioning from logic "0" to logic "1" and a successful
DT_REQ-to-DTGRT handshake.
Note that if DTGRT is hardwired to logic "0", the handshake
process is not necessary (i.e., DTACK and RTACTIVE will both
be asserted to logic "0" one clock cycle following DT_REQ).
Each of the configuration parameters is enabled if the SSRT
Mark3 reads a value of logic "1" for the respective data bit.
The auto-configuration parameters are defined in TABLE 2.
The timing signals pertaining to Auto-Configuration mode are
illustrated in Figure 13.
CLOCK INPUT
The SSRT Mark3 may be operated from one of four clock frequen-
cies: 10, 12, 16, or 20 MHz. The selected clock frequency must be
designated by means of the input signals CLK_SEL_1 and CLK_
SEL_0, as shown in TABLE 3.
12
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t1 Mid-parity crossing of received command word delay to
SA4-SA0, L-BRO, T/R Bit, and WC/MC valid ALL µs
t2 Mid-parity crossing of received command word delay to
falling edge of INCMD ALL µs
t3 Mid-parity crossing of received command word delay to
MSG_ERR and HS_FAIL rising ALL µs
t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL ns
t5 L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ALL 500 ns
t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling
edge of INCMD ALL 300 ns
t7 Mid-parity crossing of first data word to WC/CWC valid data of 1Fh ALL µs
t8 Duration of WC/CWC data value of 1Fh ALL ns
t9 RT Response time. ALL 4µs
t10 CWC transition to next word following mid-parity of subsequent
received data words. ALL µs
t11 Mid-parity crossing of last data word to DTREQ falling edge
(requesting data word burst write transfer) ALL 4µs
t12 Mid-Sync crossing of Status response to RT_FAIL rising ALL µs
t13 CWC valid following falling edge of DTREQ ALL ns
t14 GBR pulse width (see Note 1)
20 MHz ns
REF DESCRIPTION CLOCK
FREQUENCY
RESPONSE TIME UNITS
TABLE FOR FIGURE 4. RT RECEIVE COMMAND TIMING (BURST MODE)
t15 Mid-parity crossing of status word to INCMD rising ALL µs
MIN TYP MAX
1.5
2
1.5
400
1
200
6.5 7
1
4.5 5.25
1.5
30
100
3
16 MHz ns
125
12 MHz ns
167
10 MHz ns
200
(1) If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR.
1553 BUS RX COMMAND DATA #2DATA #1 STATUS
L-BRO, T/R, SA4-SA0
WC/MC/CWC
INCMD
DTREQ
DTGRT
DTACK
GBR
MEMWR
MEMOE
D15-D0
RT_FAIL
MSG_ERR
HS_FAIL
MID-PARITY MID-PARITY
MID-PARITY MID-PARITY MID-SYNC
BURST
DATA
WRITE
TRANSFER
t1
t11
t12
t6
t2
t15
t9
PREVIOUS MSG cwc
ILLEGAL, SRV_RQST
SSFLAG, BUSY VALID
t3
t5
t4 t8
WC / MC WC / MCCWC = 0 CWC = 1
RT RECEIVE COMMAND (BURST MODE)
1F
t7
t14
t13
t10
NOTE 1
NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD
is referenced from the rising edge of GBR.
(Refer to FIGURE 10)
FIGURE 4. RT RECEIVE COMMAND (BURST MODE) TIMING
13
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FIGURE 5. RT RECEIVE COMMAND (NON-BURST MODE) TIMING
t1 Mid-parity crossing of received command word delay to
SA4-SA0, L-BRO, T/R Bit, and WC/MC valid ALL µs
t2 Mid-parity crossing of received command word delay to
falling edge of INCMD ALL µs
t3 Mid-parity crossing of received command word delay to
MSG_ERR and HS_FAIL rising ALL µs
t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL ns
t5 RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ALL 500 ns
t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling
edge of INCMD ALL 300 ns
t7 Mid-parity crossing to WC/CWC value of 1Fh ALL µs
t8 Mid-parity crossing of first data word to DTREQ falling edge
t9 WC/CWC data value of 1Fh held
t10 CWC valid following falling edge of DTREQ ALL ns
t11 RT Response time. ALL 4 µs
t12 Delay from following mid-parity of last received data word to GBR low.
(see Notes 1, 2) ALL 4µs
t13 Mid-parity crossing of all data words, except first data word, to DTREQ
falling edge ALL µs
t14 GBR pulse width
20 MHz ns
REF DESCRIPTION CLOCK
FREQUENCY
RESPONSE TIME UNITS
TABLE FOR FIGURE 5. RT RECEIVE COMMAND TIMING (NON-BURST MODE)
t15 CWC transition to WC prior to Mid-Sync crossing of Status response.
MIN TYP MAX
1.5
2
1.5
400
1
30
6.5 7
1
100
16 MHz ns
125
12 MHz ns
167
10 MHz ns
200
t16 Mid-Sync crossing of status response to RT_FAIL rising ALL µs1.5
t17 Mid-parity crossing of status word to INCMD rising ALL µs3.0
20 MHz µs
1.2
16 MHz µs
1.25
12 MHz µs
1.33
10 MHz µs
1.4
20 MHz ns
75
16 MHz ns
94
12 MHz ns
125
10 MHz ns
150
20 MHz ns
200
16 MHz ns
250
12 MHz ns
333
10 MHz ns
400
(1) Assumes that DTGRT is tied to logic “0”. If DTGRT is not connected to logic “0”, the minimum time to drive GBR active low will increase by the
amount of the DTGRT (low) - to - DTGRT (low) delay.
(2) The transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter.
1553 BUS RX COMMAND DATA #2DATA #1 STATUS
L-BRO, T/R, SA4-SA0
WC/MC/CWC
INCMD
DTREQ
DTGRT
DTACK
GBR
MEMWR
MEMOE
D15-D0
RT_FAIL
MSG_ERR
HS_FAIL
MID-PARITY MID-PARITY
MID-PARITY MID-PARITY MID-SYNC
t1
t13
t16
t6
t2 t12
t17
t11
PREVIOUS MSG CWC = 1 WC / MC
ILLEGAL, SRV_RQST
SSFLAG, BUSY VALID
t3
t5
t4 t9
t10
WC / MC CWC = 0
RT RECEIVE COMMAND (NON-BURST MODE)
1F
t7
t14
t8
t15
SINGLE
WORD
WRITE
DATA WORD
#1
SINGLE
WORD
WRITE
DATA WORD
#2
(Refer to FIGURE 11)
14
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FIGURE 6. RT TRANSMIT COMMAND TIMING
1553 BUS TX COMMAND DATA #2DATA #1
STATUS
INCMD
DTREQ
DTGRT
DTACK
GBR
MEMWR
MEMOE
D15-D0
RT_FAIL
MSG_ERR
HS_FAIL
MID-PARITY MID-SYNC MID-PARITYMID-SYNC MID-SYNC
SINGLE
WORD
READ
DATA WORD
#1
SINGLE
WORD
READ
DATA WORD
#2
t15
t9
t10
t4
t1
ILLEGAL, SRV_RQST
SSFLAG, BUSY VALID
t7
t5
t13
t14
RT TRANSMIT COMMAND
L-BRO, T/R, SA4-SA0
WC/MC/CWC
t2
t3
PREVIOUS MSG cwc = 1
t6
t11
t12
WC WCCWC = 0
1F
t8
(Refer to FIGURE 12)
t1 RT Response time. ALL 4 µs
t2 Mid-parity crossing of received command word delay to
L-BRO, T/R Bit, SA4-SA0, and WC/MC valid ALL µs
t3 Mid-parity crossing of received command word delay to
falling edge of INCMD ALL µs
t4 Mid-Parity crossing of receive command word delay to
MSG_ERR and HS_FAIL rising ALL µs
t5 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
SA4-SA0, L-BRO, T/R Bit, and CWC/MC valid ALL ns
t6 L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD low ALL 500 ns
t7 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following
falling edge of INCMD ALL 300 ns
t8 Mid-Sync crossing of status word to WC/CWC valid data of 1Fh
t9 Mid-Sync crossing of status word to DTREQ falling edge
t10 Mid-Sync crossing of Status response to RT_FAIL rising (see Note 1) ALL µs
t11 Duration of WC/CWC value of 1Fh
t12 CWC valid following falling edge of DTREQ ALL ns
t13 Mid-Sync crossing of received data word to DTREQ falling edge
20 MHz µs
REF DESCRIPTION CLOCK
FREQUENCY
VALUE UNITS
TABLE FOR FIGURE 6. RT TRANSMIT COMMAND TIMING
t14 Mid-Sync crossing of last received data word for CWC to transition to
WC
MIN TYP MAX
6.5 7
1.5
2
1.5
400
1.5
30
1.75
16 MHz µs
1.81
12 MHz µs
1.92
10 MHz µs
2
t15 Mid-Parity crossing of status word to INCMD rising ALL µs
3
20 MHz µs
1.55
16 MHz µs
1.56
12 MHz µs
1.59
10 MHz µs
1.6
20 MHz µs
6.75
16 MHz µs
6.81
12 MHz µs6.92
10 MHz µs
7
20 MHz ns
200
16 MHz ns
250
12 MHz ns
333
10 MHz ns
400
ALL µs
6.5
(1) Assuming that RTFAIL was previously low.
15
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t1 RT - RT response timeout for transmitting RT. ALL 17.5 µs
t2 Mid-parity crossing of received command word delay to
L-BRO, T/R Bit, SA4-SA0, and WC/MC valid ALL µs
t3 Mid-parity crossing of received command word delay to
falling edge of INCMD ALL µs
t4 Mid-Parity crossing of received command word delay to
MSG_ERR and HS_FAIL rising ALL µs
t5 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL ns
t6 L-BRO, T/R, SA4-0, and WC/MC4-0 setup time prior to INCMD low ALL 500 ns
t7 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following
falling edge of INCMD ALL 300 ns
t8 Mid-Sync crossing of status word to WC/CWC valid data of 1Fh
t9 Mid-Sync crossing of status word to DTREQ falling edge
t10 Mid-Sync crossing of Status response to RT_FAIL rising ALL µs
t11 Duration of WC/CWC value of 1Fh
t12 CWC valid following falling edge of DTREQ ALL ns
t13 Mid-Sync crossing of received data word to DTREQ falling edge
20 MHz µs
REF DESCRIPTION CLOCK
FREQUENCY
VALUE UNITS
TABLE FOR FIGURE 7. RT-RT TRANSMIT COMMAND TIMING
t14 Mid-Sync crossing of last received data word for CWC to transition to
WC
MIN TYP MAX
18.5 19.5
1.5
2
1.5
400
1.5
30
1.75
16 MHz µs
1.81
12 MHz µs
1.92
10 MHz µs
2
t15 Mid-Parity crossing of status word to INCMD rising ALL µs
3
20 MHz µs
1.55
16 MHz µs
1.56
12 MHz µs
1.59
10 MHz µs
1.6
20 MHz µs
6.75
16 MHz µs
6.81
12 MHz µs
6.92
10 MHz µs
7
20 MHz ns
200
16 MHz ns
250
12 MHz ns
333
10 MHz ns
400
ALL µs
6.5
FIGURE 7. RT - RT TRANSMIT TIMING
INCMD
DTREQ
DTGRT
DTACK
GBR
MEMWR
MEMOE
D15-D0
RT_FAIL
MSG_ERR
HS_FAIL
SINGLE
WORD
READ
DATA WORD
#1
SINGLE
WORD
READ
DATA WORD
#2
t15
t9
t10
t4
t1
ILLEGAL, SRV_RQST
SSFLAG, BUSY VALID
t7
t5
t13
t14
RT - RT TRANSMIT COMMAND
L-BRO, T/R, SA4-SA0
WC/MC/CWC
t2
t3
PREVIOUS MSG cwc = 1
t6
t11
t12
WC WCCWC = 0
1F
t8
1553 BUS RX COMMAND STATUS
TX COMMAND DATA #1
MID-PARITY MID-PARITY
MID-SYNC MID-SYNC MID-SYNC
DATA #2 STATUS
(Refer to FIGURE 12)
16
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H-06/11-0
FIGURE 8. RT - RT RECEIVE (BURST-MODE) TIMING
L-BRO, T/R,
SA4-SA0
WC/MC/CWC
INCMD
DTREQ
DTGRT
DTACK
GBR
MEMWR
MEMOE
D15-D0
RT_FAIL
MSG_ERR
HS_FAIL
MID-PARITY MID-PARITY
MID-PARITY MID-PARITY MID-SYNC
BURST
DATA
WRITE
TRANSFER
t1
t12
t13
t6
t2
t16
t10
PREVIOUS MSG cwc
ILLEGAL, SRV_RQST
SSFLAG, BUSY VALID
t3
t5
t4 t9
WC / MC WC / MC
CWC = 0 CWC = 1
RT - RT RECEIVE COMMAND (BURST MODE)
1F
t8
t15
t14
t11
NOTE 1
NOTE 1 : If the RX message is a Broadcast message then the rising edge of INCMD
is referenced from the rising edge of GBR.
1553 BUS RX COMMAND STATUSTX COMMAND DATA #1
MID-PARITY MID-SYNC
t7
DATA #2 STATUS
(Refer to FIGURE 10)
t1 Mid-parity crossing of received command word delay to
SA4-SA0, L-BRO, T/R Bit, and WC/MC valid ALL µs
t2 Mid-parity crossing of received command word delay to
falling edge of INCMD ALL µs
t3 Mid-parity crossing of received command word delay to
MSG_ERR and HS_FAIL rising ALL µs
t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL ns
t5 L_BRO, T/R, SA4-0, and WC/MC4-0 valid prior to INCMD low. ALL 500 ns
t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY hold time following falling
edge of INCMD ALL 300 ns
t7 RT - RT response timeout for transmitting RT. ALL 17.5 µs
t8 Mid-parity crossing of first data word to WC/CWC valid data
of 1Fh ALL µs
t9 Duration of WC/CWC data value of 1Fh ALL ns
t10 RT Response time. ALL 4µs
t11 CWC transition to next word following mid-parity of subsequent
received data words. ALL µs
t12 Mid-parity crossing of last data word to DTREQ falling edge
(requesting data word burst write transfer) ALL 4µs
t13 Mid-Sync crossing of Status response to RT_FAIL rising ALL µs
t15 GBR pulse width (see Note 1)
20 MHz ns
REF DESCRIPTION CLOCK
FREQUENCY
RESPONSE TIME UNITS
TABLE FOR FIGURE 8. RT-RT RECEIVE COMMAND TIMING (BURST MODE)
t16 Mid-parity crossing of status word to INCMD rising ALL µs
MIN TYP MAX
1.5
2
1.5
400
18.5 19.5
1
200
6.5 7
1
4.5 5.25
1.5
100
3
16 MHz ns
125
12 MHz ns
167
10 MHz ns
200
t14 CWC valid following falling edge of DTREQ ALL ns
30
(1) If the RX message is a Broadcast message then the rising edge of INCMD is referenced from the rising edge of GBR.
17
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FIGURE 9. RT - RT RECEIVE (NON-BURST-MODE) TIMING
L-BRO, T/R,
SA4-SA0
WC/MC/CWC
INCMD
DTREQ
DTGRT
DTACK
GBR
MEMWR
MEMOE
D15-D0
RT_FAIL
MSG_ERR
HS_FAIL
t1
t14
t17
t6
t2 t13
t18
PREVIOUS MSG CWC = 1 WC / MC
ILLEGAL, SRV_RQST
SSFLAG, BUSY
VALID
t3
t5
t4 t10
t11
WC / MC CWC = 0
RT - RT RECEIVE COMMAND (NON-BURST MODE)
1F
t8
t15
t9
t16
SINGLE
WORD
WRITE
DATA WORD
#1
SINGLE
WORD
WRITE
DATA WORD
#2
MID-PARITY MID-PARITY
MID-PARITY MID-PARITY MID-SYNC
t12
1553 BUS
RX COMMAND STATUS
TX COMMAND DATA #1
MID-PARITY MID-SYNC
t7
DATA #2 STATUS
(Refer to FIGURE 11)
t1 Mid-parity crossing of received command word delay to
SA4-SA0, L-BRO, T/R Bit, and WC/MC valid ALL µs
t2 Mid-parity crossing of received command word delay to
falling edge of INCMD ALL µs
t3 Mid-parity crossing of receive command word delay to
MSG_ERR and HS_FAIL rising ALL µs
t4 ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
SA4-SA0, L-BRO, T/R, and CWC/MC valid ALL ns
t5 RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low ALL 500 ns
t6 ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling
edge of INCMD ALL 300 ns
t7 RT - RT response timeout for transmitting RT. ALL 17.5 µs
t9 Mid-parity crossing of first data word to DTREQ falling edge
t10 WC/CWC data value of 1Fh held
t11 CWC valid following falling edge of DTREQ ALL ns
t12 RT Response time. ALL 4µs
t13 Delay from following mid-parity of last received data word to GBR low.
(see Notes 1, 2) ALL 4µs
t14 Mid-parity crossing of all data words, except first data word, to DTREQ
falling edge ALL µs
t15 GBR pulse width
20 MHz ns
REF DESCRIPTION CLOCK
FREQUENCY
RESPONSE TIME UNITS
TABLE FOR FIGURE 9. RT-RT RECEIVE COMMAND TIMING (NON-BURST MODE)
t16 CWC transition to WC prior to Mid-Sync crossing of Status response.
MIN TYP MAX
1.5
2
1.5
400
18.5 19.5
30
6.5 7
1
100
16 MHz ns
125
12 MHz ns
167
10 MHz ns
200
t17 Mid-Sync crossing of status response to RT_FAIL rising ALL µs1.5
t18 Mid-parity crossing of status word to INCMD rising ALL µs3.0
20 MHz µs
1.2
16 MHz µs
1.25
12 MHz µs
1.33
10 MHz µs
1.4
20 MHz ns
75
16 MHz ns
94
12 MHz ns
125
10 MHz ns
150
20 MHz ns
200
16 MHz ns
250
12 MHz ns
333
10 MHz ns
400
t8 Mid-parity crossing to WC/CWC value of 1Fh ALL µs
1
(1) Assumes that DTGRT is tied to logic “0”. If DTGRT is not connected to logic “0”, the minimum time to drive GBR active low will increase by the
amount of the DTGRT (low) - to - DTGRT (low) delay.
(2) The transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter.
18
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t1 CLOCK IN rising to DTREQ low ALL ns
t2 DTREQ falling to DTGRT low ALL µs
t4 DTGRT low setup prior to CLOCK IN rising edge ALL ns
t6 CLOCK IN rising to DTACK low ALL ns
t7 Data output valid following CLOCK IN ALL ns
t8 DTGRT hold time following DTACK falling ALL ns
t10 Data output setup time prior to MEMWR low
t12 MEMWR low pulse width
t13 CLOCK IN rising to MEMWR high ALL ns
t15 Data output hold time following CLOCK IN rising ALL ns
t16 CWC (all but first data word) setup time prior to MEMWR low
20 MHz ns
REF DESCRIPTION CLOCK
FREQUENCY UNITS
TABLE FOR FIGURE 10. SSRT Mark3 DMA WRITE (BURST MODE) TIMING
t20 GBR low pulse width
16 MHz ns
12 MHz ns
10 MHz ns
t21 INCMD rising following CLOCK IN rising (see Note 3) ALL ns
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t3 CWC setup time prior to MEMWR falling for first word of burst transfer
(see Note 1)
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t5 DTGRT falling to DTACK low
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t9 DTACK low pulse width (based on a two data word transfer)
(see Note 2)
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t11 CLOCK IN rising to MEMWR low ALL ns
t14 Data output and CWC hold time following MEMWR high
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t17 CLOCK IN rising to DTREQ and DTACK high ALL ns
t18 Data output signal Tri-State following CLOCK IN rising ALL ns
t19 CLOCK IN rising to GBR falling edge ALL ns
15
15
10
VALUE @3.3 VOLTS
MIN TYP MAX
40
10
40
40
30
40
23
43
60
40
10
22
43
60
90 100
115 125
157 167
190 200
40 50
52.5 62.5
73.3 83.3
90 100
60
85
127
160
105
118
138
155
290 300
365 375
490 500
590 600
40
10
23
43
60
40
40
40
(1) Assumes DTGRT is low at the time that DTREQ is asserted low. If not, then this time will increase by the amount of the DTREQ (low) - to - DTGRT
(low) delay.
(2) DTACK pulse width is 3 clock cycles per data word transfer.
(3) Rising edge of INCMD will immediately follow the rising edge of GBR only for a broadcast message. For a non-broadcast message, the rising
edge of INCMD will occur after the mid-parity crossing of the RT status response. This additional delay time is approximately 96 clock cycles: 9.6 µs
at 10 MHz, 8 µs at 12 MHz, 6.0 µs at 16 MHz, or 4.8 µs at 20 MHz.
19
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FIGURE 10. DMA WRITE TRANSFER (BURST-MODE) TIMING
CLOCK IN
DTREQ
DTGRT
DTACK
MEMWR
MEMOE
WC/MC/CWC
D15-D0 DATA VALIDDATA VALID
t1
t2
t6
t5
t4 t8
t11
t12
t13
t7
t7
t11
t12
t13
t15
t3
t10
t14 t16
t10
t14
t19
t20
t17
L-BRO, T/R,
SA4-SA0 VALID
GBR
INCMD
CWC = 0 CWC = 1 WC
t18
t21
t9
DMA WRITE - BURST MODE
(SHOWN FOR TWO DATA WORDS)
1 INCMD rising edge is shown for the case of a RX Broadcast command message.
For the non-Broadcast case, INCMD rising edge is after the Mid-Parity crossing of the RT STATUS response.
1
20
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t1 CLOCK IN rising to DTREQ low ALL ns
t2 DTREQ (low) - to - DTGRT (low) delay time ALL µs
t4 DTGRT low setup prior to CLOCK IN rising ALL ns
t6 CLOCK IN rising to DTACK low ALL ns
t7 Data output valid following CLOCK IN rising ALL ns
t8 DTGRT hold time following DTACK falling ALL ns
t10 Data output setup time prior to MEMWR low
t12 MEMWR low pulse width
t13 CLOCK IN rising to MEMWR high ALL ns
t15 CLOCK IN rising to DTREQ and DTACK high ALL ns
REF DESCRIPTION CLOCK
FREQUENCY UNITS
TABLE FOR FIGURE 11. SSRT Mark3 DMA WRITE TIMING (NON-BURST)
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t3 CWC setup time prior to MEMWR falling
(see Note)
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t5 DTGRT falling to DTACK low
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t9 DTACK low pulse width
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t11 CLOCK IN rising to MEMWR low ALL ns
t14 Data output hold time following MEMWR high
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t17 Data output signal Tri-State following CLOCK IN rising ALL ns
15
VALUE @3.3 VOLTS
MIN TYP MAX
40
10
40
40
30
40
40
60
85
127
160
40 50
52.5 62.5
73.3 83.3
90 100
110
148
210
260
105
118
138
155
200
250
333
400
40
10
23
43
60
40
t16 Data output hold time following CLOCK IN rising ALL ns15
(1) Assumes that DTGRT is low at the time DTREQ is asserted low. If not, these values can increase by the delay time from DTREQ (low) - to -
DTGRT (low).
FIGURE 11. DMA WRITE TRANSFER (NON-BURST-MODE) TIMING
CLOCK IN
DTREQ
DTGRT
DTACK
MEMWR
MEMOE
WC/MC/CWC
D15-D0 DATA VALID
t1
t2
t6
t5
t4 t8
t11
t12
t13
t17
t16
t7 t14
t10
t3
t15
L-BRO, T/R,
SA4-SA0 VALID
CWC = 0
t9
NON-BURST DMA WRITE
NOTE: With the DTGRT pin tied to GND, the time from DTREQ to DTACK is 1 clock cycle.
21
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FIGURE 12. DMA READ TRANSFER TIMING
CLOCK IN
DTREQ
DTGRT
DTACK
MEMWR
MEMOE
WC/CWC
D15-D0 DATA VALID
t1
t2
t6
t9
t5
t4 t7
t10
t11
t13
t12
L-BRO, T/R,
SA4-SA0
VALID
CWC = 0
t8
t3
DMA SINGLE WORD READ
t1 CLOCK IN rising to DTREQ low ALL ns
t2 DTREQ (low) - to - DTGRT delay time ALL µs
t4 DTGRT low setup prior to CLOCK IN rising ALL ns
t6 CLOCK IN rising to DTACK low ALL ns
t7 DTGRT hold time following DTACK falling ALL ns
t10 MEMOE low pulse width
t11 Time for input data to become valid following falling edge of MEMOE
t12 Data input hold time following CLOCK IN rising (see Note) ALL ns
t13 CLOCK IN rising to DTREQ, DTACK, and MEMOE high ALL ns
REF DESCRIPTION CLOCK
FREQUENCY UNITS
TABLE FOR FIGURE 12. SSRT Mark3 DMA READ TIMING
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t3 CWC setup time prior to MEMOE falling
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t5 DTGRT falling to DTACK low
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t8 DTACK low pulse width
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
30
VALUE @3.3 VOLTS
MIN TYP MAX
40
10
10
40
30
40
150
188
250
300
70
95
136
170
60
85
127
160
105
118
138
155
200
250
333
400
t9 CLOCK IN rising to MEMOE low ALL ns
40
(1) The SSRT Mark3’s data sampling time occurs one clock cycle prior to the rising edge of MEMOE.
22
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FIGURE 13. AUTO-CONFIGURATION - DMA READ TRANSFER TIMING
CLOCK IN
DTREQ
DTGRT
DTACK
MEMWR
MEMOE
D15-D0
MSTCLR
RTACTIVE
DATA VALID
t2
t3
t6
t5
t4 t7
t9
t11
t13
note1
t10
t8
t12
AUTO-CONFIGURATION - DMA SINGLE WORD READ
Note1: RTACTIVE asserted high 1 clock following DTACK high assuming self-test is not enabled.
When self-test is enabled RTACTIVE is delayed in the amount of 't12'.
See the table reference for details.
t1
(1) During Auto-Configuration the SSRT Mark3 samples data three clock cycles following the falling edge of DTACK.
(2) If self-test mode is not enabled, then RTACTIVE will go active high 1 clock cycle following the rising edge of DTACK. If self-test is enabled
then RTACTIVE will be delayed from going active high in accordance with ‘t12’.
t2 CLOCK IN rising to DTREQ low ALL ns
t3 DTREQ (low) - to - DTGRT delay time ALL µs
t4 DTGRT low setup prior to CLOCK IN rising ALL ns
t6 CLOCK IN rising to DTACK low ALL ns
t7 DTGRT hold time following DTACK falling ALL ns
t9 Time for input data to become valid following falling edge of DTACK
t12 RTACTIVE high delayed from DTACK high (see Note 2)
t13 CLOCK IN rising to RTACTIVE high ALL ns
REF DESCRIPTION CLOCK
FREQUENCY UNITS
TABLE FOR FIGURE 13. AUTO-CONFIGURATION - DMA READ TIMING
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
20 MHz ms
16 MHz ms
12 MHz ms
10 MHz ms
t5 DTGRT falling to DTACK low
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
t8 DTACK low pulse width
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
VALUE @3.3 VOLTS
MIN TYP MAX
40
10
10
40
30
40
120
157
220
270
1.6
2.0
2.7
3.2
105
118
138
155
185 200 215
235 250 265
318 333 348
385 400 415
t10 Data input hold time following sampling time (see Note 1) ALL ns
30
t11 CLOCK IN rising to DTREQ, DTACK, and MEMOE high ALL ns
40
t1 MSTCLR high delay to DTREQ low
20 MHz ns
16 MHz ns
12 MHz ns
10 MHz ns
35 50 65
47.5 62.5 77.5
68.3 83.3 98.3
85 100 115
23
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FIGURE 14. CLOCK EDGE SIGNAL TIMING
CLOCK IN
SIGNAL IN
SIGNAL OUT
HIGH TO LOW
SIGNAL OUT
LOW TO HIGH
t1
t2
t3
CLOCK EDGE TO SIGNAL IN / OUT TIMING
t1 SIGNAL INPUT setup time prior to CLOCK IN rising edge ns
t2 CLOCK IN rising edge to SIGNAL OUTPUT driven low (see Note) ns
t3 CLOCK IN rising edge to SIGNAL OUTPUT driven high (see Note) ns
DESCRIPTION UNITS
TABLE FOR FIGURE 14. SSRT Mark3 CLOCK EDGE TO SIGNAL IN / OUT VALID TIMING
15
VALUE @3.3 VOLTS
MIN TYP MAX
40
40
(1) Assumes a 50 pf external load. For loading above 50pf, the validity of output signals is delayed by
an additional 0.14 ns/pf typ, 0.28ns/pf max.
REF
24
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+3.3V INTERFACE TO MIL-STD-1553 BUS (BU-64703X8/9)
The SSRT Mark3 is the world's first MIL-STD-1553 terminal
powered entirely by 3.3 volts. Unique isolation transformer turns
ratios, single output winding transformers and new interconnec-
tion methods are required in order to meet mandated MIL-
STD-1553 differential voltage levels.
FIGURE 15 illustrates the two possible interface methods
between the SSRT Mark3 series and a MIL-STD-1553 bus.
Connections for both direct (short stub, 1:3.75) and transformer
(long stub, 1:2.7) coupling, as well as nominal peak-to-peak volt-
age levels at various points (when transmitting), are indicated in
the diagram.
The center tap of the primary winding (the side of the trans-
former that connects to the SSRT Mark3) must be directly con-
nected to the +3.3 volt plane. Additionally a 10µf, low inductance
tantalum capacitor and a 0.01µf ceramic capacitor must be
mounted as close as possible and with the shortest leads to the
center tap of the transformer(s) and the ground plane.
SSRT Mark3
BU-64703X8/9
DATA
BUS
Z0
55 Ω
55 Ω
(1:3.75)
(7.4 Vpp) 28 Vpp
1 FT MAX
Z0
(1:2.7)
20 Vpp
(1:1.41)
COUPLING
TRANSFORMER
0.75 Z0
0.75 Z0
LONG STUB
(TRANSFORMER
COUPLED)
20 FT MAX
28 Vpp
SHORT STUB
(DIRECT COUPLED)
OR
DIRECT-COUPLED
ISOLATION TRANSFORMER
NOTES:
1. Transformer center tap capacitors: use a 10µF tantalum for low inductance, and a 0.01µF ceramic.
Both must be mounted as close as possible, and with the shortest leads to the center tap of the
transformer(s) and ground.
2. Connect the SSRT Mark3 hybrid grounds as directly as possible to the 3.3V ground plane.
3. Z0 = 70 to 85 Ohms.
SSRT Mark3
BU-64703X8/9
(7.4 Vpp)
TRANSFORMER-COUPLED
ISOLATION TRANSFORMER
7 Vpp
7 Vpp
10µF
.01µF
+
3.3V
10µF
.01µF
+
3.3V
TX/RX
TX/RX
TX/RX
TX/RX
FIGURE 15. BU-64703X8/9 +3.3V INTERFACE TO MIL-STD-1553 BUS
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+3.3 VOLT INTERFACE TO MIL-STD-1553 BUS
(BU-64703XC/D)
FIGURE 16 illustrates the two possible interface methods
between the SSRT Mark3 series and a MIL-STD-1553 bus.
Connections for both direct (short stub, 1:2.65) and transformer
(long stub, 1:2.038) coupling, as well as nominal peak-to-peak
voltage levels at various points (when transmitting), are indicated
in the diagram.
The center tap of the primary winding (the side of the trans-
former that connects to the Mark3) must be directly connected to
ground.
Additionally, during transmission, large currents flow from the
transceiver power supply through the TX/RX pins into the trans-
former primaries and then out the center tap into the ground
plane. The traces in this path should be sized accordingly and
the connections to the ground plane should be as short as pos-
sible.
A 10µf, low inductance tantalum capacitor and a 0.01µf ceramic
capacitor must be mounted as close as possible and with the
shortest leads to the transceiver power input of the Mini-ACE
Mark 3.
SSRT MARK3
BU-64703XC/D
DATA
BUS
Z0
55 Ω
55 Ω
TX/RX
TX/RX
(1:2.65)
28 Vpp
1 FT MAX
Z0
(1:2.038)
20 Vpp
(1:1.41)
COUPLING
TRANSFORMER
0.75 Z0
0.75 Z0
LONG STUB
(TRANSFORMER
COUPLED)
20 FT MAX
28 Vpp
SHORT STUB
(DIRECT COUPLED)
OR
DIRECT-COUPLED
ISOLATION TRANSFORMER
7 Vpp
7Vpp
SSRT MARK3
BU-64703XC/D
TRANSFORMER-COUPLED
ISOLATION TRANSFORMER
NOTES: 1. Connect the SSRT Mark3 hybrid grounds as directly as possible to the 3.3V ground plane.
2. Zo = 70 to 85 Ohms.
TX/RX
TX/RX
3.3V
.01µF
10µF +
3.3V
.01µF
10µF +
FIGURE 16. BU-64703XC/D +3.3 VOLT INTERFACE TO MIL-STD-1553 BUS
26
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+5.0V INTERFACE TO MIL-STD-1553 BUS
FIGURE 17 illustrates the interface between the SSRT Mark3
+5.0V (BU-64703X3/4) and a MIL-STD-1553 bus. Connections
for both direct (short stub) and transformer (long stub) coupling,
as well as the nominal peak-to-peak voltage levels at various
points (when transmitting), are indicated in the diagram.
SSRT MARK3
BU-64703X3/4
DATA
BUS
Z0
55 Ω
55 Ω
TX/RX
TX/RX
(1:2.5)
11.2 Vpp 28 Vpp
1 FT MAX
Z0
(1:1.79)
11.2 Vpp 20 Vpp
(1:1.41)
COUPLING
TRANSFORMER
0.75 Z0
0.75 Z0
LONG STUB
(TRANSFORMER
COUPLED)
20 FT MAX
28 Vpp
SHORT STUB
(DIRECT COUPLED)
OR
NOTES: 1. Z 0= 70 TO 85 OHMS
ISOLATION
TRANSFORMER
ISOLATION
TRANSFORMER
7 Vpp
7 Vpp
SSRT MARK3
2. NOMINAL VOLTAGE
LEVELS SHOWN
BU-64703X3/4
5V
.01µF
10µF +
5V
.01µF
10µF +
FIGURE 17. SSRT MARK3 +5.0V INTERFACE TO MIL-STD-1553 BUS
27
Data Device Corporation
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H-06/11-0
+3.3V PULSE TRANSFORMERS
In selecting isolation transformers to be used with the SSRT
Mark3 , there is a limitation on the maximum amount of leakage
inductance. If this limit is exceeded, the transmitter rise and fall
times may increase, possibly causing the bus amplitude to fall
below the minimum level required by MIL-STD-1553. In addition,
an excessive leakage imbalance may result in a transformer
dynamic offset that exceeds 1553 specifications.
The maximum allowable leakage inductance is a function of the
coupling method. For Transformer Coupled applications, it is a
maximum of 5.0 µH. For Direct it is a maximum of 10.0 µH, and
is measured as follows:
The side of the transformer that connects to the SSRT Mark3 is
defined as the "primary" winding. If one side of the primary is
shorted to the primary center-tap, the inductance should be mea-
sured across the "secondary" (stub side) winding. This induc-
tance must be less than 5.0 µH (Transformer Coupled) and 10.0
µH (Direct Coupled). Similarly, if the other side of the primary is
shorted to the primary center-tap, the inductance measured
across the "secondary" (stub side) winding must also be less
than 5.0 µH (Transformer Coupled) and 10.0 µH (Direct Coupled).
The difference between these two measurements is the "differ-
ential" leakage inductance. This value must be less than 1.0 µH
(Transformer Coupled) and 2.0 µH (Direct Coupled).
Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
configurations with the required turns ratios of 1:3.75 direct
coupled, and 1:2.7 transformer coupled for BU-64703X8/9
Models and the required turns ratios of 1:2.65 direct coupled,
and 1:2.038 transformer coupled for BU-64703XC/D Models.
TABLE 4 provides a listing of these transformers with the corre-
sponding model numbers.
For further information, contact BTTC at 631-244-7393 or at
www.bttc-beta.com.
TABLE 4. BTTC TRANSFORMERS FOR USE WITH SSRT Mark3 BU-64703X8/9
MODEL
NUMBER
BTTC PART
NUMBER
# OF CHANNELS,
CONFIGURATION
COUPLING
RATIO
DESCRIPTION
COUPLING
RATIO
(1:X)
MOUNTING MAX
HEIGHT
WIDTH
(INCLUDING
LEADS)
LENGTH
(INCLUDING
LEADS)
BU-64703X8/9 MLP-2033 Single Direct (1:3.75) SMT 0.185" 0.4" 0.52"
BU-64703XC/D MLP-2030 Single Direct (1:2.65) SMT 0.185" 0.4" 0.52"
BU-64703X8/9 MLP-3033 Single Direct (1:3.75) Through Hole 0.185" 0.4" 0.4"
BU-64703X8/9 MLP-2233 Single Transformer (1:2.7) SMT 0.185" 0.4" 0.52"
BU-64703XC/D MLP-2230 Single Transformer (1:2.038) SMT 0.185" 0.4" 0.52"
BU-64703X8/9 MLP-3233 Single Transformer (1:2.7) Through Hole 0.185" 0.4" 0.4"
BU-64703X8/9 MLP-3333 Single Direct &
Transformer
(1:3.75) &
(1:2.7) Through Hole 0.185" 0.4" 0.4"
BU-64703XC/D DSS-3330 Dual (Side-by-Side) Direct &
Transformer
(1:2.65) &
(1:2.038) SMT 0.185" 0.52" 0.675"
BU-64703X8/9 DSS-2033 Dual (Side-by-Side) Direct (1:3.75) SMT 0.13" 0.72" 0.96"
BU-64703X8/9 DSS-2233 Dual (Side-by-Side) Transformer (1:2.7) SMT 0.13" 0.72" 0.96"
BU-64703X8/9 DSS-1003 Dual (Side-by-Side) Direct &
Transformer
(1:3.75) &
(1:2.7) SMT 0.165" 0.72" 0.96"
BU-64703X8/9 TSM-2033 Dual (Stacked) Direct (1:3.75) SMT 0.32" 0.4" 0.52"
BU-64703X8/9 TSM-2233 Dual (Stacked) Transformer (1:2.7) SMT 0.32" 0.4" 0.52"
BU-64703XC/D TSM-2230 Dual (Stacked) Transformer (1:2.038) SMT 0.32" 0.4" 0.52"
28
Data Device Corporation
www.ddc-web.com
BU-64703
H-06/11-0
+5.0V PULSE TRANSFORMERS
In selecting isolation transformers to be used with the SSRT
Mark3 +5.0V (BU-64703X3/4), there is a limitation on the maxi-
mum amount of leakage inductance. If this limit is exceeded, the
transmitter rise and fall times may increase, possibly causing the
bus amplitude to fall below the minimum level required by MIL-
STD-1553. In addition, an excessive leakage imbalance may
result in a transformer dynamic offset that exceeds 1553 specifi-
cations.
The maximum allowable leakage inductance is 6.0 µH, and
is measured as follows:
The side of the transformer that connects to the SSRT Mark3
+5.0V (BU-64703X3/4) is defined as the “primary” winding. If one
side of the primary is shorted to the primary center-tap, the
inductance should be measured across the “secondary” (stub
side) winding. This inductance must be less than 6.0 µH.
Similarly, if the other side of the primary is shorted to the pri-
mary center-tap, the inductance measured across the “second-
ary” (stub side) winding must also be less than 6.0 µH.
The difference between these two measurements is the
“differential” leakage inductance. This value must be less than
1.0 µH.
Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
configurations with the required turns ratios of 1:2.5 direct cou-
pled, and 1:1.79 transformer coupled. TABLE 4A provides a list-
ing of many of these transformers.
For further information, contact BTTC at 631-244-7393 or at
www.bttc-beta.com.
Notes:
1. All Transformers in the table above can be used with BU-6XXXXX3/6 (1553B transceivers).
2. Transformers identified with "#" in the table above are not recommended for use with the BU-6XXXXX4 (McAir-Compatable transceivers)
TABLE 4A. BTTC TRANSFORMERS FOR USE WITH SSRT MARK3 +5.0V (BU-64703X3/4)
BTTC PART
NUMBER
# OF CHANNELS,
CONFIGURATION
COUPLING RATIO
DESCRIPTION
COUPLING
RATIO (1:X) MOUNTING MAX HEIGHT
WIDTH
(INCLUDING
LEADS)
LENGTH
(INCLUDING
LEADS)
MLP-2005 Single Direct (1:2.5) SMT 0.185" 0.4" 0.52"
MLP-3005 Single Direct (1:2.5) Through Hole 0.185" 0.4" 0.4"
B-3230 (-30) # Single Direct (1:2.5) Through Hole 0.25" 0.35" 0.5"
MLP-2205 Single Transformer (1:1.79) SMT 0.185" 0.4" 0.52"
MLP-3205 Single Transformer (1:1.79) Through Hole 0.185" 0.4" 0.4"
B-3229 (-29) # Single Transformer (1:1.79) Through Hole 0.25" 0.35" 0.5"
HLP-6015 # Single Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.19" 0.63" 1.13"
B-3227 (-27) # Single Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.29" 0.63" 1.13"
MLP-3305 Single Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.185" 0.4" 0.4"
B-3226 (-26) # Single Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.25" 0.625" 0.625"
HLP-6014 # Single Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.19" 0.63" 1.13"
B-3231 (-31) # Single Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.29" 0.63" 1.13"
DSS-2005 Dual (Side-by-Side) Direct (1:2.5) SMT 0.13" 0.72" 0.96"
DSS-2205 Dual (Side-by-Side) Transformer (1:1.79) SMT 0.13" 0.72" 0.96"
DSS-1005 Dual (Side-by-Side) Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.165" 0.72" 0.96"
TSM-2005 Dual (Stacked) Direct (1:2.5) SMT 0.32" 0.4" 0.52"
TSM-2205 Dual (Stacked) Transformer (1:1.79) SMT 0.32" 0.4" 0.52"
TST-9117 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) SMT 0.335" 1.125" 1.125"
TST-9107 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) Through Hole 0.335" 0.625" 0.625"
TST-9127 # Dual (Stacked) Direct & Transformer (1:2.5) &
(1:1.79) Flat Pack 0.335" 0.625" 0.625"
29
Data Device Corporation
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H-06/11-0
1553 BUS CONNECTIONS
The isolation transformers should be placed as physically close
as possible to the respective TX/RX pins on the SSRT Mark3.
Also, the distance from the isolation transformers to any connec-
tors or cables leaving the board should be as short as possible.
In addition to limiting the voltage drops in the analog signal
traces when transmitting, reducing the hybrid-to-transformer and
transformer-to-connector spacing serves to minimize crosstalk
from other signals on the board.
The general practice in connecting the stub side of a trans-
former (or direct) coupled terminal to an external system con-
nector is to make use of 78 ohm twisted-pair shielded cable.
This minimizes impedance discontinuities. The decision of
whether to isolate or make connections between the center tap
of the isolation transformer's secondary, the stub shield, the bus
shield, and/or chassis ground must be made on a system basis,
as determined by an analysis of EMI/RFI and lightning consid-
erations.
In most systems, it is specified that the 1553 terminal's input
impedance must be measured at the system connector. This is
despite the fact that the MIL-STD-1553B requirement is for it to
be measured looking directly in from the bus side of the isolation
transformer.
The effect of a relatively long stub cable will be to reduce the
measured impedance (looking in from the bus). In order to keep
the impedance above the required level of 1000 ohms (for
transformer-coupled stubs), the length of any cable between the
1553 RT and the system connector should be minimized.
"SIMULATED BUS" (LAB BENCH)
INTERCONNECTIONS
For purposes of software development and system integration, it
is generally not necessary to integrate the required couplers,
terminators, etc., that comprise a complete MIL-STD-1553B bus.
In most instances, a simplified electrical configuration will suffice.
The three connection methods illustrated in FIGURE 18 allow the
SSRT Mark3 to be interfaced over a "simulated bus" to simula-
tion and test equipment. It is important to note that the termina-
tion resistors indicated are necessary in order to ensure reliable
communications between the SSRT Mark3 and the simulation/
test equipment.
FIGURE 18. "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS
SSRT
HYBRID
TEST/
SIMULATION
EQUIPMENT
STUB
COUPLING
STUB
COUPLING
ISOLATION
TRANSFORMER
78Ω
1.5W
(A)
TEST/
SIMULATION
EQUIPMENT
DIRECT
COUPLING
DIRECT
COUPLING
ISOLATION
TRANSFORMER
39Ω
0.5W
(B)
55Ω
1W
55Ω
1W
55Ω
55Ω
TEST/
SIMULATION
EQUIPMENT
STUB
COUPLING
DIRECT
COUPLING
ISOLATION
TRANSFORMER
39Ω
0.5W
(C)
55Ω
1W
55Ω
1W
20Ω
0.5W
20Ω
0.5W
(A) TRANSFORMER COUPLED TO TRANSFORMER COUPLED
(B) DIRECT COUPLED TO DIRECT COUPLED
(C) DIRECT COUPLED TO TRANSFORMER COUPLED
Mark3
SSRT
HYBRID
Mark3
SSRT
HYBRID
Mark3
30
Data Device Corporation
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H-06/11-0
SIMPLE SYSTEM INTERFACE
FIGURE 19 illustrates the capability of the SSRT Mark3 to inter-
face to a system with no host processor in burst mode. In this
example, only one set of external latches is needed to buffer the
data words written by the SSRT Mark3 to the external system. In
burst mode, all received data words are stored in the internal
FIFO until the last word is received. At this point, the SSRT
Mark3 will transfer the entire contents of the FIFO to the system
FIGURE 19. SSRT Mark3-TO-SIMPLE SYSTEM INTERFACE
(FOR BURST MODE)
D15-D0
Write
Address
Decoder
Read
Address
Decoder
LATCH
LATCH
TRI-STATE
BUFFER
TRI-STATE
BUFFER
EN
TRI-STATE
BUFFER
EN
EN
EN
L-BRO, T/R, SA4-0,
WC/CWC4-0
MEMWR
DISCRETE
DIGITAL
INPUTS
DISCRETE
DIGITAL
OUTPUTS
AUTO-
CONFIGURATION
(OPTIONAL)
RTACTIVE
DTACK
AUTO_CFG
MEMOE
BU-64703
SSRT Mark3
EN
Clock
Oscillator
CLK-IN
RTAD4-0, RTADP
MSTCLR
+3.3V
RT
ADDRESS
BUS A
DTGRT
+V
BUS B
+3.3V
if the message is validated. In this case, GBR will be driven low
for two clock cycles following the burst transfer cycle.
If the received message is not valid, the FIFO data will not be
transferred to the external system and GBR will remain high.
31
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BIT WORD
The SSRT Mark3 provides an internally formulated Built-In-Test
word (BIT word). This word is transmitted to the BC in response
If set, indicates that, for the previous message, the SSRT Mark3 was the receiving RT for an RT-to-RT
transfer and that the transmitting RT either did not respond or responded later than the SSRT Mark3
RT-to-RT timeout time. The SSRT Mark3's RT-to-RT response timeout time is defined as the time from
the mid-bit crossing of the parity bit of the transmit Command Word to the mid-sync crossing of the
transmitting RT status word. The value of the SSRT Mark3's RT-to-RT response timeout time is in the
range from 17.5 to 19.5 µs.
Indicates that a received command word is not defined in accordance with MIL-STD-1553B. This
includes the following undefined Command Words: (1) The Command Word is a non-mode code,
broadcast, transmit command; (2) a message with a T/R bit of "0", a subaddress/mode field of 00000
or 11111, and a mode code field with a value between 00000 and 01111; (3) a mode code command
that is not permitted to be broadcast (e.g., Transmit Status) is sent to the broadcast address 11111.
Indicates that the SSRT Mark3 received one or more words containing one or more of the following
error types: sync field error, Manchester encoding error, parity error, and/or bit count error.
This bit is set if the SSRT Mark3 is the receiving RT for an RT-to-RT transfer and one or more of the
following errors occurs: (1) If the transmitting RT responds with a response time of less than 4 µs, per
MIL-STD-1553B (mid-parity bit to mid-sync); i.e., less than 2 µs dead time; and/or (2) There is an
incorrect sync type or format error (encoding, bit count, and/or parity error) in the transmitting RT
Status Word; and/or (3) The RT address field of the transmitting RT Status Word does not match the
RT address in the transmit Command Word.
If the SSRT Mark3 is the receiving RT for an RT-to-RT transfer, if this bit is set, it indicates one or
more of the following error conditions in the transmit Command Word: (1) T/R bit = logic "0"; (2) sub-
address = 00000 or 11111; (3) same RT Address field as the receive Command Word.
If set, indicates that the SSRT Mark3 detected a Command sync in a received Data Word.
Set to logic "1" if the previous message had a low word count error.
RT-RT TRANSFER
NO RESPONSE
TIMEOUT
COMMAND WORD
CONTENTS ERROR
INVALID WORD
MANCHESTER/PARITY
ERROR RECEIVED
RT-RT TRANSFER RESPONSE
ERROR (no gap, data, sync,
address mismatch)
RT-RT TRANSFER -
T/R ERROR ON
SECOND COMMAND
OR
INVALID ADDRESS
INCORRECT SYNC TYPE
RECEIVED
LOW WORD COUNT
2
0 (LSB)
4
3
1
5
6
Set to logic "1" if the previous message had a high word count error.
HIGH WORD COUNT7
Set to logic "1" to denote that the SSRT Mark3 has failed its off-line protocol self-test. This bit will be
logic "0" if the self-test passed or had not been performed.
BIT TEST FAIL8
Set to logic "1" if the SSRT Mark3's Terminal flag RT status bit has been disabled by an Inhibit termi-
nal flag mode code command. Will revert to logic "0" if an Override inhibit terminal flag mode code
command is received.
TERMINAL FLAG INHIBITED9
If this bit is set, it indicates that the subsystem had failed to respond with the DMA handshake input
DTGRT asserted within 10 µs after the SSRT Mark3 has asserted DTREQ.
HANDSHAKE FAILURE12
A loopback test is performed on the transmitted portion of every non-broadcast message. A validity
check is performed on the received version of every word transmitted by the SSRT Mark3. In addition,
a bit-by-bit comparison is performed on the last word transmitted by the RT for each message. If
either the received version of the last word does not match the transmitted version and/or the
received version of any transmitted word is determined to be invalid (sync, encoding, bit count, parity),
or a failsafe timeout occurs on the respective channel, the LOOP TEST FAILURE bit for the respective
bus channel will be set.
CH. B LOOP TEST FAILURE
CH. A LOOP TEST FAILURE
14
13
Set if the SSRT Mark3's failsafe timer detected a fault condition. The transmitter timeout circuit will
automatically shut down the CH. A or CH. B transmitter if it transmits for longer than 660.5 µs.
TRANSMITTER TIMEOUT15
(MSB)
TABLE 5. INTERNAL BUILT-IN-TEST (BIT) WORD DEFINITION
DESCRIPTIONFUNCTIONBIT
If either of these bits are logic "1", this indicates that the respective 1553 transmitter has been shut
down by means of a Transmitter shutdown mode command.
TRANSMITTER SHUTDOWN B
TRANSMITTER SHUTDOWN A
11
10
Note:
Bits 15 through 9 are cleared only following a RESET input or receipt of a Reset Remote Terminal mode command. Bits 8 through 0 are updated
as a result of every message processed.
to a Transmit BIT Word Mode Code Command. The BIT word bit
functions and descriptions are provided in TABLE 5.
32
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MODE CODES
The SSRT Mark3 fully implements all 13 of the dual redundant
MIL-STD-1553B mode codes. Four of the mode codes, Transmit
vector word, Synchronize (with data), Selected transmitter shut-
down, and Override transmitter shutdown, involve data transfers
with the subsystem. For the Transmit last command mode com-
mand, the data word transmitted is from the SSRT Mark3's last
command internal register. For the Transmit BIT word mode com-
mand, the SSRT Mark3's internally formulated BIT Word is trans-
No
Yes
Transmit BIT Word
Inhibit Terminal Flag
From Internal Register
No
10011
00110
1
1
No
Yes
Transmit Last Command
Override Transmitter Shutdown
From Internal Register
No
10010
00101
1
1
TBD
No
Yes
RESERVED
Transmit Vector Word
Initiate Self Test
From Subsystem
From Subsystem
No
10110-11111
10000
00011
1
1
1
Yes
TBD
No
Override Selected Transmitter Shutdown
(see Note)
RESERVED
Transmit Status Word
To Subsystem
No
No
10101
01001-01111
00010
0
1
1
Yes
Yes
Yes
Selected Transmitter Shutdown (see Note)
Reset Remote Terminal
Synchronize
To Subsystem
No
No
10100
01000
00001
0
1
1
Yes
No
Override Inhibit Terminal Flag
Dynamic Bus Control
No
No
00111
00000
1
1
NoUndefined No00000-011110
TABLE 6. MODE CODE SUMMARY
BROADCAST
ALLOWED
FUNCTION DATA WORDMODE CODET/R BIT
TBD
Yes
Yes
RESERVED
Synchronize with Data
Transmitter Shutdown
To Subsystem
To Subsystem
No
10110-11111
10001
00100
0
0
1
Note:
For the Selected transmitter shutdown and Override transmitter shutdown mode commands, the SSRT Mark3 responds with Clear Status but no
action is taken.
mitted. TABLE 6 provides a summary of the 1553B mode codes
supported by the SSRT Mark3.
SUMMARY OF RESPONSES TO MODE CODE
MESSAGES
The SSRT Mark3's responses to mode codes, including respons-
es to various error conditions, are summarized in TABLE 6.
33
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DETAILED MODE CODES FUNCTIONAL DESCRIPTION
The applicable Mode Codes for the SSRT Mark3 are described below:
DYNAMIC BUS CONTROL ( T/R = 1; 00000)
MESSAGE SEQUENCE = DBC + STATUS
The SSRT Mark3 responds with Status showing non-acceptance of the mode code command.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word),
Command Word Contents Error (BIT Word).
5. Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word),
Command Word Contents Error (BIT Word).
SYNCHRONIZE WITHOUT DATA WORD ( T/R = 1; 00001)
MESSAGE SEQUENCE = SYNC + STATUS
The SSRT Mark3 responds with Status.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word),
Command Word Contents Error (BIT Word).
TRANSMIT STATUS WORD ( T/R = 1; 00010)
MESSAGE SEQUENCE = TRANSMIT STATUS + STATUS
The Status register is not updated before it is transmitted and contains the resulting status from the previous command (assuming that it was
not a Transmit status or Transmit last command mode command).
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word)
3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Received bits (Status Word),
Command Word Contents Error (BIT Word).
5. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word),
Command Contents Error (BIT Word).
INITIATE SELF-TEST ( T/R = 1; 00011)
MESSAGE SEQUENCE = SELF TEST + STATUS
If the command was non-broadcast, the SSRT Mark3 responds with Status. If the command was either non-broadcast or broadcast, the SSRT
Mark3 will go offline and perform its internal off-line protocol self-test. The self-test exercises the SSRT Mark3's encoder and decoders, regis-
ters, transmitter watchdog timer, and protocol logic. This test is completed in approximately 32,000 clock cycles. That is, about 1.6 ms with a 20
MHz clock, 2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz.
While the SSRT Mark3 is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus.
The bus controller may determine the result of the self-test by means of a Transmit BIT word mode command. If the self-test passes, bit 8 of
the SSRT Mark3's BIT word (BIT Test Fail) will be logic "0"; if the self-test fails, this bit will be logic "1". In addition, if self-test fails, the terminal
flag status word bit will be set to logic “1” in response to the next non-broadcast message.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),
Command Word Contents Error (BIT Word).
5. Loopback Test Failure. Set Terminal Flag bit in internal Status register (Status Word for next non-broadcast command),
Current Channel (A or B) Loop Test Failure and CH A/B Loop Test Failure (BIT Word), assert RTFAIL output.
34
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OVERRIDE INHIBIT TERMINAL FLAG BIT ( T/R = 1; 00111)
MESSAGE SEQUENCE = OVERRIDE INHIBIT TERMINAL FLAG + STATUS
The SSRT Mark3 responds with Status and re-enables the Terminal Flag bit in its internal Status register. If the command was a broadcast,
the Broadcast Command Received bit is set and status transmission is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),
Command Word Contents Error (BIT Word).
INHIBIT TERMINAL FLAG BIT ( T/R = 1; 00110)
MESSAGE SEQUENCE = INHIBIT TERMINAL FLAG + STATUS
The SSRT Mark3 responds with Status and inhibits further setting of the Terminal Flag bit in its internal Status Word register. Once the
Terminal Flag has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT mode code commands, or by
Reset. If the command was broadcast, the Broadcast Received bit is set, the state of the Terminal Flag bit in the internal Status Word register
remains unchanged and Status transmission is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),
Command Word Contents Error (BIT Word).
OVERRIDE TRANSMITTER SHUTDOWN ( T/R = 1; 00101)
MESSAGE SEQUENCE = OVERRIDE SHUTDOWN + STATUS
This command is only used with dual redundant bus systems. The SSRT Mark3 responds with Status. At the end of the Status transmission,
the SSRT Mark3 reactivates the transmitter of the alternate redundant bus. If the command was broadcast, the Broadcast Command Received
Status Word bit is set and status transmission is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),
Command Word Contents Error (BIT Word).
TRANSMITTER SHUTDOWN ( T/R = 1; 00100)
MESSAGE SEQUENCE =SHUTDOWN + STATUS
This command is only used with dual redundant bus systems. The SSRT Mark3 responds with Status. Following the Status transmission, the
SSRT Mark3 inhibits any further transmission from the alternate redundant channel. Once shutdown, the transmitter can only be reactivated by
an Override Transmitter Shutdown or Reset RT mode command, or Hardware Reset (MSTRCLR input). Note that the receivers on both chan-
nels are always active, even when the transmitters are inhibited.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),
Command Word Contents Error (BIT Word).
35
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TRANSMIT VECTOR WORD ( T/R = 1; 10000)
MESSAGE SEQUENCE = TRANSMIT VECTOR WORD + STATUS VECTOR WORD
The SSRT Mark3 transmits a Status Word followed by a vector word. The vector word is read from the external subsystem.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word).
4. T/R bit Set to Zero plus one Data Word. The SSRT Mark3 will respond with Status
5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Command Received bits
(Status Word), and Low Word Count (BIT word).
6. Zero T/R bit and Broadcast Address, plus one Data Word. No Status response. Set Broadcast Command Received bits (Status Word)
7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word),
Command Word Contents Error (BIT word).
SYNCHRONIZE WITH DATA WORD ( T/R = 0; 10001)
MESSAGE SEQUENCE = SYNCHRONIZE COMMAND/DATA WORD + STATUS
The SSRT Mark3 will write the received 16 bit data word to the external subsystem.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Correct Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word)
3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), High Word Count (BIT word).
4. Command T/R bit set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and
High Word Count (BIT Word).
5. Command T/R bit set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is
read
from the subsystem (or single-word data block for subaddress 0000 or 1111).
6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received
bits (Status Word); Set Command Word Contents Error (BIT word).
RESERVED MODE CODES ( T/R = 1; 01001 - 01111)
MESSAGE SEQUENCE = RESERVED MODE COMMAND + STATUS
The SSRT Mark3 responds with status. If the command has been illegalized by means of the illegalization table, the Message Error Status
Word bit will be set.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),
Command Word Contents Error (BIT Word).
RESET REMOTE TERMINAL ( T/R = 1; 01000)
MESSAGE SEQUENCE = RESET REMOTE TERMINAL + STATUS
The SSRT Mark3 responds with Status and internally resets. The Message Error and Broadcast Command Received bits of the internal Status
register are reset to 0. The internal BIT Word Register is reset to 0. If either of the 1553 transmitters has been shut down, the shutdown condi-
tion is overridden. If the Terminal Flag bit has been inhibited, the inhibit is overridden.
If the command is received as a broadcast, the Broadcast Command Received bit is set and the Status Word is suppressed. Also, if the com-
mand is received as a broadcast and the Terminal Flag bit had been set as a result of the Loopback test of the previous message, the Terminal
Flag bit is not reset to zero.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Set Message Error bit (Status Word), Command Word Contents Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status word),
Command Word Contents Error (BIT Word).
36
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SELECTED TRANSMITTER SHUTDOWN ( T/R = 0; 10100)
MESSAGE SEQUENCE = TRANSMITTER SHUTDOWN/DATA + STATUS
The Data Word received is transferred to the subsystem and Status is transmitted. No other action is taken by the SSRT Mark3. No transmitters
are shut down as a result of this mode command. This command is intended for use with RTs with more than one dual redundant channel. If the
command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count Bit (BIT Word).
No status response. Bits Set: message error (SW), High Word Count, Illegal Mode Code (BIT Word)
3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count Bit
(BIT Word).
4. Command T/R bit Set to One followed by one Data Word. No Status response. Set Message Error bit (Status Word), and High Word
Count (BIT Word).
5. Command T/R bit Set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is read
from the subsystem.
6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits
(Status Word), and Command Contents Error (BIT Word).
TRANSMIT BIT WORD ( T/R = 1; 10011)
MESSAGE SEQUENCE = TRANSMIT BIT WORD + STATUS/BIT WORD
The SSRT Mark3 responds with Status followed by the Built-in Test (BIT) word.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word).
3. T/R bit Set to Zero, no Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word).
4. T/R bit Set to Zero, plus one Data Word. The SSRT Mark3 will respond with Status. The Data Word is transferred to internal registers.
5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word),
Low Word Count Error (BIT Word).
6. Zero T/R bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word). The Data Word is
transferred to internal registers.
7. Broadcast Address. No Status response. Set Message Error and Broadcast Command received bits (Status Word), Command Word
contents Error (BIT Word).
TRANSMIT LAST COMMAND ( T/R = 1; 10010)
MESSAGE SEQUENCE = TRANSMIT LAST COMMAND + STATUS/LAST COMMAND
The Status register is not updated before transmission. It contains the Status from the previous command. The Data Word transmitted con-
tains the previous valid command (providing it was not another TRANSMIT LAST COMMAND or TRANSMIT STATUS WORD mode command).
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count Error (Bit Word).
3. T/R bit Set to Zero, no Data Word. No Status response. Set Message Error bit (Status Word), Low Word Count (BIT Word).
4. T/R bit Set to Zero, plus one Data Word. The SSRT Mark3 will respond with Status. The Data Word is transferred to the internal register.
5. Zero T/R bit and Broadcast Address, no Data Word. No Status response. Set Message Error and Broadcast Received bits (Status Word),
Low Word Count Error(BIT Word).
6. Zero T/R bit and Broadcast Address, one Data Word. No Status response. Set Broadcast Received Bit (status word). The Data Word is
transferred to the internal register.
7. Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits (Status Word), Command Word
Contents Error (BIT Word).
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RESERVED MODE CODES ( T/R = 1; 11111)
MESSAGE SEQUENCE (when T/R = 1) = RESERVED MODE CODE STATUS/DATA
(when T/R = 0) = RESERVED MODE CODE DATA + STATUS
For a RESERVED receive Command, the SSRT Mark3 stores the Data Word to the subsystem. If the command was a broadcast, the
Broadcast Command Received bit is set and Status transmission is suppressed. For a RESERVED transmit Command Word, the SSRT Mark3
responds with Status plus a single Data Word. The Data Word is read from the subsystem.
ERROR CONDITIONS (T/R = 1)
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No Status response. Set Message Error bit (Status Word), High Word Count (BIT Word).
3. Broadcast Command. No Status response. Set Message Error bit (status word), and Command Word Contents Error (BIT Word).
ERROR CONDITIONS (T/R = 0)
1. Invalid Command. No response, command ignored.
2. Command not followed by Contiguous Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count
(BIT Word).
3. Command followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count
(BIT word).
OVERRIDE SELECTED TRANSMITTER SHUTDOWN ( T/R = 0; 10101)
MESSAGE SEQUENCE = TRANSMITTER SHUTDOWN/DATA + STATUS
The Data Word received is transferred to the subsystem. No transmitters that have been previously shut down are reactivated as a result of this
command. No other action is taken by the SSRT Mark3. This command is intended for use with RTs with more than one dual redundant channel.
If the command was a broadcast, the Broadcast Command Received bit is set and Status transmission is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Not Followed by Data Word. No Status response. Set Message Error bit (Status Word), and Low Word Count (BIT Word).
3. Command Followed by too many Data Words. No Status response. Set Message Error bit (Status Word), and High Word Count bit
(BIT Word).
4. Command T/R bit Set to One followed by Data Word. No Status response. Set Message Error bit (Status Word), and High Word Count
(BIT Word).
5. Command T/R bit Set to One not followed by Data Word. The SSRT Mark3 replies with Status plus one Data Word. The Data Word is read
from the subsystem.
6. Command T/R bit Set to One and Broadcast Address. No Status response. Set Message Error and Broadcast Command Received bits
(Status Word), and Command Contents Error (BIT Word).
38
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+3.3V_Xcvr
PINSIGNAL NAME
10 Transceiver power.
+3.3V_Logic
30
Logic power.
51
69
Gnd_Xcvr 22 Transceiver Ground.
79
Gnd_Logic
14
Logic Ground.
31
50
70
TABLE 7. BU-64703X8/9 POWER AND GROUND
77
DESCRIPTION
SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
Analog transmit/receive input/output signals. Connect directly to 1553 isolation transformers.
17
TX/RX-B (I/O
15TX/RX-B (I/O
5
TX/RX-A (I/O
3TX/RX-A (I/O)
+5.0V_Xcvr
PIN
SIGNAL NAME
10 Transceiver power.
+3.3V_Logic
30
Logic power.
51
69
Gnd_Xcvr 22 Transceiver Ground.
79
Gnd_Logic
14
Logic Ground.
31
50
70
TABLE 7A. BU-64703X3/4 POWER AND GROUND
77
DESCRIPTION
PIN
SIGNAL NAME
TABLE 8. MIL-STD-1553 ISOLATION TRANSFORMER INTERFACE
DESCRIPTION
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16-bit bi-directional data bus.
When the SSRT Mark3 is writing data to the external system, these signals are active outputs. At all other times, these
signals are high impedance inputs.
46
D10 (I/O)
D00 (I/O) (LSB)
42D01 (I/O)
47D02 (I/O)
48D03 (I/O)
D04 (I/O) 43
49D05 (I/O)
41D06 (I/O)
53D07 (I/O)
52D08 (I/O)
57
60
D09 (I/O)
58D11 (I/O)
55D12 (I/O)
54D13 (I/O)
56D14 (I/O)
59D15 (I/O) (MSB)
PIN
SIGNAL NAME
TABLE 9. DATA BUS (16)
DESCRIPTION
1L_BRO (O) Latched Broadcast. This two-state output signal is latched following receipt of a new command word. For a broadcast
command, this signal outputs a value of logic "1". For a non-broadcast message, this signal will output logic "0".
2T / R Transmit/Receive. This two-state output signal is latched following receipt of a new command word. For a transmit mes-
sage, this signal will output a value of logic "1". For a receive message, this signal will output logic "0".
75
SA2 (O)
Subaddress. These five two-state output signals are latched following receipt of a new command word. They provide
the subaddress field of the received command word.
PIN
78
WC / MC /
CWC2 (O)
Word Count/Mode Code/Current Word Count. Following receipt of a new command word, these five two-state output
signals provide the contents of the command word's Word Count/Mode Code field.
For a non-mode code receive message, the contents of WC/CWC are updated and incremented to reflect the value of
the current data word being transferred to the system (in non-burst mode), or to the internal FIFO (in burst mode).
CWC increments from 0 to the value of the Word Count field - 1 during the message.
At the end of a non-mode code receive message in burst mode, the contents of CWC will then increment from 0 to the
value of the word count field -1, as each word is transferred from the internal FIFO to the external system over D15-
D0. In burst mode, it takes three clock cycles to transfer each word to the external system.
For a non-mode code transmit command, the value of CWC starts from 0 and increments to the value of Word Count -
1, as each word is read from the external system and transferred to the SSRT Mark3.
For a mode code command, the WC/CWC outputs the command word mode code field, which remains latched through
the end of the message (until receipt of a subsequent command word).
TABLE 10. COMMAND / ADDRESS BUS
SIGNAL
SA4 (O)
SA3 (O)
SA1 (O) 27
12
7
SA0 (O) 74
WC / MC /
CWC4 (O) (MSB)
WC / MC /
CWC3 (O)
WC / MC /
CWC1 (O)
33
19
DESCRIPTION
13
WC / MC /
CWC0 (O) (LSB)
18
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SIGNAL
TABLE 11. DMA HANDSHAKE AND TRANSFER CONTROL SIGNALS
PIN
DTACK (O)
MEMWR (O)
MEMOE (O)
HS_FAIL (O)
DTGRT (I)
35
28
20
63
72
DESCRIPTION
Data Transfer Acknowledge. Active low output signal used to indicate the SSRT Mark3’s acceptance of the system data
bus (D15-D0), in response to a data transfer grant (DTGRT). The SSRT Mark3's data transfers over D15-D0 will be
framed by the time that DTACK is asserted low.
If AUTO_CFG is strapped to logic "0", there will be a DTREQ/DTGRT handshake cycle after the rising edge of
MSTCLR, following power turn-on. After DTGRT is sampled low, DTACK and RTACTIVE will then be asserted low to
enable configuration data to be read from an external tri-state buffer.
For transmit messages, or receive messages in non-burst mode, or for receive messages to subaddress 30 assuming
that Subaddress 30 Autowrap is disabled, DTACK will be asserted low to indicate the transfer of individual words
between the external system and the SSRT Mark3.
For receive messages in burst mode assuming a valid received message, DTACK will be asserted low after the DTREQ-
to-DTGRT handshake following the receipt of the last received data word. It will remain low for the duration of the DMA
burst write transfer from the SSRT Mark3 to the external system. The total time for a burst write transfer is three clock
cycles times the number of data words.
Memory Write. Active low two-state output signal (one clock cycle wide) asserted low during SSRT Mark3 write cycles.
Used to transfer data from the SSRT Mark3 to the external system. The external system may latch data on either the
falling or rising edge of MEMWR.
Memory Output Enable. MEMOE two-state output signal is used to enable data inputs from the external system to be
enabled on to D15-D0. MEMOE pulses low for three clock cycles for each data word read from the external system. The
SSRT Mark3 latches the data one clock cycle prior to the rising edge of MEMOE.
Handshake Fail. If this signal is asserted low, this indicates a handshake timeout condition. That is, the system did not
respond with a DTGRT in time, following the SSRT Mark3's assertion of DTREQ.
Data Transfer Grant. Input from the external subsystem that must be asserted low in response to the SSRT Mark3
asserting DTREQ low in order to enable the SSRT Mark3 to read data from or write data to the external subsystem.
The maximum allowable time from DTREQ to DTGRT is 10 µs.
If the SSRT Mark3's DMA handshake isn't required, DTGRT may be hardwired to logic "0".
Data Transfer Request. Active low level output signal used to request use of the external system data bus (D15-D0).DTREQ (O) 29
DESCRIPTION
Remote Terminal Address Error. Output Signal that reflects the parity combination of the RTAD[4:0] inputs and RTADP
input. A high level indicates odd (correct) parity. A low level indicates even (incorrect) parity.
Note, if RT_AD_ERR is low, then the SSRT Mark3 will not recognize any valid Command Word received to its own RT
address.
RT_AD_ERR (O) 6
RT Address inputs.
RTAD0 (I) (LSB)
RTAD1 (I)
RTAD2 (I)
RTAD3 (I)
RTAD4 (I) (MSB)
38
45
24
39
40
SIGNAL
TABLE 12. RT ADDRESS
Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the
RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD4-
RTAD0 and RTADP.
RTADP (I) 44
PIN
RT Address Latch. If RT_AD_LAT is connected to logic "0", then the SSRT Mark3 is configured to accept a hardwired
RT address from RTAD4-RTAD0 and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP
will be latched internally by the SSRT Mark3 on the rising edge of RT_AD_LAT.
RT_AD_LAT (I) 36
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DESCRIPTION
Busy. If this input is asserted low, the Busy bit will be set to logic "1" in the SSRT Mark3's Status Word. If the Busy bit in
the status word is logic "1", the SSRT Mark3 will not transmit any data words, except for a Transmit last command or
Transmit BIT word mode command. For a receive command, if the SSRT Mark3 is Busy, it will still transfer data words to
the external system (although these transfers may be blocked by means of external logic).
Subsystem Flag. If this input is asserted low, the Subsystem Flag bit will be set in the SSRT Mark3's Status Word.
BUSY (I)
SSFLAG (I)
61
37
SIGNAL
TABLE 13. RT STATUS WORD INPUTS
Illegal. Input to the SSRT Mark3 that is sampled after the Command Word transfer. A logic "0" will cause the Message
Error bit in the status response to be set (logic "1"), while a logic "1" on this input will have no effect on the Message
Error bit.
ILLEGAL (I) 68
PIN
Service Request. When this input is logic "0", the Service request bit in the SSRT Mark3's status word will be logic "1".
When this input is logic "1", the Service request bit in the SSRT Mark3's status word will be logic "0".
SRV_RQST (I) 66
DESCRIPTION
Remote Terminal Fail. This two-state output signal will be asserted low following a failure of the built-in self-test per-
formed following power turn-on or as the result of the receipt of an Initiate self-test mode command. The built-in off-line
self-test includes tests of the Manchester encoder and decoders, transmitter failsafe timer, and RT protocol logic.
In addition, RTFAIL will be asserted low following a failure of the on-line loop test for any non-broadcast message. The
on-line loop test verifies the validity of the received version of all transmitted words (sync, Manchester encoding, bit
count, parity), and includes a bit-by-bit comparison and verification of the last transmitted word.
If asserted to logic "0", RTFAIL will clear to logic "1" when the SSRT Mark3 begins transmission of its status word in
response to a subsequent valid non-broadcast message.
Message Error. Active low level two-state output signal used to flag to the external system that there was a message
error on the 1553 bus communication (word, gap, or word count error) for a particular message. This output goes low
upon detecting the error and is reset following the receipt of the next valid command word (to the RT) from the 1553 bus,
or if MSTCLR is asserted low. If this output goes low, all further servicing of the current message is aborted.
Good Block Received. Low level two-state output pulse (2 clock cycles wide) that is used to indicate to the external system
that a valid, legal, non-mode receive command with the correct number of valid data words has been received and trans-
ferred to the external system.
For non-burst mode, this pulse will occur after the last data word is transferred. Assuming a DTREQ-to-DTGRT time of 0,
this will be approximately 4 µs following the mid-parity bit crossing of the last received data word.
For burst mode, the GBR pulse will begin synchronous with the rising edge of DTACK at the end of the burst write transfer.
RTFAIL (O)
MSG_ERR (O)
GBR (O)
64
34
67
SIGNAL
TABLE 14. RT ACTIVITY AND MESSAGE STATUS INDICATORS
RT Active. This signal will be low (logic "0") following power turn-on, and when the SSRT Mark3 is reading its Auto-
configure word or is performing its internal self-test. After the self-test passes, or if the Auto-configure option is not used,
or if Auto-configure is used but bit 5 of the Auto-configure word is logic "1" (meaning for the RT to always go online),
RTACTIVE will then transition to logic "1". When this occurs, the SSRT Mark3 will begin processing messages over the
1553 bus.
If Auto-configure is enabled, and bit 5 of the Auto-configure word is logic "0" and the self-test fails, then RTACTIVE will
remain at logic "0". In this case, the SSRT Mark3 will remain offline and not process any 1553 messages.
A failed self test will cause RTFAIL_L to be asserted low (logic "0").
If the auto-configure option is used, the external system should enable the configuration bits on D5-D0 when RTACTIVE
and DTACK are both outputting logic "0".
RTACTIVE (O) 62
PIN
In-command. This two-state output is asserted low whenever a message is being processed by the SSRT Mark3.INCMD 32
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DESCRIPTION
Transmitter inhibit input for the MIL-STD-1553 transmitters. For normal operation, this input should be connected to logic
"0". To force a shutdown of the Channel A and Channel B transmitters, a value of logic "1" should be applied to this
input.
TX_INH (I) 65
Broadcast Enable. If this input is logic "1", the SSRT Mark3 will recognize RT address 31 as the broadcast address. If
this input is logic "0", the SSRT Mark3 will not recognize RT address 31 as the broadcast address; however, in this con-
figuration, RT address 31 may be used as a standard RT address.
BRO_ENA (I) 71
Auto-configure input. If connected to logic "1", then the auto-configure option is disabled, and the six configuration
parameters revert to their default values as listed in TABLE 2. Note that the default condition for each configuration
parameter is enabled (for the MIL-STD-1553A/B protocol selection, -1553B is the default).
If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 during a DMA
read data transfer, when RTACTIVE and DTACK are logic "0", following MSTCLR transitioning from logic "0" to logic "1".
Each of the configuration parameters is enabled if the SSRT Mark3 reads a value of logic "1" for the respective data bit.
AUTO_CFG (I) 76
Master Clear. Negative true Reset input, asserted low following power turn-on. When coming out of a “reset” condition,
note that the risetime of MSTCLR must be less than 10 µs.
MSTCLR (I) 25
SIGNAL
TABLE 15. CONTROL INPUTS
PIN
DESCRIPTION
SIGNAL
TABLE 16. CLOCK INPUT
Clock Input. The clock frequency must be designated by means of the CLK_SEL_1 and CLK_SEL_0 inputs.
CLK_IN (I) 26
PIN
These two inputs are used to designate the SSRT Mark3's clock frequency, as follows:
CLK_SEL_1 CLK_SEL_0 Clock Frequency
0 0 10 MHz
0 1 20 MHz
1 0 12 MHz
1 1 16 MHz
CLK_SEL_1 (I) 73
CLK_SEL_0 (I) 80
DESCRIPTIONSIGNAL
TABLE 17. FACTORY TEST (NO USER CONNECTIONS)
NC 4
PIN
For factory test only. Do not connect for normal operation.
8
9
16
11
21
23
43
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72
71
DTGRT
BRO_ENA
70 GROUND_LOGIC
69 +3.3V_LOGIC
68
67
ILLEGAL
GBR
66 SRV_RQST
65 TX_INH
64
63
RT_FAIL
HS_FAIL
62 RTACTIVE
61 BUSY
60
59
58
D10
D15
D11
57 D9
56 D14
55 D12
54
53
52
D13
D7
D8
51 +3.3V_LOGIC
50 GROUND_LOGIC
49 D5
48 D3
PIN
47 D2
46
45
44
D0
RTAD1
RTADP
43 D4
42 D1
41 D6
FUNCTION
L_BRO
1
T/R
TX/RX_A
PIN
N/C
2
FUNCTIONPIN FUNCTIONPIN FUNCTION
3
4
TX/RX_A
5
RT_AD_ERR
6
SA37
N/C
N/C
+3.3 V_XCVR
8
9
10
N/C11
SA212
WC3
13
GROUND_LOGIC14
TX/RX_B
15
N/C
TX/RX_B
WC0
16
17
18
WC2
19
MEMOE
20
N/C
21
GROUND_XCVR
N/C
RTAD2
22
23
24
MSTCLR
25
CLOCK_IN26
SA1
MEMWR
27
28
DTREQ
29
+3.3V_LOGIC
30
GROUND_LOGIC
INCMD
31
32
WC133
MSG_ERR
34
DTACK
RT_AD_LAT
35
36
SSFLAG
37
RTAD038
RTAD339
RTAD4
40
CLK_SEL_173
SA074
SA475
AUTO_CFG
76
GROUND_LOGIC77
WC4
78
GROUND_XCVR
79
CLK_SEL_0
80
PIN FUNCTIONS
TABLE 18. BU-64703X8/9 “GULL WING” AND FLAT PACKAGE PIN FUNCTIONS
72
71
DTGRT
BRO_ENA
70 GROUND_LOGIC
69 +3.3V_LOGIC
68
67
ILLEGAL
GBR
66 SRV_RQST
65 TX_INH
64
63
RT_FAIL
HS_FAIL
62 RTACTIVE
61 BUSY
60
59
58
D10
D15
D11
57 D9
56 D14
55 D12
54
53
52
D13
D7
D8
51 +3.3V_LOGIC
50 GROUND_LOGIC
49 D5
48 D3
PIN
47 D2
46
45
44
D0
RTAD1
RTADP
43 D4
42 D1
41 D6
FUNCTION
L_BRO
1
T/R
TX/RX_A
PIN
N/C
2
FUNCTIONPIN FUNCTIONPIN FUNCTION
3
4
TX/RX_A
5
RT_AD_ERR
6
SA37
N/C
N/C
+5.0 V_XCVR
8
9
10
N/C
11
SA212
WC313
GROUND_LOGIC14
TX/RX_B15
N/C
TX/RX_B
WC0
16
17
18
WC219
MEMOE
20
N/C
21
GROUND_XCVR
N/C
RTAD2
22
23
24
MSTCLR
25
CLOCK_IN
26
SA1
MEMWR
27
28
DTREQ
29
+3.3V_LOGIC30
GROUND_LOGIC
INCMD
31
32
WC133
MSG_ERR
34
DTACK
RT_AD_LAT
35
36
SSFLAG
37
RTAD038
RTAD339
RTAD440
CLK_SEL_173
SA074
SA475
AUTO_CFG
76
GROUND_LOGIC77
WC478
GROUND_XCVR79
CLK_SEL_080
TABLE 18A. BU-64703X3/4 “GULL WING” AND FLAT PACKAGE PIN FUNCTIONS
44
Data Device Corporation
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BU-64703
H-06/11-0
2
1
SSRT MARK3
FUNCTION
P1
PIN #
80-PIN DEVICE
PIN #
T/R
TABLE 19. BU-64703E8 SSRT-MARK3 (+3.3V) & TRANSFORMER EVALUATION BOARD PINOUTS
MADE FROM 80-PIN, SSRT MARK3 BU-64703G8
SSRT MARK3
FUNCTION
P2
PIN #
80-PIN DEVICE
PIN #
-
1-
12 BRO -
2-
6
3RT_AD_ERR -3 STUB_TX/RX_B
74 SA3 -4 STUB_TX/RX_B
18
5WC/MC/CWC0 22,31,50,70,79
5GND
19
7WC/MC/CWC2 -
7STUB_TX/RX_B
136 WC/MC/CWC3 22,31,50,70,79 6 GND
128 SA2 -8 STUB_TX/RX_B
80
9CLK_SEL_0 -
9-
22,31,50,70,79
10 GND -10 -
22,31,50,70,79
11 GND -
11 +3.3V_XFMR_CT
22,31,50,70,79
12 GND -
12 +3.3V_XFMR_CT
7713 GND_LOGIC 1013 +3.3V_XCVR
78
14 WC/MC/CWC4 10
14 +3.3V_XCVR
76
16 AUTO_CFG -
16 -
7515 SA4 -15 -
7317 CLK_SEL_1 -17 STUB_TX/RX_A
74
18 SA0 -
18 STUB_TX/RX_A
71
19 BRO_ENA 22,31,50,70,79
19 GND
72
20 DTGRT 22,31,50,70,79
20 GND
30,51,69
21 +3.3V_Logic -
21 STUB_TX/RX_A
30,51,69
22 +3.3V_Logic -
22 STUB_TX/RX_A
6823 ILLEGAL -23 -
6625 SRV_RQST
-
24 --
24 -
67
26 GBR
6427 RTFAIL
65
28 TX_INH
63
30 HS_FAIL
6229 RTACTIVE
-31 -
61
32 BUSY
45
Data Device Corporation
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BU-64703
H-06/11-0
14
1
SSRT MARK3
FUNCTION
P3
PIN #
80-PIN DEVICE
PIN #
GND_LOGIC
TABLE 19A. BU-64703E8 SSRT-MARK3 (+3.3V) & TRANSFORMER EVALUATION BOARD PINOUTS
MADE FROM 80-PIN, SSRT MARK3 BU-64703G8 (CONT.)
SSRT MARK3
FUNCTION
P4
PIN #
80-PIN DEVICE
PIN #
41
1D06
20
2MEMOE -
2-
22,31,50,70,79
3 GND 43
3 D04
-
4-42
4D01
30,51,69
5+3.3V_LOGIC 45
5RTAD1
22,31,50,70,79
7GND 47
7D02
30,51,69 6 +3.3V_LOGIC 44 6 RTADP
22,31,50,70,79
8GND 468 D00
22,31,50,70,79
9GND 49
9D05
-10 - 4810 D03
24
11 RTAD2 22,31,50,70,79
11 GND
22,31,50,70,79
12 GND 22,31,50,70,79
12 GND
25
13 MSTCLR 30,51,6913 +3.3V_LOGIC
26
14 CLOCK_IN 30,51,69
14 +3.3V_LOGIC
27
16 SA1 53
16 D07
22,31,50,70,79 15 GND 52
15 D08
2817 MEMWR 5417 D13
29
18 DTREQ 55
18 D12
30,51,6919 +3.3V_LOGIC 5619 D14
30,51,69
20 +3.3V_LOGIC 57
20 D09
-21 - 58
21 D11
-
22 -59
22 D15
3223 INCMD 6023 D10
3425 MSG_ERR
33
24 WC/MC/CWC1 -
24 -
35
26 DTACK
36
27 RT_AD_LAT
37
28 SSFLAG
39
30 RTAD3
3829 RTAD0
-
31 -
40
32 RTAD4
46
Data Device Corporation
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BU-64703
H-06/11-0
#1
Notes:
1) Dimensions are in inches (mm).
2) Tolerances = ±0.005 inches unless otherwise specified.
4 X 19 EQUAL SP @
0.040 (1.016) = 0.760 (19.304)
(TOL. NON-CUM.)
TOP VIEW
SIDE VIEW
#20
#21
#41
#60
#61
#80
PIN NUMBERS FOR
REFERENCE ONLY
4 X 0.890 (22.606)
MAX.
0.015 (0.381)
TYP.
#40
2 X 1.88 (47.75)
4 X 0.200 (5.08)
2 X 2.36 (59.94)
REF.
0.500 (12.7)
REF
0.050 (1.27)
0.008 (0.2032)
0.025 (0.635)
0.130 (3.302)
MAX.
±0.02
±0.002
4 X 0.060 (1.524)
0.910 (23.114)
MAX.
PIN #1 DENOTED
BY INDEX MARK
FIGURE 20. BU-64703FX FLAT PACKAGE MECHANICAL OUTLINE
47
Data Device Corporation
www.ddc-web.com
BU-64703
H-06/11-0
#1
4 X 0.880 (22.35)
REF
PIN #1 DENOTED
BY INDEX MARK
#20
#21
#41
#60
#61
#80
PIN #1 DENOTED
BY INDEX MARK
PIN NUMBERS FOR
REFERENCE ONLY
4 X 19 EQUAL SP @
0.040 (1.016) = 0.760 (19.304)
(TOL. NON-CUM.)
0.015 (0.381)
TYP.
#40
0.006 (0.152)
+0.010
- 0.004
(+0.254)
(- 0.102)
1.110 (28.194)
0.010 (0.254)
MAX.
0.130 (3.302)
MAX.
0.060 (1.524)
MAX.
4 X 0.060 (1.524)
0.004 (0.102)
± 0.015
SIDE VIEW
TOP VIEW
Notes:
1) Dimensions are in inches (mm).
2) Tolerances = ±0.005 inches unless otherwise specified.
FIGURE 21. BU-64703GX GULL WING PACKAGE MECHANICAL OUTLINE
48
Data Device Corporation
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BU-64703
H-06/11-0
ORDERING INFORMATION
BU-64703XX-XXXX
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = 100% Pull Test
Q = 100% Pull Test and Pre-Cap Source Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source Inspection
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source Inspection and 100% Pull Test
Blank = None of the Above
Test Criteria:
0 = Standard Testing
2 = MIL-STD-1760 Amplitude Compliant (Not available with Voltage/Transceiver Option 4, 9, & D)
Process Requirements:
0 = Standard DDC practices, no Burn-In (See Standard DDC Processing Table)
1 = MIL-PRF-38534 Compliant (Note 4)
2 = B (Note 1)
3 = MIL-PRF-38534 Compliant with PIND Testing (Note 4)
4 = MIL-PRF-38534 Compliant with Solder Dip (Note 4)
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip (Note 4)
6 = B (Note 1) with PIND Testing
7 = B (Note 1) with Solder Dip
8 = B (Note 1) with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In
Temperature Range(Note 2)/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
6 = Custom Part (Reserved)
7 = Custom Part (Reserved)
8 = 0°C to +70°C with Variables Test Data
Voltage/Transceiver Option:
3 = +5.0 Volts rise/fall times = 100 to 300 ns (-1553B)
4 = +5.0 Volts rise/fall times = 200 to 300 ns (-1553B & McAir Compatible)(Not available with test
criteria option 2 "MIL-STD-1760 Amplitude Compliant")
8 = +3.3 Volts rise/fall times = 100 to 300 ns (-1553B) (note 5)
9 = +3.3 Volts rise/fall times = 200 to 300 ns (-1553B and McAir
compatible) (Not available with Test Criteria Option 2 "MIL-STD-1760 Amplitude Compliant") (note 5)
C = +3.3 Volts rise/fall times = 100 to 300 ns (-1553B) (note 6)
D = +3.3 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible. Note: Not available with Test Criteria Option 2
“MIL-STD-1760 Amplitude Compliant”) (note 6)
Package Type:
F = Flat Pack
G = “Gull Wing” (Formed Lead)
B = BGA Package (Consult factory)
Logic Voltage
3 = 3.3 Volt (+5.0V Tolerant I/O)
Product Type:
BU-6470 = RT only with simple (non-processor) interface
BU-64703E8-300 (Ordering information for SSRT-Mark3 (+3.3V) Transceiver Evaluation Board)
Evaluation board intended to support customers who are interested in electrically connecting and evaluating the performance of the +3.3V
SSRT Mark3
Notes:
1. Standard DDC Processing with burn-in and full temperature test—see
STANDARD DDC PROCESSING TABLE.
2. Temperature range refers to “Case Temperature”.
3. The above products contain tin-lead solder finish as applicable to sol-
der dip requirements.
4. MIL-PRF-38534 product grading is designated with the following dash numbers:
Class H is a -11X, 13X, 14X, 15X, 41X, 43X, 44X, 45X
Class G is a -21X, 23X, 24X, 25X, 51X, 53X, 54X, 55X
Class D is a -31X, 33X, 34X, 35X, 81X, 83X, 84X, 85X
5. Transformer center-tap connected to +3.3V_XCVR, see FIGURE 15
(Obsolete)
6. Transformer center-tap connected to GND, see FIGURE 16
49
H-06/11-0 PRINTED IN THE U.S.A.
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001:2000
FILE NO. A5976
R
E
G
I
S
T
E
R
E
D
F
I
R
M
®
U
The information in this data sheet is believed to be accurate; however, no responsibility is assumed
by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
Please visit our web site at www.ddc-web.com for the latest information.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2426
For Technical Support - 1-800-DDC-5757 ext. 7771
Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
TABLE 11015 (note 1), 1030 (note 2)
BURN-IN
Notes:
1. For Process Requirement "B*" (refer to ordering information), devices may be non-compliant with MIL-
STD-883, Test Method 1015, Paragraph 3.2. Contact factory for details.
2. When applicable.
3000g2001CONSTANT ACCELERATION
C1010TEMPERATURE CYCLE
A and C1014SEAL
—2009, 2010, 2017, and 2032INSPECTION
CONDITION(S)METHOD(S)
MIL-STD-883
TEST
STANDARD DDC PROCESSING
FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS
RECORD OF CHANGE
For BU-64703 Data Sheet
Revision
Date
Pages
Description
F
6/2009
26 & 27
Replaced Tables 4 and 4a.
G
6/2010
24, 26, & 44
Updated Figure 15 and Tables 4 & 19A
H
6/2011
25, 26, 28, 29, &
47
Added new page 25 and Figure 16.
Incremented all subsequent figure numbers.
Updated Figure 17. Updated Table 4.
Updated Figures 18 and 19. Added
Transceiver Options “C” & “D” to ordering
information.
