SLLS098C − M AY 1980 − REVISED FEBRUARY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DMeets or Exceeds Requirements of ANSI
TIA/EIA-422-B and ITU
Recommendation V.11
D3-State, TTL-Compatible Outputs
DFast Transition Times
DHigh-Impedance Inputs
DSingle 5-V Supply
DPower-Up and Power-Down Protection
description/ordering information
The MC3487 offers four independent differential line drivers designed to meet the specifications of ANSI
TIA/EIA-422-B and ITU Recommendation V.11. Each driver has a TTL-compatible input buffered to reduce
current and minimize loading.
The driver outputs utilize 3-state circuitry to provide high-impedance states at any pair of differential outputs
when the appropriate output enable is at a low logic level. Internal circuitry is provided to ensure the
high-impedance state at the dif ferential outputs during power-up and power-down transition times, provided the
output enable is low.
The MC3487 is designed for optimum performance when used with the MC3486 quadruple line receiver. It is
supplied in a 16-pin dual-in-line package and operates from a single 5-V supply.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube MC3487N MC3487N
0°C to 70°C
SOIC − D
Tube MC3487D
MC3487
0
°
C to 70
°
C
SOIC − D Tape and reel MC3487DR MC3487
SOP − NS Tape and reel MC3487NSR MC3487
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each driver)
INPUT
OUTPUT
OUTPUTS
INPUT
OUTPUT
ENABLE Y Z
H H H L
L H L H
X L Z Z
H = TTL high level, L = TTL low level,
X = irrelevant, Z = High impedance
Copyright 2004, Texas Instruments Incorporated
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
D, N, OR NS PACKAGE
(TOP VIEW)
SLLS098C − M AY 1980 − REVISED FEBRUARY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
15
9
12
7
1
4
4A
3A
3,4EN
2A
1A
1,2EN
13
14
11
10
5
6
3
2
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
Input
VCC
9 Ω NOM
Output
TYPICAL OF ALL OUTPUTS
SLLS098C − M AY 1980 − REVISED FEBRUARY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 2 and 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential output voltage, VOD, are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
TAOperating free-air temperature 0 70 °C
SLLS098C − M AY 1980 − REVISED FEBRUARY 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VIK Input clamp voltage II = −18 mA −1.5 V
VOH High-level output voltage VIL = 0.8 V, VIH = 2 V, IOH = −20 mA 2.5 V
VOL Low-level output voltage VIL = 0.8 V, VIH = 2 V, IOL = 48 mA 0.5 V
|VOD|Differential output voltage RL = 100 Ω,See Figure 1 2
∆|VOD|
Change in magnitude of †
RL = 100 Ω,
See Figure 1
±0.4
V
∆|VOD
|
Change in magnitude of
differential output voltage†RL = 100 Ω,See Figure 1 ±0.4 V
VOC Common-mode output voltage‡RL = 100 Ω,See Figure 1 3 V
∆|VOC|
Change in magnitude of †
RL = 100 Ω,
See Figure 1
±0.4
V
∆|VOC
|
Change in magnitude of
common-mode output voltage†RL = 100 Ω,See Figure 1 ±0.4 V
IO
Output current with power off
VCC = 0
VO = 6 V 100
A
IOOutput current with power off VCC = 0 VO = −0.25 V −100 µA
IOZ
High-impedance-state output current
Output enables at 0.8 V
VO = 2.7 V 100
A
IOZ High-impedance-state output current Output enables at 0.8 V VO = 0.5 V −100 µA
IIInput current at maximum input
voltage VI = 5.5 V 100 µA
IIH High-level input current VI = 2.7 V 50 µA
IIL Low-level input current VI = 0.5 V −400 µA
IOS Short-circuit output current§VI = 2 V −40 −140 mA
ICC
Supply current (all drivers)
Outputs disabled 105
mA
I
CC
Supply current (all drivers)
Outputs enabled, No load 85
mA
†∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
‡In ANSI Standard TIA/EIA-422-B, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage,
VOS.
§Only one output at a time should be shorted, and duration of the short circuit should not exceed one second.
switching characteristics over recommended operating free-air temperature range, VCC = 5 V
PARAMETER TEST CONDITIONS MIN MAX UNIT
tPLH Propagation delay time, low- to high-level output
CL = 15 pF,
See Figure 2
20
ns
tPHL Propagation delay time, high- to low-level output
C
L
= 15 pF,
See Figure 2
20
ns
tsk Skew time CL = 15 pF, See Figure 2 6 ns
tt(OD) Differential-output transition time CL = 15 pF, See Figure 3 20 ns
tPZH Output enable time to high level
CL = 50 pF,
See Figure 4
30
ns
tPZL Output enable time to low level
C
L
= 50 pF,
See Figure 4
30
ns
tPHZ Output disable time from high level
CL = 50 pF,
See Figure 4
25
ns
tPLZ Output disable time from low level
C
L
= 50 pF,
See Figure 4
30
ns
SLLS098C − M AY 1980 − REVISED FEBRUARY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOD
50 Ω
50 Ω
VOC
Figure 1. Differential and Common-Mode Output Voltages
Skew
tPLH
Generator
(see Note A) 50 Ω
3 V
SW1 200 Ω
5 V Y Output
Z Output
Input
See Note C
1.5 V
tPHL
1.5 V
VOH
VOL
VOLTAGE WAVEFORMS
3 V
0 V
VOL
VOH
Skew
1.5 V 1.5 V
1.5 V 1.5 V
TEST CIRCUIT
tPHL
ÏÏÏ
ÏÏÏ
tPLH
CL = 15 pF
(see Note B)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 5 ns, tf ≤ 5 ns, PRR ≤ 1 MHz, duty cycle = 50%
,
ZO = 50 Ω.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or 1N3064.
Figure 2. Test Circuit and Voltage Waveforms
CL
3 V
50 ΩOutput
RL = 100 ΩInput
Output
tt(OD)
3 V
0 V
90%
10%
tt(OD)
TEST CIRCUIT VOLTAGE WAVEFORMS
Generator
(see Note A)
CL = 15 pF
(see Note B)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 5 ns, tf ≤ 5 ns, PRR ≤ 1 MHz, duty cycle = 50%,
ZO = 50 Ω.
B. CL includes probe and stray capacitance.
Figure 3. Test Circuit and Voltage Waveforms
SLLS098C − M AY 1980 − REVISED FEBRUARY 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.5 V
tPLZ
1 kΩ
tPHZ
VOLTAGE WAVEFORMS
50 Ω
0 V or 3 V
Output
See Note C
SW2
SW1
5 V
SW3 200 Ω
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
VOL
VOH
TEST CIRCUIT
tPZL
tPZH
SW1 Closed
SW2 Open
SW2 Closed
SW1 Open
Output
Output
3 V
0 V
0.5 V
VOH
SW2 Closed
SW1 Closed
≈1.5 V
≈1.5 V
SW2 Closed
SW1 Closed
VOL
Output
Enable Input
Generator
(see Note A)
CL = 15 pF
(see Note B)
Output
Output
Output
Enable Input
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 5 ns, tf ≤ 5 ns, PRR ≤ 1 MHz, duty cycle = 50%,
ZO = 50 Ω.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or 1N3064.
Figure 4. Driver Test Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
MC3487D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MC3487DE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MC3487DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MC3487DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MC3487DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MC3487DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MC3487J OBSOLETE CDIP J 16 TBD Call TI Call TI
MC3487N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
MC3487NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
MC3487NSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MC3487NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MC3487NSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MC3487DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
MC3487DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
MC3487NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MC3487DR SOIC D 16 2500 333.2 345.9 28.6
MC3487DR SOIC D 16 2500 367.0 367.0 38.0
MC3487NSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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