16 MEG x 64 SDRAM SODIMM SMALL-OUTLINE SDRAM MODULE MT8LSDT1664(L)H For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT (Front View, 100 MHz) 144-Pin Small-Outline DIMM * JEDEC-standard, PC66 and PC100, rev 1.0, 144pin, small-outline, dual in-line memory module (SODIMM) * Utilizes 100 MHz, 125 MHz and 133 MHz SDRAM components * Unbuffered * 128MB (16 Meg x 64) * Single +3.3V 0.3V power supply * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge * Programmable burst lengths: 1, 2, 4, 8 or full page * Auto Precharge and Auto Refresh Modes * Self Refresh Mode: Standard and Low Power * 64ms, 4,096-cycle refresh * LVTTL-compatible inputs and outputs * Serial Presence-Detect (SPD) OPTIONS PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 MARKING * Self Refresh Current Standard Low power None L * Package 144-pin SODIMM (gold) G * Frequency/CAS Latency 133 MHz/CL = 2 (7.5ns, 133 MHz SDRAMs) 133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs) 100 MHz/CL = 2 (8ns, 125 MHz SDRAMs) 66 MHz/CL = 2 (10ns, 100 MHz SDRAMs) -13E -133 -10E -662 KEY SDRAM COMPONENT TIMING PARAMETERS MODULE SPEED CAS ACCESS MARKING GRADE LATENCY TIME -13E -133 -10E -662 -7E -75 -8E -10 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 2 3 2 2 5.4ns 5.4ns 6ns 9ns SETUP TIME HOLD TIME 1.5ns 1.5ns 2ns 2ns 0.8ns 0.8ns 1ns 1ns FRONT VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 VSS NC NC CK0 VDD RAS# WE# S0# S1# PIN BACK 2 VSS 4 DQ32 6 DQ33 8 DQ34 10 DQ35 12 VDD 14 DQ36 16 DQ37 18 DQ38 20 DQ39 22 VSS 24 DQMB4 26 DQMB5 28 VDD 30 A3 32 A4 34 A5 36 VSS 38 DQ40 40 DQ41 42 DQ42 44 DQ43 46 VDD 48 DQ44 50 DQ45 52 DQ46 54 DQ47 56 VSS 58 NC 60 NC 62 CKE0 64 VDD 66 CAS# 68 CKE1 70 RFU (A12) 72 RFU (A13) PIN 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 FRONT DNU VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10 VDD DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS SDA VDD PIN 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 BACK CK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS SCL VDD NOTE: Symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM PART NUMBERS This module provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. This module uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing the alternate bank will hide the PRECHARGE cycles and provide seamless, high-speed, randomaccess operation. This module is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs, outputs and clocks are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 128Mb x4, x8, x16 SDRAM data sheet. PART NUMBER CONFIGURATION VERSION MT8LSDT1664HG-13E__ 16 Meg x 64 133 MHz, CL = 2 MT8LSDT1664HG-133__ 16 Meg x 64 133 MHz, CL = 3 MT8LSDT1664HG-10E__ 16 Meg x 64 100 MHz, CL = 2 MT8LSDT1664HG-662__ 16 Meg x 64 66 MHz, CL = 2 MT8LSDT1664LHG-13E__ 16 Meg x 64* 133 MHz, CL = 2 MT8LSDT1664LHG-133__ 16 Meg x 64* 133 MHz, CL = 3 MT8LSDT1664LHG-10E__ 16 Meg x 64* 100 MHz, CL = 2 MT8LSDT1664LHG-662__ 16 Meg x 64* 66 MHz, CL = 2 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8LSDT1664HG-10EB1. *Low power option. GENERAL DESCRIPTION The Micron(R) MT8LSDT1664(L)H is a high-speed CMOS, dynamic random-access, 128MB memory organized in a x64 configuration. This module uses SDRAMs that are internally configured as quad-bank DRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signals CK0-CK1). Read and write accesses to the SDRAM module are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 SERIAL PRESENCE-DETECT OPERATION This module incorporates serial presence-detect (SPD). The SPD function is implemented using a 2,048bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM's SCL (clock) and SDA (data) signals. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM FUNCTIONAL BLOCK DIAGRAM MT8LSDT1664(L)H (128MB, 66 MHz) S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ0 DQ1 U1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB5 DQM CS# DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 RAS#: SDRAMs U1-U8 CAS#: SDRAMs U1-U8 CKE0 CKE: SDRAMs U1-U8 WE# WE#: SDRAMs U1-U8 DQM CS# DQ0 DQ1 U8 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U1, U5 U2, U6 U3, U7 U4, U8 CK0 CK1 A0-A11: SDRAMs U1-U8 SPD BA0-1: SDRAMs U1-U8 VDD SDRAMs U1-U8 VSS SDRAMs U1-U8 NOTE: 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CAS# BA0-1 DQM CS# DQ0 DQ1 U7 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB7 DQM CS# DQ0 DQ1 U4 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RAS# A0-A11 DQM CS# DQ0 DQ1 U6 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB6 DQM CS# DQ0 DQ1 U3 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM CS# DQ0 DQ1 U5 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SCL All resistor values are 10 ohms. A0 U9 A1 A2 SDA U1-U8 = MT48LC16M8A2TG SDRAMs 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM FUNCTIONAL BLOCK DIAGRAM MT8LSDT1664(L)H (128MB, 133 MHz/100 MHz) S1# S0# DQMB0 DQMB4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQML CS# DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML CS# DQ0 DQ1 U6 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML CS# DQ0 DQ1 U3 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML CS# DQ0 DQ1 U7 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB5 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB2 DQML CS# DQ0 DQ1 U8 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML CS# DQ0 DQ1 U5 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML CS# DQ0 DQ1 U9 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB6 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB3 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 RAS# RAS#: SDRAMs U2-U9 CAS# CAS#: SDRAMs U2-U9 CKE0 CKE: SDRAMs U2-U5 CKE1 WE# CKE: SDRAMs U6-U9 A0-A11 BA0-1 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CK0 U2-U5 CK1 U6-U9 WE#: SDRAMs U2-U9 SPD U1 A0-A11: SDRAMs U2-U9 BA0-1: SDRAMs U2-U9 VDD SDRAMs U2-U9 VSS SDRAMs U2-U9 NOTE: 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 DQML CS# DQ0 DQ1 U4 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SCL All resistor values are 10 ohms. A0 A1 A2 SDA U2-U9 = MT48LC8M16A2TG SDRAMs 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE 65-67 RAS#, CAS#, WE# Input Command Inputs RAS#, CAS# and WE# (along with S0#) define the command being entered. 61, 74 CK0, CK1 Input Clock: CK0 and CK1 are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 62, 68 CKE0, CKE1 Input Clock Enable: CKE0 and CKE1 activates (HIGH) and deactivates (LOW) the CK0-CK1 signals. Deactivating the clock provides POWER-DOWN and SELF REFRESH operation (all banks idle) or CLOCK SUSPEND operation (burst access in progress). CKE0 and CKE1 are synchronous except after the device enters power-down and self refresh modes, where CKE0 and CKE1 become asynchronous until after exiting the same mode. The input buffers, including CK0-CK1, are disabled during power-down and self refresh modes, providing low standby power. 69, 71 S0#, S1# Input Chip Select: S0# and S1# enable (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S0# and S1# are registered HIGH. S0# and S1# are considered part of the command code. 23-26, 115-118 DQMB0-DQMB7 Input Input Mask: DQMB is an input mask signal for write accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (after a two-clock latency) when DQMB is sampled HIGH during a READ cycle. 106, 110 BA0, BA1 Input Bank Address: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA0 is also used to program the twelfth bit of the Mode Register. 29-34, 103-105, 109, 111, 112 A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/ WRITE command (column-address A0-A8/A9, with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 142 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 DESCRIPTION 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE 3-10, 13-20, 37-44, 47-54, 83-90, 93-100, 121-128, 131-138 DQ0-DQ63 Input/ Output 141 SDA Input/Output 11, 12, 27, 28, 45, 46, 63, 64, 81, 82, 101, 102, 113, 114, 129, 130, 143, 144 VDD Supply Power Supply: +3.3V 0.3V. 1, 2, 21, 22, 35, 36, 55, 56, 75, 76, 91, 92, 107,108, 119, 120, 139, 140 VSS Supply Ground. 70, 72 RFU - Reserved for Future Use: These pins should be left unconnected. 73 DNU - Do Not Use: This pin is not connected on these modules but is an assigned pin on the compatible DRAM version. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 DESCRIPTION Data I/Os: Data bus. 6 Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eightbit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 2 Definition of Start and Stop Figure 1 Data Validity SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge Figure 3 Acknowledge Response From Receiver 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM SERIAL PRESENCE-DETECT MATRIX BYTE 0 1 2 3 4 (Notes: 1) DESCRIPTION NUMBER OF BYTES USED BY MICRON TOTAL NUMBER OF SPD MEMORY BYTES MEMORY TYPE NUMBER OF ROW ADDRESSES NUMBER OF COLUMN ADDRESSES ENTRY (VERSION) 128 256 SDRAM 12 9 (-13E/-133/-10E) 10 (-662) 2 (-13E/-133/-10E) 1 (-662) 64 0 LVTTL 7 (-13E) 7.5 (-133) 8 (-10E) 10 (-662) MT8LSDT1664(L)H(Hex) 80 08 04 0C 09 0A 02 01 40 00 01 70 75 80 A0 5 NUMBER OF BANKS 6 7 8 9 MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, tCK (CAS LATENCY = 3) 10 SDRAM ACCESS FROM CLOCK, tAC (CAS LATENCY = 3) 5.4 (-13E/-133) 6 (-10E) 7.5 (-662) 54 60 75 11 12 13 MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) 14 15 16 17 18 19 20 21 22 23 ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY, tCCD BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, tCK (CAS LATENCY = 2) NONPARITY 15.6s/SELF 16 (-13E/-133/-10E) 8 (-662) NONE 1 1, 2, 4, 8, PAGE 4 2, 3 0 0 UNBUFFERED 0E 7.5 (-13E) 10 (-133/-10E) 15 (-662) 00 80 10 08 00 01 8F 04 06 01 01 00 0E 75 A0 F0 24 SDRAM ACCESS FROM CLK, tAC (CAS LATENCY = 2) 5.4 (-13E) 6 (-133/-10E) 9 (-662) 54 60 90 25 SDRAM CYCLE TIME, tCK (CAS LATENCY = 1) -- 00 26 SDRAM ACCESS FROM CLK, tAC (CAS LATENCY = 1) -- 00 27 MINIMUM ROW PRECHARGE TIME, tRP 28 MINIMUM ROW ACTIVE TO ROW ACTIVE, tRRD 15 (-13E) 20 (-133/-10E) 30 (-662) 14 (-13E) 15 (-133) 20 (-10E/-662) 0F 14 1E 0E 0F 14 NOTE: "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM SERIAL PRESENCE-DETECT MATRIX (continued) BYTE 29 DESCRIPTION MINIMUM RAS# TO CAS# DELAY, tRCD 30 MINIMUM RAS# PULSE WIDTH, tRAS 31 MODULE BANK DENSITY 32 COMMAND AND ADDRESS SETUP TIME 33 COMMAND AND ADDRESS HOLD TIME 34 DATA SIGNAL INPUT SETUP TIME 35 DATA SIGNAL INPUT HOLD TIME 36-61 62 63 ENTRY (VERSION) 15 (-13E) 20 (-133/-10E) 30 (-662) 37 (-13E) 44 (-133) 50 (-10E) 60 (-662) 64MB (-13E/-133/-10E) 128MB (-662) 1.5 (-13E/-133) 2 (-10E) 0 (-662) 0.8 (-13E/-133) 1 (-10E) 0 (-662) 1.5 (-13E/-133) 2 (-10E) 0 (-662) 0.8 (-13E/-133) 1 (-10E) 0 (-662) RESERVED SPD REVISION 1.2 (-13E/-133/-10E) 1.0 (-662) -13E -133 -10E -662 MICRON CHECKSUM FOR BYTES 0-62 64 65-71 72 MANUFACTURER'S JEDEC ID CODE MANUFACTURER'S JEDEC ID CODE (continued) MANUFACTURING LOCATION 73-90 91 MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE (Notes: 1,2) MT8LSDT1664(L)H(Hex) 0F 14 1E 25 2C 32 3C 10 20 15 20 00 08 10 00 15 20 00 08 10 00 00 12 01 58 A6 EE 58 2C FF 01 02 03 04 05 06 07 08 09 x 1 2 3 4 5 6 7 8 9 01 02 03 04 05 06 07 08 09 NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. x = Variable Data. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM SERIAL PRESENCE-DETECT MATRIX (continued) BYTE 92 93 94 95-98 99-125 126 127 DESCRIPTION IDENTIFICATION CODE (continued) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY (Notes: 1,2) ENTRY (VERSION) 0 MT8LSDT1664(L)H(Hex) 00 x x x 133/100 (-13E/-133/-10E) 66 (-662) -13E/-133/-10E -662 SDRAM COMPONENT AND CLOCK DETAIL 64 66 CF 06 NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. x = Variable Data. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM COMMANDS Truth Table 1 provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 128Mb x4, x8, x16 SDRAM data sheet. TRUTH TABLE 1 - COMMANDS AND DQMB OPERATION (Notes: 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQs NOTES COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3 Bank/Col X 4 4 READ (Select bank and column, and start READ burst) L H L H L/H8 WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X X X 6, 7 LOAD MODE REGISTER L L L L X Op-Code X 2 Write Enable/Output Enable - - - - L - Active 8 Write Inhibit/Output High-Z - - - - H - High-Z 8 NOTE: 1. 2. 3. 4. 5. 6. 7. 8. CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the Mode Register. A0-A11 provide row address and BA0, BA1 determine which bank is made active. A0-A8/A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine which bank is being precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM A11 11 A10 A9 10 9 Reserved* WB A8 8 A6 A7 6 7 Op Mode A5 5 A4 A3 4 CAS Latency 3 1 2 BT A1 A2 Table 1 Burst Definition Address Bus A0 0 Mode Register (Mx) Burst Length Burst Length *Should program M11, M10 = "0, 0" to ensure compatibility with future devices. Burst Length M2 M1 M0 2 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved 4 Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access 8 Full Page (Y) NOTE: 1. For full-page accesses: y = 512 (133 MHz/100 MHz), y = 1,024 (66 MHz). 2. For a burst length of two, A1-A8/A9 select the block-of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A8/A9 select the block-of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A8/A9 select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected, and A0-A8/A9 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A8/A9 select the unique column to be accessed, and Mode Register bit M3 is ignored. All other states reserved Figure 4 Mode Register Definition 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 Starting Column Order of Accesses Within a Burst Address Type = Sequential Type = Interleaved A0 0 0-1 0-1 1 1-0 1-0 A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Cn, Cn+1, Cn+2 n = A0-A8/A9 Cn+3, Cn+4... (location Not supported ...Cn-1, 0-Y) Cn... 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS .... -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ..................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0C to +70C Storage Temperature (plastic) ............ -55C to +125C Power Dissipation ................................................... 8W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2 VDD+0.3 V 2 INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V VIN VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V VOUT VDD VIL -0.5 0.8 V 2 CK0, CK1, S0#, S1#, CKE0, CKE1 RAS#, CAS#, WE#, BA0, BA1, A0-A11 DQMB0-DQMB7 I I1 -20 20 A 3 I I2 -40 40 A I I3 -10 10 A 4 DQ0-DQ63 IOZ -10 10 A 4 VOH 2.4 - V VOL - 0.4 V OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) NOTE: 1. All voltages referenced to VSS. 2. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns. 3. 133 MHz/100 MHz module values for SO# and CDED will be twice those shown. 4. 66 MHz module values will be half of those shown. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM IDD SPECIFICATIONS AND CONDITIONS (Notes: 1, 2, 3, 4) (VDD = +3.3V 0.3V) MAX PARAMETER/CONDITION SYMBOL -13E -133 -10E -662 OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN); CAS latency = 3 IDD1 840 800 720 1,040 mA 5, 6, 7, 8 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD2 16 16 16 16 mA 8 STANDBY CURRENT: Active Mode; S0#, S1# = HIGH; CKE = HIGH; All banks active after tRCD met; No accesses in progress IDD3 400 400 320 400 mA 5, 7, 8, 9 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 IDD4 860 800 720 1,120 mA 5, 6, 7, 8 tRC = tRC (MIN); CL = 3 tRC = 15.625s; CL = 3 IDD5 1,520 1,440 1,240 1,600 mA IDD6 24 24 24 24 mA 5, 6, 7, 8, 10, 12 Standard Low power (L) IDD7 IDD7 16 8 16 8 16 8 16 8 mA mA AUTO REFRESH CURRENT: CKE = HIGH; S0# = HIGH SELF REFRESH CURRENT: CKE 0.2V UNITS NOTES 11 NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously, VSS and VSSQ must be at the same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to the 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crossover point. 4. IDD specifications are tested after the device is properly initialized. 5. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. The IDD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 7. Address transitions average one transition every two clocks. 8. tCK = 7.5ns for -13E/-133; tCK = 10ns for -10E. 9. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 10. CKE is HIGH during refresh command period (tRFC [MIN]) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 11. Enables on-chip refresh and address counters. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM CAPACITANCE -13X/-10E PARAMETER -662 SYMBOL MIN MAX MIN MAX UNITS NOTES Input Capacitance: A0-A11, BA0, BA1, RAS#, CAS#, WE# CI 1 22 32 22 32 pF 1 Input Capacitance: S0#, S1#, CKE0, CKE1 CI 2 12 18 22 32 pF 1 Input Capacitance: CK0, CK1 CI 2 12 18 12 18 pF 1 Input Capacitance: DQMB0#-DQMB7# CI 3 7 10 4 6 pF 1 Input Capacitance: SCL, SDA CIO1 - 10 - 10 pF 1 Input/Output Capacitance: DQ0-DQ63 CIO2 10 14 6 8 pF 1 NOTE: This parameter is sampled. VDD = +3.3V; f = 1 MHz. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS (Notes: 1, 2, 3, 4, 5, 6) AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS#,RAS#,CAS#,WE#,DQM hold time CS#,RAS#,CAS#,WE#,DQM setup timetCMS Data-in hold time Data-in setup time Data-out high-impedance CL = 3 time CL = 2 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time SYM tAC tAC tAH tAS tCH tCL tCK tCK tCKH tCKS tCMH 1.5 tDH tDS tHZ tHZ tLZ tOH tOH N tRAS tRC tRCD tREF tRFC tRP tRRD tT tWR Exit SELF REFRESH to ACTIVE command tXSR CL = 3 CL = 2 CL = 3 CL = 2 -13E -133 -10E -662 MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES 5.4 5.4 6 7.5 ns 5.4 6 6 9 ns 0.8 0.8 1 1 ns 1.5 1.5 2 2 ns 2.5 2.5 3 3 ns 2.5 2.5 3 3 ns 7 7.5 8 10 ns 7 7.5 10 10 15 ns 7 0.8 0.8 1 1 ns 1.5 1.5 2 2 ns 0.8 0.8 1 1 ns 1.5 2 2 ns 0.8 0.8 1 1 ns 1.5 1.5 2 2 ns 5.4 5.4 6 8 ns 8 5.4 6 7 10 ns 8 1 1 1 2 ns 2.7 2.7 3 3 ns 1.8 1.8 1.8 n/a ns 9 37 120,000 44 120,000 50 120,000 60 120,000 ns 60 66 70 90 ns 15 20 20 30 ns 64 64 64 64 ms 66 66 70 90 ns 15 20 20 30 ns 10 14 15 20 20 ns 0.3 1.2 0.3 1.2 0.3 1.2 1 1.2 ns 11 1 CK + 1 CK + 1 CK + 1 CK + - 12 7ns 7.5ns 7ns 7ns 14 67 15 75 15 80 15 90 ns ns 13 14 *Specifications for the SDRAM components used on the module. NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA +70C) is ensured. 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC characteristics assume tT = 1ns. 4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5. Outputs measured at 1.5V with equivalent load: Q 50pF 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM NOTES (continued) 6. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to the 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crossover point. 7. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 8. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 9. Parameter guaranteed by design. 10. Based on tCK = 133 MHz (-13E/-133), 100 MHz (-10E), or 66 MHz (-662). 11. AC characteristics assume tT = 1ns. 12. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed. 13. Precharge mode only. 14. CK must be toggled a minimum of two times during this period. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM AC FUNCTIONAL CHARACTERISTICS (Notes: 1, 2, 3, 4, 5, 6) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH tROH -13E 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 -133 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 -10E/-662 UNITS NOTES tCK 1 7 tCK 1 8 tCK 1 8 tCK 0 7 tCK 0 7 tCK 2 7 tCK 0 7 tCK 4 9, 10 tCK 2 10, 11 tCK 1 7 tCK 1 7 tCK 2 10, 11 tCK 2 12 tCK 3 7 tCK 2 7 NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA +70C) is ensured. 2. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC characteristics assume tT = 1ns. 4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5. Outputs measured at 1.5V with equivalent load: Q 50pF 6. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to the 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crossover point. 7. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 8. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 9. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 10. Based on tCK = 133 MHz (-13E/-133), 100 MHz (-10E), or 66 MHz (-662). 11. Timing actually specified by tWR. 12. JEDEC and PC100 specify three clocks. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VDD 3 3.6 INPUT HIGH VOLTAGE: Logic 1; All inputs VIH INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 OUTPUT LOW VOLTAGE: IOUT = 3mA VDD x 0.7 VDD + 0.5 UNITS NOTES V V V VOL - 0.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI - 10 A OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO - 10 A STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% ISB - 30 A POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz IDD - 2 mA NOTE: 1. All voltages referenced to VSS. SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWRC MIN 0.3 4.7 300 MAX 3.5 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 UNITS s s ns ns s s s ns s s KHz ns s s ms NOTES 2 NOTE: 1. All voltages referenced to VSS. 2. Timing actually specified by tWR. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM SPD EEPROM tF t HIGH tR t LOW SCL t HD:STA t SU:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 MIN 0.3 4.7 300 MAX 3.5 300 0 4 SYMBOL tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO UNITS s s ns ns s s 20 MIN 4 4.7 MAX 1 250 4.7 4.7 UNITS s s s ns s s Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM 144-PIN SODIMM (128MB, 66 MHz) FRONT VIEW .150 (3.80) MAX 2.667 (67.75) 2.656 (67.45) .079 (2.00) R (2X) 1.056 (26.82) 1.044 (26.52) .071 (1.80) (2X) .787 (20.00) TYP .236 (6.00) .157 (4.00) .100 (2.55) .043 (1.10) .035 (0.90) .079 (2.00) .130 (3.30) (2X) PIN 1 .059 (1.50) .024 (.60) TYP TYP .0315 (.80) TYP PIN 143 (PIN 144 ON BACKSIDE) 2.386 (60.60) 2.504 (63.60) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM 144-PIN SODIMM (128MB, 133 MHz/100 MHz) FRONT VIEW .100 (2.54) MAX 2.666 (67.72) 2.656 (67.45) .079 (2.00) R (2X) 1.155 (29.34) 1.145 (29.08) .071 (1.80) (2X) .787 (20.00) TYP .236 (6.00) .157 (4.00) .100 (2.55) .043 (1.10) .035 (0.90) .079 (2.00) .130 (3.30) (2X) PIN 1 .059 (1.50) .024 (.60) TYP TYP .0315 (.80) TYP PIN 143 (PIN 144 ON BACKSIDE) 2.386 (60.60) 2.504 (63.60) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 16 MEG x 64 SDRAM SODIMM 144-PIN SODIMM (128MB, 133 MHz/100 MHz) FRONT VIEW .150 (3.80) MAX 2.666 (67.72) 2.656 (67.45) .079 (2.00) R (2X) 1.255 (31.88) 1.245 (31.62) .071 (1.80) (2X) .787 (20.00) TYP .236 (6.00) .157 (4.00) .100 (2.55) .043 (1.10) .035 (0.90) .079 (2.00) .83.82 (3.30) PIN 1 .059 (1.50) .024 (.60) TYP TYP .0315 (.80) TYP PIN 143 (PIN 144 on backside) 2.386 (60.60) 2.504 (63.60) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 16 Meg x 64 SDRAM SODIMM ZM29_3.p65 - Rev. 6/00 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. Micron Memory DRAM Module Reference Guide Density 4MB 4MB 4MB 8MB 8MB 8MB 8MB 8MB 16MB 16MB 16MB 16MB 16MB 32MB 32MB 32MB 32MB 32MB 32MB 32MB 32MB 32MB 64MB 64MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 256MB 256MB Description SS 1 Meg x 32 Gold SIMM/Tin SIMM SS 1 Meg x 32 3.3V Gold SODIMM SS 1 Meg x 32 3.3V Gold DIMM DS 2 Meg x 32 Gold SIMM/Tin SIMM SS 2 Meg x 32 3.3V Gold SODIMM SS 2 Meg x 32 3.3V Gold DIMM SS 1 Meg x 64 3.3V Gold SODIMM DS 1 Meg x 64 3.3V Gold DIMM SS 4 Meg x 32 Gold SIMM/Tin SIMM SS 4 Meg x 36 ECC Gold SIMM/Tin SIMM DS 4 Meg x 32 3.3V Gold SODIMM SS 4 Meg x 32 3.3V Gold SODIMM SS 4 Meg x 32 3.3V Gold DIMM DS 8 Meg x 32 Gold SIMM/Tin SIMM DS 8 Meg x 36 ECC Gold SIMM/Tin SIMM DS 8 Meg x 32 3.3V Gold SODIMM DS 8 Meg x 32 3.3V Gold DIMM DS 4 Meg x 64 3.3V Gold SODIMM SS 4 Meg x 64 3.3V Gold DIMM DS 4 Meg x 64 3.3V Gold DIMM DS 4 Meg x 72 3.3V ECC Gold DIMM SS 4 Meg x 72 3.3V ECC Gold DIMM DS 8 Meg x 64 3.3V Gold SODIMM DS 8 Meg x 64 3.3V Gold DIMM SS 8 Meg x 64 3.3V Gold DIMM DS 8 Meg x 72 3.3V ECC Gold DIMM SS 8 Meg x 72 3.3V ECC Gold DIMM SS 8 Meg x 72 3.3V ECC Gold DIMM DS 16 Meg x 64 3.3V Gold DIMM DS 16 Meg x 72 3.3V ECC Gold DIMM DS 16 Meg x 72 3.3V ECC Gold DIMM DS 32 Meg x 72 3.3V ECC Gold DIMM DS 32 Meg x 72 3.3V ECC Gold DIMM Pins Components on Module 72 (2) 1 Meg x 16 72 (2) 1 Meg x 16 3.3V TSOP 100 (2) 1 Meg x 16 3.3V TSOP 72 (4) 1 Meg x 16 72 (4) 1 Meg x 16 3.3V TSOP 100 (4) 1 Meg x 16 3.3V 144 (4) 1 Meg x 16 3.3V TSOP 168 (4) 1 Meg x 16 3.3V TSOP 72 (8) 4 Meg x 4 72 (9) 4 Meg x 4 72 (8) 4 Meg x 4 3.3V TSOP 72 (2) 4 Meg x 16 3.3V TSOP 100 (2) 4 Meg x 16 3.3V TSOP 72 (16) 4 Meg x 4 72 (18) 4 Meg x 4 72 (4) 4 Meg x 16 3.3V TSOP 100 (4) 4 Meg x 16 3.3V TSOP 144 (4) 4 Meg x 16 3.3V TSOP 168 (4) 4 Meg x 16 3.3V TSOP 168 (16) 4 Meg x 4 3.3V 168 (18) 4 Meg x 4 3.3V 168 (5) 4 Meg x 16 3.3V TSOP 144 (8) 8 Meg x 8 3.3V TSOP 168 (32) 4 Meg x 4 3.3V 168 (8) 8 Meg x 8 3.3V 168 (36) 4 Meg x 4 3.3V 168 (9) 8 Meg x 8 3.3V 168 (9) 8 Meg x 8 3.3V TSOP 168 (16) 16 Meg x 4 3.3V 168 (18) 16 Meg x 4 3.3V 168 (18) 16 Meg x 4 3.3V TSOP 168 (36) 16 Meg x 4 3.3V 168 (36) 16 Meg x 4 3.3V TSOP Part Number MT2D132G/M (X) MT2LDT132HG (X) MT2LD132UG (X) MT4D232DG/M (X) MT4LDT232HG (X) MT4LD232UG (X) MT4LDT164HG (X) MT4LDT164AG (X) MT8D432G/M (X) MT9D436G/M (X) MT8LDT432HG (X) MT2LDT432HG (X) MT2LDT432UG (X) MT16D832G/M (X) MT18D836G/M (X) MT4LDT832HG (X) MT4LDT832UG (X) MT4LDT464HG (X)(S) MT4LDT464AG (X) MT16LD464AG (X) MT18LD472(A)G (X) MT5LDT472(A)G (X) MT8LDT864HG (X)(S) MT32LD864AG (X) MT8LD864AG (X) MT36LD872(A)G (X) MT9LD872(A)G (X) MT9LDT872G (X) MT16LD1664AG (X) MT18LD1672(A)G (X) MT18LDT1672G (X) MT36LD3272G (X) MT36LDT3272G (X) Speed 50,60 60 60 50,60 60 60 60 60 50, 60 50, 60 60 60 60 50, 60 50, 60 60 60 50,60 50,60 60 60 60 60 60 50, 60 60 50, 60 50, 60 50,60 50,60 50,60 50, 60 50, 60 Height .800" 1.000" 1.000" .800" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" Unbuff = 1.000", Buff = 1.000" Unbuff = 1.000", Buff = 1.050" 1.050" 1.500" 1.100" Unbuff = 1.500", Buff = 1.500" Unbuff = 1.100", Buff = 1.250" 1.350" 1.250" Unbuff = 1.250", Buff = 1.100" 2.000" 2.000" 2.000" Availability Samples Prod. Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Rev. 8/22/00 SS - Single Sided DS - Double Sided G - Gold Plated M - Tin Plated U - 100-pin DIMM (H) - Small-Outline DIMM (SODIMM) (X) - EDO; no "X" denotes FPM version (A) - 8-CAS; SPD version; unbuffered (no "A" denotes buffered version for x72 DIMMs) (S) - Self Refresh Micron Technology, Inc. reserves the right to change products or specifications without notice. Micron Memory SDRAM Module Reference Guide Density Description 4MB SS 1 Meg x 32 3.3V Gold DIMM Pins 100 Components on Module (2) 1 Meg x 16 3.3V TSOP Base Part Number MT2LSDT132UG 1 Meg x 32 AIMM 1 Meg x 32 AIMM 2 Meg x 32 3.3V Gold DIMM 100 (2) 1 Meg x 16 (1) 2 Meg x 32 (4) 1 Meg x 16 3.3V TSOP 3.3V TSOP 3.3V TSOP MT2LSDT132AGP MT1LSDT132AGP MT4LSDT232UDG 16MB SS 4 Meg x 32 3.3V Gold DIMM 100 (2) 4 Meg x 16 3.3V TSOP MT2LSDT432UG 32MB DS 8 Meg x 32 3.3V Gold DIMM 100 (4) 4 Meg x 16 3.3V TSOP MT4LSDT832UDG 32MB DS 4 Meg x 64 3.3V Gold SODIMM 144* (4) 4 Meg x 16 3.3V TSOP MT4LSDT464(L)HG 8MB SS SS DS 32MB SS 4 Meg x 64 3.3V Gold DIMM 168 (4) 4 Meg x 16 3.3V TSOP MT4LSDT464AG 32MB SS 4 Meg x 72 3.3V ECC Gold DIMM 168* (5) 4 Meg x 16 3.3V TSOP MT5LSDT472AG 64MB DS 16 Meg x 32 3.3V Gold DIMM 100 (4) 16 Meg x 8 3.3V TSOP MT4LSDT1632UG 64MB DS 8 Meg x 64 3.3V Gold SODIMM 144* 64MB DS 8 Meg x 64 3.3V Gold SODIMM 144* (4) 8 Meg x 16 3.3V TSOP MT4LSDT1632UDG (8) 8 Meg x 8 3.3V TSOP MT8LSDT864(L)HG (8) 4 Meg x 16 3.3V TSOP (4) 8 Meg x 16 3.3V TSOP MT4LSDT864(L)HG 64MB SS 8 Meg x 64 3.3V Gold DIMM 168 (8) 8 Meg x 8 3.3V TSOP MT8LSDT864AG 64MB SS 8 Meg x 64 3.3V Gold DIMM 168 (4) 8 Meg x 16 3.3V TSOP MT4LSDT864AG 64MB SS 8 Meg x 72 3.3V ECC Gold DIMM 168 (9) 8 Meg x 8 3.3V TSOP MT9LSDT872AG 64MB SS 8 Meg x 72 3.3V ECC Gold DIMM 168 (9) 8 Meg x 8 3.3V TSOP MT9LSDT872G 128MB DS 32 Meg x 32 3.3V Gold DIMM 100 (8) 16 Meg x 8 3.3V TSOP MT8LSDT3232UG (8) 8 Meg x 16 3.3V TSOP MT8LSDT3232UDG 128MB DS 16 Meg x 64 3.3V Gold SODIMM 144 (8) 8 Meg x 16 3.3V TSOP MT8LSDT1664(L)HG 16 Meg x 8 8 Meg x 16 3.3V TSOP 3.3V TSOP 128MB DS 16 Meg x 64 3.3V Gold DIMM 168 (16) 8 Meg x 8 3.3V TSOP MT16LSDT1664AG 128MB DS 16 Meg x 64 3.3V Gold DIMM 168 (8) 16 Meg x 8 3.3V TSOP MT8LSDT1664AG 128MB DS 16 Meg x 72 3.3V ECC Gold DIMM 168 (18) 8 Meg x 8 3.3V TSOP MT18LSDT1672AG 128MB SS 16 Meg x 72 3.3V ECC Gold DIMM 168 (9) 16 Meg x 8 3.3V TSOP MT9LSDT1672AG 168 (9) 16 Meg x 8 3.3V TSOP MT9LSDT1672G 128MB DS 16 Meg x 72 3.3V ECC Gold DIMM 168 (18) 16 Meg x 4 3.3V TSOP MT18LSDT1672G 256MB DS 32 Meg x 64 3.3V Gold DIMM 168 (16) 16 Meg x 8 3.3V TSOP MT16LSDT3264AG DS 32 Meg x 64 3.3V Gold SODIMM 144 (8) 16 Meg x 16 3.3V TSOP MT8LSDT3264HG DS 32 Meg x 64 3.3V Gold SODIMM 144 (16) 16 Meg x 8 3.3V fBGA 256MB DS 32 Meg x 72 3.3V ECC Gold DIMM 168 (18) 16 Meg x 8 3.3V TSOP MT18LSDT3272AG 256MB DS 32 Meg x 72 3.3V ECC Gold DIMM 168 (18) 32 Meg x 4 3.3V TSOP MT18LSDT3272G DS 32 Meg x 72 3.3V ECC Gold DIMM 168 (18) 16 Meg x 8 3.3V TSOP MT18LSDT3272DG 512MB DS 64 Meg x 72 3.3V ECC Gold DIMM 168 (36) 32 Meg x 4 3.3V FBGA DS 64 Meg x 72 3.3V ECC Gold DIMM 168 (36) 32 Meg x 4 3.3V TSOP MT36LSDT6472G DS 64 Meg x 64 3.3V ECC Gold DIMM 168 (16) 32 Meg x 8 3.3V TSOP MT16LSDT6464AG DS 64 Meg x 72 3.3V ECC Gold DIMM 168 (18) 32 Meg x 8 3.3V TSOP MT18LSDT6472AG DS 64 Meg x 72 3.3V ECC Gold DIMM 168 (18) 64 Meg x 4 3.3V TSOP MT18LSDT6472G DS 128 Meg x 72 3.3V ECC Gold DIMM 168 (36) 64 Meg x 4 3.3V TSOP MT36LSDT12872G 1GB MT16LSDF3264HG MT36LSDF6472G Speed -10E1 -8E1 -6E2 -6E1 -10E1 -8E1 -10C1 -8C1 -10C1 -8C1 -662C1 -662C2 -10EC3 -133C3 -13EC3 -10EC4 -133C4 -13EC4 -662C6 -10CC6 -10EC6 -133C6 -13EC6 -662C6 -10CC6 -10EC6 -133C6 -13EC6 -10B1 -8B1 -10B1 -8B1 -662C3 -10EC5 -133C5 -13EC5 -662B1 -10EB1 -133B1 -13EB1 -10EB2 -133B2 -13EB2 -662C7 -10CC7 -10EC7 -133C7 -13EC7 -662B1 -10CB1 -10EB1 -133B1 -13EB1 -662C7 -10CC7 -10EC7 -133C7 -13EC7 -10CC3 -10EC3 -133C3 -13EC3 -10B1 -8B1 -10B1 -8B1 -10CB1 -10EB1 -133B1 -13EB1 -662B2 -10EB3 -133B3 -13EB3 -662C7 -10CC7 -10EC7 -133C7 -13EC7 -10CB1 -10EB1 -133B1 -13EB1 -662C7 -10CC7 -10EC7 -133C7 -13EC7 -10CB1 -10EB1 -133B1 -13EB1 -10CB1 -10EB1 -133B1 -13EB1 -10CC2 -10EC2 -133C2 -13EC2 -10CB1 -10EB1 -133B1 -13EB1 -10EA1 -133A1 -10EB2 -133B2 -10CB1 -10EB1 -133B1 -13EB1 -10EB1 -133B1 -13EB1 -10EB1 -133B1 -10EB1 -133B2 -13EB2 -10EB2 -133B2 -13EB2 -10EA1 -133A1 -13EA1 -10EA1 -133A1 -13EA1 -10EA1 -133A1 -13EA1 -10EA1 -133A1 -13EA1 a Die Rev. E = Y72G PCB (height) 1 = 6649 (1.000") E = Y72G E = Y84W E = Y72G 2 = 0164B (1.4") 1 = 0178 (1.4") 1 = 6649 (1.000") C = Y84 1 = 6660 (1.000") C = Y84 1 = 6660 (1.000") C = Y84 1 = 6645 (1.150") 2 = 6669 (1.000") 3 = 0118B (1.000") 4 = 0180 (1.000") C = Y84 6 = 0134B (1.000") C = Y84 6 = 0134B (1.000") B = Y85B 1 = 6692(1.15") B = Y85B 1 = 6660(1.00") C = Y84 3 = 6678 (1.050") 5 = 0115C (1.250") B = Y85B 1 = 0118B (1.000") 2 = 0180 (1.000") C = Y84 7 = 0104B (1.375") B = Y85B 1 = 0134B (1.00") C = Y84 7 = 0104B (1.375") C = Y84 3 = 0144 (1.500") B = Y85B 1 = 6692 (1.15") B = Y85B 1 = TBD (1.15") B = Y85B 1 = 0115C (1.25") 2 = 6678 (1.050") 3 = 0179 (1.050") C = Y84 7 = 0104B(1.375") B = Y85B 1 = 0104B(1.375") C = Y84 7 = 0104B(1.375") B = Y85B 1 = 0104B(1.375") B = Y85B 1 = 0144(1.500") C = Y84 2 = 0129 (1.700") B = Y85B 1 = 0104B (1.375") A = Y86 1 = 0115C (1.25") B = Y85B 2 = 0155 (1.25") B = Y85B 1 = 0104B (1.375") B = Y85B 1 = 0129 (1.700") B = Y85B 1 = 0156 (1.6") B = Y85B 1 = 0123(1.60") 2 = 0142(1.60") B = Y85B 2 = 0129 (1.700") A = Y86 1 = 0104B (1.375") A = Y86 1 = 0104B (1.375") A = Y86 2 = 0129 (1.700") A = Y86 2 = 0129 (1.700") b MHz* 100 125 133 133 100 125 100 125 100 125 66 66 100 133 133 100 133 133 66 100 100 133 133 66 100 100 133 133 100 125 100 125 66 100 133 133 66 100 133 133 100 133 133 66 100 100 133 133 66 100 100 133 133 66 100 100 133 133 100 100 133 133 100 125 100 125 100 100 133 133 66 100 133 133 66 100 100 133 133 100 100 133 133 66 100 100 133 133 100 100 133 133 100 100 133 133 100 100 133 133 100 100 133 133 100 133 100 133 100 100 133 133 100 133 133 100 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 Availability Samples Production Now Now Now Now Now Now SEP OCT Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now SEP OCT SEP OCT SEP OCT Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now SEP OCT SEP OCT SEP OCT Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Jan TBD TBD Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now TBD TBD TBD TBD Now Now Now Now Now Now TBD TBD Now Now SEP OCT SEP OCT SEP OCT Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now TBD TBD Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now TBD TBD Now Now Now Now Now Now TBD TBD Now Now Now Now Now Now Now Now Now Now Now Now Now Now TBD TBD SEP NOV SEP NOV SEP NOV SEP NOV Now Now Now Now Now Now TBD TBD Now Now Now Now TBD TBD Now Now Now Now Now Now OCT NOV TBD TBD Now Now Now Now TBD TBD OCT 4Q00 OCT 4Q00 TBD TBD OCT 4Q00 OCT 4Q00 TBD TBD SEP 4Q00 SEP 4Q00 TBD TBD SEP 4Q00 SEP 4Q00 TBD TBD Notes AIMM AIMM PC100 CL3 CL2 PC133 rev 1.2 PC133 rev 1.2 PC133 rev 1.2 CL3 CL2 CL3 CL2 PC100 CL3 CL2 PC100 CL3 CL2 PC133 rev 1.2 PC133 rev 1.2 PC133 rev 1.2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 PC100 PC100 CL3 CL2 PC133 rev 1.2 PC133 rev 1.2 PC133 rev 1.2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 11x13pkg CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 Rev. 8/22/00 Part Number = a + b Example: MT36LSDT12872G-13EA1 EOL = end of life *For 144- and 168-pin DIMMs (66 MHz/100 MHz), adheres to Intel's 4-Clock SDRAM module specs (66 MHz will use -10 components; 100 MHz will use -8 components). For 100-pin DIMMs, 100 MHz uses -10 components; adheres to SS - Single Sided DS - Double Sided G - Gold Plated (H) - Small-Outline DIMM (SODIMM) LP - Low Power Intel is a registered trademark of Intel Corporation. U - 100-pin DIMM UDG - Double-sided, dual-bank 100-pin DIMM (A) - 8-CAS; SPD version; unbuffered (no "A" denotes registered version for x72 DIMMs) Micron Technology, Inc. reserves the right to change products or specifications without notice. Micron Memory DDR SDRAM Module Reference Guide Density 64MB Description DS 8 Meg x 64 2.5V Gold DIMM Pins 184 Components on Module (8) 8 Meg x 8 TSOP Base Part Number MT8VDDT864AG 64MB DS 8 Meg x72 ECC 2.5V Gold DIMM 184 (9) 8 Meg x 8 TSOP MT9VDDT872AG DS 8 Meg x72 ECC 2.5V Gold DIMM 184 (9) 8 Meg x 8 TSOP MT9VDDT872G DS 16 Meg x64 2.5V Gold DIMM 184 (16) 8 Meg x 8 TSOP MT16VDDT1664AG DS 16 Meg x64 2.5V Gold DIMM 184 (8) 16 Meg x 8 TSOP MT8VDDT1664AG DS 16 Meg x72 ECC 2.5V Gold DIMM 184 (18) 8 Meg x 8 TSOP MT18VDDT1672AG DS 16 Meg x72 ECC 2.5V Gold DIMM 184 (18) 8 Meg x 8 TSOP MT18VDDT1672DG DS 16 Meg x72 ECC 2.5V Gold DIMM 184 (18) 16 Meg x 4 TSOP MT18VDDT1672G DS 16 Meg x72 ECC 2.5V Gold DIMM 184 (9) 16 Meg x 8 TSOP MT9VDDT1672AG DS 16 Meg x72 ECC 2.5V Gold DIMM 184 (9) 16 Meg x 8 TSOP MT9VDDT1672G 256MB DS 32 Meg x64 2.5V Gold DIMM 184 (16) 16 Meg x 8 TSOP MT16VDDT3264AG 256MB DS 32 Meg 72 ECC 2.5V Gold DIMM 184 (18) 16 Meg x 8 TSOP MT18VDDT3272AG DS 32 Meg 72 ECC 2.5V Gold DIMM 184 (18) 32 Meg x 4 TSOP MT18VDDT3272G DS 32 Meg 72 ECC 2.5V Gold DIMM 184 (18) 16 Meg x 8 TSOP MT18VDDT3272DG DS 64 Meg 72 ECC 2.5V Gold DIMM 184 (36) 32 Meg x 4 TSOP MT36VDDT6472G 128MB 128MB 512MB Speed -202A1 -265A1 -202A2 -265A2 -262A2 -202A1 -265A1 -202A2 -265A2 -262A2 -202A1 -265A1 -262A1 -202A1 -265A1 -202A2 -265A2 -262A2 -202A1 -265A1 -262A1 -202A1 -265A1 -202A2 -265A2 -262A2 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 -202A1 -265A1 -262A1 a b Part Number = a + b Example MT36VDDT6472G-262A1 SS - Single Sided DS - Double Sided G - Gold Plated (H) - Small-Outline DIMM (SODIMM) (A) - 8-CAS; SPD version; unbuffered (no "A" denotes registered version for x72 DIMMs) Die Rev. A = T84 PCB (height) 1 = 0116A (1.25") 2 = 0161 (1.25") A = T84 1 = 0116A (1.25") 2 = 0161 (1.25") A = T84 1 = 0162 (1.80") A = T84 1 = 0116A(1.25") 2 = 0116B (1.25") A = T85 1 = 0161 (1.25") A = T84 1 = 0116A (1.25") 2 = 0116B (1.25") A = T84 1 = 0162 (1.80") A = T84 1 = 0163 (1.80") A = T85 1 = 0161 (1.25") A = T85 1 = 0162 (1.80") A = T85 1 = 0116B (1.25") A = T85 1 = 0116B (1.25") A = T85 1 = 0163 (1.80") A = T85 1 = 0162 (1.80") A = T85 1 =TBD (1.80") MHz 200 266 200 266 266 200 266 200 266 266 200 266 266 200 266 200 266 266 200 266 266 200 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 200 266 266 Availability Samples Production Now N/A Now N/A Now Now Now Now TBD TBD N/A Now N/A Now Now Now Now Now TBD TBD Now Now Now Now TBD TBD Now N/A Now N/A Now Now Now Now TBD TBD Now Oct Now Oct TBD TBD N/A Now N/A Now Now Now Now Now TBD TBD Now Now Now Now TBD TBD Now Now Now Now TBD TBD Now Oct Now Oct TBD TBD Now Oct Now Oct TBD TBD Now Oct Now Oct TBD TBD Now Oct Now Oct TBD TBD Now Oct Now Oct TBD TBD Now Oct Now Oct TBD TBD SEP Nov SEP Nov TBD TBD Rev. 8/22/00 Micron Memory Rambus(R) RIMMTM Module Reference Guide Density 128MB Description SS 64 Meg x 16 non-ECC Pins 184 Components on Module (4) 16 Meg x 16 Base Part Number MT4VR6416AG 128MB SS 32 Meg x 18 ECC 184 (4) 16 Meg x 18 MT4VR6418AG 256MB SS 64 Meg x 16 non-ECC 184 (8) 16 Meg x 16 MT8VR12816AG 256MB SS 64 Meg x 18 ECC 184 (8) 16 Meg x 18 MT8VR12818AG 512MB DS 128 Meg x 16 non-ECC 184 (16) 16 Meg x 16 MT16VR25616AG 512MB DS 128 Meg x 18 ECC 184 (16) 16 Meg x 18 MT16VR25618AG Speed -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 a b Part Number = a + b Example MT16VR25618AG-840A1 Die Rev. A = R96A PCB (height) 1 = TBD (1.25") A = R96A 1 = TBD (1.25") A = R96A 1 = TBD (1.25") A = R96A 1 =TBD (1.25") A = R96A 1 = TBD (1.25") A = R96A 1 = TBD (1.25") MHz 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 Availability Samples Production TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Rev. 8/22/00