73M2901CE
V.22bis Single Chip Mode m
Simplifying System Integration™ DATA SHEET
DS_2901CE_031 January 2010
R ev. 3.4 © 20 10 Teridian Semico nduct or Corporation 1
DESCRIPTION
The 73M2901C E l ow speed modem integrates a
dat a pum p, con trol ler, and an alog front end in a
3.3 V device with a powerful "AT" co mmand host
interface. The modem reduces ext er nal
compon ent count /co st by in corporating m any
fe atures li ke parallel phone de te ct , Li ne -In-Use
and Ring detection in so ftwar e w it hout requi r i ng
additional components.
The device is a "one chip fi ts all” solution for
applications incl uding set-top boxes, point-of-sale
terminals, au tomatic teller machines, utility
meters, vending m achines and sm ar t ca r d
readers.
Another distinctive feature of this device is pin
com patibility wit h Teridian’s flagship embedded
hard modems, the 73M2901C L, and the
73M1903 soft modem AFE. This offe rs
customers a cost effective met hod to design for
bot h hard or soft mod em solutions in the sa me
system as a risk-free co st reducti on path.
Complete support, modem reference designs
and error co r recti on softwa r e are part of the
sol uti on offered by Teridian. Our in-house
application engineer i ng team i s here to help
meet your i nternational cer tifi cat ion n eeds.
FEATURES
• True one chip solution for emb edded sy stems
• A s low as 9.5 mA operating with standby and
power down mode available
• Power supply operation from 3.6 V to 2.7 V
• Data modes and speeds:
V.22bis – 2400 bps
V.22/Bell212 – 1200 bps
V.21/Bell103 – 300 bps
V.23 – 1200/75 bps (with PAVI turnaround)
Bell202 – 1200 bps
Be l l 202 /V23 1 20 0 bps FD X 4-wi re op erati on
• V.22/Bell 212A/V.22bis synchronous modes
• I nternational Call Pr ogr ess support:
FCC p art 68, CTR21, JATE , etc.
• DTMF generation and detection
• Worldwid e Caller ID capab ility
U.S. Typ e I and II support
• E IA 777A co m pl i ant
• SIA-2000 com pli a nt
• SMS messaging support
• On chip hybrid driver
• Blacklisting capabilit y
• Line-In-Use and P arallel Pick-Up (911) detection
wi th v oltage or low cos t ener gy detection method
• I ncoming r ing en er gy detection through C ID
pat h; no optocoupl er cir cuitry requir ed
• Manufacturing Self Test capability
• Backward com patible with 73M2901CL
• P ackaging: 32 lead QFN, 32-pin TQFP
73M2901CE Data Sheet DS_2901CE_031
2 Rev. 3.4
Table of Contents
1 Hardware Description .................................................................................................................... 4
1.1 Power Supply ....................................................................................................................... 4
1.2 Lo w Power Mode .................................................................................................................. 4
1.3 Analog Line / Hybrid Interface ............................................................................................... 4
1.4 Interrupt P ins ........................................................................................................................ 4
1.5 Crystal Osci llator................................................................................................................... 5
1.5.1 Specifyin g a C r ystal ..................................................................................................... 5
1.6 Reset .................................................................................................................................... 5
1.7 Asynchronous and Synchr onous S er ial Data Interface .......................................................... 5
2 Pinout ............................................................................................................................................. 6
3 Pin Descriptions ............................................................................................................................ 7
3.1 Power Pins ........................................................................................................................... 7
3.2 Analog Interface Pi ns ............................................................................................................ 7
3.3 Digital Interface P ins ............................................................................................................. 7
3.4 External Inte r r upt Pi ns .......................................................................................................... 8
3.5 Oscillator Pins ....................................................................................................................... 8
4 Electrical Specifications ................................................................................................................ 9
4.1 Abso lu te Maximum Ratings................................................................................................... 9
4.2 Recommend ed Operati ng C ondi ti ons .................................................................................... 9
4.3 Receiver ............................................................................................................................... 9
4.4 Transmitter ......................................................................................................................... 10
4.5 Maximum Transmit Level .................................................................................................... 10
4.6 DC Characteristics, Vcc = 3.3 V .......................................................................................... 11
4.6.1 DC S upply Current, VDD = 2.7 V (Battery EOL ) ......................................................... 11
4.6.2 DC S upply Current , VDD = 3.0 V .............................................................................. 11
4.6.3 DC S upply Current VDD = 3.3 V ................................................................................ 12
4.6.4 DC S upply Current VDD = 3.6 V ................................................................................ 12
5 Firmware Description .................................................................................................................. 13
5.1 Firmware Overview ............................................................................................................. 13
5.2 Firmware Features .............................................................................................................. 13
6 Design Considera tions ................................................................................................................ 14
6.1 Layout Consi der ati ons ........................................................................................................ 14
6.2 73M2901CE Design Compatibility ....................................................................................... 15
6.3 Telephone Line Interface .................................................................................................... 15
6.4 Fu nct ional Consider ations ................................................................................................... 16
6.4.1 SMS and V.23 Half D upl ex ........................................................................................ 16
6.4.2 Lease d Lin e M ode ..................................................................................................... 16
6.4.3 73M2901CE Energy Ring Detection .......................................................................... 17
6.4.4 C al le r ID M ode C hanges ........................................................................................... 18
6.4.5 Selectable Answer Ton e Frequency Detection ........................................................... 18
6.4.6 73M2901CE S99 Country Code Support ................................................................... 18
7 Reference Designs ...................................................................................................................... 21
7.1 Low Cost D esign Using D SP R i ng and Status M onitor ing .................................................... 21
7.2 Refer ence Design Using Traditional H ar dware Line Monit or i ng ........................................... 22
8 Modem Performance Characteristics ......................................................................................... 23
8.1 BER versus SNR ................................................................................................................ 23
8.2 BER versus Rece ive Level .................................................................................................. 23
9 Pack age Mech an i cal Dra wi ng ..................................................................................................... 24
9.1 32-Pin QFN ........................................................................................................................ 24
9.2 32-Pin TQFP....................................................................................................................... 25
10 Ordering Informati on ................................................................................................................... 26
11 Related Documentation ............................................................................................................... 26
12 Contac t Information ..................................................................................................................... 26
Revisi on H istor y .................................................................................................................................. 27
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 3
Figures
Figure 1: 32-Pin QFN Pinout ................................................................................................................ 6
Figure 2: 32-Pin TQFP Pinout .................................................................................................................. 6
Figure 3: Low Cost Design Using DSP R in g and Status M oni torin g ........................................................ 21
Fi gur e 4: 73M2901C E Wor l dwide Demo B oar d: Daughter Board Schematic .......................................... 22
Figure 5: BER versus SNR .................................................................................................................... 23
Figure 6: BER versus R eceive Level ...................................................................................................... 23
Figure 7: 32-Pin QFN Drawin g ............................................................................................................... 24
Figure 8: 32-Pin TQF P Drawing ............................................................................................................. 25
Tables
Table 1: 73M2901CE QFN and TQFP Pinout ........................................................................................... 6
Tabl e 2: Lease d Li ne Initi al ization Commands ....................................................................................... 16
Tabl e 3: Approximate Thr esholds for Energy Ring Detection .................................................................. 17
Tabl e 4: 73M2901CE Order Nu m ber s and Packaging Mar ks .................................................................. 26
73M2901CE Data Sheet DS_2901CE_031
4 Rev. 3.4
1 Hardware Description
The 73M2901CE is designed to operate from a +3.6 to +2.7 volt supply with low power consumption
(~30 mW @ 3.0 volts). Th e modem su pports aut om atic standby idle m ode. Th e mod em will also accept
a request to power d own from t he D TE via h ar dware co ntrol . N o addi tional major components ar e
requir ed to co m pl ete the modem core logic. The modem provides direct fir mware LED support via the
po r t pins (pi n s 3 , 4, 5, 6, 31 , an d 32) .
The 73M2901 CE includes the following hardware features:
• Fully self-contained. “AT” Command int er preter and data pump.
• Use r pins availab le.
• S ynchronous seri al data I/ O available.
• A sy nchronous ser i al p or t.
• On-chip hybrid and line driver.
• Autobaud capability from 300 bps to 9600 bps.
• Reduced external hardware support required with energy incoming ring detection.
1.1 Po wer Sup ply
P ower is supplied to th e 73M 2901C E by the VPD and VPA pins. The 73M2901CE is designed for a
single +3.6 to +2.7 volt supply and for low power consumption (~30mW @ 3.0 volts). Gr o un d is suppl i ed
t o the 73M2901C E by the VND and V NA p ins.
The 73M2901CE has been designed with separated analog and digital supplies to insure the best
performance of the part by using separately filtered pow er suppli es. It is recommended that separate
loca lly b ypassed trace s be used to apply power to the analog supply VP A and the digi tal supply VPD.
1.2 Low Power Mode
The Teridian 73M 2901C E supp or ts a low power standby mode. If t he l ow power standby option i s
enabled, the 73M2901CE will go i nto a power saving mode wh en idle.
Whil e i n thi s mode, t he oscill ator will be r unni ng and clocks will be supplied t o the UAR T, ti mers and
int e r r upt bl o cks, but no clocks will be suppl i ed to the CPU . Instruction processing and activity on the
internal busses is halted. Normal operati on i s resumed when an i nterr uption such as assertion of DTR or
RING occurs, a character is se nt to th e 73M 2901C E TX D input, or a r eset occurs.
1.3 Anal og Lin e / Hy brid Int erf a ce
The 73M2901C E pr ovides a dif ferential an alog out put (TX AP and TXAN ) and a single-ended analog input
(RX A) with i nternal A/D and D/ A converter s. A driver is provided for an internal hybrid function.
The internal hybrid driver is capable of driving an external load matching impedance and a line-coupling
transformer. The i nternal hybrid/ l ine d r iver sense s the load and adapt s itse lf to i ts requir emen ts.
The 73M2901C E pr ovides firmware control for a hook relay driver (RELAY) as well as i nterr upt sup por t
for a ring detect opto-coupl er ( RING).
1.4 Interrupt Pins
The external interrupt sources, DTR and RING, co me from dedicat ed inp ut pin s of the same name.
DTR informs the 73M2901CE that the host has requested the 73M2901CE to perform a specific function.
The function of DTR can be changed by “AT” commands ( described in the 73M2901CE AT Command
Use r Guide).
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 5
RING is used to inform the 73M2901CE that the external DAA circuitry or ring energy detector has
det ected a ring signal . It wil l go active when each “RING” m essage is sent on R XD.
In addition, sending any character on the TXD line al so generates an i nternal int er r upt.
1.5 C ry st al O sc il l at or
The Teridian 73M 2901C E single chip modem can use an external 11.0592 MHz reference cl ock or can
generate a cl ock u sing onl y a cr ystal and two capacit or s. If an external clock is used, it should be applied
to the OSCIN pin.
1.5.1 S p ecifying a Crystal
The manufactur er of a crystal resonator verifies its frequency of oscillation in a test set-up, but to ensure
t hat the same frequen cy i s obtained in the appli cation, t he circuit conditions must be the sa me.
The Teridian 73M 2901C E modem r equi r es a paral l el mode (anti-resonan t) crystal, the im por tant
specificat ions of whi ch are as follo ws:
Mode: P ar allel ( anti -resonant)
Frequency: 11.0592 MHz
Frequency tol er ance: ±50 ppm at ini tial t em perature
Temperature drift: An additional ± 50 ppm over ful l range
Load capacitance: 18 pF to 22 pF
ESR: 75 Ω max
Drive level: Less than 1 mW
The peak vol tage level of the oscil l ator should be checked to assure it will not violate the maximum
voltage levels allowed on the oscillator pins. A resistor i n seri es wi th the cr ystal can be used, if
necessary, to reduce the oscillator’s peak vol tage l evels.
Crystal s wit h l ow E SR s may oscillate at hi gher than sp ecified voltage levels.
1.6 Reset
A r eset is accompli shed by hol din g the R ESET pin hi g h. To ensure a proper pow er-on r eset , the rese t
pin must be held high for a minimum of 3 µs. At p ower on, t he voltage at V PD , VPA, and R ESET must
come up at the sa me t ime for a proper reset.
The signals DCD, CTS and DSR will be held inactive for 25 ms, acknowledging the reset operation, within
a 250 ms t ime win dow a fter the rese t-triggering event. The 73M 2901C E i s ready fo r operati on after the
250 ms window an d/or after the signals DCD, CTS and DSR become acti ve.
1.7 Asynchronous and Synchrono us S erial Data In t er f ac e
The serial data i nterface consists of the TXD and R XD data paths ( LSB shifted in and out first) and the
TXCLK and R XCL K serial synchr onous cl ock out puts associ ated wit h the data pins; CTS/RTS flow
control; DCD, DSR and DTR. In asyn chronous mode, t he data is passed at t he bi t rate (toler ance is +1% ,
-2.5%).
73M2901CE Data Sheet DS_2901CE_031
6 Rev. 3.4
2 Pinout
The 73M2901C E i s availabl e i n a 32-pin QF N or 32-pin TQFP package. Table 1 lists the pins for both
packages.
Table 1: 73M2901CE QFN and TQFP Pinout
Pin Name Pin Name Pin Name Pin Name
1 VND 9 RESET 17 VND 25 VPD
2 VPD 10 VPA 18 OSCOUT 26 RXD
3 DCD 11 TXAN 19 OSCIN 27 RXCLK
4 DSR 12 TXAP 20 VPD 28 DTR
5 CTS 13 VREF 21 NC 29 USR20
6 RTS 14 VBG 22 VND 30 RING
7 USR11 15 RXA 23 TXD 31 RELAY
8 USR10 16 VNA 24 TXCLK 32 RI
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
VND
VPD
DCD
DSR
CTS
RTS
USR11
USR10
TXCLK
TXD
VND
NC
VPD
OSCIN
OSCOUT
VND
RESET
VPA
TXAN
TXAP
VREF
VBG
RXA
VNA
TERIDIAN
73M2901CE
VPD
RI
RELAY
RING
USR20
DTR
RXCLK
RXD
Figure 1: 32-Pin QFN Pinout Figure 2: 32-Pin T QF P Pinout
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
VND
VPD
DCD
DSR
CTS
RTS
USR11
USR10
TXCLK
TXD
VND
NC
VPD
OSCIN
OSCOUT
VND
RESET
VPA
TXAN
TXAP
VREF
VBG
RXA
VNA
TERIDIAN
73M2901CE
VPD
RI
RELAY
RING
USR20
DTR
RXCLK
RXD
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 7
3 Pin Descriptions
3.1 Power Pins
Pi n Na me Pin Number Type Description
VPA 10 I P ositive analog voltage (anal og supply)
VNA 16 I Negative analog voltage (anal og ground)
VPD 2, 20, 25 I P ositive digi tal voltage (digital supply)
VND 1, 17, 22 I Negati ve digi tal voltage (digital ground)
3.2 Analog Interface Pins
Pi n Na me Pin Num ber Type Description
RXA 15 I Receive analog input
TXAN 11 O Transmit analog - output
TXAP 12 O Transmit analog + output
VBG 14 O Analog Band Gap volt age r eference (0.1 µF to VNA). This pin
must not be co nnected t o ext er nal ci r cuitry other th an the
decoupl i ng capacit or .
VREF 13 O A nalog reference voltage (0.1 µF to VNA)
3.3 Digital Interface Pins
Pi n Na me Pin Number Type Description
RESET 9 I Reset
RXCLK 27 O Rece ive d ata synchronous cl ock, valid on rising edge
TXCLK 24 O Transmit data synchronous clock, valid on rising edge
TXD 23 I Serial data input from DTE
RXD 26 O Seri al output t o DTE
USR10 8 I/O Programmable I/O port. T hi s pin can optionally be used to
control an external switch for external Line In Use circuitry.
USR11 7 I/O Programma ble I /O po r t. This pi n ca n opt iona l ly be use d to
control an external switch for ca ller ID oper ation.
RTS 6 I Request to se nd
CTS 5 O C l ear to send
DSR 4 O Data se t ready
DCD 3 O Data carrier detect
RI 32 O Ring indicator
RELAY 31 O Relay d riv er output
USR20 29 I/O Programmable I/O port
73M2901CE Data Sheet DS_2901CE_031
8 Rev. 3.4
3.4 External Interrupt Pins
Pi n Na me Pin Number Type Description
RING 30 I External interrupt – Line interface ring detection circuitry input
DTR 28 I External interrupt – DTE DTR signal input
3.5 Oscillator Pins
Pi n Na me Pin Number Type Description
OSCIN 19 I Crystal inpu t for in ternal oscillat or , also input for extern al source
OSCOUT 18 O Crystal oscillato r ou tput
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 9
4 Electrical Specifications
4.1 Absolute Maximum Ratings
Parameter Rating
S upply Voltage -0.5 V to +4.0 V
P in Inp ut Voltage (except OS CI N ) -0.5 V to + 6.0 V
P in Inp ut Voltage (OSCIN) -0.5 V to VPD + 0.5 V
S torage Temperature -55 ºC to 150 ºC
A bsolute maximum ratings ar e st ress rat in gs ONLY, functional oper ati on of the devi ce at t hese
or any other conditions above those i ndicated in the recommended oper ati on sections of t hi s
sp ecification is not imp lied. Exposur e to abso lut e maximum co ndi tions for extended period s of
time m ay affect reliability.
4.2 Recommended Operating Conditions
Parameter Rating
S upply Voltage 2.7 V to 3.6 V
O scill ator Frequency 11.0592 MHz +/- 50 ppm
O per ating Temperature -40 ºC to 85 ºC
4.3 Receiver
Parameter Conditions Min Nominal Max Units
Carrier Detect On Tip an d Ring -43 dBm0
1
Carrier Detect Off
Tip an d Ring -48 dBm0
1
Carr ier Detect Hysteresis Tip and Ring 2 dB
Rece ive L evel Tip and Ring -43 -9 dBm0
1
Idle Channel Noise 0.2 kHz to 4.0 kHz -70 -65 dB
Input Impedance RXA 150 kΩ
Rece ive Gai n Boost S1 10 bi t 5= 1 , CI D mode 18.8 19.3 19.8 dB
Max Input Level at RX A VREF=1.25 V 0.587 0.622 0.658 Vpk
Total H ar monic Distor ti on
(THD) 1kHz 450 mVpk on RXA
THD=2nd and 3rd harmonic -70 -50 dB
1 dBm0 refers to the Ter i dian r ecommended line interface (8 dB loss from t r ansmi t pi ns t o the line an d
5 dB l oss from th e line to t he r eceiver pin) . Results may vary depending on the selected DAA
compon ents. 0dBm=0. 775 m Vrms; dBm=10log(Vrms2/(1mW)(600Ω))
73M2901CE Data Sheet DS_2901CE_031
10 Rev. 3.4
4.4 Transmitter
Parameter Conditions Min Nominal Max Units
I TU Guard tone power 550 Hz (relative to carr ier) -5 -3.5 -2 dB
1800 Hz (relat i ve to car rier) -8 -6.5 -5 dB
Calling Tone 1300 Hz -11 -10 -9 dBm0
1
A nswer Tone power
2225 Hz / 2100 Hz -11 -10 -9 dBm01
DTMF Transmit power Hi gh ba nd tones -12 -11.5 -11 dBm0
1
Low band tones -13.7 -13.2 -12.7 dBm01
G ai n adju st t ol er ance By step -0.3 0 0.3 dBm0
1
Total H ar monic Distor ti on
(THD) 1 kHz sine wave at output
(TXAP-TXAN)
1.5 Vpk (2.7 dBm) for
VREF=1.25 V
THD=2nd and 3rd harmonic
-50 dB
I ntermod Distortion At output (TXAP-TXAN)
1 kHz, 1.2 kHz sine waves
summed
2 Vpk for VREF=1.25 V
Ea c h unwante d
frequency component -33 dBm
Sum of unwa nted
frequency components
in pass ba nd
-20 dB
below
low tone
Power supply rejection
ratio -30 dBm signal at VPA
300 Hz to 30 kHz
measur ed TX AP to TXAN 30 dB
4.5 Maximum Transmit Level
Parameter Conditions Min Nominal Max Units
QAM VREF=1.25 V
VPA=3.3 V -9.6 dBm01
DPSK VREF=1.25 V
VPA=3.3 V -7.4 dBm01
FSK VREF=1.25 V
VPA=3.3 V -5.3 dBm01
D TMF (High Tone) VREF=1.25 V S13=$20,
VPA=3.3 V S85=80 -8 -7 dBm01
DTMF (Low Tone) VREF=1.25V S13=$20,
VPA=3.3V S85=80 -9.7 -8.7 dBm0
1
1 dBm0 refers to the Ter i dian r ecommended line interface (8 dB loss from t r ansmi t pins to th e l in e and
5 dB l oss from th e line to t he r eceiver pin) . Results may vary depending on the selected DAA
compon ents. 0dBm=0. 775 m Vrms; dBm=10log(Vrms2/(1mW)(600Ω)).
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 11
4.6 DC Characteristics, Vcc = 3.3 V
(Vdd stands for V PD and VPA)
Parameter Symbol Conditions Min Nom Max Unit
I nput low voltage ( except OSCIN) VIL -0.5 0.8 V
I nput low voltage OSCIN VIL -0.5 0.2 Vdd V
Input high volt age ( exce pt OS CI N ) VIH 0.7 Vdd +5.5 V
I nput high voltage OS CI N VIH 0.7 Vdd Vdd+0.5 V
Output low vol ta ge (except OSCOUT ) VOL IOL=4 mA 0.45 V
O utput low voltage OSCOUT VOLOSC IOL=3 mA 0.7 V
Output hi gh vo lta ge (ex cept O SC OUT) VOH IOH=-4 mA Vdd-0.45 V
O utput high voltage O SC OUT VOHOSC IOH=-3 mA Vdd-0.9 V
Input lea ka ge cur rent (except OSCIN) IIH Vss<Vin<Vdd 1 µA
I nput leakage cur r ent OSCIN IIH Vss<Vin<Vdd 1 30 µA
Parameter
Conditions Min Nom Max Unit
VBG Vdd=3.3 V 1.19 1.25 1.31 V
VREF Vdd=3.3 V 1.19 1.25 1.31 V
TXAP to TXAN offset Vdd=3.3 V, steady state 50 mV
4.6.1 DC Supply Current, VDD = 2.7 V (Batter y E OL)
Parameter Symbol Conditions Min Nom Max Unit
Maximum power suppl y,
normal oper ation IDD1 30 pF / pi n 9.5 10.5 mA
Maximum power suppl y,
I dl e mode IDD2 30 pF/pin 900 1500 µA
Maximum power suppl y,
Power Down mode IDD3 30 pF/pin 10 µA
4.6.2 DC Supply Current , V DD = 3.0 V
Parameter Symbol Conditions Min Nom Max Unit
Maximum power suppl y,
normal oper ation IDD1 30 pF/pin 10.6 11.9 mA
Maximum power suppl y,
I dl e mode IDD2 30 pF/pin 1.1 1.7 mA
Maximum power suppl y,
Power Down mode IDD3 30 pF/pin 10 µA
73M2901CE Data Sheet DS_2901CE_031
12 Rev. 3.4
4.6.3 DC S u pply Cur r en t VDD = 3.3 V
Parameter Symbol Conditions Min Nom Max Unit
Maximum power suppl y,
normal oper ation IDD1 30 pF / pi n 11.8 13.6 mA
Maximum power suppl y,
I dl e mode IDD2 30 pF/pin 1.25 1.85 mA
Maximum power suppl y,
Power Down mode IDD3 30 pF/pin 10 µA
4.6.4 DC S upp ly Cu rrent VDD = 3.6 V
Parameter Symbol Conditions Min Nom Max Unit
Maximum power supply, normal
operation IDD1 30 pF / pi n 13.4 15.5 mA
Maximum power suppl y, Id l e mode IDD2 30 pF/pin 1.4 2.0 mA
Maximum power suppl y, P ower
Down m ode IDD3 30 pF / pi n 10 µA
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 13
5 Firmware Description
A n “A T” co mmand interpreter pr ovides command and configuration of the 73M2901CE. This provides the
user a uni form interface to con trol t he mod em in embedded appli cat ion s. The signal pr ocessing i s
performed to provide data to the D AC an d pr ocess dat a from t he A/D converter . A MAC har dware
copr ocessor i s provided for comput ation.
To provide maximum flexibil ity, t he system host pr ocessor can access the internal RA M and C ontrol
Register space in the modem . This will allow the OEM use r to modi fy parameters such as filt er r esponse
and t r ansmit l evels t hrough the AT command set usi ng pr opr i etary co mmands. The h ost proce ssor can
also access t he modem I/ O port pins, pr ovidi ng ext ended I/O capability.
Refer to t he 73M2901CE AT Command User Guide for a complete description of t he software.
5.1 Firmware Overview
The modem always powers up in the idle (on hook) mode. “AT” commands ar e i ssued via the se r i al
interface from t he host. Al l m odem configuration commands are received in t hi s manner. The data
modem fir mware i s contai ned i n an i nternal ROM.
The fir mware will automatically enter a powe r saving idle m ode if the modem is on hook and th er e ar e no
incoming host commands. The modem automaticall y powers up upon rece i ving the next command. This
power up sequence occurs wit hout del ay t o the host. This function, while saving power, i s transpar ent to
t he host proce ssor and can be disa bl ed by the host via an “AT” comman d. Th e host can al so program
t he m odem to power do wn vi a an external pin (DTR) or via a firmware command.
5.2 Fir m w ar e Fe at ures
• “AT” comman d set
• Supports data standards through V.22bis
• P r ovides DAA co ntrol fir mware (e. g. ri ng detect, hook control )
• Multinat ion al Call Progress support (FCC part 68, ITU CTR21, Japan JATE, etc.)
• Caller ID capability
• FSK demodulation (V.23, V.21, Bell 202 and Bell 103)
• DTMF detection and deco di ng
• S electable number of rings and line r eversal for C ID data operation
• O n hook CID data operation
• On ho o k Line-In-Use detection support (No line seizure will occur when a Line-In-Use condition is
detected)
• Off hook Parallel Pick-Up de tection support (Line seizu r e will b e abor ted as soon as a P ar allel Pick-Up
condition is detecte d)
• Off hook voltage change detection (requires external ci rcuitry)
• Rece ive energy chan ge detection
• Dir ectly interfaces wi th stand ar d V.24/EI A-232 bus dr i vers (3. 3 V invert ed l evel) serial interface using
t he bui lt i n seri al por t and firmware cont r ol of p or t pins
• P r ovides t one gener ation and detection including four imprecise and four precise call progress d etect
filters with pr ogr ammable frequency and detecti on threshold
• Blacklistin g capability
• Long Space disconnect support
• Inactivity timeout
• Host access t o pr ogr am RAM provided
• Use r pr ogr ammable general purpose I/O
73M2901CE Data Sheet DS_2901CE_031
14 Rev. 3.4
6 Design Considerations
The 7 3M2 9 0 1CE single c hip mo dem inclu des al l t he ba sic modem func t ions . Programmable configuration
opt i ons make this device h ighly ad aptabl e to a wide vari ety of applications.
Unlike di gi tal l ogic circuitry, modem designs must co ntend wit h pr ecise frequ ency tolerances and verify
low-level analog si gnals to ensu r e acceptable per formance. Usi ng good anal og circuit design practice s
will general ly resul t in a sound design. The cr ystal oscillat or should be hel d to a 50 ppm tol er ance. The
recommendations in this section should be taken into consideration when starting new designs.
6.1 Layout Considerations
G ood anal og/digit al design rules m ust be used t o control system noise in or der to obtain high
performance in modem designs. The more digit al cir cuitry prese nt in the appl i cation, th e m or e attent ion
t o noi se co ntrol is needed.
High speed, di gital device s sh ould be l ocall y bypassed, and the t elephone line interface and the modem
should be located next to each other near wh er e the telephone l in e connection is accesse d. I t is
recomme nde d that power supplies and ground traces be ro uted separately to the analog a nd digi tal portions
on the board. Digital signals should not be ro uted near low-level or hig h impedance anal og traces.
The 73M2901CE should be consider ed a high per formance analog device . A 3.3 µF electrol yt ic capacitor in
parall el with a 0.1 µF Cera mic capacitor should be placed be tw een each VPD and VND pin a nd a 10 µF and
0.1 µF between VPA and VNA. A 0.1 µF ceramic capa citor s ho uld be placed be tween VREF a nd VN A a s
well as between V BG and VNA. Use of ground planes and large traces on power is reco m mended.
K eep OSCIN and OSCOUT si gnals as shor t as possible and l ocate t he crystal near the pi ns. U se an
11.0592 M Hz par al lel mode crystal onl y. Do not use ground planes under the oscillator cir cuit since this
will i ncrease the parasitic capacitance on the pins. The values of C2 and C3 depend on the load
capacitance r ating of the cr ystal that is used, not th e 73M 2901C E. This l oad capacit ance will typ ical ly be
between 15 pF and 27 pF, but usually 18 or 22 pF. Parallel resonant crystals are tuned with a specific
capacit ive load an d will b e wit hin their specifications wh en this load is used. Th is rating is th e
capacitance measured between the crystal pins including all parasitic capacitance s. I t i s not the values of
t he capacit or s used. Th e selection of t hese capacitors can vary with the layou t of the P CB, so do not
assume the values used with the 73M2901C E demo boar d ar e correct fo r al l desi gns.
S ystem noise i s the most l ikel y ca use of p oor C aller ID and l ow-level r eceive performance. The lowest
ampli tude signals th at the modem will need to receive are on th e or der of 5 mV rms. Th e C aller ID
rece ive levels are al so very low due to t he r equi r ement to have a high (60 kΩ) AC input impedance while
on hook. Having a 20 dB gain boost during C al ler ID recept ion comp ensates for this, but i f there is
excessive noise, i t will al so be amplified. Keepi ng the analog and dig it al gr ounds separ ate helps co ntrol
t he amoun t of noise t hat gets to the receive r inp ut. Dr amat i c im provements i n low-leve l performance can
be gained by proper layout.
K eep the VCC t r ace as short as possible. Make t he power t r ace a mi nimum of 0.5 mm thick. The anal og
and digital power and ground should be kept se par ate for best low receive level performance. Route t he
power to the digital pins and bypass capacitors on one net and the analog power and VBG bypass pins
on anot her net wit h inductors separ ating the two. If p ower planes are use d, se par ate the power and
ground planes so there ar e separate analog and digi tal planes for the 73M2901CE.
K eep all analog signal i ng away from any high-speed digital circuitry and tr aces that may b e on the board.
O bserve the separation of th e network and mod em side circuitry. Maintain at l east ¼ inch (6 mm )
separ ation between the two. Do not run power planes under the network side circu i try and maintai n the
same spacing for the planes from t he network. Use only UL, CSA, or TUV appr oved com ponents that
cr oss the i solation barr ier or for networ k protection to assur e compl i ant performan ce for the DAA.
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 15
The transf ormer use d for coupli ng will have an influence on t he values of the co mpon ents in the DAA
ci r cui try. The windin g r esistance, i nduct ances and other characteristics of the t r ansformer affect the
val ues of t he i mped ance matching com ponents. M ake sur e you have the transf ormer manufactur er ’s
reco mmended circuit valu es when using other transf or mers. Th e values can be determined t hr ough
simu lations, bu t may still require some adj ust ment to optimize the design.
6.2 73M2901CE Design Compatibility
The Teridian 73M 2901C E i s an enhanced version of the Teridian 73M 2901C L and has a number of
additional features. These par ts are highl y compat ib le with the earl i er 73M 2901, however, users should
pay special att ention when changing an existing 73M2901 design to use the 73M2901CE or 73M2901CL.
From a hardware standpoint, the key di fference s involve t he U ser I/O pin s USR10 and U SR1 1, the
ASRCH pin and the HBDEN pin. An addi ti onal user I/O pi n, USR20, r epl aces the ASRCH pin on the
73M2901CE. Thi s pin may remain safely co nnected to TX D as long as th e host soft w are does not
reconfigure USR20 as an output (S104 bit0=0).
The 73M 2901CE contains a hi gh-ef fi cie ncy , low-power hy brid driver . Due to this enhancement, HBDEN is no
longer required. This pin is an internal no-co nnect a nd ca n safely re main co nne c te d to its previo us VPD or
GND. T he f unctions of USR 10 a nd USR 11 are relate d to Ca ller ID and Line In Use/ Para llel Pickup suppor t.
Software enhancem ents to the 73M2901CE ar e typ ical ly achieved by th e addit i on of new AT commands.
The device can be considered a superse t of the 73M2901CL a nd 73M2901C . When converting a design to
the 73M2901CE, it is recommended that the user check the commands and regist er sett ings for backward
compa tibility to the earlier parts (refer to the 73M2901CE AT Command User Guide for complete details).
6.3 Telephone Line Interface
Transmi t levels at the line are dependent on the interface used bet ween the pins and the line. T he inter nal
hybr id line dr i vers elim inate the need for additional active ci rcuitry t o dr ive the line-coupling transformer.
The anal og outputs TXA P and TXAN can be conne cte d directly to the tra nsformer (w ith the re quired
impedance ma tching series resist or or n etwork) . Depe ndin g upon transf o rme r de sign ( spe ci fi ca l l y dr y
t r ansf or mers), op er ati on may be affected by the limi ted a mount of DC current genera ted by the analog
outpu ts (DC offset). For th is r eason, Teri di an recommends using a coupling capacitor with those
transformers to insure maximum performance.
The l i ne in terface ci r cui ts shown in Section 7 Referen ce Designs represent the basic components and
values for i nterfacing the Teridian 73M2901CE analog pins to the telephone line. The values of these
compon ents have been calculated t o minimize the transmission and recept i on path hyb r i d losses and ar e
linked by the following equation: R3 and R6 i n Figure 3 and R15=0.242 x R13 in Figure 4.
73M2901CE Data Sheet DS_2901CE_031
16 Rev. 3.4
6.4 Functional Considerations
6.4.1 S MS and V.23 Half Dup lex
S M S ( Short messag ing S er vices) is the co m munica ti ons mode use d to transmit t ext messages for cel l
phon es and even tually wire l i ne phones as well ( see the 73 M 29 01CE SM S an d H al f Du pl ex V . 23
Operation application note). The V.23 half duplex mode has been inclu ded with t he addi ti on of the B1 0
comm and (ATB10). The B10 command allows the used to turn the transm itter on and off using the se r i al
interface RTS signal . In this way the modems can easil y communicat e in half duplex mode usi ng RTS to
enable transmission and CTS to indi cate t he modem is r eady t o send dat a. Th e V.23 receiver response
t i me has also been improved to all ow f or fast line turnaround (r eversa l of the data flow). The pat tern
generator has also been mod ified t o send th e pr oper al ternati ng pattern used in the SM S handshake.
S M S m essaging is very si milar to the format used for Caller ID , so the 2901CE can als o be used t o send
Caller ID messages to equ ipment desi gned to use and di splay Cal ler ID informat i on. A typi cal command
line for a di al up connection would be: ATY0B10S73-32C2 R 2S10=255< CR>. These co mmands ar e
broke n out as follows:
Y0 Clear channel mod e (1 20 0 bps)
B10 V .23 HDX gated by RTS
S73-32 N o 125m S wait between com man ds
C2 DCD follows the raw received carrie r
R2 Toggle DTR to ha ng up
S10=255 Disable l oss o f carrier timeout
Note t hat RTS/CTS flow control cannot be used when using V.23 half duplex since RTS is used to turn
t he carri er on and off. XON/XOFF flow cont r ol should be used instead if flo w control is needed. The
transmitter RTS to carrier on delay t ime is 10mS and t he off delay is 5m S.
6.4.2 Leased Line Mo de
O ne of the drawbacks to the earlier 73M2901 modems is that they are designed prim arily for dial-up
modem applications. Thi s made it difficult to use them in some n on-dial-up designs. The 73M2901CE
adds a l eased li ne mod e that all ows a modem t o go int o the data mode without having t o go through a
normal handshake or the need for a connection to anoth er modem. The l eased line mode is enabled
usi ng the @L1 command i n the ini ti al ization stri ng. The 73M 2901C E l eased li ne mod e should not be
t hought of as l imited to only lease d l ine. It is also suited to radio links and any ap plica ti ons where the
modem needs to be r eady to go when it is first connected. L eased line m ode can be used with all
modulation modes that are su ppor ted by the 73M2901CE. Table 1 sh ows typ ical command initial i zation
str i ngs tha t can be used.
Table 2: Leased Line Initializat ion Commands
V2 2bi s LL ATFS99=1Y6K3C1R2S30=4S70=12S26+4O2@L1
V 22 LL ATFS99=1Y6K3C1R2S30=8@L1
B212 LL ATFS99=1Y6K3C1R2S30=16@L1
B103 LL ATFS99=1Y6K3C1R2S30=32@L1
B202 RX LL
B2 02 TX LL ATFS99=1Y6K3C1R2B5@L1
V 23 HDX LL ATFS99=1Y0C2R2B10@L1
V 23 TX1200 LL ATFS99=1Y6K3C1R2B3@L1
V 23 TX75 LL ATFS99=1Y6K3C1R2B2@L1
V 21 LL ATFS99=1Y6K3C1R2S30=64@L1
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 17
These commands are b r oken out as follows:
F S et to factor defaults
S99=1 S et to U.S confi gurati on ( default)
Y0 Used clear channel mode (no speed buffering)
Y6 Use D TE/ D CE speed buffering
K3 Use RTS/CTS flow con trol
C1 Use qualifi ed carrier detection
C2 Use raw carrier detection
R2 Di scon nect on DTR toggle
S30=n S et S30 t o a modulation mode
Bn Set to modulation mode
O2 Respond to retrai n r equests
S26+4 E nabl e auto retrai n r equests
S70=12 Lower retrain request threshold to 12
@L1 L eased li ne mode
O nce th e in it i aliza ti on string i s given, the modems are started by sending ATD t o one modem and A TA to
t he other. The m odems will t hen begi n sending ca r r iers and l ook fo r carrier from the other modem. When
the modems disconnect using R2 and DTR, an “OK” r esult co de i s se nt on RXD. The modem will stop
sendi ng carri er at the end of the OK message, the delay time det er mined by the DTE speed an d the tim e
it t akes to output the message.
It is important to note the auto retrain feature (O2) should be enabled when using V.22bis. V.22bis
requires training when it connects and auto retrai n i s off b y defau l t. Make sure “ S26+ 4” i s also sent so it
can al so ini ti ate a retrai n as wel l .
6.4.3 73M2901CE Energy Ring Detection
The 73M2901C E has a featur e that was add ed with t he int ention of lowering the total modem cost by
eliminating some of t he m or e expensi ve external comp onents. Th e threshold for the ring d etector
depen ds on the setting of t he S123 register and the co m ponents in t he C aller ID path, especial ly the
t r ansf or mer. The number that S12 3 is set to repr esents the amplitu de threshold of the ring signal ( see
Tabl e 2). In a conventional ring detect circuit the threshold is set by the hardware, usually the values of
t he Zener diodes used i n the ri ng detect ci r cuit.
Table 3: A pproxima t e Thr e s holds for Energy Ring Detec ti on
Typ ic al U S W et Trans f o rmer
S123 Register Setting with Frequency Checking
20 15 10 5 3
V r ms m in off to on 45 34 24 12 7
Vrms min on to off 42 32 22 10 5
Typi ca l ETSI TS 203 Dry Transformer Design
S 123 Reg ister Setting with Frequency Checking 20 15 10 5 3
V r ms m in off to on 5 5 5 5 5
Vrms min on to off 5 5 5 5 5
Having th e ability t o set the threshold over a wid e ran ge through the S123 register eliminates the need to
change components to adjust t he r i ng detection se nsitivity. Energy ring detection uses t he C aller ID path
and coupl i ng transformer to path t o pass the i ncoming r ing signal to the modem so it ca n detect the ri ng
si gnal u sing the internal DSP. In an average design thi s can save at l east $0.35 i n the total parts cost or
even more in lower volume products. The 73M2901CE is still compatible with the earlier 2901 products
and still supports the opto-coupled ring detection method, although not on our current demo boar ds. We t
t r ansf or mers gener al ly have poorer frequency response in the ring frequency range than dry
t r ansf or mers. This means that th e threshold mu st be sent to a low er number for wet transf or mers than
with some V.9 0-rated dry t r ansf or mers. This also mean s that lower frequency r in g signal detection will
also r equire a lower setting. The r ange of va lues for S123 ca n be from 1 to 127 wh en checking frequency
73M2901CE Data Sheet DS_2901CE_031
18 Rev. 3.4
or 129 to 25 5 when not checking frequency. The pr actical range i s from 3 to 30 when checking
frequen cy , depending on the transfor mer, Caller ID se r ies r esistor, capacitor, and the ring frequency.
The other rin g par amet er s such as r i ng frequency ( S17 and S18) and cadence (S51-S58 ) stil l need to be
programm ed when using energy ring detection.
Th e typical initialization strin g for ring d et ect ion an d auto answer for the U.S. would be:
ATS123=7S0=1<CR><LF>
For other count r ies, the oth er r in g par amet er s should also be i ndivid ual ly pr ogr ammed, or t he S99
register ca n be used t o pr ogr am al l t he count r y parameters.
6.4.4 Caller ID Mode Chang es
The C al ler ID modes have also had some enhancement s. There is now two di fferent types of TYPE II
cal ler ID; normal TYP E II and snoop m ode TYPE II.
Normal T YPE II C aller ID is on wh en S110 bit 3 i s t urn ed on. Th e mod em mu st be of f hook ( in use) for
this mode to be active. When the modem detects an al er ting tone tell i ng it that a call is wai ting and that a
Caller ID message is about to be sent, t he m odem then send s a DTMF digit “D” to notify the C O that A
TYPE I I C al ler ID device i s prese nt. The CO then se nds th e Caller ID message, and after receivin g the
message the 73M2901CE will go on-hoo k (ha ng u p) .
TYPE I I snoop mode is enabled wh en S95=$99 (99 hex). In thi s mode the modem wi ll repor t ei ther a
TYPE I or TYP E II Cal l er ID m essage wh en the modem i s on hook. If anot her C aller ID device is off hook
t he m odem wil l det ect th e C aller ID handshake and output th e C aller ID data, but the 73M 2901CE wil l not
actively participate ot herwise.
TYPE II Caller ID performance has been improved and, using proper coupling circuitry to monit or the CID
si gnal, the 73M2901C E can pass all EIA-777A tests.
6.4.5 S electable An swer Tone Frequency Detection
I t is now possible to se l ect whi ch frequencies will be d etected as an answer tone duri ng the handshake.
A new S r egister, S120, h as been added for t his purpose. Thi s adds some flexibility to the handshake i n
dial-up appli cations. The register bit defini tions are as f ol lows:
Bit 0 1650Hz – V 21 M ar ks ( defaul t)
B it 1 1300Hz – V 23 M ar ks
Bit 2 2100Hz – I TU Answer Tone ( default)
Bit 3 Reserved
Bit 4 2225Hz – B ell Answer Tone ( default)
Bit 5 2250Hz – S 0 ( default)
B it 6 Reserved
B it 7 Reserved
6.4.6 73M2901CE S99 Cou n try Code Support
A feature of th e 73M2 901 family o f modem IC s is t he count r y confi gur ation r egi ster S99. Thi s register
can be used t o p r ogr am a variety of co untry parameters with a singl e r egi ster se tting. See t he
73M2901CE AT Command User Guide i f the countri es you ar e i nterested are not listed for S9 9; the
individual parameters can still be programmed through the S-registers. Tables with all the register
settings control l ed by S99 are provided. B y finding the co untry with the se ttings closest t o wh at are
requir ed, you can minimize t he num ber of regi sters that need t o be pr ogr am med . The fol lowing
information can be used to tail or the behavior of the 73M2901CE for specific support for countries not
listed for S99.
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 19
6.4.6.1 Rin g Detection Parameters
The ring detector is programmable in a num ber of ways. S-registers S 17 and S18 cont r ol the frequency
range of t he ring frequ encies th at are vali d. R i ngin g tones ou tside these sett i ngs will not be detected.
S-registers S51-S58 d etermine the cadences ( on and off t i ming of t he tones) th at are allowed. Either one
of two d if ferent ca dences can be accept ed or a dual cadence can be defined, depending on the se tting of
bit 6 in regi ster S29. S123 enables the energy ring det ection feature. With S123 set to 0, energy ring
det ection is disabled and the opt ocoupler input i s used as in the 73M2901CL. Wi th S123 se t to a
non-zero number , the ampl it ude threshold and wh ether the ri ng frequency is checked ca n be cont r olled.
6.4.6.2 Dial Tone Parameters
The di al tone paramet er s can al so be co ntrol led over a w i de r ange. S29 co ntrol s whether a con ti nuous
dial tone (bit 7=1, the default), one of two different single cadences (b it 4=0, default) or a dual cadence
(bit 4=1) dial tone will be detected. Regi sters S35 – S42 , cont r ol the two cadences’ on and off t i mes.
There is al so co ntrol for the tones that are detected as valid. Register S20 cont r ol s whether pr ecise
frequenci es wi ll be detected or a band of frequencies selected as a va l id. S20 also se l ects wh ether an
individual tone or al l t ones sel ected by S19 m ust be detected. The l ow nibble of regi ster S19 se l ects
which tones will be used for di al tone detecti on. Register S88 se lects the imprecise frequency r ange for
imprecise detection mode.
I n addi ti on register S66 determin es the maximum tim e to wait for di al t one, S67 t he tone qualification
duration, and S 75 and S77 select the mi nimum l evel for detecti on for i mprecise and pr ecise t ones,
respectively.
6.4.6.3 Bus y Tone Parameters
The busy tone parameters ca n al so be controlled ove r a wide range. S29 control s whether one of two
different single cadences (bit 5=0, default) or a dual cadence (bit 5=1) dial tone will be detected.
Registers S 43 – S50, cont r ol th e two cadence s’ on and off times.
There is al so co ntrol for the tones that are detected as valid. Register S20 cont r ol s whether pr ecise
frequen cies wi l l be det ected or a band of freq uencies sel ected as a vali d tone. S20 also selects wh ether
an individual tone or al l t ones sel ected by S19 must be det ected. The high ni bble of reg ister S19 selects
which tones will be used for busy tone detection. Reg i ster S88 selects the imprecise frequency r ange for
impr ecise det ection mode.
I n addi ti on, regi sters S 76 and S78 se lect the mini m um level for detection for i mprecise and precise t ones,
respectively.
6.4.6.4 P ulse Dialing
Registers S 32 through S34 co ntrol the ti ming of pulse di aling. S 32 sets the duration of off h ook switch
closure (make ti me). S33 cont r ols the off h ook open t ime (break t ime). S34 controls the time between
digits. S32 and S33 times are in ms, while S34 is in 10 ms increments.
S ome countri es use di fferent pulse pat terns t o r epr esent the digit s, so S72 can be used to set the pulse
pat tern so digits are co r r ectly sent. The default is t he m ost common, where the d igit equals th e numb er
of pulses, except for 0, which is 10 pulses.
6.4.6.5 DTMF Dialing
DTMF on and off timing can be adjusted by S11. Th e r equirements for the timing can var y with different
countri es. The D TMF transmi t levels can be adj usted using t he upper nibble of register S13 and t he twist
(level of the lower frequency relative to the higher frequency) can be changed using S12 bits 4-6 .
A ddit i onal ad justment of t he transmit l evel i s provided by S85, but setting S85 at too hi gh of a level can
also incr ease the THD, so restraint is advised. DTMF should be transmitted at the highest level allowed
by count r y specific li mitations, but do not exceed t hi s li mit.
73M2901CE Data Sheet DS_2901CE_031
20 Rev. 3.4
6.4.6.6 Calling Tone
Calling tone is enabled by se tting S28 bit 7 to one. S15 se ts th e call i ng tone off time in 100 ms
increments and S16 set s t he call i ng tone on time in 10 ms increments.
6.4.6.7 Call Pr ogress and Data C arrier Tr ansmit Levels
The l evels for the carri er and call progr ess t ones (ca l ling tone, answer tone) can be adjusted using the
lower n ibb le of S13. Thi s ca n be used t o compensa te for transmit path losses and t o adj ust for t he
highest transm it levels allowable with a particular hardware configuration and cou ntry li mitation. The call
progress and data levels can only be changed in 2 dB increments, therefore S13 bit 3 is ignored.
6.4.6.8 Caller ID – Type I and Type II
The 73M2901C E supports worldw i de Caller ID ( CI D ) standards. M ost of the CI D controls are in r egister
S 95, but so me are also fou nd i n other r egi sters. Looking for the Ja panese CID and T ype II snoop mode
Marking preamble are co ntrol led by S72 bit 5. S72 bi t4 con trols Japanese on-hook CI D m ode. CID
wetting pulse control is controlled by S72 bit 3. Type II CID is enabled with S110 bit 3. When a Type II
CID messag e is detected, the modem will go back on hook aft er the message i s retri eved.
Register S95 co ntrol s all other aspects of t he C ID m ode, such as FSK or D TMF C ID , aler ti ng tone
det ection, th e num ber of line reversal s or rin gs before CID is expected, and enabling CI D . Th er e is al so a
continuous CID m ode and a D TMF r eceive mode wi thout a prece di ng “ CI D :” so DTMF di git s can be
detected. When S95 is set to 99 Hex (ATS95=$99) both US Type I and Type II sn oop mode ar e enabl ed.
6.4.6.9 ITU A nswer Tone Phase R eversals
The 73M2901CE supports ITU answer tone 180º phase reversal s during the handsh ake. S etting S92 bit
6 enab les phase reve r sals and is set t o zero by d efaul t (no phase reve r sals).
6.4.6.10 1200 BP S Fast Connect Mode
The 73M2901C E supports the fast conn ect handshake used in P OS termin al application s. Both Bel l
21 2A and V.22 fast conn ect are supported for t he call i ng side. It does not support the answering fast
connect as exactl y defined, but the Ln com mands can be used to shorten th e handshake ti me. To use
t he call i ng fast connect handshake, Set register S89 bit 5 (ATS89+6 4) and set regist er S30 to Bell 212A
only (ATS30=16). This applies to both Bell 212A and V.22 since the originating side handshake is the
same for bot h modes. S etting S30 to any other value will overri de the ori ginat e fast connect mode. Th e
origi nati ng fast connect mode will send flags in stead of marks i f the modem i s set for synchronous mode
(Y1 or Y4).
For the answering side, the L1 co m mand will byp ass t he bi l ling delay and answer t one to significantly
speed up the handshake. Thi s will wor k wit h the ori gi nating Bel l 212A or V.22 fast co nnect or normal
connect, as well as the stan dar d V.22 bis co nnection. O f course the fastest connect ion s will be with Bell
212A and V.22 operating in the fast connect mode. L2 wil l still use the 2-second billing delay, but the
2-second answer tone will not be sent. L3 will use t he normal billing delay, and se nd a short 400 ms
answer tone. L1 will give the fastest handshake with the 1200 bps or ig inat e fast connect mode enabl ed.
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 21
7 Reference Designs
7.1 Low Cost Design U s ing DSP Ring and Status Monitoring
Figure 3: Low Cost Design Using DSP Ring and Status Monitoring
73M2901CE Data Sheet DS_2901CE_031
22 Rev. 3.4
L3
NLV32T-4R7J-PF
L4
NLV32T-4R7J-PF
C29
220pF, 3k V
R20
20K
C26
82nF
VCC3_3A
Q1
MMBTA06 B
E C
R17
100
-E MIT4033 is required f or Austalia only;
t he non- enca psulated MIT4033 can be
used f or designs not r equir ing Austalian
operation.
VCC3_3D Q2
MMBTA06 B
E C
Q3
BCP-56
1
2
34
U2A 74LVC4066D
12
13
AUST
U2B 74LVC4066D
11 10
12
-This version suppor t s only:
---Ring-E
---PPU-E
---LIU-E
D1
RS1G
CTR-21
US600
CTR-21
AUST
US600
U2C 74LVC4066D
SOIC14
43
5
-To use the pr ogr ammable ter mination:
F or all: S102-3, S104-1, S 95- 128, S110-64
600 O hm ter mination: S101+1, S 101- 2, S103-1
CT R- 21 terminat ion: S101-1, S101+2, S 103- 1
Aust r alian terminat ion: S101-1, S101-2,
S103+1
VCC3_3
-All r esistor s 0603 footprint except R25 which is
1206
D2
MMSZ5248BT
2 1
VCC3_3
-K eep Vr ef and Vbg trace s away fr om digital
t r ace s, especially clocks. K eep traces short and
connect Vref and V bg ca ps to analog gr ound.
-K eep analog and digital power and
ground separat e up to J1 connector.
Not e: A ter mination MUST be programmed
or no terminat ion will be activated.
18V
C27
.047uF
D3
MMSZ52C2V4S
2
1
C18
0.22uF
250V
R28
47K
C19
0.22uF
250V
RING/CID detection
R8
30K
R9
30K
HOOK
RING/CIDdetection
C20 150nF
TXAN
R27 420
R26 820
C25 115nF
F1
MF-R015/600
Bourns
PTC f use
E1
TISP4350T3BJR
Bourns
Thyristor
R15
5.1K
R25
18
1/2W
+
C21
3.3uF , 25V
R12
62K
R23
33K
+C22
3.3uF , 16V
L2
NLV32T-4R7J-PF
L1
NLV32T-4R7J-PF
U4
TLP627
12
4
3
-+
BR1
HD04
4
1
3
2
J2
RJ-11
1
2
3
4
VCC3_3D
RXA
VBG
C3
33pF
C11
0.1uF
VCC3_3A
DTRB
J1
1
2
3
4
5
6
7
8
9
10
DCDB C4
0.002uF(NC)
C7
0.1uF
OSCIN
R2
2K(NC)
+C12
3.3uF
RESET
C8
0.1uF
C24
3.3uF
C14
0.1uF
DSRB
DCDB
RXDB R13
21K
Y1
11.0592 MH z
TXAP
C10
0.1uF
TXD B
R16
100
OSCOUT
VCC3_3D
VCC3_3
RIB
+C1
10uF
C2
27pF
CTSB
U1A 2901CE_QFN/TQFP32
USR20
29
RING
30
RELAY
31
RI
32
DTR
28 RXCLK
27 RXD
26
VND
1
VPD
2
DCD
3
DSR
4
CTS
5
RTS
6
USR11
7
USR10
8
RESET 9
VPA 10
TXAN 11
TXAP 12
VREF 13
VBG 14
RXA 15
VNA 16
VND 17
OSCOUT 18
OSCIN 19
VPD 20
N/C 21
TXD 23
TXCLK 24
VPD
25
VND 22
+
C5
3.3uF
+C13
3.3uF
C6
0.1uF R1
10K
+C9
10uF
RTSB
VREF
RELAYB
VCC3_3D
R24 750
VCC3_3D
T1
EMIT4033
Sumida
1
4
2
3
C28
220pF, 3k V
7.2 Reference Design Using Traditional Hardware Line Monitoring
Figure 4: 73M2901CE Worldwide Demo Board: Daughter Board Schem atic
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 23
8 Modem Performance Characteristics
The curves presented in this dat a sheet define modem IC per forman ce under a variety o f line condi tions
t ypical of t hose encountered over the Publi c Switched Telep hone Net w or k.
8.1 BER versus SNR
Thi s t est represent s the ab ility of the mod em to operate over noisy lines with a mi nimum amount of dat a
transfer erro rs. Since som e noise i s generated in the best di al up l ines, the modem must operate with the
lowest si gnal t o noi se ratio (SN R) possible.
B etter modem per formance i s indi cat ed by test cu r ves that are closest to t he BER axis. A narrow spread
bet we en curves r epr esent ing t he four l i ne par amet er s indi cat es min i mal variation i n per formance wh ile
operating ove r a r ange of typ i cal operati ng conditions. A DPSK or QAM modem will exh ibit bet ter BER
performance test curves rec eiving in the low band (answer mode) than in the high band (originate mode).
8.2 BER versus Receive Level
Thi s t est measures the dyn amic r ange of the modem. Beca use signal levels vary widely o ver dial up
lines, th e widest possible dynamic range is desirable. Th e SN R is hel d constant at t he i ndi cated valu es
as the recei ve level is lowe r ed from a ver y high to a ver y low si gnal l evel. Th e width of the bowl of these
cur ves, take n at the BE R br eak points i s the measur e of the dyn amic r ange.
Figure 5: BER versus S NR Figure 6: BER versus Recei ve Level
73M2901CE Data Sheet DS_2901CE_031
24 Rev. 3.4
9 Package Mechanical Drawing
9.1 32-Pin Q F N
2.5
5
2.5
5
TOP VIEW
1
2
3
Figure 7: 32-Pin QF N Drawing
0.85 NOM.
/
0.9MAX. 0.00 / 0.005
0.20 REF.
SEATING
PLANE
SIDE VIEW
0.2 MIN.
0.35 / 0.45
1.5 / 1.875
3.0 / 3.75
0.18 / 0.3
BOTTOM VIEW
1
2
3
0.25
0.5
0.5
0.25
3.0 / 3.75
1.5 / 1.875
0.35 / 0.45
CHAMFERED
0.30
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 25
9.2 32-Pin TQFP
Figure 8: 32-Pin TQFP Drawing
73M2901CE Data Sheet DS_2901CE_031
26 Rev. 3.4
10 Ordering Information
Table 4 lists the order num ber s and packaging mar ks used to identify 73M2901CE products.
Table 4: 73M2901CE Order Numbers and Packaging Mar ks
Part Description Order Number Packaging Mark
73M2901CE 32-Pin Q FN Lead Fr ee 73M2901CE-IM/F M2901CEM
73M2901CE 32-Pin Q FN Lead Fr ee Tape & Reel 73M2901CE-IMR/F M2901CEM
73M2901CE 32-Pin Thin Q ua d F lat Pa ck Lead Free 73M2901CE-IGV/F 73M2901CEIGV
73M2901CE 32-
P in Thi n Quad Flat Pack Lead F r ee
Tape & Reel 73M2901CE-IGVR/F 73M2901CEIGV
11 Related Documentation
The following 73M2901CE documents ar e avail able from Teridian Semiconductor Cor por ation:
73M2901CE AT Command User Guide
73M2901CE Demo Board User Guide
12 Contact Infor mation
For more informat i on about Teridian Semiconduct or pr oduct s or to check t he avail abi l it y of the
73M2901CE, contact us at:
64 40 Oa k Cany on Road
Suite 100
I r vine, CA 92618-5201
Telephone: (714) 508-8800
FAX : (71 4) 50 8-8878
Email: mode m.support@teridian.com
For a compl ete list of worldwid e sales of fices, go to http://www.teridian.com.
DS_2901CE_031 73M2901CE Dat a Sheet
Rev. 3.4 27
Rev isi on Histor y
Revision Date Description
2.2.1 4/20/2004 First p ub lication.
3.1 12/14/2007 Replaced 32QFN pun ched with SAWN package, removed l eaded package
opt i on, updated schematic and minor clean up.
3.2 1/21/2008 Changed dim ension of bot tom expose d pad on 32QFN m echanical package
figure.
3.3 4/3/2009 F or matted to new Teridi an style.
Assigned new documen t number .
Made minor corrections to Section 5. 3 and Section 6.3.
3.4 1/15/2010 In Section 6.1, d upl i cate d the hardwa re design co nsiderations from the
73 M 29 01CE Demo Bo ar d U ser Ma nu al .
Move d the 73M2901C E/CL di fference s from the 73 M 29 01CE D emo Bo ar d
Use r Ma nu al to Section 6.4.
Replaced th e schemat i cs in Figure 3 and Figure 4 with new schemat ics.
I m pr oved t he charts in Figure 5 and Figure 6.
Miscellaneous edi torial changes.
Teridian Semiconductor C or por ation is a r egi stered trademar k of Teridian S emicondu ctor Cor por ation .
S impli fying System Int egr ation i s a trademark of Teridian Semiconductor C or por ation.
A ll other trademar ks ar e the proper ty of their r espective o wn er s.
Teridian Semiconductor C or por ation makes no warran ty fo r the use of its products, other than exp r essly
contained i n the C om pany’s warranty d etailed in the Teridian Semi conductor Corporation standard Terms
and Conditions. The company assu mes no r esponsibil ity for any errors whi ch may appear in this
documen t, reserves the right to change devices or specificat i ons det ailed herei n at any time without
not i ce and does not make any commitment to update the information cont ained herein. Accordin gl y, the
reader i s cauti oned to verify that th is document is curr ent by com par i ng i t to the latest version on
ht tp://www.teri di an.co m or by checking with your sales representat i ve.
Teridian Semiconductor C or p., 6440 O ak Canyon, Sui te 100, I r vine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
Mouser Electronics
Authorized Distributor
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