S1R72901
SEIKO EPSON CORPORATION
PF1286-02
Single chip LSI for high-speed interface IEEE1394a-2000
DESCRIPTIONS
The S1R72901 is the single c hip c ontroller that bridges the IEEE1394 inter f ac e conform ing to 1394-1995 and
1394a-2000 of the IEEE standard, with the IDE interface conforming to the ATA5.
The following components are integrated into single chip; two-port cable PHY, the LINK/Transaction
controller most suitable to the SBP-2 protocol, Seiko Epson original 32-bit RISC processor and the Flash
memory for Firmware storage.
Hardware includes a part of transaction functions that allows automatic PageTable fetch and the data transfer
once the PageTable address and size for the SBP-2 protocol are set.
The S1R72901 provides the IEEE1394 inter f ac e to the computer per ipheral devic es , espec ially to the storage
devices that are most suitable.
FEATUR ES
z Cable PHY Transceiver/Arbitor
Built-in 2 port high-precision small amplitude differential high-speed transceiver.
Built-in on-chip 400MHz PLL that realizes the S400/S200/S100 transmission and reception, and the
50MHz SCLK output.
Cable Power Status function that detects the cable power drop.
z Link/Transaction Controller
Realizes duplex data transfer including Asynchronous and Isochronous transfer.
Realizes stable duplex data transfer up to the Maxpayload at 100Mbps, 200Mbps and 400Mbps with the
built-in SRAM.
z SBP-2 Support
A part of transactions is realized by hardware (a dedicated area is secured) to prevent actual transfer
rate drop due to the overhead.
The header area and the data area are separated to sim plify the com munication with the upper layers.
The data area is divided into the stream area and the ORB area.
The ring buffer is applied to the receiving header area, the receiving data area (receiving stream area,
receiving ORB area) and sending data area (sending stream area).
Sizes of the respective areas can be set as desired, independently.
The busy status is automatically controlled by hardware when receiving a signal.
Once the PageTable address and size in the SBP-2 are set, the PageTable fetch and the data transfer
can be done automatically.
z IDE interface
Compatible with PIO mode 0/1/2/3/4, multiword DMA mode 0/1/2 and Ultra-DMA mode 0/1/2/3/4/5
3.3V single power source is applicable with the 5V tolerant cell.
z C33 RISC CPU
32-bit RISC CPU EIAC332×501 operating at 25MHz (CPU cycle minimum 2τ operation)
Built-in SRAM: 8KB, no wait operation
Built-in Flash ROM: 64KB, no wait operation
Programmable timer: built-in 3-channel timers
z Flash ROM
Built-in 64KB Flash ROM, no need of external Flash ROM
z ICD33 interface
Incorporates the ICD33 interface that facilitates development of Firmware to operate the CPU. The
ICD33 can be connected with as few as six pins.
This terminal can be used as a JTAG terminal to rewrite the data in the built-in Flash ROM easily.
z Power voltage
3.3V±0.3V
z 100-pin flat package (pin pitch is 0.5 mm).
Radiation-proof design is not done.
S1R72901
BLOCK DIAGRAM
http://www.epsondevice.com/
■ EPSON Electronic devices Webs i te
Link
Interface
Cable
Power
Status
Voltage-
Current
Gen.
LPS
SCLK
LREQ
CTL[0:1]
D[0:7]
LINKON
PS0,PS1,PS2
CPS
TpBias0
TpBias1
R1
R0
TpA0_P
TpB0_P
TpA1_P
TpB1_P
393.216MHz CLK
PLL
TpBias
Gen.
DS-Link
Encoder/Decoder
XI,XO
xSBRI
PHY
Interface
Internal Packet Memory (8KByte)
Buffer Manager
LINK
&
TRAN
Core
SBP2
&
TRAN
Control
IDE
Control
IDE
Interface
S1C33
Mini
Core
Periphe-
ral
Flash
Control
FlashROM
(64KByte)
HDD[15:0]
HDMARQ
xHIOR
xHIOW
xHDMACK
HIORDY
HINTRQ
xHPDIAG
HDA[2:0]
xCS[1:0]
xHDASP
xHRST TpA0_N
TpB0_N
TpA1_N
TpB1_N
xRESET
xNMI
xINT0
xINT1
DCLK/TCK
DPCO/TMS
DST2/TDI
DST0
DST1/TDO
DSIO
GPIO[3:0]
TESTMD
TEST0
TEST1
TEST2
TVEP
Transmitter
&
Receiver
Transmitter
&
Receiver
PHY
Control
Unit
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson.
Seiko Epson reserves the right to m ake changes to this m aterial without notice. Seiko Epson does not as sume any liability of any kind
arising out of any inaccuracies contained in this material or due to it s application or us e in any product or circui t and, further, there i s no
representation t hat this m aterial is applic able to products requiring high level reliabilit y, such as, m edical product s. Moreover, no licens e
to any intel lectual property right s is granted by i mplicat ion or otherwise, and there is no repres entation or warranty that anything made in
accordance with t his m aterial will be free from any patent or copyright inf ringem ent of a t hird party. This m aterial or portio ns t hereof m ay
contain t echnology or the s ubject rel ating to s trategic products under the control of the Foreign Exchange and Foreign Trade Control Law
of Japan and may require an export license from the Ministry of Int ernational Trade and Industry or other approval from anther government
agency.
All other product names mentioned herei n are trademarks and/or registered trademarks of their respective companies.
This product uses SuperFlash® t echnology licensed from S ilicon Storage Technology, Inc.
©Seiko E pson Corporation 2003, A l l ri ghts reserved.
ELECTRONIC DEVICES MARKETING DIVISION
SEIKO EPSON CORPORATION
IC Marketing & Engineering Group
ED International Marketing Department
421-8 Hino, Hino-s hi , Tokyo 191-8501, JAPAN
Phone: 042-587-5814 FAX: 042-587-5117
First issue June, 2002
Printed June, 2003 in Japan H
