July 2012
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7WV07 • Rev. 1.0.2
NC7WV07 — TinyLogic
®
ULP-A Dual Buffer (Open-Drain Output)
NC7WV07
TinyLogic® ULP-A Bual Buffer (Open-Drain Output)
Features
0.9V to 3.6V VCC Supply Operation
3.6V Over-Voltage Tolerant I/Os at VCC from
0.9V to 3.6V
Extremely High Speed tPD
- 1.0ns: Typical for 2.7V to 3.6V VCC
- 1.2ns: Typical for 2.3V to 2.7V VCC
- 2.0ns: Typical for 1.65V to 1.95V VCC
- 3.2ns: Typical for 1.4V to 1.6V VCC
- 6.0ns: Typical for 1.1V to 1.3V VCC
- 13.0ns: Typical for 0.9V VCC
Power-Off High-Impedance Inputs and Outputs
High Static Drive (IOH/IOL)
- 24mA at 3.00V VCC
-18mA at 2.30V VCC
-6mA at 1.65V VCC
- 4mA at 1.4V VCC
- 2mA at 1.1V VCC
- 0.1mA at 0.9V VCC
Uses Proprietary Quiet Series™ Noise/EMI
Reduction Circuitry
Ultra-Small MicroPak™ Packages
Ultra-Low Dynamic Power
Description
The NC7WV07 is a dual buffer with open drain output
from Fairchild's Ultra Low Power-A series of TinyLogic®
ULP-A is ideal for applications that require extreme high
speed, high drive and low power. This product is
designed for a wide low voltage operating range (0.9V to
3.6V VCC) and applications that require more drive and
speed than the TinyLogic ULP series, but still offer best
in class low power operation.
The NC7WV07 is uniquely designed for optimized power
and speed, and is fabricated with an advanced CMOS
technology to achieve high-speed operation while
maintaining low CMOS power dissipation.
Ordering Information
Part Number Top Mark Package Packing Method
NC7WV07P6X V07 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel
NC7WV07L6X BC 6-Lead MicroPak™, 1.00mm Wide 5000 Units on Tape & Reel
TinyLogic®is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak™and Quiet Series™are trademarks of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7WV07 • Rev. 1.0.2 2
NC7WV07 — TinyLogic
®
ULP-A Dual Buffer (Open-Drain Output)
Battery Life
700
600
500
400
300
200
100
00.9 1.2
ULP-A (SV)
UL P ( S P )
UHS (SZ)
1.5 1.8 2.5 3.3 5.0
Battery Life
(Days)
V
CC
Su p ply Volta g e
Figure 1. Battery Life vs. VCC Supply Voltage
Notes:
1. TinyLogic® ULP and ULP-A with up to 50% less power consumption can extend battery life significantly.
Battery Life (Vbattery•Ibattery•.9)/(Pdevice)/24hrs/day
where, Pdevice (ICC • VCC) (CPD CL) • VCC2 • f.
2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at
10MHz, with CL=15pF load.
Pin Configurations
Figure 2. SC70 (Top View) Figure 3. MicroPak (Top Through View)
Pin Definitions
Pin # SC70 Pin # MicroPak Name Description
1 1 A1 Data Inputs
2 2 GND Ground
3 3 A2 Data Inputs
4 4 Y2 Output
5 5 VCC Supply Voltage
6 6 Y1 Output
Function Table
Inputs Output
A Y
L L
H *H
H=HIGH Logic Level
L=LOW Logic Level
*H=HIGH Impedance Output Status (Open Drain)
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7WV07 • Rev. 1.0.2 3
NC7WV07 — TinyLogic
®
ULP-A Dual Buffer (Open-Drain Output)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage -0.5 4.6 V
VIN DC Input Voltage -0.5 4.6 V
VOUT DC Output Voltage -0.5 4.6 V
IIK DC Input Diode Current VIN < 0V -50 mA
IOK DC Output Diode Current VOUT < 0V -50 mA
IOL DC Output Sink Current +50 mA
ICC or IGND DC VCC or Ground Current per Supply Pin ±50 mA
TSTG Storage Temperature Range -65 +150 °C
TJ Junction Temperature Under Bias +150 °C
TL Junction Lead Temperature, Soldering 10 Seconds +260 °C
PD Power Dissipation at +85°C SC70-5 150
mW MicroPak-6 130
MicroPak2-6 120
ESD Human Body Model, JEDEC:JESD22-A114 4000 V
Charge Device Model, JEDEC:JESD22-C101 2000
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Conditions Min. Max. Unit
VCC Supply Voltage 0.9 3.6 V
VIN Input Voltage 0 3.6 V
VOUT Output Voltage 0 3.6 V
IOL Output Current in IOL
VCC=3.0V to 3.6V +24.0
mA
VCC=2.3V to 3.6V +18.0
VCC=1.65V to 1.95V +6.0
VCC=1.4V to 1.6V +4.0
VCC=1.1V to 1.3V +2.0
VCC=0.9V +0.1
TA Operating Temperature, Fr ee Air -40 +85 °C
t/V Minimum Input Edge Rate VIN=0.8V to 2.0, VCC=3.0V 10 ns/V
JA Thermal Resistance SC70-5 425
°C/W
MicroPak-6 500
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7WV07 • Rev. 1.0.2 4
NC7WV07 — TinyLogic
®
ULP-A Dual Buffer (Open-Drain Output)
DC Electrical Characteristics
Symbol Parameter VCC Conditions TA=25°C TA=-40 to 85°C Units
Min. Max. Min. Max.
VIH HIGH Level Input
Voltage
0.90
.65 x VCC .65 x VCC
V
1.10 VCC 1.30 .65 x VCC .65 x VCC
1.40 VCC 1.60 .65 x VCC .65 x VCC
1.65 VCC 1.95 .65 x VCC .65 x VCC
2.30 VCC 2.70 1.6 1.6
2.70 VCC 3.60 2.0 2.0
VIL LOW Level Input
Voltage
0.90
.35 x VCC .35 x VCC
V
1.10 VCC 1.30 .35 x VCC .35 x VCC
1.40 VCC 1.60 .35 x VCC .35 x VCC
1.65 VCC 1.95 .35 x VCC .35 x VCC
2.30 VCC 2.70 0.7 0.7
2.70 VCC 3.60 0.8 0.8
VOL LOW Level Output
Voltage
0.90
IOL=100µA
0.1 0.1
V
1.10 VCC 1.30 0.1 0.1
1.40 VCC 1.60 0.2 0.2
1.65 VCC 1.95 0.2 0.2
2.30 VCC 2.70 0.2 0.2
2.70 VCC 3.60 0.2 0.2
1.10 VCC 1.30 IOL=2mA 0.25 x VCC 0.25 x VCC
1.40 VCC 1.60 IOL=4mA 0.25 x VCC 0.25 x VCC
1.65 VCC 1.95 IOL=6mA 0.3 0.3
2.30 VCC 2.70 IOL=12mA 0.4 0.4
2.70 VCC 3.60 0.4 0.4
2.30 VCC 2.70 IOL=18mA 0.6 0.6
2.70 VCC 3.60 0.4 0.4
2.70 VCC 3.60 IOL=24mA 0.55 0.55
IIN Input Leakage
Current 0.90 to 3.60 0 VIN 3.60 ±0.1 ±0.5 µA
IOFF Power Off
Leakage Current 0 0 (VIN, VO)
3.60 0.5 0.5 µA
ICC Quiescent Supply
Current 0.90 to 3.60
VIN=VCC, or
GND 0.9 0.9
µA
VCC VIN
3.6V ±0.9
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7WV07 • Rev. 1.0.2 5
NC7WV07 — TinyLogic
®
ULP-A Dual Buffer (Open-Drain Output)
AC Electrical Characteristics
Symbol Parameter VCC Conditions
TA=25°C TA=-40 to 85°C Units Figure
Min. Typ. Max. Min. Max.
tPZL, tPLZ Propagation
Delay
0.90 CL=15pF,
RU=RD=1M 13
ns Figure 4
Figure 5
1.10 VCC 1.30 CL=15pF,
RU=RD=2k 2.0 6.0 15.0 1.0 18.6
1.40 VCC 1.60 1.0 3.2 8.7 1.0 9.7
1.65 VCC 1.95 CL=30pF,
RU=RD=500
1.0 2.0 6.0 1.0 6.8
2.30 VCC 2.70 0.7 1.2 3.6 0.6 4.7
2.70 VCC 3.60 0.5 1.0 3.3 0.4 4.0
CIN Input
Capacitance 0 2 pF
COUT Output
Capacitance 0 6.5
CPD Power
Dissipation
Capacitance 0.90 to 3.60 VIN=0V or VCC,
f=10MHz 10 pF
AC Loadings and Waveforms
Figure 4. AC Test Circuit
Test Switch
tPZL, tPLZ 6V at VCC=3.3±0.3V; VCC x 2 at VCC=0.9-2.7V
Figure 5. AC Waveforms for Inverting and Non-Inverting Functions
Symbol VCC
3.3V ± 0.3V 2.5V ± 0.2V 1.8V ±
0.15V 1.5V ± 0.1V 1.2V ± 0.1V 0.9V
Vmi 1.5V VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
Vmo V
OL + 0.30V VOL + 0.15V VOL + 0.15V VOL + 0.10V VOL + 0.10V VOL + 0.10V
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7WV07 • Rev. 1.0.2 6
NC7WV07 — TinyLogic
®
ULP-A Dual Buffer (Open-Drain Output)
Physical Dimensions
DETAIL A
SCALE: 60X
B
1.90
2.00±0.20
0.50 MIN
1.00
0.80
1.10
0.80
0.10 C
0.25
0.10
0.46
0.26
0.20
GAGE
PLANE (R0.10)
30°
0°
SEATING
PLANE
C0.10
0.00
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO EIAJ
SC-88, 1996.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BU RRS
OR MOLD FLASH.
D) DRAWING FILENAME: MKT-MAA06AREV6
2.10±0.30
0.10 AB
0.65
1.30
(0.25) 0.30
0.15
1
1.25±0.10
3
1.30 0.40 MIN
SEE DETAIL A
LAND PATTERN RECOMMENDATION
6
A
4
C
0.65 L
SYMM
PIN ONE
Figure 6. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent r evision. Package specifications do not expand the terms of Fairchild’s worldwide term s and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf.
Package Designator Tape Section Cavity Number Cavity Status Cover Type Status
P6X Leader (Start End) 125 (Typical) Empty Sealed
Carrier 3000 Filled Sealed
Trailer (Hub End) 75 (Typical) Empty Sealed
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7WV07 • Rev. 1.0.2 7
NC7WV07 — TinyLogic
®
ULP-A Dual Buffer (Open-Drain Output)
Physical Dimensions
2. DIMENSIONS ARE IN MILLIMETERS
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
4. FILENAME AND REVISION: MAC06AREV4
Notes:
3. DRAWING CONFORMS TO ASME Y14.5M-1994
TOP VIEW
RECOMMENED
LAND PATTERN
BOTTOM VIEW
1.45
1.00
A
B
0.05 C
0.05 C
2X
2X
0.55MAX
0.05 C
(0.49)
(1)
(0.75)
(0.52)
(0.30)
6X
1X
6X
PIN 1
DETAIL A
0.075 X 45
CHAMFER
0.25
0.15
0.35
0.25
0.40
0.30
0.5
(0.05)
1.0
5X
DETAIL A
PIN 1 TERMINAL
0.40
0.30
0.45
0.35
0.10
0.00
0.10 CBA
0.05 C
C0.05 C
0.05
0.00
5X
5X
6X (0.13)
4X
6X
PIN 1 IDENTIFIER
(0.254)
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
5
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 7. 6-Lead, Micro Pak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator Tape Section Cavity Number Cavity Status Cover Type Status
L6X Leader (Start End) 125 (Typical) Empty Sealed
Carrier 5000 Filled Sealed
Trailer (Hub End) 75 (Typical) Empty Sealed
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
NC7WV07 • Rev. 1.0.2 8
NC7WV07 — TinyLogic
®
ULP-A Dual Buffer (Open-Drain Output)
