433 54F/74F 433 First-In First-Out (FIFO) Buffer Memory contr nication buffer applications. It is organized as 64 words by ma expanded to any number of words or any number of bits It f four. Data may be entered or extracted asynchronously in sertal allowing economical implementation of buffer memories. The F433 has 3-state outputs that pri ed compatible with all TTL families. Serial or Parallel Input Serial or Parallel Output Expandable without Additional Logic 3-State Outputs Fully Compatible with all TTL Families Slim 24-Pin Package D ption i@ an expandabie fall-through type high-speed first-in first-out IFO) ory that is optimized for high-speed disk or tape e a rsatility, and is fully Ordering Code: See Section 5 Logic Symbol | tilt PL Dg Ds Dy D, Dy TTS s ze IES IRF O cPSi TOP TOS OES cPSO ORE|O EO MR Q3 Q) Q; Qy Os TEPty | gobs] bbe 4-347 Connection Diagrams IRF [3 | ~ [24] Voc PL[2 | 23] ORE pa) [21] Qo D2[5 | [20], ds[ | [13 ]Q2 ds[7 | [18] cpsi[s | 17 ]E6 iEs[9 | [16 CPS TTS [10 | 15 OES MAI 11 14}TOS Gna [12 [i3]TOP Pin Assignment for DIP and SOIC we a 9 o D gs oP mis =) 9 3) o aD 8 fq am fi GNO fidl 14] D ia} PL (2) IRE fy] ne 2a] v. [27] ORE : Go NC |t5| TOP (16) TOS [17] GES 181 (3! * es as] 20 ei ar ba By PSO EO nc a ic O18 Pin Assignment for LCC and PCC433 Input Loading/Fan-Out: See Section 3 for U.L. definitions 54F/74F(U.L.) Pin Names Description HIGH/LOW PL Parallel Load Input 1.0/0.23 CPSI Serial Input Clock 1.0/0.23 TES Serial Input Enable 1.0/0.23 TTs Transfer to Stack Input 1.0/0.23 MR Master Reset 1.0/0.23 OES Serial Output Enable 1.0/0.6 TOP Transfer Out Parallel 1.0/0.23 TOS Transfer Out Serial 1.0/0.23 CPSO Serial Output Clock 1.0/0.23 OE Output Enable 1.0/0.23 Do-D3 Parallel Data Inputs 1.0/0.23 Ds Serial Data Input 1.0/0.23 Qq-Q3 Parallel Data Outputs 130/10 Qs Serial Data Output 10/10 TRF Input Register Full 10/5 ORE Output Register Empty 10/5 Functional Description As shown in the block diagram, the F433 consists of three sections: 1. An Input Register with parallel and serial data inputs, as well as control inputs and outputs for input handshaking and expansion. 2. A 4-bit-wide, 14-word-deep fall-through stack with self-contained control logic. 3. An Output Register with parallel and serial data outputs, as well as control inputs and outputs for output handshaking and expansion. These three sections operate asynchronously and are virtually independent of one another. input Register (Data Entry) The Input Register can receive data in either bit- serial or 4-bit parallel form. It stores this data until it is sent to the fall-through stack, and also generates the necessary status and control signals. This 5-bit register (see Figure 1) is initialized by setting flip-flop F; and resetting the other flip- flops. The Q-output of the last flip-flop (FC) is brought out as the Input Register Full (IRF) signal. After initialization, this output is HIGH.Parallel EntryA HIGH on the Parallel Load (PL) input toads the D,-D; inputs into the F,-F, flip-flops and sets the FC flip-flop. This forces the IRF output LOW, indicating that the input register if full. During parallel entry, the Serial Input Clock (CPSI) input must be LOW. Serial Entry Data on the Serial Data (Dg) input is serially entered into the shift register (F3, Fo, Fy, Fo, FC) on each HIGH-to-LOW transition of the CPSi input when the Serial input Enable (IES) signal is LOW. During serial entry, the PL input should be LOW. After the fourth clock transition, the four data bits are located in flip-flops F9-F3. The FC flip-flop is set, forcing the IRF output LOW and internally inhibiting CPSi pulses from affecting the register. Figure 2 illustrates the final positions in an 'F433 resulting from a 256-bit serial bit train (By is the first bit, Bos, the last). Fall-Through StackThe outputs of flip-flops Fo-F, feed the stack. A LOW level on the Transfer to Stack (TTS) input initiates a fall-through action; if the top location of the stack is empty, data is loaded into the stack and the input register is reinitialized. (Note that this initialization is delayed until PL is LOW.) Thus, automatic FIFO action is achieved by connecting the IRF output to the TTS input. An RS-type flip-flop (the initialization flip-flop) in the control section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack even through IRF and TTS may still be LOW; the initialization flip-flop is not cleared until PL goes LOW. Once in the stack, data falls through automatically, pausing only when it is necessary to wait for an empty next location. In the F433, the master reset (MR) input only initializes the stack control section and does not clear the data. 4-349 433 Output Register The Output Register (see Figure 3) receives 4-bit data words from the bottom stack location, stores them, and outputs data on a 3-state, 4-bit parallel data bus or on a 3-state serial data bus. The output section generates and receives the necessary status and control signals. Parallel ExtractionWhen the FIFO is empty after a LOW pulse is applied to the MR input, the Output Register Empty (GRE) output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the Transfer Out Parallel (TOP) input is HiGH. As a result of the data transfer, ORE goes HIGH, indicating valid data on the data outputs (provided that the 3-state buffer is enabled). The TOP input can then be used to clock out the next word. When TOP goes LOW, ORE also goes LOW, indicating that the output data has been extracted; however, the data itself remains on the output bus until a HIGH level on TOP permits the transfer of the next word (if available) into the output register. During paratlel data extraction, the serial output clock (CPSO) line should be LOW. The Transfer Out Serial (TOS) line should be grounded for single-slice operation or connected to the appropriate ORE line for expanded operation (refer to the Expansion section). The TOP signal is not edge-triggered. Therefore, if TOP goes HIGH before data is available from the stack but data becomes availabie before TOP again goes LOW, that data is transferred into the output register. However, internal control circuitry prevents the same data from being transferred twice. If TOP goes HIGH and returns to LOW before data is available from the stack, ORE remains LOW, indicating that there is no valid data at the outputs.433 Serial ExtractionWhen the FIFO is empty after a LOW is applied to the MR input, the ORE output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the TOS input is LOW and TOP is HIGH. As a result of the data transfer, ORE goes HIGH, indicating that valid data is in the register. The 3-state Serial Data Output (Qs) is automatically enabled and puts the first data bit on the output bus. Data is serially shifted out on the HIGH-to- LOW transition of CPSO. To prevent false shifting, CPSO should be LOW when the new word is being loaded into the output register. The fourth transition empties the shift register, forces ORE LOW, and disables the serial output, Qs. For serial operation, the ORE output may be tied to the TOS input, requesting a new word from the stack as soon as the previous one has been shifted out. Expansion Vertical ExpansionThe 'F433 may be vertically expanded, without external components, to store more words. The interconnections necessary to form a 190-word by 4-bit FIFO are shown in Figure 4. Using the same technique, any FIFO of (63n + 1)-words by 4-bits can be configured, where nis the number of devices. Note that expansion does not sacrifice any of the 'F433 flexibility for serial/parallel input and output. Horizontal ExpansionThe F433 can be horizontally expanded, without external logic, to store long words (in multiples of 4-bits). The interconnections necessary to form a 64-word by 12-bit FIFO are shown in Figure 5. Using the same technique, any FIFO of 64-words by 4n-bits can be constructed, where n is the number of devices. The right-most (most significant) device is connected to the TTS inputs of all devices. Similarly, the ORE output of the most significant device is connected to the TOS inputs of all devices. As in the vertical expansion scheme, horizontal expansion does not sacrifice any of the "F433 flexibility for serial/parallel input and output. it should be noted that the horizontal expansion scheme shown in Figure 5 exacts a penalty in speed. Horizontal and Vertical ExpansionThe F433 can be expanded in both the horizontal and vertical directions without any external components and without sacrificing any of its FIFO flexibility for serial/parallel input and output. The interconnections necessary to form a 127-word by 16-bit FIFO are shown in Figure 6. Using the same technique, any FIFO of (63m + 1)-words by 4n-bits can be configured, where m is the number of devices in a column and n is the number of devices in a row. Figures 7 and 8 illustrate the timing diagrams for serial data entry and extraction for the FIFO shown in Figure 6. Figure 9 illustrates the final positions of bits in an expanded 'F433 FIFO resulting from a 2032-bit serial bit train. Interlocking Circuitry Most conventional FIFO designs provide status signal analogous to [RF and ORE. However, when these devices are operated in arrays, variations in unit-to-unit operating speed require external gating to ensure that all devices have completed an operation. The 'F433 incorporates simple but effective master/slave interlocking circuitry to eliminate the need for external gating. In the 'F433 array of Figure 6, devices 1 and 5 are the row masters; the other devices are slaves to the master in their rows. No slave in a given row initializes its input register until it has received a LOW on its TES input from a row master or a slave of higher priority. Similarly, the ORE outputs of staves do not go HIGH until their inputs have gone HIGH. This interlocking scheme ensures that new input data may be accepted by the array when the IRF output of the final slave in that row goes HIGH and that output data for the array may be extracted when the ORE output of the final slave in the output row goes HIGH. The row master is established by connecting its TES input to ground, while a slave receives its TES input from the IRF output of the next-higher priority device. When an array of 'F433 FIFOs is initialized with a LOW on the MR inputs of all devices, the IRF outputs of all devices are HIGH. Thus, only the row master receives a LOW on the {ES input during initialization.433 Figure 10 is a conceptual logic diagram of the A similar operation takes place for the output internal circuitry that determines master/siave register. Either a TOS or TOP input initiates a load- operation. When MR and IES are LOW, the master from-stack operation and sets the ORE request flip- latch is set. When TTS goes LOW, the initialization flop. lf the master latch is set, the last output flip-flop is set. If the master latch if HIGH, the register flip-flop is set and the ORE line goes input register is immediately initialized and the HIGH. If the master latch is reset, the ORE output initialization flip-flop reset. If the master latch is is LOW until a Serial Output Enable (OES) input is reset, the input register is not initialized until IES received. goes LOW. In array operation, activating TTS initiates a ripple input register initialization from the row master to the last slave. Block Diagram Og 63 1D, 40, 10 3 | 2 | \ | o | INPUT DATA crs. =O _ fia WNPUT 1O____ 1ESOF conacs. INPUT REGISTER SO oO i STACK y MR )] CONTROL 62 x 4 STACK o68o} ont (o_ OuTPuT OuTPUT REGISTER TOP =~ CONTROL Tos O OUTPUT DATA P80 -OF Os 03 ]0, Jo, [o433 Fig. 1 Conceptual Input Section f INPUT DATA | ( De oy So PL INITIALIZE I 8 % S Dg D a c a 2 u G - Fy Fo Fy FQ ee pei CP mO CP rte cP mye oy oP RF a R a 2 R os| __J INPUT REG + STACK (PULSE DERIVED FROM TTS! {ar APUTS TU STACK Fig. 2 Final Positions in an F433 Resulting from a 256-Bit Serial Train by Up, ty oe Oy [1 || | INPUT 863 Be? 851 bso PREWISTER Ld F433 Pouteur FEG STER By B; By By 4-362433 Fig. 3 Conceptual Output Section OUTPUT FROM STACK LOAD FROM STACK - | - . . . | INITIALIZE s s Ss dD a o Qa D a F3 Fo Fy ce Q cP o> cP R A F a a a ey TE CATA ! o fe} D m433 Fig. 4 A Vertical Expansion Scheme PARALLEL DATA IN MASTER PARALLEL [_1 RESET LOAD =: 3. D2. D1 Do SERIAL DATA IN ORE Q1 Qo Os Q3 NC ORE Q3 G2 Q1Q0 Qs NC TTS HES CPSI OES TOS TOP cPSO ORE OE mMRG3020; DATA VALID SERIAL OUTPUT CLOCK OUTPUT ENABLE SERIAL DATA OUTPUT PARALLEL DATA OUT 4-354433 Fig. 5 A Horizontal Expansion Scheme ___ a PARALLEL DATA INPUT er D3 Dz Dy Do 07 De Ds Da Di1Di0D9 Dg CPSi PL Ds PL Ds D3 Dy Do IES IRF CPS! oOcs TOS F433 TOP CPSO DATA OE MR READY DUMP CPSO OE SR = Q3 Q2 Qs Qo Q7 Gg Qs Os Q11 G19 Qo Q5 Teen CTS L-________- PARALLEL DATA OUTPUT 4-355433 Fig.6 A 127x16 FIFO Array PARALLEL DATA INPUT 03022 1D D7Dg De Og 01101909 0g 5913013912 SE DATA INPUT PL DgD3D70,Dy PL Dg 03D50,Dg 3 PL MGT y070-Dy, TTS rh IRF IRE es IRF 1 2 | 7 4 1F433 ORE F433 ; 5 16433 OFF ros TOS PL Og 24020 109 D523 290 ,0g TS ouTPUT SERIAL ENABLE DATA OUTPUT OUTPUT CLOCK OUMP 030,0,0 070, 0,0 Sironnte! 5944043949 ge2nito 6 Oe pete DATA QUTEUT Hoe 8 IN| 4-356433 Fig. 7 Serial Data Entry for Array of Fig. 6 TLLILILI LL LLL LI LIL LIL Li DEVICE 1 'tpH be 1 [_ "RE 1 rT ra rot DEVICE 2 'p++1 e_- OEVICE 3 1p +> ke . DEVICE 4 TTS ALL DEVICES 'pa | IRE. | \ | INPUTS 0 | 1 2 | 3 | 4 | | 8 | g | 10 | W | 12 | 13 | 14 15 | BITS STOREO IN STORED IN STOREDIN STORED IN DEVICE 1 DEVICE 2 DEVICE 3 DENCE 4 w o Fig. 8 Serial Data Extraction for Array of Fig. 6 4 ol DEVICES o4 ' one [ TOT bord Poel DEVICE 6 tp +4 14 ORE | 4 | T ' 4 ' i DEVICE ? a ! \ ORE ' ' | 11 | ot Device B TOS ALL DEVICES tp>+} -. I ORE i SERIAL OATA OUTPUT a [ o% [| % | % | | % | 3 | o% | = fo | om | % fa | o fo | DEVICE 5 DEVICE 6 DEVICE? DEVICE 8 4-357433 Fig. 9 Final Position of a 2032-Bit Serial Input SERIAL INPUT by D2 0; Dg J | 4 4 Lj Os 0; Dy Dy, By Sty. LETT I Pc rot | Tj ft fd D3 Dp 9, Og 8493 8482 Bag: Bago 8ag7 Bags Bas Bagg Bagi Bago Bagg Baas Bags Saga Bag3 8492 811 B19 83 Bg Fig. 10 Conceptual Diagram, Interlocking Circuitry INPUT REG - 5TACK IDEAIVED FROM TTS: LOAD OUTPUT (DERIVED FAOM TOP AND TOS REGISTER Toe TH OES MASTER LaTcH 5 REGUEST INITIALIZATION FLIP-FLOP s 4-358 ORE REQUFS" LIP FLOP J} i | | | PoP TT a ep GT Uy a { | | | ToT Tas Fe SEE Frog Rt n a SERIAL OuTeur a 7 ALTE VEE CHE ygDC Characteristics over Operating Temperature Range (unless otherwise specified) 433 54F/74F Symbol Parameter Min Typ Max Units Conditions loc Supply Current 75 110 mA Voc = Max, Inputs Open AC Characteristics: See Section 3 for waveforms and load configurations S4F/74F 54F 74F Ta = + 25C Ta: Vec= Ta, Voc= Fi Symbol Parameter Veco= +5.0V Mil Com Units No. C, = 50 pF C, = 50 pF GC, = 50 pF . Min Typ Max | Min Max Min Max t Propagation Delay, Negative- 27.0 PHL Going CP to IRF Output . 3-1 . ns 403-a t Propagation Delay, Negative- 62.0 403-b PLH Going TTS to [RF , teLH Propagation Delay, Negative- 39.0 ns 3-1, 403-c teHL Going GPSO to Qs Output 26.0 403-d teLH Propagation Delay, Positive- 73.0 ns 3-1 teyL Going TOP to Q,-Q, Outputs 61.0 403-e t Propagation Delay, Negative- 27.0 ns 3-1, 403-c PHL Going CPSO to ORE . 403-d t Propagation Delay, Negative- 40.0 PHL Going TOP to ORE , ns 3-1, 403-e t Propagation Delay, Positive- 70.0 PLH Going TOP to ORE . Propagation Delay, Negative- 3-1 tety Going TOS to 70.0 ns 403-c Positive-Going ORE 403-d t Propagation Delay, Positive- 34.0 PHL Going PL to Negative-Going , IRF 3-1 ns 403-g t Propagation Delay, Negative- 38.0 403-h PLH Going PL to Positive-Going IRF Propagation Delay, Positive- - teu Going OES to ORE 31.0 ns 3 Propagation Delay teLy Positive-Going IES to 28.0 ns _|3-1, 403-h Positive-Going IRF433 AC Characteristics (cont'd) 54F/74F 54F 74F Ta = +25C Ta, Vec = Tas Voc = Fi Symbol Parameter Veo = +5.0V Mil Com Units No C, = 50 pF C, = 50 pF C, =50 pF . Min Typ Max | Min Max Min Max tezy Enable Time 12.0 tpz, OE to Qo-Q4 12.0 3-1 ns 3-12 tpyz Disable Time 14.0 3-13 tpiz OE to Q,-Q, 14.0 tezH Enable Time 12.0 tpz Negative-Going OES to Q, 12.0 3-1 ns 3-12 tpuz Disable Time 14.0 3-13 teLz Negative-Going OES to Q, 14.0 torr Fall-Through Time 3.6 uS 3-1, 403-f t Parallel Appearance Time 12.0 AP ORE to Qo-Q3 , ns 3-1 tas Serial Appearance Time 14.0 ORE to Q,AC Operating Requirements: See Section 3 for waveforms 433 54F/74F 54F 74F Ta = + 25C Tas Vec= Ta: Voc= Fig. Symbol Parameter Voo= +5.0V Mil Com Units No. Min Typ Max | Min Max Min Max t,(H) Setup Time, HIGH or LOW 6.0 t,(L) Dg to Negative CPSI 6.0 ne 403-a ta(H) Hold Time, HIGH or LOW 3.0 403-b th(L) Dg to CPSI 3.0 . 403-a te(H) Setup Time, HIGH or LOW 22.0 403-b TTS to IRF ns ts(L) Serial or Paraliel Mode 22.0 403-9, 403-h Setup Time, HIGH or LOW ny Negative-Going ORE to O ns foe s Negative-Going TOS Setup Time, HIGH or LOW Py Negative-Going les ns 403-b s ES to CPSI Set-Up Time, HIGH or LOW ath Negative-Going ae ns 403-b 8 TTS to CPSI . t,(H) Setup Time, HIGH or LOW -16.0 t,(L) Parallel Inputs to PL -16.0 ns 3-14 t,(H) Hold Time, HIGH or LOW 10.0 t,(L) Parallel Inputs to PL 10.0 ty(H) CPS! Pulse Width 10.0 ns 403-a tL) HIGH or LOW 15.0 403-b : 403-g ty(H) PL Pulse Width, HIGH 10.0 ns 403-h 403-a TTS Pulse Width, LOW 403-b tall) Serial or Parallel Mode 23.0 ns 403-9 403-h ty(L) MR Pulse Width, LOW 22.0 ns 403-f ty(H) TOP Pulse Width 40.0 ty(L) HIGH or LOW 24.0 ns 403-e ty(H) CPSO Pulse Width 10.0 ns 403-c ty(L) HIGH or LOW 16.0 403-d tec Recovery Time 23.0 ns 403-f MR to Any Input 4-361433 Fig. 433-a Serial Input, Unexpanded or Master Operation twil) BRS a HR BEYER, Stable ___+ 1.5 V Fig. 433-b Serial Input, Expanded Slave Operation ts Stable Stable Stable tPHL mn 1.5V Fig. 433-c Serial Output, Unexpanded or Master Operation tw(L) a _twiH) cesottis/ \ --f- \-- >| PLH > ea ~~ tw(L) tw{H) 1.5V Qs 4s5v Ee Say ! TE ESD [eR BE 4-362433 Fig. 433-d_ Serial Output, Slave Operation OES \ 1.5V CPSO + a as ue we an Fig. 433-e Parallel Output, 4-Bit Word or Master in Parallel Expansion TOP UN _ i +| tPHL <_ +| tPLH ORE \ ___}+ 15 V tPLH tPHL Qo-Q3 1.5 Vv NEW OUTPUT Fig. 433-f Fall Through Time {oT} MR ___ JF 15 trec <_ PL ] ee 1.5 V < ty << tbFT >| Q0-Q3 Yi Vv 4-363433 Fig. 433-g Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion - | th th le 1.5 V STABLE 1.5 V a tpHL-| | IRF Yer ts = 07 ten Ts Y f (note 2) ty tw PL 15 V Do-D3 Fig. 433-h Parallel Load, Slave Mode PL lr _| th CMAARAAY YY AAAAAARAAAA? OO AR OOD BRR RN RR KERR CRY) Do-Ds eee SAE AER yl te tPLH < IES 1.5V 7 1.5V het tPHE tPLH IRF 1.5V 15V ts > Tis ON 4-364