MC14017BCPG - ON Semiconductor - Datasheet.Directory

June, 2011 − Rev. 7

1Publication Order Number:

MC14017B/D

MC14017B

Decade Counter

The MC14017B is a five−stage Johnson decade counter with

built−in code converter. High speed operation and spike−free outputs

are obtained by use of a Johnson decade counter design. The ten

decoded outputs are normally low, and go high only at their

appropriate decimal time period. The output changes occur on the

positive−going edge of the clock pulse. This part can be used in

frequency division applications as well as decade counter or decimal

decode display applications.

Features

•Fully Static Operation

•DC Clock Input Circuit Allows Slow Rise Times

•Carry Out Output for Cascading

•Divide−by−N Counting

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

•Pin−for−Pin Replacement for CD4017B

•Triple Diode Protection on All Inputs

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

MC14017BCP

AWLYYWWG

SOIC−16

D SUFFIX

CASE 751B

14017BG

AWLYWW

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Indicator

SOEIAJ−16

F SUFFIX

CASE 966

MC14017B

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

16

1

16

1

16

MC14017B

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2

BLOCK DIAGRAMFUNCTIONAL TRUTH TABLE

(Positive Logic)

Clock Decode

Clock Enable Reset Output=n

0X0 n

X10 n

XX1 Q0

0 0 n+1

X0 n

X0n

1 0 n+1

X = Don’t Care. If n < 5 Carry = “1”,

Otherwise = “0”.

CLOCK

ENABLE

RESET

14

13

15 Cout

Q9

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0 3

2

4

7

10

1

5

6

9

11

12

VDD = PIN 16

VSS = PIN 8

LOGIC DIAGRAM

CLOCK

ENABLE CARRY

RESET

Q5 Q1 Q7 Q3 Q9

117621

12

Q0 Q6 Q2 Q3 Q4

354910

14

13

15

C

D

RR

Q

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Cout

CE

CLOCK

RESET

VDD

Q8

Q4

Q9

Q2

Q0

Q1

Q5

VSS

Q3

Q7

Q6

C

D

RR

Q

C

D

RR

Q

C

D

RR

Q

C

D

RR

Q

MC14017B

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ

(Note 2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

—

ÎÎÎ

0.05

ÎÎÎÎ

—

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

—

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

—

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

—

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

—

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

—

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

—

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

3.5

7.0

11

ÎÎÎ

—

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

—

ÎÎÎ

3.5

7.0

11

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

—

ÎÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎÎ

—

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

—

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

—

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

—

ÎÎÎ

± 0.1

ÎÎÎÎ

—

ÎÎÎ

±0.00001

ÎÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎ

± 1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

5.0

ÎÎÎÎ

7.5

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

—

ÎÎÎ

5.0

10

20

ÎÎÎÎ

—

ÎÎÎ

0.005

0.010

0.015

ÎÎÎÎ

5.0

10

20

ÎÎÎ

—

ÎÎÎ

150

300

600

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

ÎÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.27 mA/kHz) f + IDD

IT = (0.55 mA/kHz) f + IDD

IT = (0.83 mA/kHz) f + IDD

ÎÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0011.

ORDERING INFORMATION

Device Package Shipping†

MC14017BCPG PDIP−16

(Pb−Free)

500 Units / Rail

MC14017BDG SOIC−16 48 Units / Rail

MC14017BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

MC14017BFELG SOEIAJ−16 2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC14017B

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

—

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

Reset to Decode Output

tPLH, tPHL = (1.7 ns/pF) CL + 415 ns

tPLH, tPHL = (0.66 ns/PF) CL + 197 ns

tPLH, tPHL = (0.5 ns/pF) CL + 150 ns

ÎÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

—

ÎÎÎÎ

500

230

175

ÎÎÎÎ

1000

460

350

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

Clock to Cout

tPLH, tPHL = (1.7 ns/pF) CL + 315 ns

tPLH, tPHL = (0.66 ns/pF) CL + 142 ns

tPLH, tPHL = (0.5 ns/pF) CL + 100 ns

ÎÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

—

ÎÎÎÎ

400

175

125

ÎÎÎÎ

800

350

250

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

Clock to Decode Output

tPLH, tPHL = (1.7 ns/pF) CL + 415 ns

tPLH, tPHL = (0.66 ns/pF) CL + 197 ns

tPLH, tPHL = (0.5 ns/pF) CL + 150 ns

ÎÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

—

ÎÎÎÎ

500

230

175

ÎÎÎÎ

1000

460

350

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Turn−Off Delay Time

Reset to Cout

tPLH = (1.7 ns/pF) CL + 315 ns

tPLH = (0.66 ns/pF) CL + 142 ns

tPLH = (0.5 ns/pF) CL + 100 ns

ÎÎÎÎÎ

tPLH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

—

ÎÎÎÎ

400

175

125

ÎÎÎÎ

800

350

250

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Width

ÎÎÎÎÎ

tw(H)

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

250

100

75

ÎÎÎÎ

125

50

35

ÎÎÎÎ

—

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Frequency

ÎÎÎÎÎ

fcl

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

—

ÎÎÎÎ

5.0

12

16

ÎÎÎÎ

2.0

5.0

6.7

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset Pulse Width

ÎÎÎÎÎ

tw(H)

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

500

250

190

ÎÎÎÎ

250

125

95

ÎÎÎÎ

—

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset Removal Time

ÎÎÎÎÎ

trem

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

750

275

210

ÎÎÎÎ

375

135

105

ÎÎÎÎ

—

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Input Rise and Fall Time

ÎÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎ

No Limit

ÎÎÎ

—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Enable Setup Time

ÎÎÎÎÎ

tsu

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

350

150

115

ÎÎÎÎ

175

75

52

ÎÎÎÎ

—

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Enable Removal Time

ÎÎÎÎÎ

trem

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

420

200

140

ÎÎÎÎ

260

100

70

ÎÎÎÎ

—

ÎÎÎ

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14017B

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5

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

VDD

Vout

VSS

VDD

VSS

S1

A

B

VSS

ID

EXTERNAL

POWER

SUPPLY

CLOCK

ENABLE

RESET

CLOCK Cout

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Output

Sink Drive

Output

Source Drive

Decode

Outputs

Clock to

desired

outputs

(S1 to B)

(S1 to A)

Carry

Clock to 5

thru 9

(S1 to B)

S1 to A

VGS = − VDD

VDD

VDS =V

out − VDD

Vout

Figure 2. Typical Power Dissipation Test Circuit

VDD

VSS

ID

CLOCK

ENABLE

RESET

CLOCK

Cout

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

500 mF0.01 mF

CERAMIC

PULSE

GENERATOR

fc

CLCLCLCLCLCLCLCLCLCLCL

MC14017B

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6

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are

sequential within each stage and from stage to stage, with no dead time (except propagation delay).

Figure 3. Counter Expansion

RESET

CLOCK

CE MC14017B

Q0 Q1 Q8 Q9

•••

9 DECODED

OUTPUTS

CLOCK

FIRST STAGE INTERMEDIATE STAGES LAST STAGE

RESET

CLOCK

CE MC14017B

Q0Q1 Q8 Q9

•••

RESET

CLOCK

CE MC14017B

Q1 Q8 Q9

•••

8 DECODED

OUTPUTS

8 DECODED

OUTPUTS

Figure 4. AC Measurement Definition and Functional Waveforms

Pcp Ncp

CLOCK

ENABLE

trem

RESET

20 ns

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Cout

tPHL

tPLH

tTHL

tTLH

tPLH

tTLH tPLH

tPHL

50%

tPHL

90%

10%

tTHL

tPHL

tTHL tPHL

tTHL

tTLH

tTHL

tPHL

trem tsu 20 ns 20 ns

20 ns20 ns

tPLH

90%

10% 50%

tTLH

tTHL

tPHL

tTHL

90%

50%

10%

20 ns

tPLH

tTLH

VDD

VSS

VDD

VSS

VDD

VSS

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

MC14017B

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7

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

SOEIAJ−16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966−01

ISSUE A

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005) 0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

MC14017B

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8

PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE K NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

89

8X

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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MC14017B/D

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