DS25BR204EVK/NOPB - NATIONAL SEMICONDUCTOR

January 18, 2008

DS25BR204

3.125 Gbps 1:4 LVDS Repeater with Transmit Pre-

Emphasis and Receive Equalization

General Description

The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater opti-

mized for high-speed signal routing and switching over lossy

FR-4 printed circuit board backplanes and balanced cables.

Fully differential signal paths ensure exceptional signal in-

tegrity and noise immunity.

The device has two different LVDS input channels and a se-

lect line determines which input is active. Both inputs have

programmable equalization providing maximum signal

strength. A loss-of-signal (LOS) circuit monitors both input

channels and a unique LOS pin reports when no signal is de-

tected at that input.

Wide input common mode range allows the switch to accept

signals with LVDS, CML and LVPECL levels; the output levels

are LVDS. A very small package footprint requires a minimal

space on the board while the flow-through pinout allows easy

board layout. Each differential input and output is internally

terminated with a 100Ω resistor to lower device return losses,

reduce component count and further minimize board space.

Features

■DC - 3.125 Gbps low jitter, low skew, low power operation

■Pin selectable transmit pre-emphasis and receive

equalization eliminate data dependant jitter

■Wide Input Common Mode Range allows DC-coupled

interface to LVDS, CML and LVPECL drivers

■Redundant inputs

■Integrated 100Ω input and output terminations

■8 kV ESD on LVDS I/O pins protects adjoining

components

■Small 6 mm x 6 mm LLP-40 space saving package

Applications

■Clock and data distribution

■Clock and data buffering and muxing

■OC-48 / STM-16

■SD/HD/3GHD SDI Routers

Typical Application

30007703

DS25BR204 3.125 Gbps 1:4 LVDS Repeater with Pre-Emphasis and Equalization

Ordering Code

NSID Function Available Equalization

Levels

Available Pre-Emphasis

Levels

DS25BR204TSQ 1:4 Repeater Off / On Off / On

Block Diagram

30007701

Connection Diagram

30007702

DS25BR204 Pin Diagram

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DS25BR204

Pin Descriptions

Pin Name Pin

Number

I/O, Type Pin Description

IN1+, IN1-,

IN2+, IN2-,

4, 5,

6, 7,

I, LVDS Inverting and non-inverting high speed LVDS input pins.

OUT0+, OUT0-,

OUT1+, OUT1-,

OUT2+, OUT2-,

OUT3+, OUT3-

29, 28,

27, 26,

24, 23,

22, 21

O, LVDS Inverting and non-inverting high speed LVDS output pins.

EQ1, EQ2, 39,11 I, LVCMOS Receive equalization level select pins.

PE0, PE1,

PE2, PE3

31, 20,

19, 18

I, LVCMOS Transmit pre-emphasis level select pins.

SEL_in 14 I, LVCMOS Input select pin.

LOS2

LOS1

36,

O, LVCMOS Loss of Signal output pin, LOSn, reports when an open input fault

condition is detected at the input, INn. These are open drain

outputs. External pull up resistors are required.

PWDN0,

PWDN1,

PWDN2,

PWDN3

35,

34,

33,

I, LVCMOS Channel output power down pins. When the PWDNn is set to L,

the channel output, OUTn, is in the power down mode.

NC 1, 2,

9, 10,

12, 13,

17, 40

NC NO CONNECT pins. May be left floating.

PWDN 38 I, LVCMOS Device power down pin. When the PWDN is set to L, the device

is in the power down mode.

VDD 3, 8,

15,25, 30

Power Power supply pins.

GND 16, DAP Power Ground pin and a pad (DAP - die attach pad).

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DS25BR204

Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage −0.3V to +4V

LVCMOS Input Voltage −0.3V to (VCC + 0.3V)

LVCMOS Output Voltage −0.3V to (VCC + 0.3V)

LVDS Input Voltage −0.3V to +4V

LVDS Differential Input Voltage 0.0V to +1V

LVDS Output Voltage −0.3V to (VCC + 0.3V)

LVDS Differential Output Voltage 0.0V to +1V

LVDS Output Short Circuit Current

Duration 5 ms

Junction Temperature +150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature Range

Soldering (4 sec.) +260°C

Maximum Package Power Dissipation at 25°C

SQA Package 4.65W

Derate SQA Package 37.2 mW/°C above +25°C

Package Thermal Resistance

θJA +26.9°C/W

θJC +3.8°C/W

ESD Susceptibility

HBM (Note 1) ≥8 kV

MM (Note 2) ≥250V

CDM (Note 3) ≥1250V

Note 1: Human Body Model, applicable std. JESD22-A114C

Note 2: Machine Model, applicable std. JESD22-A115-A

Note 3: Field Induced Charge Device Model, applicable std.

JESD22-C101-C

Recommended Operating

Conditions

Min Typ Max Units

Supply Voltage (VCC) 3.0 3.3 3.6 V

Receiver Differential Input

Voltage (VID)

0 1 V

Operating Free Air

Temperature (TA)

−40 +25 +85 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 6, 7, 10)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS DC SPECIFICATIONS

VIH High Level Input Voltage 2.0 VDD V

VIL Low Level Input Voltage GND 0.8 V

IIH High Level Input Current VIN = 3.6V

VCC = 3.6V

0 ±10 μA

IIL Low Level Input Current VIN = GND

VCC = 3.6V

0 ±10 μA

VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V −0.9 −1.5 V

VOL Low Level Output Voltage IOL= 4 mA 0.4 V

LVDS INPUT DC SPECIFICATIONS

VID Input Differential Voltage 0 1 V

VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV

VTL Differential Input Low Threshold −100 0 mV

VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC -

0.05

IIN Input Current VIN = 3.6V or 0V

VCC = 3.6V or 0V

±1 ±10 μA

CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF

RIN Input Termination Resistor Between IN+ and IN- 100 Ω

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DS25BR204

Symbol Parameter Conditions Min Typ Max Units

LVDS OUTPUT DC SPECIFICATIONS

VOD Differential Output Voltage

RL = 100Ω

250 350 450 mV

ΔVOD Change in Magnitude of VOD for Complimentary

Output States -35 35 mV

VOS Offset Voltage

RL = 100Ω

1.05 1.2 1.375 V

ΔVOS Change in Magnitude of VOS for Complimentary

Output States -35 35 mV

IOS Output Short Circuit Current (Note 8) OUT to GND -35 -55 mA

OUT to VCC 7 55 mA

COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF

ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω

SUPPLY CURRENT

ICC Supply Current PE = OFF, EQ = OFF, PWDN = H 150 185 mA

ICCZ Power Down Supply Current PWDN = L 47 65 mA

Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and

ΔVOD.

Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

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DS25BR204

AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)

Symbol Parameter Conditions Min Typ Max Units

LVDS OUTPUT AC SPECIFICATIONS

tPLHD Differential Propagation Delay Low to

High (Note 11) RL = 100Ω

460 600 ps

tPHLD Differential Propagation Delay High to

Low (Note 11)

420 600 ps

tSKD1 Pulse Skew |tPLHD − tPHLD|

(Notes 10, 12)

40 100 ps

tSKD2 Channel to Channel Skew

(Notes 13, 11)

55 110 ps

tSKD3 Part to Part Skew

(Notes 11, 14)

50 190 ps

tLHT Rise Time (Note 11) RL = 100Ω 80 160 ps

tHLT Fall Time (Note 11) 80 160 ps

tON Any PWDN to Output Active Time 8 20 μs

tOFF Any PWDN to Output Inactive Time 5 12 ns

tSEL Select Time 5 12 ns

JITTER PERFORMANCE WITH EQ = Off, PE = Off(Note 11) (Figure 5)

tRJ1 Random Jitter (RMS Value)

No Test Channels

(Note 15)

VID = 350 mV

VCM = 1.2V

Clock (RZ)

2.5 Gbps 0.5 1 ps

tRJ2 3.125 Gbps 0.5 1 ps

tDJ1 Deterministic Jitter (Peak to Peak)

No Test Channels

(Note 16)

VID = 350 mV

VCM = 1.2V

K28.5 (NRZ)

2.5 Gbps 11 19 ps

tDJ2 3.125 Gbps 13 24 ps

tTJ1 Total Jitter (Peak to Peak)

No Test Channels

(Note 17)

VID = 350 mV

VCM = 1.2V

PRBS-23 (NRZ)

2.5 Gbps 0.05 0.10 UIP-P

tTJ2 3.125 Gbps 0.07 0.13 UIP-P

JITTER PERFORMANCE WITH EQ = Off, PE = On (Note 11)(Figure 6 Figure 9

tRJ1B Random Jitter (RMS Value)

Test Channel B

(Note 15)

VID = 350 mV

VCM = 1.2V

Clock (RZ)

2.5 Gbps 0.5 1 ps

tRJ2B 3.125 Gbps 0.5 1 ps

tDJ1B Deterministic Jitter (Peak to Peak)

Test Channel B

(Note 16)

VID = 350 mV

VCM = 1.2V

K28.5 (NRZ)

2.5 Gbps 10 23 ps

tDJ2B 3.125 Gbps 4 20 ps

tTJ1B Total Jitter (Peak to Peak)

Test Channel B

(Note 17)

VID = 350 mV

VCM = 1.2V

PRBS-23 (NRZ)

2.5 Gbps 0.06 0.10 UIP-P

tTJ2B 3.125 Gbps 0.05 0.13 UIP-P

JITTER PERFORMANCE WITH EQ = On, PE = Off (Note 11)(Figure 7 Figure 9)

tRJ1D Random Jitter (RMS Value)

Test Channel D

(Note 15)

VID = 350 mV

VCM = 1.2V

Clock (RZ)

2.5 Gbps 0.5 1 ps

tRJ2D 3.125 Gbps 0.5 1 ps

tDJ1D Deterministic Jitter (Peak to Peak)

Test Channel D

(Note 16)

VID = 350 mV

VCM = 1.2V

K28.5 (NRZ)

2.5 Gbps 17 30 ps

tDJ2D 3.125 Gbps 15 28 ps

tTJ1D Total Jitter (Peak to Peak)

Test Channel D

(Note 17)

VID = 350 mV

VCM = 1.2V

PRBS-23 (NRZ)

2.5 Gbps 0.07 0.13 UIP-P

tTJ2D 3.125 Gbps 0.08 0.15 UIP-P

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DS25BR204

Symbol Parameter Conditions Min Typ Max Units

JITTER PERFORMANCE WITH EQ = On, PE = On (Note 11)(Figure 8 Figure 9

tRJ1BD Random Jitter (RMS Value)

Input Test Channel D

Output Test Channel B

(Note 15)

VID = 350 mV

VCM = 1.2V

Clock (RZ)

2.5 Gbps 0.5 1 ps

tRJ2BD

3.125 Gbps 0.5 1 ps

tDJ1BD Deterministic Jitter (Peak to Peak)

Input Test Channel D

Output Test Channel B

(Note 16)

VID = 350 mV

VCM = 1.2V

K28.5 (NRZ)

2.5 Gbps 10 20 ps

tDJ2BD

3.125 Gbps 8 21 ps

tTJ1BD Total Jitter (Peak to Peak)

Input Test Channel D

Output Test Channel B

(Note 17)

VID = 350 mV

VCM = 1.2V

PRBS-23 (NRZ)

2.5 Gbps 0.07 0.12 UIP-P

tTJ2BD

3.125 Gbps 0.08 0.15 UIP-P

Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 11: Specification is guaranteed by characterization and is not tested in production.

Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel.

Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to

all outputs).

Note 14: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to

devices at the same VCC and within 5°C of each other within the operating temperature range.

Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.

Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted

algebraically.

Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.

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DS25BR204

DC Test Circuits

30007720

FIGURE 1. Differential Driver DC Test Circuit

AC Test Circuits and Timing Diagrams

30007721

FIGURE 2. Differential Driver AC Test Circuit

30007722

FIGURE 3. Propagation Delay Timing Diagram

30007723

FIGURE 4. LVDS Output Transition Times

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DS25BR204

Pre-Emphasis and Equalization Test Circuits

30007729

FIGURE 5. Jitter Performance Test Circuit

30007727

FIGURE 6. Pre-emphasis Performance Test Circuit

30007726

FIGURE 7. Equalization Performance Test Circuit

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DS25BR204

30007730

FIGURE 8. Pre-emphasis and Equalization Performance Test Circuit

30007728

FIGURE 9. Test Channel Block Diagram

Test Channel Loss Characteristics

The test channel was fabricated with Polyclad PCL-FR-370-

Laminate/PCL-FRP-370 Prepreg materials (Dielectric con-

stant of 3.7 and Loss Tangent of 0.02). The edge coupled

differential striplines have the following geometries: Trace

Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.

Test Channel Length

(inches)

Insertion Loss (dB)

500 MHz 750 MHz 1000 MHz 1250 MHz 1500 MHz 1560 MHz

A 10 -1.2 -1.7 -2.0 -2.4 -2.7 -2.8

B 20 -2.6 -3.5 -4.1 -4.8 -5.5 -5.6

C 30 -4.3 -5.7 -7.0 -8.2 -9.4 -9.7

D 15 -1.6 -2.2 -2.7 -3.2 -3.7 -3.8

E 30 -3.4 -4.5 -5.6 -6.6 -7.7 -7.9

F 60 -7.8 -10.3 -12.4 -14.5 -16.6 -17.0

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DS25BR204

Functional Description

The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater opti-

mized for high-speed signal routing and switching over lossy

FR-4 printed circuit board backplanes and balanced cables.

The DS25BR204 SEL_in pin selects one out of two available

LVDS inputs. The following is the input select truth tables.

Input Select Truth Table

CONTROL Pin (SEL_in) State Input Selected

0 IN1

1 IN2

The DS25BR204 has a pre-emphasis control pin for each

output for switching the transmit pre-emphasis to ON and

OFF setting and an equalization control pin for each input for

switching the receive equalization to ON and OFF setting. The

following are the transmit pre-emphasis and receive equal-

ization truth tables.

Transmit Pre-Emphasis Truth Table

OUTPUT OUTn, n = {0, 1, 2, 3}

CONTROL Pin (PEn) State Pre-emphasis Level

0 OFF

1 ON

Transmit Pre-emphasis Level Selection for an Output OUTn

Receive Equalization Truth Table

INPUT INn, n = {1, 2}

CONTROL Pin (EQn) State Equalization Level

0 OFF

1 ON

Receive Equalization Level Selection for an Input INn

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DS25BR204

Input Interfacing

The DS25BR204 accepts differential signals and allows sim-

ple AC or DC coupling. With a wide common mode range, the

DS25BR204 can be DC-coupled with all common differential

drivers (i.e. LVPECL, LVDS, CML). The following three fig-

ures illustrate typical DC-coupled interface to common differ-

ential drivers. Note that the DS25BR204 inputs are internally

terminated with a 100Ω resistor.

30007731

Typical LVDS Driver DC-Coupled Interface to an DS25BR204 Input

30007732

Typical CML Driver DC-Coupled Interface to an DS25BR204 Input

30007733

Typical LVPECL Driver DC-Coupled Interface to an DS25BR204 Input

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DS25BR204

Output Interfacing

The DS25BR204 outputs signals compliant to the LVDS stan-

dard. Its outputs can be DC-coupled to most common differ-

ential receivers. The following figure illustrates typical DC-

coupled interface to common differential receivers and

assumes that the receivers have high impedance inputs.

While most differential receivers have a common mode input

range that can accomodate LVDS compliant signals, it is rec-

ommended to check respective receiver's data sheet prior to

implementing the suggested interface implementation.

30007734

Typical DS25BR204 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver

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DS25BR204

Typical Performance

30007750

Total Jitter as a Function of Data Rate

30007751

Residual Jitter as a Function of Data Rate, FR4 Stripline

Length and EQ Level

30007755

Residual Jitter as a Function of Data Rate, FR4 Stripline

Length and PE Level

30007757

Supply Current as a Function of Data Rate and PE Level

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DS25BR204

Physical Dimensions inches (millimeters) unless otherwise noted

Order Number DS25BR204TSQ

NS Package Number SQA40A

(See AN-1187 for PCB Design and Assembly Recommendations)

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DS25BR204

Notes

DS25BR204 3.125 Gbps 1:4 LVDS Repeater with Pre-Emphasis and Equalization

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