1999-2013 Microchip Technology Inc. DS41120C-page 1
PIC16C717/770/771
18/20-Pin, 8-Bit CMOS Microcont rollers with 10/12-Bit A/D
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Interrupt capability (up to 10 internal/external
inter rupt so urc es)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Pow er- on Reset (POR )
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscilla tor f or relia ble opera tion
• Selectable oscillator options:
- INTRC - Internal RC, dual speed (4 MHz and
37 kHz nominal) dynamic ally s witc hable for
power savings
- ER - External resistor, dual speed (user
selectable frequency and 37 kHz nominal)
dynamically switchable for power savings
- EC - External clock
- HS - High speed crystal/resonator
- XT - Crystal/re son ator
- LP - Low power crystal
• Low power, high speed CMOS EPROM
technology
• In-Circuit Serial Programming™(ICSP™
• Wide operating voltage range: 2.5V to 5.5V
• 15 I/O pins with individual control for:
- Direction (15 pins)
- Digital/Analog input (6 pins)
- PORTB interrupt on change (8 pins)
- PORTB weak pull-up (8 pins)
- High voltage open drain (1 pin)
• Commercial and Industrial temperature ranges
• Low power consumption:
- < 2 mA @ 4V, 4 MHz
-11 A typical @ 2.5V, 37 kHz
-< 1 A typical standby current
Pin Diagr am
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be increm ent ed duri ng SLEEP via extern al
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Enhanced Capture, Compare, PWM (ECCP)
module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
- Enhanced PWM:
- Single, Half-Bridge and Full-Bridge Output
modes
- D ig it a lly pr ogra mmable deadband del ay
• Analog-to-Digital converter:
- PIC16C770/771 12-bit resolution
- PIC16C717 10- bit r esolution
• On-chip absolute bandgap voltage reference
generator
• Programmable Brown-out Reset (PBOR)
circuitry
• Programmable Low-Voltage Detection (PLVD)
circuitry
• Master Synchronous Serial Port (MSSP) with two
modes of opera tion:
- 3-wire SPI™ (supports all 4 SPI modes)
-I
2C™ compatible including Master mode
support
• Program Memory Read (PMR) capability for look-
up table, character string storage and checksum
calculation purposes
Device Memory Pins A/D
Resolution A/D
Channels
Program
x14 Data
x8
PIC16C717 2K 256 18, 20 10 bits 6
PIC16C770 2K 256 20 12 bits 6
PIC16C771 4K 256 20 12 bits 6
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
AVDD
AVSS
10 11
PIC16C770/771
20-Pin PDIP, SOIC, SSOP
PIC16C717/770/771
DS41120C-page 2 1999-2013 Microchip Technology Inc.
Pin Diagram s
18-Pin PDIP, SOIC
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PIC16C717
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD(2)
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS(1)
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
PIC16C717
VDD(2)
VSS(1)
10 11
20-Pin SSOP
Note 1: VSS pins 5 and 6 must be tied together.
2: VDD pins 15 and 16 must be tied together.
Key Features
PICmicroTM Mid-Range MCU Family
Reference Manual, (DS33023) PIC16C717 PIC16C770 PIC16C771
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR, MCLR,
WDT (PWRT, OST) POR, BOR, MCLR,
WDT (PWRT, OST) POR, BOR, MCLR,
WDT (PWRT, OST)
Program Memory (14-bit words) 2K 2K 4K
Data Memory (bytes) 256 256 256
Interrupts 10 10 10
I/O Ports Ports A,B Ports A,B Ports A , B
Timers 333
Enhanced Capture/Compare/PWM (ECCP)
modules 111
Serial Communications MSSP MSSP MSSP
12-bit Analog-to-Digital Module –6 input channels 6 input channels
10-bit Analog-to-Digital Module 6 input channels ––
Instruction Set 35 Instructions 35 Instructions 35 Instructions
1999-2013 Microchip Technology Inc. DS41120C-page 3
PIC16C717/770/771
Table of Contents
1.0 Device Overview......................................................................................................................................................5
2.0 Memory Organization...............................................................................................................................................9
3.0 I/O Ports.................................................................................................................................................................25
4.0 Program Memory Read (PMR) ..............................................................................................................................41
5.0 Timer0 Module.......................................................................................................................................................45
6.0 Timer1 Module.......................................................................................................................................................47
7.0 Timer2 Module.......................................................................................................................................................51
8.0 Enhanced Capture/Compare/PWM (ECCP) Modules............................................................................................53
9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................65
10.0 Voltage Reference Module and Low-voltage Detect..........................................................................................101
11.0 Analog-to-Digital Converter (A/D) Module..........................................................................................................105
12.0 Special Features of the CPU .............................................................................................................................117
13.0 Instruction Set Summary....................................................................................................................................133
14.0 Development Support ........................................................................................................................................141
15.0 Electrical Characteristics....................................................................................................................................147
16.0 DC and AC Characteristics Graphs and Tables................................................................................................. 179
17.0 Packaging Information .......................................................................................................................................197
APPENDIX A: Revision History ............................................. ...... ..... ...... ...................... ...... ..... ................................207
APPENDIX B: Device Differences ... ..... ...... ..... ...... ...... ...................... ...... ..... ....................... ..... ................................208
Index ..........................................................................................................................................................................209
On-Line Support..........................................................................................................................................................215
Reader Response.......................................................................................................................................................216
PIC16C717/770/771 Product Identification System....................................................................................................217
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PIC16C717/770/771
DS41120C-page 4 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 5
PIC16C717/770/771
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicroTM
Mid-Range MCU Family Reference Manual,
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip website. The Reference Manual should
be considered a complementary document to this data
sheet, and is highly recommended reading for a better
understanding o f the device arc hi tec ture a nd operatio n
of the peripheral modules.
There are thr ee devices (PIC16C7 17, P IC16C770 and
PIC16C771) covered by this data sheet. The
PIC16C717 device comes in 18/20-pin packages and
the PIC1 6C770/771 dev ices come in 2 0-p in packages.
The following two figures are device block diagrams of
the PIC16C717 and the PIC16C770/771.
FIGURE 1-1: PIC16C717 BLOCK DIAGRAM
EPROM
Program
Memory
2K x 14
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
256 x 8
Direct Addr 7
Addr(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
PORTA
PORTB
RA4/T0CKI
RB0/AN4/INT
RB4/SDI/SDA
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register .
Enhanced CCP Master
Timer0 Timer1 Timer2
Synchronous
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1/LVDIN
RA0/AN0
8
3
Timing
Generation
10-bit
ADC
RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
Internal
4 MHz, 37 kHz
and ER mode
(ECCP) Serial Port (MSSP)
B andgap
Reference Low-voltage
Detect
RAM
Program Memory
Read (PMR)
PIC16C717/770/771
DS41120C-page 6 1999-2013 Microchip Technology Inc.
FIGURE 1-2: PIC16C770/771 BLOC K DIAGRAM
EPROM
Program
Memory(2)
13 Data B us 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
256 x 8
Direct Addr 7
Addr(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
PORTA
PORTB
RA4/T0CKI
RB0/AN4/INT
RB4/SDI/SDA
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
2: Program memory for PIC16C770 is 2K x 14. Program memory for PIC16C771 is 4K x 14.
Enhanc ed C CP Master
Timer0 Timer1 Timer2
Synchronous
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1/LVDIN
RA0/AN0
8
3
Timing
Generation
12-bit
ADC
RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
Internal
4 MHz, 37 kHz
and ER mode
(ECCP) Serial Po rt (MSSP)
Bandgap
Reference Low-voltage
Detect
RAM
Program Memory
Read (PMR)
AVDD
AVSS
1999-2013 Microchip Technology Inc. DS41120C-page 7
PIC16C717/770/771
TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0 RA0 ST CMOS Bi-directional I/O
AN0 AN A/D input
RA1/AN1/LVDIN
RA1 ST CMOS Bi-directional I/O
AN1 AN A/D input
LVDIN AN LVD input reference
RA2/AN2/VREF-/VRL
RA2 ST CMOS Bi-directional I/O
AN2 AN A/D input
VREF- AN Negative analog reference input
VRL AN Internal voltage reference low output
RA3/AN3/VREF+/VRH
RA3 ST CMOS Bi-directional I/O
AN3 AN A/D input
VREF+ AN Positive analog reference input
VRH AN Internal voltage reference high output
RA4/T0CKI RA4 ST OD Bi-d irectional I/O
T0CKI ST TMR0 clock input
RA5/MCLR/VPP
RA5 ST Input port
MCLR ST Master clear
VPP Power Programming voltage
RA6/OSC2/CLKOUT
RA6 ST CMOS Bi-directional I/O
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
RA7/OSC1/CLKIN
RA7 ST CMOS Bi-directional I/O
OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/ER resistor connection
RB0/AN4/INT
RB0 TTL CMOS Bi-directional I/O(1)
AN4 AN A/D input
INT ST Interrupt input
RB1/AN5/SS
RB1 TTL CMOS Bi-directional I/O(1)
AN5 AN A/D input
SS ST SSP slave select input
RB2/SCK/SCL
RB2 TTL CMOS Bi-directional I/O(1)
SCK ST CMOS S erial clock I/O for SPI
SCL ST OD Serial clock I/O for I2C
RB3/CCP1/P1A
RB3 TTL CMOS Bi-directional I/O(1)
CCP1 ST CMOS Capture 1 input/Compare 1 output
P1A CMOS PWM P1A output
RB4/SDI/SDA
RB4 TTL CMOS Bi-directional I/O(1)
SDI ST Serial data in for SP I
SDA ST OD Serial data I/O for I2C
RB5/SDO/P1B
RB5 TTL CMOS Bi-directional I/O(1)
SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.
PIC16C717/770/771
DS41120C-page 8 1999-2013 Microchip Technology Inc.
RB6/T1OSO/T1CKI/P1C
RB6 TTL CMOS Bi-directional I/O(1)
T1OSO XTAL Crystal/Resonator
T1CKI CMOS TMR1 clock input
P1C CMOS PWM P1C output
RB7/T1OSI/P1D
RB7 TTL CMOS Bi-directional I/O(1)
T1OSI XTAL TMR1 crystal/resonator
P1D CMOS PWM P1D output
VSS VSS Power Ground reference for logic and I/O pins
VDD VDD Power Positive supply for logic and I/O pins
AVSS(2) AVSS Power Ground reference for analog
AVDD(2) AVDD Pow er Positive supply for analog
TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.
1999-2013 Microchip Technology Inc. DS41120C-page 9
PIC16C717/770/771
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these PIC®
microcontrollers. Each block (Program Memory and
Data Memory) has its own bus, so that concurrent
access can occur.
Addit ional informat ion on devi ce memory may be found
in the PICmicro Mid-Range MCU Family Reference
Manual, (DS33023).
2.1 Program Memory Organization
The PIC16C717/770/771 devices have a 13-bit pro-
gram counter capable of addressing an 8K x 14 pro-
gram memory space. The PIC16C717 and the
PIC16C770 have 2K x 14 words of program memory.
The PIC16C771 has 4K x 14 words of program mem-
ory. Accessing a location above the physically imple-
mented address will cause a wrap-around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK OF THE
PIC16C717 AND PIC16C770
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK OF THE
PIC16C771
2.2 Data Memory Organization
The data memory is partitioned into multiple banks,
whic h contain th e General Pu rpose Re gisters a nd the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00 Bank0
= 01 Bank1
= 10 Bank2
= 11 Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some frequently used special func-
tion registers from one bank are mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The registe r file can be accesse d either dire ctly , or ind i-
rectly, through the File Select Register FSR.
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Program
Memory Page 0 07FFh
3FFFh
RP1 RP0 (STATUS<6:5>)
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
3FFFh
PIC16C717/770/771
DS41120C-page 10 1999-2013 Microchip Technology Inc.
FIGURE 2-3: REGISTER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Indirect addr.(*)
ADRESL
PIR2 PIE2
ADRESH
ADCON0 ADCON1
General
Purpose
Register
General
Purpose
Register
EFh
F0h
accesses
70h-7Fh
96 Bytes
80 Bytes
LVDCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
17Fh
Bank 2
16Fh
170h
File
Address
PCL
STATUS
FSR
PCLATH
INTCON
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
1FFh
Bank 3
Indirect addr.(*)
OPTION_REG
1EFh
1F0h
accesses
70h - 7Fh
TRISB
PCL
STATUS
FSR
PCLATH
INTCON
Indirect addr.(*)
TMR0
General
Purpose
Register
accesses
70h - 7Fh
PORTB
80 Bytes
File
Address
File
Address
File
Address
REFCON
SSPCON2
WPUB
IOCB
ANSEL
P1DEL
PMDATL
PMADRL
PMDATH
PMADRH
PMCON1
1999-2013 Microchip Technology Inc. DS41120C-page 11
PIC16C717/770/771
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The spec ial function regi sters can be clas sified into two
sets ; core (CPU) and pe riphera l. Thos e regis ters a sso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Bank 0
00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
01h TMR0 Timer0 module’s register xxxx xxxx 45
02h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
03h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
04h(3) FSR Indirect data memory address pointer xxxx xxxx 23
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 25
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xx11 33
07h —Unimplemented — —
08h —Unimplemented — —
09h —Unimplemented — —
0Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
0Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
0Ch PIR1 —ADIF—— SSPIF CCP1IF TMR2IF TMR1IF -0---0000 18
0Dh PIR2 LVDIF — — —BCLIF— — — 0--- 0--- 20
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx 47
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx 47
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 47
11h TMR2 Timer2 module’s reg ister 0000 0000 51
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 51
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 70
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 67
15h CC PR1L Capture/Co mpare/PWM Register1 (LSB) xxxx xxxx 54
16h CC PR1H Capture/C ompare/PWM Register1 (MSB) xxxx xxxx 54
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53
18h —Unimplemented — —
19h —Unimplemented — —
1Ah —Unimplemented — —
1Bh —Unimplemented — —
1Ch —Unimplemented — —
1Dh —Unimplemented — —
1Eh ADRESH A/D High Byte Result Register xxxx xxxx 107
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 107
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
PIC16C717/770/771
DS41120C-page 12 1999-2013 Microchip Technology Inc.
Bank 1
80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15
82h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
83h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
84h(3) FSR Indirect data memory address pointer xxxx xxxx 23
85h TRISA PORTA Data Direction Register 1111 1111 25
86h TRISB POR TB Data Direction Register 1111 1111 33
87h —Unimplemented — —
88h —Unimplemented — —
89h —Unimplemented — —
8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
8Ch PIE1 —ADIE—— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 17
8Dh PIE2 LVDIE — — —BCLIE— — — 0--- 0--- 19
8Eh PCON — — — —OSCF—PORBOR ---- 1-qq 21
8Fh —Unimplemented — —
90h —Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 69
92h PR2 Timer2 Period Register 1111 1111 52
93h SSPADD Synch ro no us Serial Port (I2C mode) Address Regist er 0000 0000 76
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 66
95h WPUB PORTB Weak Pull-up Control 1111 1111 34
96h IOCB PORTB Interr upt on C han ge Contro l 1111 0000 34
97h P1DEL PWM 1 Delay value 0000 0000 62
98h —Unimplemented — —
99h —Unimplemented — —
9Ah —Unimplemented — —
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 102
9Ch LVDCON —— BGST LVDEN LVV3 LVV2 LVV1 LVV0 --00 0101 101
9Dh ANSEL — — Analog Channel Select --11 1111 25
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx 107
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 107
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
1999-2013 Microchip Technology Inc. DS41120C-page 13
PIC16C717/770/771
Bank 2
100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
101h TMR0 Timer0 module’s register xxxx xxxx 45
102h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
103h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
104h(3) FSR Indirect data memory address pointer xxxx xxxx 23
105h —Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx11 33
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
10Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
10Ch PMDATL Program memory read data low xxxx xxxx
10Dh PMADRL Program memory read address low xxxx xxxx
10Eh PMDATH —— Program memory read data high --xx xxxx
10Fh PMADRH — — — — Program memory read address high ---- xxxx
110h-
11Fh —Unimplemented — —
Bank 3
180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15
182h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
183h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
184h(3) FSR Indirect data memory address pointer xxxx xxxx 23
185h —Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 33
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
18Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
18Ch PMCON1 Reserved — — — — — —RD1--- ---0
18Dh-
18Fh —Unimplemented — —
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
PIC16C717/770/771
DS41120C-page 14 1999-2013 Microchip Technology Inc.
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the ar ithmetic st atus of th e ALU, the RESET st atus and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set t he Z bit. T his leav es the STA T US regist er
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affe ct the Z, C or D C bits from th e ST ATUS register. For
other instructions not affecting any status bits, see the
"Instruction Set Summary."
REGISTER 2-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Regist er Bank Select bit (used for indire ct add ressing)
1 = Bank 2, 3 ( 100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instru cti on
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF in st ruct ion s) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 15
PIC16C717/770/771
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register, which cont ains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able re gister known a lso as the pres caler), t he Ext ernal
INT Int errupt, T MR0 and the w eak pul l-up s on POR TB.
REGISTER 2-2: OPTION REGISTER (OPTION_REG: 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit(1)
1 = PORTB weak pull-ups are disabled
0 = PORTB weak pull-ups are enabled by the WPUB register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit
1 = Transition on RA4/T0 CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: Individua l w ea k pul l-u p on R B pin s ca n be enab led/disable d from the w ea k pu ll-u p
PORTB Register (WPUB).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C717/770/771
DS41120C-page 16 1999-2013 Microchip Technology Inc.
2.2.2.3 INTCON REGISTER
The INTCO N Register is a read able and writ able regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interru pt fla g bit s get se t when an in terru pt
conditi on occ urs , re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all int erru pts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR 0 interr upt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit(1)
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 regist er has overfl owed (must be clear ed in softw are)
0 = TMR0 reg i ster did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cl eared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB<7:0> pins changed state (must be cleared in software)
0 = None of the RB<7:0> pins have changed state
Note 1: Individual RB pin interrupt-on-change can be enabled/disabled from the
Interrupt-on-Change PORTB register (IOCB).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 17
PIC16C717/770/771
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1: 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE—— SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 Unimplemented: Read as ’0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D inte rru pt
bit 5-4 Unimplemented: Read as ’0’
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP inte rru pt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrup t
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 18 1999-2013 Microchip Technology Inc.
2.2.2.5 PIR1 REGISTE R
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5: PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch)
Note: Interru pt fla g bit s get se t when an in terru pt
conditi on occ urs , re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIF—— SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’.
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ’0’
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interru pt condition ha s occurred, and must be c leared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI A transmission/reception has taken place.
I2 C Slave / Master
A transmission/reception has taken place.
I2 C Master
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was IDLE (Multi-master system).
A STOP condition occurred while the SSP module was IDLE (Multi-master system).
0 = No SSP interrupt condition has occurred.
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR 1 register capture occurred (must be cleared in softw are)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 reg i ster did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 19
PIC16C717/770/771
2.2.2.6 PIE2 REGISTER
This register contains the individual enable bits for the
SSP bus collision and low voltage detect interrupts.
REGISTER 2-6: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2: 8Dh)
R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
LVDIE ———BCLIE———
bit 7 bit 0
bit 7 LVDIE: Low Voltage Detect Interrupt Enable bit
1 = LVD Interrupt is enabled
0 = LVD Interrupt is disabled
bit 6-4 Unimplemented: Read as '0'
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Bus Collision interrupt is enabled
0 = Bus Collision interrupt is disabled
bit 2-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 20 1999-2013 Microchip Technology Inc.
2.2.2.7 PIR2 REGISTE R
This register contains the SSP Bus Collision and low-
voltage detect interrupt flag bits.
.
REGISTER 2-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)
Note: Interru pt fla g bit s get se t when an in terru pt
conditi on occ urs , re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
LVDIF ———BCLIF———
bit 7 bit 0
bit 7 LVDIF: Low Voltage Detect Interrupt Flag bit
1 = The supply vo ltage has fallen b elow the spe cified LVD voltage (must be c leared in s oftware)
0 = The supply voltage is greater than the specified LVD voltage
bit 6-4 Unimplemented: Read as '0'
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred while the SSP module configured in I2C Master was
transmitting (must be cleared in software)
0 = No bus collision occurred
bit 2-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 21
PIC16C717/770/771
2.2.2.8 PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry con-
tain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
The PCON register also contains the frequency select
bit of the INTRC or ER oscilla tor.
REGISTER 2-8: POWER CONTROL REGISTER (PCON: 8Eh)
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR is
clear, indicati ng a brown-ou t has occurre d.
The BOR status bit is a don't care and is
not necessarily predictable if the bro wn-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-q R/W-q
————OSCF—PORBOR
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3 OSCF: Oscillator Speed bit
INTRC Mode
1 = 4 MHz nominal
0 = 37 kHz nominal
ER Mode
1 = Oscillator frequency depends on the external resistor value on the OSC1 pin.
0 = 37 kHz nominal
All other modes
x = Ignored
bit 2 Unimplemented: Read as '0 '
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit (See Section 2.2.2.8 Note)
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend: q = Value depends on conditions
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 22 1999-2013 Microchip Technology Inc.
2.3 PCL and PCLATH
The pr ogra m cou nter (PC) speci fie s th e a ddress of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits an d is n ot d irec tly re ada ble or writ ab le. All upd ate s
to the PCH register occur through the PCLA TH register .
2.3.1 PROGRAM MEMORY PAGING
PIC16C717/770/771 devices are capable of address-
ing a continuous 8K word block of program memory.
The CALL and GOTO instruc tions provi de onl y 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the us er must ensure tha t the page select bit s are
programmed so that the desired program memory
page is addressed. A return instruction pops a PC
address off the stack onto the PC register. Therefore,
manipu lation of the PCLATH<4:3> bit s are not req uired
for the return instructions (which POPs the address
from the stack).
2.4 Stack
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address f rom this b ranch in program execution.
Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writ able. The PC is PUSHed ont o the st ack
when a CALL instruction is executed or an interrupt
causes a bran ch . The s t ac k is PO Ped in the ev en t of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH i s n ot mo di fie d wh en t h e s tack i s P US Hed o r
POPed.
Aft er the st ack has been PUSHed e ight times, the nin th
push ov erwrite s the va lue tha t was store d fro m the first
push. The tenth pus h ov erwr i tes the se cond push (an d
so on).
FIGURE 2-4: LOADING OF PC IN
DIFFERENT SITUATIONS
Instruction with
PCL as
Destination
8ALU
12 0
11 Opcode <10:0>
GOTO, CALL
PCLATH<4:3>
PCLATH
PCLATH
87
PCLATH<4:0>
12 1110 870
PCH PCL
PCH PCL
5
2
1999-2013 Microchip Technology Inc. DS41120C-page 23
PIC16C717/770/771
The INDF register is not a physical register. Address-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: How to Clear RAM Using
Indirect Addressing
An effective 9-bit address is obtained by concatenating
the 8-bit FSR reg ister and the IRP bi t (ST A TU S<7>), as
shown in Figure 2-5.
FIGURE 2-5: DIRECT/INDI RECT ADDRE SSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
Note 1: For register file map detail see Figure 2-3.
Data
Memory(1)
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
PIC16C717/770/771
DS41120C-page 24 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 25
PIC16C717/770/771
3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al inf orm atio n o n I/O port s ma y be found i n th e
PIC Mid-Range MCU Family Reference Manual,
(DS33023).
3.1 I/O Port Analog/Digital Mode
The PIC16C717/770/771 have two I/O ports: PORTA
and PORTB. Some of th ese port pins are mixed - si gna l
(can be digital or analog). When an analog signal is
prese nt on a pin, the pin must be co nfigured as an ana-
log inpu t to prev ent unn eces sary c urrent d raw from th e
power supply. The Analog Select Register (ANSEL)
allows the user to individually select the Digital/Analog
mode on these pins. When the Analog mode is active,
the port pin will always read 0.
REGISTER 3-1: ANALOG SELECT REGISTER (ANSEL: 9Dh)
3.2 PORTA and the TRISA Register
PORTA is a 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bi t (=1) will m ake t he co rrespon ding POR TA pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISA bit (=0) will
make the correspon ding POR TA pin an out put (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, where as wri tin g to i t wi ll write to th e port latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read, thi s valu e is mod ified, and the n writ ten to th e port
data l atch.
Pins RA<3:0> are multiplexed with analog functions,
such as analog inputs to the A/D converter, analog
VREF inputs, and the onboard bandgap reference out-
puts. When the analog peripherals are using any of
these pins as analog input/output, the ANSEL register
must have the proper value to individually select the
Analog mode of the corresponding pins.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schm itt Trigger inp ut and an ope n drai n outpu t.
Pin RA5 i s multi plexed wi th the device RESET (MCLR)
and programming input (VPP) functions. The RA5/
MCLR/VPP input only pin has a Schmitt Trigger input
buffer. All other RA port pins have Schmitt Trigger input
buffers and full CMOS output buffers.
Pins RA6 and RA7 are multiplexed with the oscillator
input and output functions.
The TRISA register controls the direction of the RA
pins, ev en w he n th ey a re being used as ana log inp uts.
The user mu st ensure the bit s in the TRISA registe r are
maintained set when using them as analog inputs.
Note 1: On a Power-on Reset, the ANSEL regis-
ter configures these mixed-signal pins as
Analog mode.
2: If a pin is config ured as Analog mo de, the
RA pin w ill a lways read '0' and RB pi n will
always read '1', even if the digital output is
active.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—— ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
bit 7-6 Reserved: Do not use
bit 5-0 ANS<5:0>: Analog Select between analog or digital function on pins AN<5:0>, respectively.
0 = Digital I/O. Pin is assigned to port or special function.
1 = Analog Input. Pin is assigned as analog input.
Note: Setting a pin to an analog input disables the digital input buffer on the pin. The cor-
responding TRIS bit should be set to Input mode when using pins as analog inputs.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
Note: Upon RESET, the ANSEL register config-
ures the RA<3:0> pins as analog inputs.
All RA<3:0> pins will read as '0'.
PIC16C717/770/771
DS41120C-page 26 1999-2013 Microchip Technology Inc.
EXAMPLE 3-1: Initializing PORTA
FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0, RA1/AN1/LVDIN
BCF STATUS, RP0 ; Select Bank 0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0Fh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<7:4> as outputs. RA<7:6>availability depends on oscillator selection.
MOVLW 03 ; Set RA<1:0> as analog inputs, RA<7:2> are digital I/O
MOVWF ANSEL
BCF STATUS, RP0 ; Return to Bank 0
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
PORT
WR
TRIS
Data Latch
TRIS Mode
VSS
VDD
Schmitt
Trigger
To A/D Converter input or LVD Module input
RD
TRIS
QD
Q
CK
Analog Select
WR
ANSEL
RD
PORT
VDD
VSS
1999-2013 Microchip Technology Inc. DS41120C-page 27
PIC16C717/770/771
FIGURE 3-2: BLOCK DIAGRAM OF RA2/AN2/VREF-/VRL AND RA3/AN3/VREF+/ VRH
To A/D Converter input
VRH, VRL outputs
(From VREF-LVD-BOR Module)
and VREF+, VREF- inputs
Sense input for
VRH, VRL amplifier
VRH, VRL output enable
Data
Bus
QD
Q
CK
QD
Q
CK P
N
WR
PORT
WR
TRIS
Data Latch
TRIS Mode
VSS
VDD
Schmitt
Trigger
RD
TRIS
QD
Q
CK
Analog Select
WR
ANSEL
RD
PORT
VDD
VSS
QD
EN
PIC16C717/770/771
DS41120C-page 28 1999-2013 Microchip Technology Inc.
FIGURE 3-3: BLOCK DIAGRAM OF RA4/T0CKI
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
N
WR
Port
WR
TRIS
Data Latch
RD
VSS
Schmitt Trigger
Input Buffer
TMR0 clock input
RD
TRIS
TRIS Latch
PORT
VSS
1999-2013 Microchip Technology Inc. DS41120C-page 29
PIC16C717/770/771
FIGURE 3-4: BLOCK DIAGRAM OF RA5/MCLR/VPP
Data
Bus
QD
EN
RD PORT
Schmitt
Trigger
RD
TRIS
VSS
To MCLR Circuit MCLR Filter
VSS
HV Detect
Program Mode
PIC16C717/770/771
DS41120C-page 30 1999-2013 Microchip Technology Inc.
FIGURE 3-5: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
Q
D
Q
CK
Schmitt Trigger
Input Buffer
Oscillator
Circuit
From OSC1
1
0
CLKOUT (Fosc/4)
(INTRC or ER) and CLKOUT
VDD
VSS
DQ
EN
EC or [(ER or INTRC) and CLKOUT]
1999-2013 Microchip Technology Inc. DS41120C-page 31
PIC16C717/770/771
FIGURE 3-6: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Vss
VDD
Q
D
Q
CK
Schmitt Trigger
Input Buffer
Oscillator
Circuit
To OSC2
INTRC
INTRC
Schmitt Trigger
Input Buffer
To Chip Clock Drivers
EC Mode
VDD
DQ
EN
PIC16C717/770/771
DS41120C-page 32 1999-2013 Microchip Technology Inc.
TABLE 3-1: PORTA FUNCTIONS
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Function Input
Type Output
Type Description
RA0/AN0 RA0 ST CMOS Bi-directional I/O
AN0 AN A/D input
RA1/AN1/LVDIN
RA1 ST C MOS B i-directional I/O
AN1 AN A/D input
LVDIN AN LVD input reference
RA2/AN2/VREF-/VRL
RA2 ST C MOS B i-directional I/O
AN2 AN A/D input
VREF- AN Negative analog reference input
VRL AN Internal voltage reference low output
RA3/AN3/VREF+/VRH
RA3 ST C MOS B i-directional I/O
AN3 AN A/D input
VREF+ AN Positive analog reference input
VRH AN Internal voltage reference high output
RA4/T0CKI RA4 ST OD Bi-directional I/O
T0CKI ST TMR0 clock input
RA5/MCLR/VPP
RA5 ST Input port
MCLR ST Master clear
VPP Power Programming voltage
RA6/OSC2/CLKOUT
RA6 ST C MOS B i-directional I/O
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
RA7/OSC1/CLKIN
RA7 ST C MOS B i-directional I/O
OSC1 XTAL Crystal/resonator
CLKIN ST/AN External clock input/ER resistor connection
Address Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 uuuu 0000
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
1999-2013 Microchip Technology Inc. DS41120C-page 33
PIC16C717/770/771
3.3 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bi t (=1) will m ake the c orresponding POR TB pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e.,
put the contents of the outpu t latch on the select ed pin).
EXAMPLE 3-2: Initializing PORTB
Each of the PO R TB pins has an inte rnal pul l-up , whic h
can be individually enabled from the WPUB register. A
single global enabl e bit can turn o n/off th e enabled pul l-
ups. Clearing the RBPU bit, (OPTION_REG<7>),
enables t he wea k pul l-up r esi stors. The weak pul l-up i s
automat icall y turned of f when the port pi n is co nfigure d
as an output. The pull-ups are di sabled on a Powe r-on
Reset.
Each of the PORTB pins, if configured as input, also
has an interrupt-on-change feature, which can be indi-
vidually selected from the IOCB register. The RBIE bit
in the INTCON reg ister functio ns as a gl obal enable b it
to turn on/off the interrupt-on-change feature. The
selected inputs are compared to the old value latched
on the l ast read of POR TB. The "m ismatch" out puts are
OR'ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrup t service routin e, can clear the int er-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
a) Clear flag bit RBIF.
A mism at c h c ond it i on wi ll cont i n ue to s et f lag bi t RB IF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
BCF STATUS, RP0;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
MOVLW 0x30 ; Set RB<1:0> as analog
inputs
MOVWF ANSEL ;
BCF STATUS, RP0; Return to Bank 0
PIC16C717/770/771
DS41120C-page 34 1999-2013 Microchip Technology Inc.
REGISTER 3-2: WEAK PULL-UP PORTB REGIS TER (WPU B: 95h)
REGISTER 3-3: INTERRUPT-ON-CHANGE PORTB REGISTER (IOCB: 96h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
bit 7-0 WPUB<7:0>: PORTB Weak Pull-Up Control bits
1 = Weak pull-up enabled
0 = Weak pull-up disabl ed
Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG
register must be cleared.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRIS = 0).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
bit 7 bit 0
bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note: The interrupt enable bits GIE and RBIE in the INTCON Register must be set for indi-
vidual interrupts to be recognized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 35
PIC16C717/770/771
The RB0 pin i s mu ltiple xed w ith th e A /D conv erter an a-
log input 4 and the external interrupt input (RB0/AN4/
INT). Whe n the pin is used as anal og input, the ANSEL
register must have the proper value to select the RB0
pin as Analog mo de.
The RB1 pin i s mu ltiple xed w ith th e A/D co nverte r an a-
log input 5 and the MSSP module slave select input
(RB1/AN5/SS). When the pin is used as analog input,
the ANSEL register must have the proper value to
select the RB1 pin as Analog mode.
FIGURE 3-7: BLOCK DIAGRAM OF RB0/AN4/INT, RB1/AN5/SS PIN
Note: Upon RESET, the ANSEL register config-
ures th e RB1 and RB0 pins as analog inputs.
Both R B1 an d R B0 pi ns w i ll re ad as '1 '.
Data Bus
WR
WR
RD
PORTB Reg
TRIS Reg
To INT input or MSSP module
Q
D
CK
Q
D
CK
EN
QD
EN
RD
RBPU weak
pull-up
TTL
Schmitt
Trigger
P
N
VSS
VDD
Q
D
CK
Q
D
CK
WPUB Reg
IOCB Reg
PORT
TRIS
PORT
TRIS
WR
WPUB
Q
D
Q
EN
D
Q
EN
Q3
Q1
...
Set
RBIF
From
RB<7:0> pins
Q
QD
Q
CK
Analog Select
WR
ANSEL
WR
IOCB
VDD
VSS
Q
P
VDD
Q
To A/D Converter
PIC16C717/770/771
DS41120C-page 36 1999-2013 Microchip Technology Inc.
FIGURE 3-8: BLOCK DIAGRAM OF RB2/SCK/SCL, RB3/CCP1/P1A, RB4/SDI/SDA,
RB5/SDO/P1B
Data Bus
WR
WR
RD
PORTB Reg
TRIS Reg
SCK, SCL, CC, SDI, SDA inputs
Q
D
CK
Q
D
CK
EN
QD
EN
RD
RBPU weak
pull-up
Schmitt
Trigger
P
N
VSS
VDD
Q
D
CK
Q
D
CK
WPUB Reg
IOCB Reg
PORT
TRIS
PORT
TRIS
WR
WPUB
Q
D
Q
EN
D
Q
EN
Q3
Q1
...
Set
RBIF
From
RB<7:0> pins
Q
WR
IOCB
VDD
VSS
Q
P
VDD
Q
1
0
Spec. Func En.
SDA, SDO, SCK, CCP1, P1A, P1B
TTL
1999-2013 Microchip Technology Inc. DS41120C-page 37
PIC16C717/770/771
FIGURE 3-9: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/P1C
Data Latch
TRIS Latch
RD TRISB
P
VSS
Q
D
Q
CK
Q
D
QCK N
VDD
RD PORTB
WR PORTB
WR TRISB
T1OSCEN
TMR1 Clock
RBPU VDD
weak pull-up
P
From R B7
From QD
EN
Set RBIF
RB<7:0> pins RD Port
Q3
Q1
Serial programming clock
TTL
Input
Buffer
TMR1 Oscillator
QD
EN
VDD
Data Bus Q
D
CK
WPUB Reg
WR
WPUB Q
IOCB Reg
WR
IOCB
Q
D
CK Q
Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB6 I/O port and P1C functions.
...
Schmitt
Trigger
CMOS
PIC16C717/770/771
DS41120C-page 38 1999-2013 Microchip Technology Inc.
FIGURE 3-10: BLOCK DIAGRAM OF THE RB7/T1OSI/P1D
Data Latch
TRIS Latch
RD TRISB
P
VSS
Q
D
QCK
Q
D
Q
CK N
VDD
RD PORTB
WR PORTB
WR TRISB
T10SCEN
T1OSCEN
To RB6
RBPU VDD
weak pull-up
P
TTL
Input
Buffer
From QD
EN
QD
EN
Set RBIF
RB<7:0> pins RD Port
Q3
Q1
Serial programming input
Schmitt Trigger
TMR1 Oscillator
VDD
Data Bus Q
D
CK
WPUB Reg
WR
WPUB Q
Q
D
CK
IOCB Reg
WR
IOCB Q
Note: The TMR1 oscillator enable (T1OSCEN = 1) overr ides the RB7 I/O port and P1D functions.
...
1999-2013 Microchip Technology Inc. DS41120C-page 39
PIC16C717/770/771
TABLE 3-3: PORTB FUNCTIONS
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Function Input
Type Output
Type Description
RB0/AN4/INT
RB0 TTL CMOS Bi-directional I/O(1)
AN4 AN A/D input
INT ST Interrupt input
RB1/AN5/SS
RB1 TTL CMOS Bi-directional I/O(1)
AN5 AN A/D input
SS ST S SP slave select input
RB2/SCK/SCL
RB2 TTL CMOS Bi-directional I/O(1)
SCK ST CMOS S erial clock I/O for SPI
SCL ST OD Serial clock I/O for I2C
RB3/CCP1/P1A
RB3 TTL CMOS Bi-directional I/O(1)
CCP1 ST CMOS Capture 1 input/Compare 1 output
P1A CMOS PWM P1A output
RB4/SDI/SDA
RB4 TTL CMOS Bi-directional I/O(1)
SDI ST Serial data in for SP I
SDA ST OD Serial data I/O for I2C
RB5/SDO/P1B
RB5 TTL CMOS Bi-directional I/O(1)
SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output
RB6/T1OSO/T1CKI/P1C
RB6 TTL CMOS Bi-directional I/O(1)
T1OSO XTAL Crystal/Resonator
T1CKI CMOS TMR1 clock input
P1C CMOS PWM P1C output
RB7/T1OSI/P1D
RB7 TTL CMOS Bi-directional I/O(1)
T1OSI XTAL T MR1 cry stal/resonator
P1D CMOS PWM P1D output
Note 1: Bit programmable pull-ups.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
V alue on all
other
RESETS
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB 0 xxxx xx11 uuuu uu11
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
95h W PUB PORTB Weak Pull-up Control 1111 1111 1111 1111
96h IOCB PORTB Interrupt on Change Control 1111 0000 1111 0000
9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C717/770/771
DS41120C-page 40 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 41
PIC16C717/770/771
4.0 PROGRAM MEMORY READ
(PMR)
Program memory is readable during normal operation
(full VDD range). It is indirectly addressed through the
Special Function Registers:
•PMCON1
•PMDATH
•PMDATL
• PMADRH
• PMADRL
When interfacing the program memory block, the
PMDATH & PMDATL registers form a 2-byte word,
which hold s the 14-bit dat a. The PMADRH & PMADRL
registers form a 2-byte word, which holds the 12-bit
address of the program memory location being
accessed. Mid-range devices have up to 8K words of
program EPROM with an address range from 0h to
3FFFh. When the device contains less memory than
the full address range of the PMADRH:PMARDL regis-
ters, the Most Significant bits of the PMADRH register
are ignored.
4.1 PMCON1 REGISTER
PMCON1 is the control register for program memory
accesses.
Control bit RD initiates a rea d operation. This bit cann ot
be cleared, only set, in software. It is cleared in hard-
ware at completion of the read operation.
REGISTER 4-1: PROGRAM MEMORY READ CONTROL REGISTER 1 (PMCON1: 18Ch)
4.2 PMDATH AND PMDATL
REGISTERS
The PMDATH:PMDATL registers are loaded with the
contents of program memory addressed by the
PMADRH and PMADRL registers upon completion of a
Program Memory Read command.
R-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0
Reserved ——————RD
bit 7 bit 0
bit 7 Reserved: Read as ‘1’
bit 6-1 Unimplemented: Read as '0'
bit 0 RD: Read Control bit
1 = Initiates a Program memory read (read takes 2 cycles). RD is cleared in hardware.
0 = Reserved
Legend: S = Settable (cleared in hardware)
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 42 1999-2013 Microchip Technology Inc.
REGISTER 4-2: PROGRAM MEMORY DATA HIGH (PMDATH: 10Eh)
REGISTER 4-3: PROGRAM MEMORY DATA LOW (PMDATL: 10Ch)
REGISTER 4-4: PROGRAM MEMORY ADDRESS HIGH (PMADRH: 10Fh)
REGISTER 4-5: PROGRAM MEMORY ADDRESS LOW (PMADRL: 10Dh)
U-0 U-0 R-x R-x R-x R-x R-x R-x
—— PMD13 PMD12 PMD11 PMD10 PMD9 PMD8
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL
after a Program Memory Read command.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
R-x R-x R-x R-x R-x R-x R-x R-x
PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0
bit 7 bit 0
bit 7-0 PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after
a Progr am Memory Read command.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
———— PMA11 PMA10 PMA9 PMA8
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3-0 PMA<11:8>: PMR Address bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0
bit 7 bit 0
bit 7-0 PMA<7:0>: PMR Address bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 43
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4.3 READING THE EPROM PROGRAM
MEMORY
To read a program memory location, the user must
write 2 bytes of the address to the PMADRH and
PMADRL registers, then set control bit RD
(PMCON1<0>). Once the read control bit is set, the
Program Memory Read (PMR) controller will use the
second instruction cycle after to read the data. This
causes the second instruction immediately following
the “BSF PMCON1,RD” instruction to be ign ored. Th e dat a
is ava il abl e, in the very nex t c y cle , i n the PM DATH and
PMDATL registers; therefore it can be read as 2 bytes
in the following instructions. PMDATH and PMDATL
registers will hold this value until another Program
Memory Read or until it is written to by the user.
EXAMPLE 4-1: OTP PROGRAM MEMORY Read
4.4 OPERATION DURING CODE
PROTECT
When the device is code protected, the CPU can still
perform the P rogram Memory Read function .
FIGURE 4-1: PROGRAM MEMO RY READ CYCLE EXECUTION
Note: The two instructions that follow setting the
PMCON1 read bit must be NOPs.
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW MS_PROG_PM_ADDR ;
MOVWF PMADRH ; MS Byte of Program Memory Address to read
MOVLW LS_PROG_PM_ADDR ;
MOVWF PMADRL ; LS Byte of Program Memory Address to read
BSF STATUS, RP0 ; Bank 3
BSF PMCON1, RD ; Program Memory Read
NOP ; This instruction must be an NOP
NOP ; This instruction must be an NOP
next instruction ; PMDATH:PMDATL now has the data
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF PMCON1,RD
Executed here INSTR(PC+1)
Executed here Forced NOP
Executed here
PC PC+1 PMADRH,PMADRL PC+3 PC+5
Program
RD bit
PC+3 PC+4
INSTR(PC-1)
Executed here INSTR(PC+3)
Executed here INSTR(PC+4)
Execut ed her e
PMDATH
PMDATL
register
Memory
ADDR
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TABLE 4-1: PROGRAM MEMORY READ REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
18Ch PMCON1 Reserved ——————RD
1--- ---0 1--- ---0
10Eh PMDATH — — PMD13 PMD12 PMD11 PMD10 PMD9 PMD8 --xx xxxx --uu uuuu
10Ch PMDATL PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 xxxx xxxx uuuu uuuu
10Fh PMADRH — — — — PMA11 PMA10 PMA9 PMA8 ---- xxxx ---- uuuu
10Dh PMADRL PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not us ed by Program Memory Read.
1999-2013 Microchip Technology Inc. DS41120C-page 45
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5.0 TIMER0 MODULE
The T imer0 modul e timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 5-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PIC Mid-Range MCU Family Reference Manual,
(DS33023).
5.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule wi ll i ncr em en t ev ery instruction cycle (w ith ou t pre s-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in below.
When an external cl ock input i s used for T ime r0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the PIC Mid-Range MCU Family Refer-
ence Manual, (DS33023).
5.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 5-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
availa ble which is mutuall y exclusive ly shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
The prescaler is not readable or writable.
The PSA and PS<2:0> bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing b it PSA will assign t he prescaler to the T imer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 regist er (e.g. CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
FIGURE 5-1: TIMER0 BLOCK DIAGRAM
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Note 1: T0CS, T0SE, PSA, PS<2:0> (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 5- 2 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
Fosc/4
Programmable
Prescaler
Sync with
Internal
clocks TMR0
PSout
(2 Tcy delay)
PSout
Data Bus
8
PSA
PS2, PS1, PS0 Set interrupt
flag bit T0IF
on overflow
3
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5.2.1 SWITCHING PRESCA LER
ASSIGNMENT
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
5.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in sof tware b y the Timer0 module interrup t ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
FIGURE 5-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PIC Mid-Range Reference Manual,
DS33023) must be executed when chang-
ing the prescaler assignment from Timer0
to the WDT. This sequence must be fol-
lowed even if the WDT is disabled.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other
RESETS
01h,101h TMR0 Timer0 register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Ti mer0.
RA4/T0CKI
T0SE
Pin
M
U
X
CLKOUT (= Fosc/4)
SYNC
2
Cycles TMR 0 re g
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS<2:0>
8
Note: T0CS, T0SE, PS A , PS<2:0 > a re (OPTIO N_ R EG< 5:0 > ).
PSA
WDT Enable Bit
M
U
X
0
10
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
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6.0 TIMER1 MODULE
The T imer1 modul e timer/counter has the following fea-
tures:
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• Readable and writable (Both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• RESET from ECCP module trigger
Timer1 has a control register, shown in Register 6-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1O N (T1CON <0 >).
Figure 6-2 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PIC Mid-Range MCU Family Reference Manual,
(DS33023).
6.1 Timer1 Operation
Timer1 can ope rate in one of these mo des :
•As a timer
• As a synchronous counter
• As an asynchronous counter
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
REGISTER 6-1: TIMER1 CONTROL REGISTER (T1CON: 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillato r is shut off(1)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external cl ock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI /P1C (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: The oscil lator inverter a nd feedback r esistor are turn ed off t o eliminate p ower drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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6.1. 1 TIMER1 COUNTER OPERATION
In this m ode, T imer1 is being incre mented vi a an exter-
nal source. Increments occur on a rising edge. After
Timer1 is enabled in Counter mode, the module must
first have a falling edge before the counter begins to
increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Initially high)
T1CKI
(Initially low)
Note: Arrows indicate counter increments.
First falling edge
of the T1ON enabled
First falling edge
of the T1ON enabled
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS<1:0> SLEE P input
T1OSCEN
Enable
Oscillator(1)
Fosc/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
Note 1: W hen the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow TMR1
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6.2 Timer1 Oscillator
A cryst al oscillator circuit is built in be tween pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The o scilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 6-1 shows the capacitor
selection for the Timer1 os cillato r.
The Timer1 oscillator is identical to the LP oscillator.
The user m us t prov id e a so ftware tim e de lay to en su re
proper oscillator start-up.
TABLE 6-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched i n interrupt f lag bit TMR 1IF (PIR1<0>).
This in terrupt ca n be e nabled/di sabled by settin g/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
6.4 Resetting Timer1 using a CCP
Trigger Output
If the ECCP mo dul e is co nfig ure d in C om pare mode to
generate a “special event trigger" (CCP1M<3:0> =
1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the even t that a write to T imer1 coi ncides with a spe-
cial event trigger from ECCP, the write will take prece-
dence.
In this mode of o peration, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
These values are for design guidance only.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
char acteristi cs, the use r should co nsult t he
resonator/crystal manufacturer for appro-
priate values of external components.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
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NOTES:
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7.0 TIMER2 MODULE
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 matc h of PR2
• SSP module optional use of TMR2 output to gen-
erate clock sh ift
Timer2 has a control register, shown in Register 7-1.
Timer2 ca n be shut off by cl eari ng control bit T MR2O N
(T2CON<2>) to minimize power consumption.
Figure 7-1 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the PIC Mid-Range MCU Family Reference Manual,
(DS33023).
7.1 Timer2 Operation
Timer2 can be used as the PWM time-base for PWM
mode of the ECCP module.
The TMR2 register is readable and writable, and is
cleared on any device RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS<1:0>
(T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 7-1: TIMER2 CONTROL REGISTER (T2CON1: 12h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as '0 '
bit 6-3 TOUTPS<3:0>: Timer2 Ou tpu t Post s cale Sele ct bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 P ostscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Pres cal e Selec t bit s
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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7.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
7.3 Output of TMR2
The output of TMR2 (before the post scaler) is fed to the
Synchro nou s Seri al Port m odu le w hi ch optio nally uses
it to generate shift clock.
FIGURE 7-1: Timer2 Block Diagram
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2
Sets flag
TMR2 reg
output (1)
RESET
Postscaler
Prescaler
PR2 reg
2
Fosc/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note: TMR2 register output can be software
selected by the SSP Module as a baud
clock.
to
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
11h TMR2 Timer2 register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Time r2 P erio d Re gis te r 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
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8.0 ENHANCED CAPTURE/
COMPARE/PW M (ECCP)
MODULES
The ECCP (Enhanced Capture/Compare/PWM)
module cont ai ns a 16 -bit regi ster w hich c an opera te as
a 16-bit capture register, as a 16-bit compare register
or as a PWM master/slave Duty Cycle register.
Table 8-1 shows the ti mer resources of the ECCP mod-
ule modes.
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON and P1DEL reg-
isters control the operation of ECCP. All are readable
and writable.
REGISTER 8-1: CCP1 CONTROL REGISTER (CCP1CON: 17h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
bit 7-6 PWM1M<1:0>: PWM Output Configuration
CCP1M<3:2> = 00, 01, 10
xx = P1A assigned as Capture input, Compare output. P1B, P1C, P1D assigned as Port pins.
CCP1M<3:2> = 11
00 = Single output. P1A modulated. P1B, P1C, P1D assigned as Port pins.
01 = Full-bridge output forward. P1D modulated. P1A active. P1B, P1C inactive.
10 = Half-bridge output. P1A, P1B modulated with deadband control. P1C, P1D assigned as
Port pins.
11 = Full-bridge output reverse. P1B modulated. P1C active. P1A, P1D inactive.
bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: Th ese bit s are the tw o LSbs of the PWM duty cycl e. The ei ght MSbs are found in
CCPRnL.
bit 3-0 CCP1M<3:0>: ECCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, every fallin g edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mo de, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Comp are mode, trigger special event (CCP1IF bit is set; ECCP resets TMR1, and st arts
an A/D conversion, if the A/D module is enabled.)
1100 = PWM mode. P1A, P1C active high. P1B, P1D active high.
1101 = PWM mode. P1A, P1C active high. P1B, P1D active low.
1110 = PWM mode. P1A, P1C active low. P1B, P1D active high.
1111 = PWM mode. P1A, P1C active low. P1B, P1D active low.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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TABLE 8-1: ECCP MODE - TIMER
RESOURCE
8.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit valu e of the TMR1 regi ster when an ev ent occurs on
pin CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cle ared in so ftware. If a nother captu re occurs b efore
the value in register CCPR1 is read, the old captured
value wi ll be los t.
8.1.1 CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the TRISB<3> bit.
8.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode. In Asynchronous Counter mode,
the capture operation may not work.
8.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
8.1.4 ECCP PRESCALER
There are three prescaler settings, specified by bits
CCP1M<3:0>. Whenever the ECCP module is turned
off or the ECCP module is not in Capture mode, the
prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cl e are d , t h ere f o re t h e f i rs t ca pt u re m ay be f r om
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1: Changing Between
Capture Prescalers
FIGURE 8-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
8.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
• driven High
•driven Low
• toggle output (High to Low or Low to High)
• remains Unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0>. At the same time, interrupt flag bit
CCP1IF is set.
Changing the ECCP mode select bits to the clear out-
put on Match mode (CCP1M<3.0> = “1000”) presets
the CCP1 output latch to the logic 1 level. Changing the
ECCP mode select bits to the clear output on Match
mode (CCP1M<3:0> = “1001”) presets the CCP1 out-
put latch to the logic 0 level.
8.2.1 CCP1 PIN CONFIGURATION
The user m us t co nfig ure t he CC P1 p in a s an outp ut b y
clearing the appropriate TRISB bit.
8.2.2 TIMER1 MODE SELECTIO N
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the ECCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
ECCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
Note: If the R B3/C CP1/P1 A pin is conf igur ed as
an output, a write to the port can cause a
capture co ndition.
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the port data
latch.
CLRF CCP1CON ; Turn ECCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and ECCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RB3/CCP1/
Prescaler
³ 1, 4, 16
and
edge det ect
P1A Pin
1999-2013 Microchip Technology Inc. DS41120C-page 55
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8.2.3 SOFTWARE INTERRUPT MODE
When gen erat e soft ware i nterrup t is c hosen, the CCP 1
pin is not affected . Only an ECCP interrupt is generate d
(if enabled).
8.2.4 SPECIAL EVENT TRIGGER
In this mod e, an internal ha rdware trigg er is generated,
which may be used to initiate an action.
The special event trigger output of ECCP resets the
TMR1 register pair. This allows the CCPR1 re gister to
effe ctively be a 16-bit progra mmable pe riod registe r for
Timer1.
The special event trigger output of ECCP module will
also start an A/D conversion if the A/D module is
enabled.
FIGURE 8-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Note: The special event trigger will not set the
interrupt flag bit TMR1IF (PIR1<0>).
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Speci a l Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RB3/CCP1/
TRISB<3> CCP1CON<3:0>
Mode Select
Output Enable
P1A Pin
Special event tri gger will:
RESET Timer1, but not set interrupt flag bit
TMR1IF (PIR1<0>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Valu e on
all other
RESETS
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISB PORTB Data Direction Register 1111 1111 1111 1111
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
T1CON —— T1CKPS
1T1CKP
S0 T1OSCEN T1SYNC TMR1CS TMR1O
N--00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer 1.
PIC16C717/770/771
DS41120C-page 56 1999-2013 Microchip Technology Inc.
8.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the ECCP
module produces up to a 10-bit resolu tion PWM outpu t.
Figure 8-3 shows the simplified PWM block diagram.
FIGURE 8-3: SIMPLIFIED PWM BLOCK DIAGRAM
8.3.1 PWM PE RIOD
The PWM p eriod i s spec ified by writi ng to th e PR2 re g-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM PERIOD = [(PR2) + 1] • 4 • TOSC •
(TMR2 PRESCALE VALUE)
PWM frequency is defined as 1 / [PWM period].
When TM R2 is equa l to PR2, t he followi ng three ev ents
occur on the next increment cycle:
• TMR2 is cl eare d
• The CCP1 pin is set (exception: if PWM duty
cycl e = 0% , the CCP1 pin will not be set)
• The PWM dut y cycl e is latched fro m CCPR1L i nto
CCPR1H
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1 )
RQ
S
Duty cycle registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
Note: 8-bit timer TMR2 is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.
TRISB<3>
RB3/CCP1/P1A
TRISB<5>
RB5/SDO/P1B
TRISB<6>
RB6/T1OSO/T1CKI/
TRISB<7>
RB7/T1OSI/P1D
P1C
OUTPUT
CONTROLLER
PWM1M1<1:0>
2CCP1M<3:0>
4
P1DEL
CCP1/P1A
P1B
P1C
P1D
Note: The Timer2 posts caler (s ee Se cti on 7.0) i s
not used in the determination of the PWM
frequenc y . T he posts caler could b e used to
have a servo update rate at a different fre-
quency than the PWM output.
1999-2013 Microchip Technology Inc. DS41120C-page 57
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8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CC P1CON <5:4> c an be wri tten to at an y
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycl e. This do uble
buffering is essential for gli tchless P WM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximu m PWM resolu tion (bi ts) f or a given PWM fre-
quency:
8.3.3 PWM OUTPUT CONFIGURATIONS
The PWM1M1 bits in the CCP1CON register allows
one of the following configurations:
• Single output
• Half-Bridge output
• Full-Bridge output, Forward mode
• Full-Bridge output, Revers e mode
In the Single Output mode, the RB3/CCP1/P1A pin is
used as the PWM output. Since the CCP1 output is
multiplexed with the PORTB<3> data latch, the
TRISB<3> bit must be cleared to make the CCP1 pin
an output.
FIGURE 8-4: SINGLE PWM OUTPUT
FIGURE 8-5: EXAMPLE OF SINGLE
OUTPUT APPLICATION
In the Half-Bridge Output mode, two pins are used as
outputs. The RB3/CCP1/P1A pin has the PWM output
signal, while the RB5/SDO/P1B pin has the comple-
mentary PWM output signal. This mode can be used
for half-bri dge appl icati ons, as sho wn on Figure 8-7 , or
for full-bridge applications, where four power switches
are being modulated with two PWM signal.
Since the P1A and P1B outputs are multiplexed with
the PORTB<3> and PORTB<5> data latches, the
TRISB<3> a nd TRISB<5> bit s must be clea red t o co n-
figure P1A and P1B as outputs.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through cur-
rent in bridge power devices. See Section 8.3.5 for
more details of the deadband delay operations.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
FOSC
FPWM
------ ----- ----
log
2log
------ ---- ----------- ---- ---- bits=
Period
Duty Cycle
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
CCP1(2)
2: Output signal is shown as asserted high.
C
PIC16C717/770/771
CCP1 RVout
Using PWM as
a D/A Converter
PIC16C717/770/771
CCP1
Using PWM to
Drive a Power
V+
L
O
A
D
Load
PIC16C717/770/771
DS41120C-page 58 1999-2013 Microchip Technology Inc.
8.3.4 OUTPUT POLARITY
CONFIGURATION
The CCP1M<1:0> bits in the CCP1CON register allow
user to choose the logic conventions (asserted high/
low) for each of the outputs. See Register 8-1 for fur-
ther details.
The PWM outp ut polarities mu st be selected be fore the
PWM outputs are enabled. Charging the polarity con-
figuration while the PWM outputs are active is not rec-
ommended, since it may result in unpredictable
operation.
FIGURE 8-6: HALF-BRIDGE PWM OUTPUT
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Period
Duty Cycle
td
td
(1)
P1A(2)
P1B(2)
td = Deadband Delay
Period
(1) (1)
2: Output signals are shown as asserted high.
1999-2013 Microchip Technology Inc. DS41120C-page 59
PIC16C717/770/771
FIGURE 8-7: EXAMP LE OF HALF-BRI DGE OUTPUT MODE APPLICATIONS
PIC16C717/770/771
P1A
P1B
FET
DRIVER
FET
DRIVER
V+
V-
LOAD
+ -
+
V
-
+
V
-
PIC16C717/770/771
P1A
P1B
FET
DRIVER
FET
DRIVER
V+
V-
LOAD
+ -
FET
DRIVER
FET
DRIVER
PIC16C717/770/771
DS41120C-page 60 1999-2013 Microchip Technology Inc.
In Full-Bridge Output mode, four pins are used as out-
puts; however, only two outputs are active at a time. In
the Forw ard mode, R B3/C CP1/P1A pin is con tinuou sly
active, and RB7/T1OSI/P1D pin is modulated. In the
Reve rse mode , RB6/ T1O SO/ T1CKI /P 1C pi n is c ont in-
uously active, and RB5/SDO/P1B pin is modulated.
P1A, P1B, P1C and P1D outputs are multiplexed with
PORTB< 3> and PORTB<5:7> data latc hes. TRISB<3>
and TRISB<5:7> bits must be cleared to make the P1A,
P1B, P1C, and P1D pins output.
FIGURE 8-8: FULL-BRIDGE PWM OUTPUT
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
FORWARD MODE
(1)
Period
Duty Cycle
P1A(2)
P1C(2)
P1D(2)
P1B(2)
REVERSE MODE
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(1)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.
1999-2013 Microchip Technology Inc. DS41120C-page 61
PIC16C717/770/771
FIGURE 8-9: EXAMP LE OF FULL-BRIDGE APPLICATION
PIC16C717/770/771
P1D
P1A
FET
DRIVER
FET
DRIVER
V+
V-
LOAD
+ -
FET
DRIVER
FET
DRIVER
P1C
P1B
PIC16C717/770/771
DS41120C-page 62 1999-2013 Microchip Technology Inc.
8.3.5 PROGRAMMABLE DEADBAND
DELAY
In half-brid ge or ful l-b ridge applicat ion s, dri ven by ha lf-
bridge outputs (see Figure 8-7), the power switches
normally require longer time to turn off than to turn on.
If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches will be on for a short
period of time, until one switch completely turns off.
During this time, a very high current, called shoot-
through cu rrent, will flow throu gh bo th powe r switc hes,
shorting the bridge supply. To avoid this potentially
destructive shoot-through current from flowing during
switching, turning on the power switch is normally
delayed to all ow the o ther swi tch to compl etely turn of f.
In the Half-Bridge Output mode, a digitally program-
mable deadband delay is available to avoid shoot-
through current from destroying the bridge power
switches . The delay oc curs at the sig nal transition from
the non-active state to the active state. See Figure 8-6
for illustration. The P1DEL register sets the amount of
delay.
REGISTER 8-2: PWM DELAY REGISTER (P1DEL: 97H)
8.3.6 DIRECTION CHANGE IN FULL-
BRIDGE OUTPUT MODE
In the Full -Bridge Outp ut mode, the PWM 1M1 bit in the
CCP1CON regi ste r allo w s us er to con trol the Forwa r d/
Reverse direction. When the application firmware
changes this direction control bit, the ECCP module will
assum e the new d irec ti on on the next PWM cycle. The
current PWM cycle still continues, however, the non-
modulated outputs, P1A and P1C signals, will transition
to the new direction TOSC, 4TOS C or 16TO SC (for
Timer2 prescale T2CKRS<1:0> = 00, 01 and 1x
resp ec ti v el y) ea r lie r, befor e the en d of the pe r i od . Du r -
ing this transition cycle, the modulated outputs, P1B
and P1D, will go to the inactive state. See Figure 8-10
for illustration.
FIGURE 8-10: PWM DIRECTION CHANGE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1DEL7 P1DEL6 P1DEL5 P1DEL4 P1DEL3 P1DEL2 P1DEL1 P1DEL0
bit 7 bit 0
bit 7-0 P1DEL<7:0>: PWM Delay Count for Half-Bridge Output Mode: Number of FOSC/4 (Tosc4)
cycles between the P1A transition and the P1B transition.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
DC PERIOD
SIGNAL
P1A (Active High)
Note 1: The Direction bit in the ECCP Control Register (CCP1CON<PWM1M1>) is written anytime during the PWM cycle.
2: The P1A and P1C signals switch TOSC, 4*Tosc or 16*TOSC, depending on the Timer2 prescaler value, earlier when
changing direction. The modulated P1B and P1D signals are inactive at this time.
(1)
PERIOD
(2)
P1D (Active High)
P1C (Active High)
P1B (Active High)
1999-2013 Microchip Technology Inc. DS41120C-page 63
PIC16C717/770/771
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any deadband delay. In gen-
eral, since only one output is modulated at a time,
deadban d delay is not requ ired. However , there is a sit-
uation w here a deadb and delay mig ht be required. This
situation occurs when all of the following conditions are
true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off ti me of the power swi tch, in cluding
the power device and driver circuit, is greater
than turn on time.
Figure 8-11 shows an example, where the PWM direc-
tion changes from forward to reverse at a near 100%
duty cy cle. At time t1, the outpu t P1A and P1D bec ome
inactive, while output P1C becomes active. In this
exampl e, si nce th e turn of f ti me of the p ower devices is
longer than the turn on time, a shoot-through current
flows through the power devices, QB and QD, for the
duration of t = toff-ton. The same phenomenon will occur
to power devices, QC and QB, for PWM direction
change from reverse to forward.
If changing PWM direction at high duty cycle is required
for the user ’s application, one of the following require-
ments mu st be met:
1. Avoid c hangi ng PWM output dire ction at or ne ar
100% duty cycle.
2. Use switch drivers that com pensa te for the slow
turn off of the power devices. The total turn off
time (toff) of the power device and the driver
must be less than the turn on time (ton).
FIGURE 8-11: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
FORWARD PERIOD REVERSE PERIOD
(PWM)
P1A 1
0
(PWM) ton
toff
t = toff - ton
1
0
1
0
1
0
1
0
1
0
1
0
P1B
P1C
P1D
Ext er nal Switch D
Potential
Shoot Through
Current
Note 1: All signals are shown as active high.
2: ton is the turn on delay of power switch and driver.
3: toff is the turn off delay of power switch and driver.
Ext er nal Switch C
t1
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DS41120C-page 64 1999-2013 Microchip Technology Inc.
8.3. 7 SYSTEM IMPLEMENTATION
When the ECCP mo dule is used in the PWM mo de, the
applic ation hardware m ust use the p roper external pull-
up and/or pull-down resistors on the PWM output pins.
When the mic roc on trol ler pow e rs up , all of the I/O pin s
are in the high-impedance state. The external pull-up
and pull-down resistors must keep the power switch
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates
the PWM output(s).
8.3.8 START-UP CONSIDERATIONS
Prior to en ablin g the PW M output s, th e P1A, P1B, P1C
and P1D latches may not be in the proper states.
Enabling the TRISB bits for output at the same time
with t he C C P m odu le may cause damage to the power
switch devices. The CCP1 module must be enabled in
the proper Output mode with the TRISB bits enabled as
inputs. Once the CCP1 completes a full PWM cycle,
the P1A, P1B, P1C and P1D output latches are prop-
erly initialized. At this time, the TRISB bits can be
enabled for outputs to start driving the power switch
devices. The completion of a full PWM cycle is indi-
cated by the TMR2IF bit going from a '0' to a '1'.
8.3.9 SET UP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Configure the PWM module:
a) Disable the CCP1/P1A, P1B, P1C and/or
P1D outputs by setting the respective
TRISB bits.
b) Set the PWM period by loading the PR2
register.
c) Set the PWM duty cycle by loading the
CCPR1L register and CCP1CON<5:4>
bits.
d) Config ure the EC CP mod ule for t he desired
PWM operation by loading the CCP1CON
register. With the CCP1M<3:0> bits select
the active high/low levels for each PWM
output. With the PWM1M<1:0> bits select
one of the available Output modes: Single,
Half-Bridge, Full-Bridge, Forward or Full-
Bridge Reverse.
e) For Half-Br idge Ou tput mode, s et the dead-
band delay by loading the P1DEL register.
2. Configure and start TMR2:
a) Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
b) Set the TMR2 prescal e value by loa ding the
T2CKPS<1:0> bits in the T2CON register.
c) Enable Timer2 by setting the TMR2ON bit
in the T2CON register.
3. Enable PWM outputs after a new cycle has
started:
a) Wait until TMR2 overflows (TMR2IF bit
become s a ’1’). T he new PWM cyc le begins
here.
b) Enable the CCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISB bits.
TABLE 8-3: REGISTERS ASSOCIATED WITH PWM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
1 0 Bh, 1 8 Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 register 0000 0000 0000 0000
92h PR2 Timer2 pe riod re gister 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
97h P1DEL PWM1 Delay value 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by ECCP module in PWM mode.
1999-2013 Microchip Technology Inc. Advance I n formation DS41120C-page 65
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9.0 MASTER SYNCHRONOUS
SERIAL PORT (MS SP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
periphera l or m icroc ontroll er dev ices. Th ese p eriphera l
devices may be serial EEPROMs, shift registers, dis-
play dri vers, etc. The M SSP module can op erate in one
of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I2C™)
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DS41120C-page 66 Advance Information 1999-2013 Microchip Technology Inc.
REGISTER 9-1: SYNC SERIAL PORT STATUS REGISTER (SSPSTAT: 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bi t 0
bit 7 SMP: Sa m ple bit
SPI Master Mode
1 = Input data sampled at end of da ta output time
0 = Input data sampled at mid dl e of data out put tim e
SPI S l ave Mode
SMP m ust be c le ar ed when SPI is us ed i n Slave mode
In I2C Master or Slave mode:
1= Slew rate control dis abled for Standar d Speed mode (10 0 kH z and 1 MHz)
0= Slew rate control enabled for High Speed mode (40 0 kH z )
bit 6 CKE: SPI Clock Edg e Select (Figure 9 -3 , Fig ure 9-5, and Figure 9-6)
CKP = 0
1 = Data transmi tte d on rising edge of S CK
0 = Data transmit ted on falling ed ge of SCK
CKP = 1
1 = Data transmit ted on falling ed ge of SCK
0 = Data transmi tte d on rising edge of S CK
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicate s th at th e la st byt e received or transmitted was data
0 = Indicate s th at th e la st byt e received or transmitted was addr ess
bit 4 P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicate s th at a STOP bi t has been detecte d l ast (thi s bit is '0' on RE SET)
0 = STOP bit was not detected last
bit 3 S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates th at a START bit has bee n detected las t (this bit is '0' on RE SET)
0 = START bit w as not detected last
bit 2 R/W: Read/Write bit informatio n (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit, or NACK bit.
In I2 C Slave mod e:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Tran sm i t is no t in pr ogress.
ORing this bit with SEN, RSEN, PEN, RCEN, or AKEN will indicate if the MSSP is in IDLE mode
bit 1 UA: Update Address (10-bit I2C mode only)
1 = Indicate s th at th e user need s to update the ad dress in the SSPADD reg is ter
0 = Address do es not nee d to be update d
bit 0 BF: Buffer Full St atus bit
Receive (SPI and I2 C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode onl y)
1 = Data Transmi t in progress (does not include t he ACK and STOP bits), S SPBUF is full
0 = Data Tra n s mit c o mp lete (d oes not in clude th e ACK and STOP bits), S SPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemen te d bi t , read as ‘0’
- n = Value at P O R ’1’ = Bit is set ’0’ = Bit is cle ar ed x = Bit is unknown
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REGISTER 9-2: SYNC SERIAL PORT CONTROL REGI STER (SSPCON: 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
Master Mode:
1 = A write to th e SSPBUF r egi ster wa s atte mp ted whi le th e I2C cond itions were not vali d for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new b yte is rec eived while th e SSPBUF regist er is stil l hold ing the p reviou s dat a. In c ase
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave
mode, the user m ust read th e SSPBUF, even if o nly trans mitting dat a, to avoid se tting ov er-
flow. In Mas ter m ode, th e over flow bit i s not se t sinc e each new r ecepti on (a nd tran smis-
sion) is initiated by writing to the SSPBUF register. (Must be cleared in software).
0 = No overflow
In I2 C mode
1 = A byte is receive d while the SSPBUF regis ter is still hol ding the previou s byte. SSPOV is a
"don’t care" in Transmit mode. (Must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, the I/O pins must be properly configured as input or output.
In SPI mode
1 = Enables s erial port and configure s SCK, SDO, SDI, an d SS a s the s ourc e of th e s eri al po rt
pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial
port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode
1 = IDLE state for clock is a high level
0 = IDLE state for clock is a low level
In I2 C Slave mode SCK release control
1 = Enable clock
0 = Holds clock low (clock st retch) (use d to ensure data setup time)
In I2 C Master mode
Unused in this mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-2: SYNC SERIAL PORT CONTROL REGISTER (SSPCON: 14h) (CONTINUED)
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI S lave m od e, c lock = SC K pi n. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC / ( 4 (SSPADD+1) )
1001 = Reserved
1010 = Reserved
1011 = Firmware controlled Master mode (slave idle)
1100 = Reserved
1101 = Reserved
1110 = 7-bit Slave mode with START and STOP condition interrupts
1111 = 10-bit Slave mode with START and STOP condition interrupts
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-3: SYNC SERIAL PORT CONTROL REGISTER2 (SSPCON2: 91h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (In I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1 = Not Acknowledge (NACK)
0 = Acknowledge (ACK)
bit 4 ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only).
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence IDLE
bit 3 RCEN: Receive Enable bit (In I2C Master mode only).
1 = Enables Receive mode for I2C
0 = Receive IDLE
bit 2 PEN: STOP Condition Enable bit (In I2C Master mode only).
SCK Release Control
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition IDLE
bit 1 RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by
hardware.
0 = Repe ated START co ndition IDLE
bit 0 SEN: START Condition Enabled bit (In I2C Master mode only)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition IDLE
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
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DS41120C-page 70 Advance Information 1999-2013 Microchip Technology Inc.
9.1 SPI Mode
The SPI mode allows eight bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish com-
munication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Ser ial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Sla ve Select (SS)
9.1.1 OPERATION
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase
(middle or end of data output t ime)
• Clock edge
(output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
Figure 9-1 shows the block diagra m of the MSSP mod-
ule when in SPI mode.
FIGURE 9-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The MSSP cons ists of a trans mit/recei ve Sh ift Regist er
(SSPSR) and a Buffer Register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR, until the received data is ready. Once the eig ht
bits of data have been received, that byte is moved to
the SSPBUF regi ster. Then the buf fer full dete ct bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF
(PIR1<3>), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSP-
BUF registe r com ple ted su cc es sfu lly.
Read Write
Internal
Data Bus
SSPSR reg
SSPBUF reg
SSPM<3:0>
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
Tosc
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX i n SSPSR
Data direction bit
2
SMP:CKE
SDI
SDO
SS
SCK
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When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of dat a to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when the SSP-
BUF has bee n loaded with the recei ved data (trans mis-
sion is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be rea d and/or written. If the
inter rupt metho d is not going to be used, the n softw are
polling can be d one to ensure that a write collision does
not o ccu r. Example 9-1 shows the loading of the SSP-
BUF (SSPSR) for data transmission.
EXAMPLE 9-1: Loading the SSPBUF
(SSPSR) Register
The SSPSR is not directly readable or writable, and
can onl y be acce ss ed b y addressing the SSPBUF re g-
ister. Additionally, the MSSP STATUS register
(SSPSTAT) indicates the various status conditions.
9.1.2 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. Fo r the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is a utom at ic all y c ontrolled by t he SPI module
• SDO must have TRISB<5> cleared
• SCK (Master mode) must have TRISB<2>
cleared
• SCK (Slave mode) must have TRISB<2> set
•SS
must have TRISB<1> set, and ANSEL<5>
cleared
Any serial po rt function that is not desired may be ov er-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
9.1.3 TY PIC AL CONNEC TION
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (SSPCON<4>), then
both controllers would send and receive data at the
same tim e. Whet her the dat a is meaningful (or dum m y
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data—Slave sends dumm y data
• Master sends data—Slave sends data
• Master sends dummy data—Slave sends data
FIGURE 9-2: SPI MAST E R/S LAVE CONNECTION
BSF STATUS, RP0 ;Specify Bank 1
LOOP BTFSS SSPSTAT, BF ;Has data been
;received
;(xmit complete)?
GOTO LOOP ;No
BCF STATUS, RP0 ;Specify Bank 0
MOVF SSPBUF, W ;Save SSPBUF...
MOVWF RXDATA ;...in user RAM
MOVF TXDATA, W ;Get next TXDATA
MOVWF SSPBUF ;New data to xmit
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM<3:0> = 00xx b
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCE SSO R 2
SCK
SPI Slave SSPM<3:0> = 010xb
Serial Clock
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9.1.4 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-2) is to broad-
cast dat a by the so ftware protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will conti nue to shif t in the signa l present on th e
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
The clock polarity is selected by appropr iately program-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 9-3, Figure 9-5 and Figure 9-6, where the MSb
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the follow-
ing:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allo ws a maximu m bit clock freq uency (at 20 MHz)
of 8.25 MHz.
Figure 9-3 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
FIGURE 9-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
modes
Input
Sample
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(CKE = 0)
(CKE = 1)
Next Q4 cycle
after Q 2
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9.1.5 SLAVE MODE
In Slave m ode , the data is trans mitted and receiv ed a s
the external clock pulses appear on SCK. When the
last bi t is latc hed th e inte rrupt flag bit SSPIF (PIR1<3 >)
is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
9.1.6 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON<3:0> = 0100). The pin must not
be driven low for the SS pin to function as an input.
TRISB<1> must be set. When the SS pin is low,
transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output.
External pull-up/ pull-down resistors may be desir-
able, depending on the application.
When the SPI module RESETS, the bit counter is
forced to 0. This can be done by either forcing the SS
pin to a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function)
since it cann ot cre ate a bus con flict.
FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI module is in Slave mode
with SS pin control enabled, (SSP-
CON<3:0> = 0100) the SPI module will
RESET if the SS pin is set to VDD.
2: If the SPI is used in Slave Mode with
CKE = '1', then SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7
SDO bit7 bit6 bit7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPS R to
SSPBUF
SS
Flag
bit0
bit7 bit0
Next Q4 cycle
after Q2
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FIGURE 9-5: SPI SLAVE MODE WAVEFORM (CKE = 0)
FIGURE 9-6: SPI SLAVE MODE WAVEFORM (CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
optional
Next Q4 cycle
after Q 2
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
not optional
Next Q4 cycle
after Q2
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9.1.7 SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operat es asy nchron ously to the devi ce. Th is al lows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the SSPIF
interrupt flag bit will be set and if enabled will wake the
device from SLEEP.
9.1.8 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF —— SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE ——SSPIECCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/T ransmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
9Dh ANSEL --11 1111 --11 1111
86h TRISB 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Sha ded cells are not used by the MSSP in SPI mode.
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9.2 MSSP I 2C Operation
The MSSP module in I2C mode fully implements all
master an d sla ve func tion s (in cl udi ng general call su p-
port) and pro vid es interrup ts on STAR T and ST O P bits
in hardware to determine when the bus is free (multi-
master function). The MSSP module implements the
Standard mode specifications, as well as 7-bit and 10-
bit addr essing.
Two pins are used to transfer data. They are the SCL
pin (clock) and the SDA pin (data). The MSSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>). The SCL and SDA pins are
"glitch" filtered when operating as inputs. This filter
functions in both the 100 kHz and 400 kHz modes.
When these pins operate as outputs in the 100 kHz
mode, ther e is a slew rate control of the pin that is inde-
pendent of device frequency.
Before selecting any I2C mode, the SCL and SDA pins
must be programmed as inputs by setting the appropri-
ate TRIS bits. This allows the MSSP module to configure
and drive the I/O pins as required by the I2C protocol.
The MSSP module has six registers for I2C operation.
They are list ed below.
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP STATUS Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not di rec tl y ac c essi ble
• SSP Address Register (SSPADD)
The SSPCON register allows for control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
configure the MSSP as any one of the following I2C
modes:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Master mode
SCL Freq = FOSC / [4 (SSPADD + 1)]
•I2C Slav e mode w ith START and STOP i nterrupt s
(7-bit address)
•I2C Slav e mode w ith START and STOP i nterrupt s
(10-bit address)
• Firmware Controlled Master mode
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit. It specifies whether the
received byte was data or address, if the next byte is
the completion of 10-bit address, and if this will be a
read or write data transfer.
SSPBUF is the register to which the transfer data is
written, and from which the transfer data is read. The
SSPSR register shifts the data in or out of the device.
In receive op eration s, the SSPBUF and SSPSR create
a doubled, buffered receiver. This allows reception of
the next byte to begin before reading the last byte of
receive d data. Whe n the complete byte is receiv ed, it is
transferred from the SSPSR register to the SSPBUF
register and flag bit SSPIF is set. If another complete
byte is received before the SSPBUF register is read a
receiver ov erflow occurs , in which cas e, the SSPOV bit
(SSPCON<6>) is set and the byte in the SSPSR is lost.
FIGURE 9-7: I2C SLAVE MODE BLOCK
DIAGRAM
9.2.1 UPWARD COMPATIBILITY WITH
SSP MODULE
The MSSP module in clude s three SSP modes of op er-
ation to maintain upward compatibility with the SSP
module. These modes are:
• Firmware controlled Master mode (slave idle)
• 7-bit Slave mode with START and STOP
conditi on inte rrupts.
• 10-bit Slave mode with START and STOP
conditi on inte rrupts.
The firmware controlled Master mode enables the
START and STOP condition interrupts but all other I2C
function s are gen erated through firmware inclu din g:
• Generating the START and STOP conditions
• Generating the SCL clock
• Supplying the SDA bits in the proper time and
phase relationship to the SCL signal.
In firmware controlled Ma st er m ode , the SCL an d SD A
lines a re manipu lated by c learing an d setting the corre-
spondin g TR IS bit s. The output level is al ways l ow i rre-
spective of the value(s) in the PORT register. A ‘1’ is
output by setting the TRIS bit and a ‘0’ is output by
clearing the TRIS bit
The 7-bit and 10-bit Slave modes with START and
STOP condition interrupts operate identically to the
MSSP Slave modes except that START and STOP
conditions generate SSPIF interrupts.
Read Write
SSPSR reg
Match detect
SSPADD reg
START and
STOP bit detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, RESET
S, P bits
(SSPSTAT reg)
RB2/SCK/
Shift
Clock
MSb LSb
SCL
RB4/SDI/
SDA
1999-2013 Microchip Technology Inc. Advance I n formation DS41120C-page 77
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For more information about these SSP mod es see Sec-
tion 15 of the PIC Mid-Range MCU Family Reference
Manual (DS33023).
9.2.2 SLAVE MODE
When an address is matched or the data transfer after
an add res s mat ch i s rece ived , th e ha rdw are au tom ati -
cally will generate the Acknowledge (ACK) pulse.
Then, it loads the SSPBUF register with the received
value currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module to generate a NACK pulse in lieu of
the ACK pulse:
a) The buffer full bit BF (SSPSTAT<0>) is set
before the transfer is received.
b) The overflow bit SSPOV (SSPCON<6>) is set
before the transfer is received.
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF. However , both t he SSPIF and
SSPOV bits are set. Table 9-2 shows what happens
when a data transfer byte is received, given the status
of bit s BF and SSPOV. The sha ded cells show the co n-
dition where user software did not properly clear the
overflow condition. The BF flag bit is cleared by reading
the SSPBUF register. The SSPOV flag bit is cleared
through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of th e I2C specification as well as the requirements of
the MSSP module are shown in timing parameters
#100 and #101 of the Electrical Specifications.
9.2.2.1 7-BIT ADDRESSING
Once the MSSP module has been enabled
(SSPEN=1), the slave module waits for a START con-
dition to occur. Following the START condition, eight
bits are shifted into the SSPSR register. All incoming
bits are sampled on the rising edge of the clock (SCL)
line. The received address (register SSPSR<7:1>) is
compared to the stored address (register
SSPADD<7:1>). SSPSR<0> is the R/W bit and is not
consid ere d in the co mparison. Comparison is mad e o n
the falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
a) The SSPSR register value is transferred to the
SSPBUF register on the falling edge of the
eighth SCL pulse.
b) The bu ffer ful l bit; BF is set o n the falling e dge of
the eighth SCL pulse.
c) An ACK pulse is generated during the ninth
clock cycle.
d) SSP interrupt flag bit; SSPIF (PIR1<3>) is set
(interrupt is genera ted if e nabled ) - on the fallin g
edge of the ninth SCL pulse.
9.2.2.2 10-BIT ADDRESSING
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match are more complex.
Two address bytes need to be received by the slave.
The five Most Significant bits (MSbs) of the first
address byte specify that this is a 10-bit address. The
LSb of the first received address byte is the R/W bit,
which must be zero, specifying a write so the slave
device will receive the second address byte. For a 10-
bit address, the first byte equals ‘11110 A9 A8 0’,
where A9 and A8 are the two MSbs of the address. The
sequence of events for a 10-bit address is as follows,
with steps 7 through 9 applicable only to the slave-
transmitter:
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT <1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the f irst (high)
byte of Address. This will clear bit UA and
release the SCL line.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
8. Receive fi rst (hi gh) by te of Address w ith R/W bit
set to 1 (bits SSPIF and BF are set). This also
puts the MSSP module in the Slave-transmit
mode.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Note: Following the Repeated START condition
(step 7) in 10-bit mode, the user only
needs to match th e first 7-bi t address. Th e
user does not update the SSPADD for the
second half of the address.
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9.2.2.3 SLAVE RECEPTION
When the R/W bit of the address byte is clear
(SSPSR<0> = 0) and an a ddre ss mat ch o ccurs , the R/
W bit of the SSPSTAT register is cleare d. The re ceived
address is loaded into the SSPBUF register on th e fall-
ing edge of the eighth SCL pulse.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) or
bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. F lag bit SSPIF (PIR1<3>) must be cle ared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS
FIGURE 9-8: I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSP-
BUF is update d.
Status Bits as Data
Transfer is Received
SSPSR SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
0 0 Yes Yes Yes
1 0 No No Yes
1 1 No No Yes
0 1 Yes No Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
P
9
8
76
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 123456789123456789123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Ad dr ess
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
NACK
NACK is sent because of overflow
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FIGURE 9-9: I2C SLAVE MODE FOR RECEPTION (10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456 789 1 23456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in softwa re
Bus Master
terminates
transfer
D2
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
Cleared in software
Dummy read of SSPBUF
to clear BF flag Read of SSPBUF
clears BF flag
Cleared by hardware when
SSPADD is updated with high
byte of address.
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9.2.2.4 SLAVE TRANSMISSION
When the R/W bit of th e incoming addres s byte is se t
and an address match occurs, the R/W bit of the SSP-
STAT register is set. The received address is loaded
into the SSPBUF register on the falling edge of the
eighth SCL pulse. The ACK pulse will be sent on the
ninth bit , and the SCL pin i s held low . Th e slave modul e
automatically stretches the clock by holding the SCL
line low so that the master will be unable to assert
another c lock pulse u ntil the slav e is fin ished prep aring
the transmit data. The transmit data must be loaded
into the SSPBUF register, which a lso loads th e SSPSR
register. The CKP bit (SSPCON<4>) must then be set
to release the SCL pin from the forced low condition.
The eight data bits are shifted out on the falling edges
of the SCL input. This ensures that the SDA signal is
valid during the SCL high time (Figure 9-10).
The ACK or NACK signal from the master-receiver is
latched on the rising edge o f the ni nth SC L inpu t pulse.
The master-receiver terminates slave transmission by
sending a NACK. If the SDA line is high (NACK), then
the data transfer is complete. When the NACK is
latched by the slave, the slave logic is RESET which
also resets the R/W bit to '0'. The slave module then
monitors for another occurrence of the START bit. The
slave firmware knows not to load another byte into the
SSPBUF register by sensing that the buffer is empty
(BF = 0) and the R/W bit has gone low. If the SDA line
is low (ACK), the R/W bit remains high indicating that
the next transmit data must be loaded into the SSPBUF
register.
An MSSP interrupt (SSPIF flag) is generated for each
data transfer byte on the falling edge of the ninth clock
pulse. The SSPIF flag bit must be cleared in software.
The SSPSTAT register is used to determine the status
of the byte transfer.
For more information about the I2C Slav e mode, re fer
to Application Note AN734, “Using the PIC® SSP for
Slave I2C™ Communication”.
FIGURE 9-10: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK
Transmitting Data
R/W = 1
Receiving Address
123456789 123456789 P
cleared in software
SSPBUF is written in software From SSP interrupt
service ro utine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
until SSPBUF
is written
(the SSPBUF must be written-to
before the CKP bit can be set)
R/W 0
Master terminates transmission
by responding with NACK
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FIGURE 9-11: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S1234567891
2345678912345 789 P
11110A9A8 A7A6A5A4A3A2A1A0 11110 A8
R/W=1ACK
ACK
ACK
Receive First Byte of Address
Cleared in software
Master sends NACK
A9
6
(PIR1<3>)
Receive Second Byte of Addre ss
Cleared by hardware when
SSPADD is updated.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1 NACK
D2
6
Transmitting Data Byte D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Transmit is complete
CKP has to be set for clock to be released
Master releases
bus with STOP
condition
R/W=0 R/W0
Restart condition
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9.2.3 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is su ch that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is set (SSPCON2<7> is
set). Fo llowing a START bit detect, eight bits are shif ted
into the SSPSR, and the address is compared against
SSPADD. It is also compared to the general call
address, fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF flag is set.
When the i nterrupt is servic ed, t he sou r ce f or the int er-
rupt can be checked by reading the contents of the
SSPBUF to determine if the address was device spe-
cific or a gener al call address.
If the general call address is sampled with GCEN set
and the slave configured in 10-bit Address mode, the
second half of th e address is not n ecessary. The UA b it
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 9-12).
FIGURE 9-12: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7- OR 10-BIT MODE)
SDA
SCL S
SSPIF
BF
SSPOV
Cleared in softwa re
SSPBUF is read
R/W = 0ACK
General Call Address
Address is compared to General Call Address
GCEN
Receiving data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt flag
'0'
'1'
(SSPSTAT<0>)
(SSPCON<6>)
(SSPCON2<7>)
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9.2.4 SLEEP OPERATION
While in SLEEP mode, the I2C slave module can
receive addresses or data. When an address match or
complete byte transfer occurs, it wakes the processor
from SLEEP (if the SSP interrupt bit is enabled).
9.2.5 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
9.2.6 MASTER MODE
Master mode operation supports interrupt generation
on the detection of the START and STOP conditions.
The STOP (P) and START (S) bits are cleared from a
RESET or when the MSSP module is disabled. Control
of t he I2C bus may be t aken wh en the P bit is s et or the
bus is idle with both the S and P bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit
(SSPIF) to be set (SSP Interrupt, if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeat ed START
FIGURE 9-13: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Read Write
SSPSR
START bit, STO P bi t,
START bit detect,
SSPBUF
Internal
Data Bus
Set/RESET, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
STOP bit detect
Write collision detect
Clock Arbitration
S tate counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable
clock cntl
clock arbitrate/WCOL detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
RESE T ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM<3:0>,
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9.2.7 MULTI-MASTER OPERATION
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP modul e is dis abl ed . Contro l of the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expect ed output level. This c heck is perfo rmed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
Refer to Application Note AN578, "Use of the SSP
Module in the I2C™ Multi-Master Environment."
9.2.8 I2C MASTER OPERATION
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has si x opti ons .
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to th e SSPBUF register initiati ng transmis-
sion of data/address.
4. Generate a STOP condition on SDA a nd SCL.
5. Configure the I2C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
The master device g enerates all serial clock pulses an d
the START and STOP conditions. A transfer is ended
with a ST OP c ondit ion or with a Repeated START con-
dition. Since the R epeate d START condi tion i s also th e
beginni ng of the next serial tra nsfer , the I2C bus will not
be released.
9.2.9 BAUD RATE GENERATOR
The baud rate generator used for SPI mode operation
is used in the I2C Mas ter mode to set th e SCL clock f re-
quency. Standard SCL clock frequencies are 100 kHz,
400 kHz, and 1 MH z. One of the se frequ enc ies can be
achiev ed b y setti ng th e SSPADD registe r to the app ro-
priate number for the selected Fosc frequency. One
half of the SCL period is equal to
[(SSPADD+1) 2]/Fosc.
The baud rate generator reload value is contained in
the lower seven bits of the SS PADD register (Figure 9-
14). When the BRG is loaded with this value, the BRG
count s down to 0 a nd stops u ntil another relo ad occurs.
The BRG count is decremented twice per instruction
cycle (TCY) on the Q2 and Q4 clock.
In I2C Mas ter mode, the BRG is rel oaded autom aticall y
provided that the SCL line is sampled high. For exam-
ple, if Clock Arbitration is taking place, the BRG reload
will be s up pres s ed unti l t he SCL line is rel ea sed by th e
slave allowing the pin to float high (Figure 9-15).
FIGURE 9-14: BAUD RATE GENERATOR
BLOCK DIAGRAM
Note: The MSSP Module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to, and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
SSPM<3:0>
BRG Down Counter
BRG CLKOUT Fosc/2
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control Reload
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FIGURE 9-15: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
9.2.10 I2C MASTER MODE START
CONDITION TIMING
To initiate a START co nditio n, the user set s the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL p ins are sam pled h igh, ind icating th at the bu s
is available, the baud rate generator is loaded with the
contents of SSPADD<6:0> and starts its count. If SCL
and SDA are both sampled high when the baud rate
generator times out (TBRG) indicating the bus is still
available, the SDA pin is driven low . The SDA transition
from high to lo w w hil e SCL is hi gh i s th e START cond i-
tion. This causes the S bit (SSPSTAT<3>) to be set.
When the S bit is set, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
resume s its count. Whe n the ba ud rate generator time s
out (TBRG) the START condition is complete, concur-
rent with the following events:
• The SEN bit (SSPCON2<0>) is automatically
cleared by hardware,
• The baud rate genera tor is sus pended l eaving th e
SDA line held low.
• The SSPIF flag is set.
9.2.10.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a START
sequenc e is in pro gress , the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur ).
FIGURE 9-16: FIRST START BIT TIMING
SDA
SCL
SCL de-asserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place, and BRG starts its count.
03h 02h 01h 00h (hold off) 03h 02h
reload
BRG
value
SCL low (clock arbitration) SCL allowed to transition hig h
BRG decrements
(on Q2 and Q4 cycles)
Note: If at the begi nni ng of START co nd itio n, th e
SDA and SCL pins are already sampled
low, or if during the START condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs.
Thus, the Bus Collision Interrupt Flag
(BCLIF) is set, the START condition is
aborted, a nd the I2C module i s RESET into
its IDLE state.
Note: Because queueing of events is not
allowed, writing to the lower five bits of
SSPCON2 is disabled until the START
conditi on is complete.
SDA
SCL
S
TBRG
1st Bit 2nd Bit
TBRG
SDA = 1, At com pletion of START bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here. Set S bit (SSPSTAT<3>)
and sets SSPI F bit
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9.2.11 I2C MASTER MODE REPEA TED
START CONDITION T IMING
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is set high while the I2C module is
in the id le st ate. W hen the RSEN bit is set , the SC L pin
is asserted low. When the SCL pin is sampled low, the
baud rate generator is loaded with the contents of
SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (TBRG). Wh en the baud ra te gene rator tim es out,
if SDA i s samp led high, the SCL pi n will be de-asserte d
(brought high). When SCL is sampled high, the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled h igh for o ne TBRG peri od. Thi s actio n
is then followed by assertion of the SDA pin (SDA is
low) fo r one TBRG period while SCL is high. As soon as
a START condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. Following
this, the baud rate generator is reloaded with the con-
tents of SSPAD<6:0> and begins counting. When the
BRG times out a third time, the RSEN bit in the
SSPCON2 registe r is auto maticall y cleare d and SCL is
pulled low. The SSPIF flag is set, which indicates the
Restart sequence is complete.
Immediately following the SSPIF bit transition to true,
the user may write the SSPBUF with the 7-bit address
in 7-bit mode, or the default first address in 10-bit
mode. After the first eight bits are transmitted and an
ACK is receiv ed , the use r ma y th en perform one of th e
following:
• Transmit an additional eight bits of address (if the
user transmitted the first half of a 10-bit address
with R/W = 0),
• Transmit eight bits of data (if the user transmitted
a 7-bit address with R/W = 0), or
• Receive eight bits of data (if the user transmitted
either the first half of a 10-bit address or a 7-bit
address with R/W = 1).
9.2.11.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated
START sequence is in progre ss, then WCOL i s set and
the contents of the buffer are unchanged (the write
doesn’t occur).
FIGURE 9-17: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is set while another event is in
progre ss, it will not t ake ef fect. Que uing of
events is not allowed.
2: A bus collision during the Repeated
START condition occurs if either of the
following is true:
a) SDA is sampled low when SCL
goes from low to high.
b) SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data “1”.
Note: Because queueing of events is not
allowed, writing of the lower five bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
SDA
SCL
Sr = Repeated START
Write to SSPCON2
Write to SSPBUF occurs here.
Falling edge of ninth clock
End of Xmit
At completion of START bit,
hardware clears RSEN bit
1st Bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change) SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
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9.2.12 I2C MASTER MODE
TRANSMISSION
In Master-transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains seven bits of address
data and the Read/Write (R/W) bit. In this case, the R/
W bit will be logic '0'. Subsequent serial data is trans-
mitted eight bits at a time. After each byte is transmit-
ted, an Ac knowledge bit is rec eived. START and ST OP
conditions are output to indicate the beginning and the
end of a seria l transfe r.
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit a dd ress i s ac com pl is hed b y s im pl y writ-
ing a val ue to the SSPBUF regi ste r. This action wil l s et
the buf fe r full fl ag (BF) and allow th e baud ra te gene ra-
tor to begin counting and start the next transmission.
Each bit of address/data will be shifted out onto the
SDA pin after the falling edge of SCL is asserted (see
data hold t ime s pec). SCL is he ld low for o ne bau d rate
generator roll over count (TBRG). Data should be valid
before SCL is released high (see data setup time
spec). Wh en the SCL pin is rel eased high, it is he ld that
way for TBRG, the data on the SDA pin must remain st a-
ble for that duration and some hold time after the next
falling edge of SCL. After the eighth bit is shifted out
(the falling edge of the eighth clock), the BF flag is
clear ed a nd th e ma ste r rel eas es SD A. T his allow s t he
slave device being addressed to respond with an ACK
bit during the ninth bit time. The status of ACK is re ad
into the ACKDT on the risi ng edg e of the ni nth cl oc k. If
the master receives an Acknowledge, the Acknowl-
edge status bit (ACKSTAT) is cleared. Otherwise, the
bit is set. The SSPIF is set on the falling edge of the
ninth cl ock, a nd the ma ster cl ock (b aud rate generat or)
is suspended until the next data byte is loaded into the
SSPBUF leaving SCL low and SDA unchanged
(Figure 9-18).
A typical transmit sequence would go as follows:
a) The user generates a START Condition by set-
ting the STAR T enab le bit (SEN) in SSPCON2.
b) SSPIF is set at the completion of the START
sequence.
c) The user resets the SSPIF bit and loads the
SSPBUF with seven b its of add ress plus R/W bit
to transmit.
d) Addres s and R/W is shifted out the SDA pin until
all eight bits are transmitted.
e) The MSSP Modu le shift s in the ACK bi t from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) Th e mo dul e generates a n i nte rrup t at the en d of
the ninth clock cycle by setting SSPIF.
g) The user resets the SSPIF bit and loads the
SSPBUF with eight bits of data.
h) DAT A is shif ted out the SDA pin until all eight bits
are transmitted.
i) The MSSP M odule shift s in the ACK bi t f rom th e
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) The M SSP mo dule g enerate s an int errupt a t th e
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
k) The user resets the SSPIF bit and generates a
STOP co nditi on by se ttin g t he STOP ena ble bi t
PEN in SSPCON2.
l) SSPIF is set when the ST OP condition is complete.
9.2.12.1 BF STATUS FLAG
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all eight bits are shifted out.
9.2.12.2 WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
9.2.12.3 ACKSTAT STATUS FLAG
In T ran smit mod e, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the sl ave does not Acknowl-
edge (ACK = 1). A slave sends an Ac knowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
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FIGURE 9-18: I2C MASTER MODE WAVEFORMS FOR TRANSMISSION (7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0
NACK
Transmittin g Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
cleared in software service routine
SSPBUF is written in software
From SSP in ter rup t
After START condition SEN c leared by hardware.
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
SEN = 0
of 10-bit Addre ss
Write SSPCON2 < 0> SEN = 1
START condition begins ACK from slave clea rs ACKSTAT bit (SSPCON2<6>)
cleared in software
SSPBUF written
PEN
Cleared in software
PEN is set to initiate STOP condition
NACK from slave sets ACKSTAT bit (SSPCON2<6>)
until SSPBUF is
written.
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9.2.13 I2C MASTER MODE RECE PTI ON
In Master-receive mode, the first byte transmitted con-
ta ins seve n bits of address data an d the R/W bit. In this
case, the R/W bit will be logic '1'. Thus, the first byte
tran sm it te d i s a 7- bit s la ve ad d res s f o ll ow ed by a ' 1' to
indicate receive. Serial data is received via SDA, while
SCL outputs the serial clock. Serial data is received
eight bits at a time. After each byte is received, an
Acknowledge bit is transmitted. The START condition
indicates the beginning of a transmission. The master-
receiver terminates slave transmission by responding
to the last byte with a NACK Acknowledge and follows
this with a STOP condition to indicate to other masters
that the bus is free.
Master mode reception is enabled by setting the
receive enable bit, RCEN (SSPCON2<3>), immedi-
ately following the Acknowledge sequence.
The baud rate generator b egi ns cou nti ng, and on eac h
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the fallin g edge of the eighth cl ock, the follow ing event s
occur:
• The receive enable bit is automatically cleared.
• The contents of the SSPSR are loaded into the
SSPBUF.
• The BF flag is set.
• The SSPIF is set.
• The baud rate generator is suspended from
counting, holding SCL low.
The SSP is now in IDLE state, awaiting the next com-
mand. Whe n the buf fer is read by the CPU, the BF flag
is automatically cleared. The user can then send an
Acknow ledge bit a t the e nd of recept ion by clea ring th e
ACKDT bit (SSPCON2<5>) and setting the Acknowl-
edge sequence enable bit, ACKEN (SSPCON2<4>).
A typical receive sequence would go as follows:
a) The user generates a START Condition by set-
ting the STAR T enab le bit (SEN) in SSPCON2.
b) SSPIF is set at the completion of the START
sequence.
c) The user resets the SSPIF bit and loads the
SSPBUF with seven b its of a ddress in the MSbs
and the LSb (R/W bit) set to '1' for receive.
d) Addres s and R/W is shifted out the SDA pin until
all eight bits are transmitted.
e) The MSSP Modu le shift s in the ACK bi t from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) Th e mo dul e generates a n i nte rrup t at the en d of
the ninth clock cycle by setting SSPIF.
g) The user resets the SSPIF bit and sets the
RCEN bit to enable reception.
h) DATA is shifted into the SDA pin until all eight
bits are received.
i) The MSSP module set s the SSPIF bit and clears
the RCEN bit at the falling edge of the eighth
clock.
j) The user resets the SSPIF bit and sets the
ACKDT bit to '0' (ACK), if another byte is antici-
pated. Otherwise, the ACKDT bit is set to '1'
(NACK) to terminate reception. The user sets
ADKEN to start the Acknowledge sequence.
k) The MSSP module sets the SSPIF bit at the
completion of the Acknow ledge.
l) If a NACK was sent in step ( j), then the user pro-
ceeds with step ( m). Otherwise, reception con-
tinues by repeating steps ( g) through ( j).
m) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
n) SSPIF is set when the STOP condition is complete.
9.2.13.1 BF STATUS FLAG
In receiv e operation, BF is se t when an addr ess or data
byte is loaded into SSPBUF from SSPSR. It is cleared
by hardware when SSPBUF is read.
9.2.13.2 SSPOV STATUS FLAG
In receive operation, SSPOV is set when eight bits are
received in to the SSPSR and the BF flag is alread y set
from a previous reception.
9.2.13.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The MSSP Module must be in an IDLE
STATE before the RCEN bit is set or the
RCEN bit will be disregarded.
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FIGURE 9-19: I2C MASTER WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus Master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
Master sends NACK to
Write to SSPCO N2<0 >, (SEN = 1)
Write to SSPBUF ACK from Slave
Master configured as a receiv e r
by programming SSPCON2<3>, (RCEN = 1) PEN bit = 1
written her e
Data shifted in on falling edge of CLK
starts transmit
SEN = 0
(SSPSTAT<0>)
NACK
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPIF occurs
at end of receive
SSPIF occurs at end
ACK from Master
SSPIF occurs at
SSPIF occurs
at end of Acknowledge
sequence
SSPIF occurs
at end of Acknow-
ledge sequ en ce
end of receive
RCEN clear ed
automatically
RCEN = 1 to start
next receive
and set ACKEN (SSPCON2<4>) = 1
to start ACK Acknowledge sequence
Set ACKDT (SSPCON2<5>) = 0
RCEN clear ed
automatically
ACKEN
Begin START Condition
Cleared in software
SDA = ACKDT = 0
Writing SSPBUF causes
BF to go high
SSPIF occurs at end of transmit
SSPIF occurs at end of Start
terminate slave transmission
and set ACKEN (SSPCON2<4>) = 1
to start NACK Acknowledge sequence
Set ACKDT (SSPCON2<5>) = 1
of STOP sequence
SSPBUF is read
clearing BF flag
ACKEN bit is set to initiate
Acknowledge sequence ACKEN is cleared by hardware
BF clears automatically
when the last bit is shifted out.
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9.2. 14 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
ACKDT (SSPCON2<5>) is presented on the SDA pin.
If the user wishes to generate an Acknowledge (ACK),
then the ACKDT bit should be cleared. Otherwise, the
user should set the ACKDT bit (NACK) before starting
an Ackno wledge seq uence. The baud rat e generator i s
then loaded from SSPADD<6:0> and counts for one
rollove r period (TBRG). The SCL pin is then de-asserted
(pulled hig h). When the SCL pin is sa mpled high (cl ock
arbitration), the baud rate generator is reloaded and
count s for anothe r TBRG. At the comp letion of the TBRG
period, the following events occur (see Figure 9-20):
• The SCL pin is pulled low.
• The ACKEN bit is automatically cleared.
• The baud rate generator is turned off.
• The MSSP module goes into IDLE mode.
9.2.14.1 WCOL STATUS FLAG
If the user writes the SSPBUF when an Acknowledge
sequenc e is in pro gress , the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-20: ACKNOWLEDGE SEQUEN CE WAVEFORM
Note: TBRG = one baud rate generator period.
SDA
SCL
SSPIF occ u rs at the
Acknowledge sequence starts here,
Write to SSPCON 2 ACKEN automatically cleared
Cleared in
TBRG TBRG
end of receive
ACK
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software SS PIF occ urs at the end
of Acknowledge sequence
Cleared in
software
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9.2.15 STOP CONDITION TIMING
The master asserts a STOP condition on the SDA and
SCL pin s at th e end o f a rece ive/tra nsmit by settin g the
S top Sequence Enable bit PEN (SSPCON2<2>). At the
end of a receive/transmit plus Acknowledge, the SCL
line is he ld low immediat ely followi ng the falling edg e of
the ninth SCL pu lse. Wh en the PEN bit is se t, the ma s-
ter will assert the SDA line low. When the SDA line is
sampled low, the baud rate generator is loaded from
SSPADD<6:0> and counts down to 0. When the baud
rate generator times out, the SCL pin is brought high,
the BRG is relo ade d and one TBRG (bau d rate gene ra-
tor rollover count) later, the SDA pin is de-asserted.
The SDA pin transition from low to high while SCL is
high is the ST OP co ndi tio n and cause s the P bit (SSP-
STAT<4>) to be set. Following this the baud rage gen-
erator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the baud rate generator
times out (TBRG) th e STOP cond ition is complete and
the PEN bit is cleared and the SSPIF bit is set
(Figure 9-21).
Whenever the firmware decides to take control of the
bus, it should f irst determ ine if the bus is busy by ch eck-
ing the S a nd P bit s in the SSPSTAT register. When the
MSSP module detect s a START or ST OP con dition th e
SSPIF flag is set. If the bus is busy (S bit is set), then
the CPU can be configured to be interrupted when
when the bus is free by enab ling the SSPIF interrup t to
detect the STOP bit.
9.2.15.1 WCOL STATUS FLAG
If the use r writes t he SSPBUF when a STO P sequenc e
is in progress, then WCOL is set and the content s of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-21: STOP COND ITION RECEIVE OR TRANSMIT MODE
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON 2
Set PEN
Falling edge of
9th clock
SCL brought high after TBRG
Note: TBRG = one baud rate generator period.
TBRG TBRG
P bit (SSPSTAT<4>) is set
TBRG
to setup STOP condition.
NACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
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9.2.16 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin i s actua ll y sa mpled high. Wh en the SC L p in i s
sample d high, the baud rate gen erator is reloa ded wi th
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least on e BRG rollov er count in th e event tha t the cloc k
is held low by an external device (Figure 9-22).
FIGURE 9-22: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count BRG overflow occur s,
Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting
clock high interval.
SCL line sampled once every machine cycle (Tosc 4).
Hold off BRG until SCL is sampled high.
TBRG TBRG TBRG
to measure high time interval
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9.2.17 MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
Multi-master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, bus ar bi trati on is init iate d w hen one ma s-
ter outputs a '1' on SDA (by letting SDA float high) and
another master asserts a '0'. If the expected data on
SDA is a '1 ' and the da ta s ampled o n the SD A pin = '0',
then a bus collision has taken place. The master that
expected a ‘1’ will set the Bus Collision Interrupt Flag,
BCLIF, and reset the I2C port to its IDLE state.
(Figure 9-23).
A bus collision during transmit results in the following
events:
• The transmission is halted.
• The BF flag is cleared
• The SDA and SCL lines are de-asserted
• The restriction on writing to the SSPBUF during
transmission is lifted.
When the user services the bus collision interrupt ser-
vice routine, and if the I2C bus is free, the user can
resume communication by asserting a START condi-
tion.
A bus collision during a START, Repeated START,
STOP or Acknowledge condition results in the foll owing
events:
• The condition is aborted.
• The SDA and SCL lines are de-asserted.
• The respect ive cont rol bit s in th e SSPCON2 regis -
ter are cleared.
When the user services the bus collision interrupt ser-
vice routine, and if the I2C bus is free, the user can
resume communication by asserting a START condi-
tion.
The Master will continue to monitor the SDA and SCL
pins, an d if a ST OP cond ition occ urs, the SSPIF b it will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be t aken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
FIGURE 9-23: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high
data doesn’t match what is driven
Bus collision has occurred.
Set bus collision
interrupt.
by the master.
by master
Data changes
while SCL = 0
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9.2.17.1 BUS COLLISION DURING A START
CONDITION
During a START condition, a bus collision occurs if:
a) SDA or SC L are sampled low at the begi nning of
the START condition (Figure 9-24).
b) SCL is sampled low before SDA is asserted low.
(Figure 9-25).
During a START condition both the SDA and the SCL
pins are monitored.
If: the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 9-24).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
whil e SD A is hi g h, a bus co l li si o n oc cur s, be ca use it is
assumed that another master is attempting to drive a
data '1 ' during the START cond iti on.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-26). If however a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
count s down to 0, and during thi s time, if the SCL pin is
sampled as '0', a bus collision does not occur. At the
end of the BRG count the SCL pin is asserted low.
FIGURE 9-24: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a START condition is that no two
bus mas ters can a ssert a START condi tion
at the exact same time. Therefore, one
master will always assert SDA before the
other. This conditio n does no t cause a bus
collis ion, because the two masters must be
allow ed to arbitrate t he first addres s follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continu e in to t he d ata portio n, REPEATED
START or STOP conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into IDLE state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable START
condition if SDA = 1, SCL=1
SDA = 0, SCL = 1
BCLIF
S
SSPIF
SDA = 0, SCL = 1
SSPI F an d BCLIF ar e
cleared in software.
SSPIF and BCLIF are
cleared in software.
Set BCLIF,
Set BCLIF.
START condition.
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FIGURE 9-25: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 9-26: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA
SCL
SEN Bus collision occurs, Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable START
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupts cleared
in software.
Bus collision occurs, Set BCLIF.
SCL = 0 before BRG time out,
'0'
'0'
'0'
'0'
SDA
SCL
SEN
Set S
Set SEN, enable START
sequence if SDA = 1, SCL = 1
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
s
Interrupts cleared
in software.
Set SS PIF
SDA = 0, SCL = 1
SDA pulled low by other master.
Reset BRG and assert SDA
SCL pulled low after BRG
Time-out
Set SS PIF
'0'
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9.2.17.2 BUS COLLISION DURING A REPEATED
START CONDITION
During a Repeated START condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’ .
When the master module de-asserts SDA and the pin
is allowed to float high, the BRG is loaded with
SSPADD<6:0>, and count s dow n to ‘0’. The SCL pin is
then de-asserted, and when sampled high, the SDA pin
is sampled. If SDA is low, a bus collision has occurred
(i.e., another master is attempting to transmit a data
’0’). If however SDA is sampled high, then the BRG is
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs,
becaus e no tw o maste rs can a ssert SDA at exactl y the
same time.
If, however, SCL goes from hig h to low before the BRG
times ou t and SDA has not already been asserted, then
a bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
START condition.
If at the end of the BRG time-out both SCL and SDA are
still high, the SDA pin is driven low, the BRG is
reloaded , and begins cou nting. At the end of the c ount,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is com-
plete (Figure 9-27).
FIGURE 9-27: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 9-28: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
Cleared in software
'0'
'0'
'0'
'0'
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
TBRG TBRG
'0'
'0'
'0'
'0'
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9.2.17.3 BUS COLLISION DURING A STOP
CONDITION
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low bef ore SDA goes hig h.
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the baud rate generator is loaded with SSPADD<6:0>
and count s down to ‘0’. After the BRG tim es out SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a d at a '0 ' (Fig ure 9-29 ). If the SCL pin is s am ple d
low before SDA is allowed to float high, a bus collision
occurs. This is an other case of another master attempt-
ing to drive a data '0' (Figure 9-30).
FIGURE 9-29: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 9-30: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
Set BCLIF
'0'
'0'
'0'
'0'
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high
Set BCLIF
'0'
'0'
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9.2.18 CONNE CTION CONSIDERATIONS
FOR I2C BUS
For Standard mode I2C bus devices, the values of
resistors Rp and Rs in Figure 9-31 depends on the fol-
lowing parameters
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
leakage current).
The sup ply v olt age limi ts the m inimu m va lue of res istor
Rp due to the specified minimum sink current of 3 mA
at VOL max = 0.4V for the specified output stages. For
example, with a supply voltage of VDD = 5V+10% a nd
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 k VDD as a function of Rp is shown in Figure 9-31.
The desired noise margin of 0.1VDD for the low level
limits the maximum value of Rs. Series resistors are
optional and used to improve ESD susceptibility.
The bus capacitance is the total capacitance of wire,
connec tions, and p ins. This c apacit ance limit s the m ax-
imum value of Rp due to the specified rise time
(Figure 9-31).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
FIGURE 9-31: SAMPLE DEVICE CONFIGURATION FOR I2C BUS
TABLE 9-3: REGISTERS ASSOCIATED WITH I2C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF ——SSPIFCCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE —— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
0Dh PIR2 LVDIF — — —BCLIF — — CCP2IF 0--- 0--0 0--- 0--0
8Dh PIE2 LVDIE — — —BCLIE — — CCP2IE 0--- 0--0 0--- 0--0
13h SSPBUF Synchronous Serial Port Receive Buffer/T ransmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
93h SSPADD Synchronous Serial Port (I2C Mode) Address Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the MSSP in I2C mode.
RpRp
VDD + 10%
SDA
SCL
Note: I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also
DEVICE
Cb=10 pF to 400 pF
RsRs
connected.
PIC16C717/770/771
DS41120C-page 100 Advance Information 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 101
PIC16C717/770/771
10.0 VOLTAGE REFERENCE
MODULE AND LOW-VOLTAGE
DETECT
The Voltage Reference module provides reference
voltages for the Brown-out Reset circuitry , the Low-volt-
age Detect circuitry and the A/D converter.
The source for the reference voltages comes from the
bandgap ref erence circu it. The band gap ci rcuit is en er-
gized anytime the reference voltage is required by the
other sub-modules, and is powered down when not in
use. The c ontrol re giste rs fo r this mo dule are LVDCON
and REFCON, as shown in Register 10-1 and
Figure 10-2.
REGISTER 10-1: LOW-VOLTAGE DETECT CONTROL REGISTER (LV DCON: 9Ch)
U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
—— BGST LVDEN LV3 LV2 LV1 LV0
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5 BGST: Bandgap Stable Status Flag bit
1 = Indicates that the bandgap voltage is stable, and LVD interrupt is reliable
0 = Indicates that the bandgap voltage is not stable, and LVD interrupt should not be enabled
bit 4 LVDEN: Low-volt age Detect Power Enab le bit
1 = Enables LVD, powers up bandgap circuit and reference generator
0 = Disables LVD, powers down bandgap circuit if unused by BOR or VRH/VRL
bit 3-0 LV<3:0>: Low Voltage Detection Limit bits(1)
1111 = External analog input is used
1110 = 4.5V
1101 = 4.2V
1100 = 4.0V
1011 = 3.8V
1010 = 3.6V
1001 = 3.5V
1000 = 3.3V
0111 = 3.0V
0110 = 2.8V
0101 = 2.7V
0100 = 2.5V
0011 = Reserved. Do not use.
0010 = Reserved. Do not use.
0001 = Reserved. Do not use.
0000 = Reserved. Do not use.
Note: These are the min imum trip points fo r the LVD. See Table 15-8 for the trip point to l-
erances. Selection of reserved setting may result in an inadvertent interrupt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 102 1999-2013 Microchip Technology Inc.
REGISTER 10-2: VOLTAGE REFERENCE CONTROL REGISTER (REFCON: 9BH)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
VRHEN VRLEN VRHOEN VRLOEN ————
bit 7 bit 0
bit 7 VRHEN: Voltage R eference High Enable bit (VRH = 4.096V nominal)
1 = Enabled, powers up reference generator
0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRL
bit 6 VRLEN: Voltage Reference Low Enable bit (VRL = 2.048V nominal)
1 = Enabled, powers up reference generator
0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRH
bit 5 VRHOEN: High Voltage Reference Output Enable bit(1)
1 = Enabled, VRH analog reference is output on RA3 if enabled (VRHEN = 1)
0 = Disabled, analog reference is used internally only(1)
bit 4 VRLOEN: Low Voltage Reference Output Enable bit
1 = Enabled, VRL analog reference is output on RA2 if enabled (VRLEN = 1)
0 = Disabled, analog reference is used internally only
bit 3-0 Unimplemented: Read as '0’
Note 1: RA2 and RA 3 must be co nfigured as analog in puts when the VREF output functions
are enabled (See ANSEL on page 25).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 103
PIC16C717/770/771
10.1 Bandgap Voltage Reference
The bandgap module gen erat es a st able volt a ge refer-
ence of over a range of temperatures and device sup-
ply voltages. This module is enabled anytime any of the
following are enabled:
• Brown-out Reset
• Low-vo lt a ge D etec t
• Either of the internal analog references (VRH,
VRL)
Whenever the above are all disabled, the bandgap
module is disabled and draws no current.
10.2 Internal VREF fo r A /D C o n verter
The bandgap output voltage is used to generate two
stable references for the A/D converter module. These
references are enabled in software to provide the user
with the means to turn them on and off in order to min-
imize curre nt consumption. Each ref erence can be indi-
vidually enabled.
The V RH re f ere nc e is en a ble d w i th co nt ro l bi t V RH EN
(REFCON<7>). When this bit is set, the gain amplifier
is enabled. After a specified start-up time a stable ref-
erence of 4.096V nominal is generated and can be
used by the A/D converter as a reference input.
The VRL reference is enabled by setting control bit
VRLEN (REFCON<6>). When this bit is set, the gain
amplifier is enabled. After a specified start-up time a
stable reference of 2.048V nominal is generated and
can be use d by the A/D co nverte r as a referen ce input.
Each vol tag e referen ce is a vailable for exte rnal us e via
VRL and VRH pins.
Each reference, if enabled, can be output on an exter-
nal pin by setting the VRHOEN (high reference output
enable) o r VRLOEN (low refe rence output ena ble) con-
trol bit. If the reference is not enabled, the VRHOEN
and VRLOEN bits will have no effect on the corre-
sponding pin. The device specific pin can then be used
as general purpose I/O.
FIGURE 10-1: BLOCK DIAGRAM OF LVD AND VOLTAGE REFERENCE CIRCUIT
Note: If VRH or VRL is enabled and the other ref-
erence (VRL or VRH), the BOR, and the
LVD modules are not enabled, the band-
gap will require a start-up time before the
bandgap reference is stable. Before using
the intern al V RH or VRL re ference , ensu re
that the bandgap reference voltage is sta-
ble by moni toring the BGST bit in the LVD-
CON register. The voltage references will
not be reliable until the bandgap is stable
as shown by BGST being set.
VDD
generates
16 to 1 MUX
BGAP
VRH
VRL
LVDEN
LVDCON REFCON
BODEN
LVDEN VRHEN + VRLEN
RA1/AN1/LVDIN LVDIF
PIC16C717/770/771
DS41120C-page 104 1999-2013 Microchip Technology Inc.
10.3 Low Voltage Detect (LVD)
This module is used to generate an interrupt when the
supply voltage falls below a specified “trip” voltage.
This module operates completely under software
control. This allows a user to power the module on
and off to periodically monitor the supply voltage, and
thus minimize total current consumption.
The LVD module is enable d by setting the LVDEN b it in
the LVDCON register. The “trip point” voltage is the
minimum supply voltage level at which the device can
operate before the LVD module asserts an interrupt.
When the supp ly voltage is equa l to or less than the tri p
point, the module will generate an interrupt signal set-
ting inte rrupt flag bit LVDIF. If inter rupt enable bit LVDIE
was set, then an interrupt is generated. The LVD inter-
rupt can wake the device from SLEEP. The "trip point"
volt age is sof tware pr ogrammab le to any one of 16 va l-
ues , five of w h ic h a re r es e rv e d ( See Fi g ur e 10-1) . T he
trip poi nt is selec ted by pr og rammi ng t he LV <3: 0> bi ts
(LVDCON<3:0>).
Once the LV bits have been programmed for the spec-
ified trip volt age, the low-v olt age dete ct circ uitry is the n
enabled by setting the LVDEN (LVDCON<4>) bit.
If the bandgap reference voltage is previously unused
by either the brown-out circuitry or the voltage refer-
ence circuitry, then the bandgap circuit requires a time
to st art-up and becom e stable bef ore a low voltage con-
dition can be reliably detected. The low-voltage inter-
rupt flag is prevented from being set until the bandgap
has reached a stable refe rence voltage.
When the bandgap is stable the BGST (LVDCON<5>)
bit is s et ind icating t hat the lo w-volt age i nterrupt fla g bit
is released to be set if VDD is equal to or less than the
LVD trip point.
10.3.1 EXTERNAL ANALOG VOLTAGE INPUT
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when
LV<3:0> = 1111. When these bits are set the compar-
ator input is multiplexed from an external input pin
(RA1/AN1/LVDIN).
Note: The LVDIF bit can not be cleared until the
supply voltage rises above the LVD trip
point. If interrupts are enabled, clear the
LVDIE bit once the first LVD interrupt
occurs to prevent reentering the interrupt
service routine immediately after exiting
the ISR.
1999-2013 Microchip Technology Inc. DS41120C-page 105
PIC16C717/770/771
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has six
inputs for the PIC16C717/770/771.
The PIC16C717 analog-to-digital converter (A/D)
allows conversion of an analog input signal to a corre-
sponding 10-bit digital value, while the A/D converter
in the PIC16C770/771 allows conversion to a corre-
sponding 12-bit digital value. The A/D module has up
to 6 analog inputs, which are multiplexed into one
sample and hold. The output of the sample and hold is
the input into the converter, which generates the result
via successive approximation. The analog reference
voltages are software selectable to either the device’s
analog positive and negative supply voltages (AVDD/
AVSS), the voltage level on the VREF+ and VREF- pins,
or internal voltage references if ena bled (VRH, VRL).
The A/D converter can be triggered by setting the GO/
DONE bit, or by the special event Compare mode of
the ECCP module. When conversion is complete, the
GO/DONE bit returns to ’0’, the ADIF bit in the PIR1
register is set, and an A/D interrupt will occur, if
enabled.
The A/D converter has a unique feature of being able
to opera te while th e device i s in SLEEP mode. To op er-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The A/D module has four registers. These registers
are: • A/D Result Register Low ADRESL
• A/D Result Register High ADRESH
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conve r si on is aborted .
11.1 Control Registers
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins, the voltage reference configura-
tion and the result format. The ANSEL register, shown
in Register 3-1, selects between the Analog or Digital
Port Pin modes. The port pins can be configured as
analog inputs or as digital I/O.
The combination of the ADRESH and ADRESL regis-
ters contain the result of the A/D conversion. The reg-
ister pair is referred to as the ADRES register. When
the A/D conversion is complete, the result is loaded
into ADRES, the GO/DONE bit (ADCON0<2>) is
cleared, and the A/D interrupt flag ADIF is set. The
block diagram of the A/D module is shown in
Figure 11-3.
PIC16C717/770/771
DS41120C-page 106 1999-2013 Microchip Technology Inc.
REGISTER 11-1: A/D CONTROL REGISTER 0 (ADCON0: 1Fh).
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON
bit 7 bit 0
bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits
If internal VRL and/or VRH are not used for A/D reference (VCFG<2:0> = 000, 001, 011
or 101):
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from a dedicated RC oscillator)
If internal VRL and/or VRH are used for A/D reference (VCFG<2:0> = 010, 100, 110 or 111):
00 = FOSC/16
01 = FOSC/64
10 = FOSC/256
11 = FRC/8
bit 5-3, 1 CHS:<3:0>: Analog Channel Select bits
0000 = channel 00 (AN0)
0001 = channel 01 (AN1)
0010 = channel 02 (AN2)
0011 = channel 03 (AN3)
0100 = channel 04 (AN4)
0101 = channel 05 (AN5)
0110 = reserved, do not select
0111 = reserved, do not select
1000 = reserved, do not select
1001 = reserved, do not select
1010 = reserved, do not select
1011 = reserved, do not select
1100 = reserved, do not select
1101 = reserved, do not select
1110 = reserved, do not select
1111 = reserved, do not select
bit 2 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter is shutoff and consumes no operating current
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 107
PIC16C717/770/771
REGISTER 11-2: A/D CONTROL REGISTER 1 (ADCON1: 9Fh)
The value that is in the ADRESH and ADRESL regis-
ters are not modified for a Power-on Reset. The
ADRESH and ADRESL registers will contain unknown
data after a Power-on Reset.
The A/D conversion results can be left justified (ADFM
bit cleared), or right justified (ADFM bit set).
Figure 11-1 through Figure 11-2 show the A/D result
data format of the PIC16C717/770/771.
FIGURE 11-1: PIC16C770/771 12-BIT A/D RESULT FORMATS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG2 VCFG1 VCFG0 Reserved Reserved Reserved Reserved
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6-4 VCFG<2:0>: Voltage Reference Configuration bits
bit 3-0 Reserved: Do not use.
Note 1: This parameter is VDD for the PIC16C717.
2: This parameter is VSS for the PIC16C717.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
A/D VREF+A/D VREF-
000 AVDD(1) AVSS(2)
001 External VREF+ External VREF-
010 Internal VRH Internal VRL
011 External VREF+AVSS(2)
100 Internal VRH AVSS(2)
101 AVDD(1) External VREF-
110 AVDD(1) Internal VRL
111 Internal VRL AVSS
ADRESH (1Eh) ADRESL (9Eh)
Left Justified
(ADFM = 0) MSB LSB
bit7 bit7
12-bit A/D Result Unused
Right Justified
(ADFM = 1) MSB LSB
bit7 bit7
Unused 12-bit A/D Result
PIC16C717/770/771
DS41120C-page 108 1999-2013 Microchip Technology Inc.
FIGURE 11-2: PIC16C717 10-BIT A/D RESULT FORMAT
After the A/D module has been configured as desired,
the sele cted channe l m ust be acquire d b efore the con-
version is started. The analog input channels must
have their corresponding TRIS and ANSEL bits
select ed as an input. To determine acquisition time, see
Section 11.6. After this acquisition time has elapsed,
the A/D co nv ers ion ca n b e s tarted. Th e following s teps
should be followed for doing an A/D conversion:
11.2 Configuring the A/D Module
11.2.1 CONFIGURING ANALOG PORT
PINS
The ANSEL and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bit
set (input ). If the TRIS bit is cleared (out put) , the digit al
output level (VOH or VOL) will be co nv erted. The prop er
ANSEL bits must be set (analog input) to disable the
digital input buffer.
The A/D operation is independent of the state of the
TRIS bits and the ANSEL bits.
11.2.2 CONFIGURING THE REFERENCE
VOLTAGES
The VCFG bits in the ADCON1 register configure the
A/D module reference inputs. The reference high input
can come from an internal reference (VRH) or (VRL),
an external reference (VREF+), or AVDD. The low refer-
ence inp ut c an co me from an inte rnal refe ren ce (VRL ),
an external reference (VREF-), or AVSS. If an external
reference is chosen for the reference hig h or referenc e
low inputs, the port pin that multiplexes the incoming
external references is configured as an analog input,
regardles s of the val ues co nt ained in the A/D port con-
figuration bits (PCFG<3:0>).
(ADFM = 0) MSB LSB
bit7 bit7
10-bit A/D Result Unused
(ADFM = 1) MSB LSB
bit7 bit7
Unused 10-bit A/D Result Unused
Note 1: When reading the PORT A register , all pins
configured as analog input channels will
read as ’0’.
2: When reading the PORTB register, all
pins configured as analog pins on
PORTB will be read as ’1’.
3: Analog l evels on any p in that is defined a s
a digital input, including the ANx pins, may
cause the inp ut b uffer to consume c urre nt
that is out of the devices specification.
1999-2013 Microchip Technology Inc. DS41120C-page 109
PIC16C717/770/771
After the A/D module has been configured as desired
and the analog input channels have their correspond-
ing TRIS bits selected for port inputs, the selected
channel must be acquired before conversion is
started. The A/D conversion cycle can be initiated by
setting the GO/DONE bit. The A/D conversion begins
and lasts for 13TAD. The f oll owin g ste ps shoul d be f ol-
lowed for performing an A/D conversion:
1. Configure port pins:
• Configure Analog Input mode (ANSEL)
• Configure pin as input (TRISA or TRISB)
2. Configure the A/ D module
• Configure A/D Result Format / voltage refer-
ence (ADCON1)
• Select A/D input channel (ADCON0)
• Selec t A/D conve rsi on clock (ADCON0)
• Turn on A/D module (ADCON0)
3. Confi g ure A /D interrupt (if requir ed)
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
4. Wait the required acquisition time.
5. START conversion
• Set GO/DONE bit (ADCON0)
6. Wa it 13TAD until A/D co nv ers ion is com ple te, b y
either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
7. Read A/D Result registers (ADRESH and
ADRESL), clear ADIF if required.
8. For next co nv ers ion , g o to s tep 1, step 2 or ste p
3 as required.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRESH and
ADRESL registers will be updated with the partially
completed A/D conversion value. That is, the
ADRESH and ADRESL registers will contain the value
of the current incomplete conversion.
FIGURE 11-3: A/D BLOCK DIAGRAM
Note: Do not set the ADON bit and the GO/
DONE bit in the sam e instru ction. Do ing so
will cause the GO/DONE bit to be automat-
ically cleared.
(INPUT VOLTAGE)
VAIN
VREF+
(REFERENCE
VOLTAGE +)
AVDD
VCFG<2:0>
CHS<3:0>
RB1/AN5/SS
RB0/AN4/INT
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
RA0/AN0
A/D
CONVERTER
VREF-
(REFERENCE
VOLTAGE -) AVSS
VCFG<2:0>
VRH
VRL
VRL
PIC16C717/770/771
DS41120C-page 110 1999-2013 Microchip Technology Inc.
11.3 Selecting the A/D Conversion
Clock
The A/D conversion cycle requires 13T AD: 1 TAD for set-
tling tim e, and 12 TAD for convers ion. The so urce of the
A/D conversion clock is sof tware selected. If neither the
internal VRH nor VRL are used for the A/D converter,
the four possible options for TAD are:
•2 T
OSC
•8 TOSC
•32 TOSC
• A/D RC oscil la tor
If the VR H or VR L are used f or the A /D co nverter ref er-
ence, then the TAD requirement is automatically
increased by a factor of 8.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s. Table 11-1 shows the resultant TAD times
derived from the device operating frequencies and the
A/D clock sou rce selected.
The ADIF bit is set on the rising edge of the 14th TAD.
The GO/DONE bit is cleared on the falling edge of the
14th TAD.
TABLE 11-1: TAD vs. DEVICE OPERATING FREQUENCIES
A/D Reference
Source A/D Clock Source (TAD) Device Frequency
External VREF or
Analog Supply
Operation ADCS<1:0> 20 MHz 5 MHz 4 MHz 1.25 MHz
2 TOSC 00 100 ns(2) 400 ns(2) 500 ns(2) 1.6 s
8 TOSC 01 400 ns(2) 1.6 s2.0 s6.4 s
32 TOSC 10 1.6 s6.4 s(3) 8.0 s(3) 25.6 s(3)
A/D RC 11 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4)
Internal VRH or
VRL 16 TOSC 00 800 ns(2) 3.2 s(2) 4 s(2) 12.8 s
64 TOSC 01 3.2 s(2) 12.8 s 16 s 51.2 s(3)
256 TOSC 10 12.8 s51.2 s(3) 64 s(3) 204.8 s(3)
A/D RC 11 16 - 48 s(4,5) 16 - 48 s(4,5) 16 - 48 s(4,5) 16 - 48 s(4,5)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be
performed during SLEEP.
5: A/D RC clock source has a typical TAD time of 32 s f or VDD > 3.0V.
1999-2013 Microchip Technology Inc. DS41120C-page 111
PIC16C717/770/771
11.4 A/D Conversions
Example 11-1 shows an example tha t perfor ms an A/D
conversion. The port pins are configured as analog
input s. The ana log referenc e V REF+ is the device AVDD
and the analog reference VREF- is the device AVSS.
The A/D interrupt is enabled and the A/D conversion
clock i s TRC. The conversion is performed on the AN0
channel.
EXAMPLE 11-1: PERFORMING AN A/D CONVERSI ON
BSF STATUS, RP0 ;Select Bank 1
CLRF ADCON1 ;Configure A/D Voltage Reference
MOVLW 0x01
MOVWF ANSEL ;disable AN0 digital input buffer
MOVWF TRISA ;RA0 is input mode
BSF PIE1, ADIE ;Enable A/D interrupt
BCF STATUS, RP0 ;Select Bank 0
MOVLW 0xC1 ;RC clock, A/D is on,
;Ch 0 is selected
MOVWF ADCON0 ;
BCF PIR1, ADIF ;Clear A/D Int Flag
BSF INTCON, PEIE ;Enable Peripheral
BSF INTCON, GIE ;Enable All Interrupts
;
; Ensure that the required sampling time for the
; selected input channel has lapsed. Then the
; conversion may be started.
BSF ADCON0, GO ;Start A/D Conversion
: ;The ADIF bit will be
;set and the GO/DONE bit
: ;cleared upon completion-
;of the A/D conversion.
; Wait for A/D completion and read ADRESH:ADRESL for result.
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DS41120C-page 112 1999-2013 Microchip Technology Inc.
11.5 A/D Converter Module Operation
Figure 11-4 shows the flowchart of the A/D converter
module.
FIGURE 11-4: FLOW CHART OF A/D OPERATION
Sample
ADON = 0
ADON = 0?
GO = 0?
A/D Clock
GO = 0
ADIF = 0
Abort Conversion
SLEEP
Power-down A/D
Wake-up
Yes
No
Yes
No
No
Yes
Finish Conversi on
GO = 0
ADIF = 1
SLEEP
No
Yes
Finish Conversi on
GO = 0
ADIF = 1
Stay in SLEEP
Selected Channel
= RC?
Instruction?
SLEEP
No
Yes
Instruction?
Start of A/D
Conversion Delayed
1 Instruction Cycle
From SLEEP?
Power-down A/D
Yes
No
Finish Conversion
GO = 0
ADIF = 1
1999-2013 Microchip Technology Inc. DS41120C-page 113
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11.6 A/D Sample Requirements
11.6.1 RECOMMENDED SOURCE
IMPEDANCE
The maximum recommended impedance for ana-
log sources is 2.5 k. This value is calculated based
on the maximum leakage current of the input pin. The
leakage current is 100 nA max., and the analog input
voltage cannot be varied by more than 1/4 LSb or
250 V due to leakage. This places a requirement on
the input impedance of 250 V/100 nA = 2.5 k.
11.6.2 SAMPLING TIME CALCULATION
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-5. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance va rie s over the dev ice vol tag e
(VDD), see Figure 11-5. The maximum recom-
mended impedance for analog sources is 2.5 k.
After the analog input channel is selected (changed)
this sampling must be done before the conversion can
be started.
To calculate the minimum sampling time, Equation 11-
2 may be used. This equation assumes that 1/4 LSb
error is used (16384 steps for the A/D). The 1/4 LSb
error is the maxim um error allowed for the A/D to me et
it s spe ci fie d re so luti on.
The CHOLD is assumed to be 25 pF for the 12-bit
A/D.
EXAMPLE 11-2: A/D SAMPLING TIME
EQUATION
Figure 11-3 shows th e calc ulatio n of the mi nimum time
required to c harge CHOLD. This calc ulatio n is based on
the following system assumptions:
CHOLD = 25 pF
RS = 2.5 k
1/4 LSb error
VDD = 5V RSS = 10 k(worst ca se)
Temp (s yste m Max.) = 50C
Note 1:The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2:The charge holding capacitor (CHOLD) is
not discharged after each conversion.
3:The maximum recommended impedance
for analog sources is 2.5 k. This is
required to meet the pin leakage specifi-
cation.
VHOLD VREF VREF
16384
----------------
–=
VREF VREF
16384
----------------
–VREF1e
TC–
CHOLD RIC RSS RS++
-------------------------------------------------------------------
–
=
VREF 11
16384
----------------
–
VREF1e
TC–
CHOLD RIC RSS RS++
-------------------------------------------------------------------
–
=
TCCHOLD 1kRSS RS++
1
16384
----------------
ln–=
Solving for TC:
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EXAMPLE 11 -3: CALCULATING THE
MINIMUM
REQUIRED SAMPLE TIME
FIGURE 11-5: ANALOG INPUT MODEL
TACQ = Amplifier Settling Time
+ Holding Capacitor Charging Time
+Temperature offset †
TACQ =5 s
+ TC
+ [(Temp - 25C)(0.05s/C)] †
TC = Holding Capacitor Charging Time
TC =(CHOLD) (RIC + RSS + RS) In (1/16384)
TC = -25 pF (1 k +10 k + 2.5 k) In (1/16384)
TC = -25 pF (13.5 k) In (1/16384)
TC = -0.338 (-9.704)s
TC =3.3 s
TACQ =5s
+ 3.3 s
+ [(50C - 25C)(0.05s / C)]
TACQ = 8.3 s + 1.25s
TACQ = 9.55 s
† The temperature coefficient is only required for
temperatures > 25C.
CPIN
VA
RSPort Pin
5 pF
VDD
Vt = 0.6V
VT = 0.6V ILEAKAGE
RIC ~ 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
6V
Sampling Switch (RSS)
5V
4V
3V
2V
567891011
( k )
VDD
± 100 nA
Legend CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= lea kage cu rrent at the pin due to
= interconnec t resistance
= sampling switch
= sample/h old capacitance
various junctions
~
1999-2013 Microchip Technology Inc. DS41120C-page 115
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11.7 Use of th e ECCP Trigger
An A/D conversion can be started by the “special
event trigger” of the CCP module. This requires that
the CCP1M<3:0> bits be programmed as 1011b and
that the A/D module is enabled (ADON is set). When
the trigger occurs, the GO/DONE bit will be set on Q2
to start the A/D conversion and the Timer1 counter will
be reset to zero. Timer1 is RESET to automatically
repeat the A/D conversion cycle, with minimal soft-
ware overhead (moving the ADRESH and ADRESL to
the desired location). The appropriate analog input
channel must be selected before the “special event
trigger” sets the GO/DONE bit (starts a conversion
cycle).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still RESET the Timer1 counter.
11.8 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. The value that is in the
ADRESH and ADRESL registers are not modified.
The ADRESH and ADRESL registers will contain
unknown data after a Power-on Reset.
11.9 Faster Conversion - Lower
Resolution Trade-off
Not all applic ation s requi re a resu lt with 12 bit s of reso-
lution, but may instead require a faster conversion
time. The A/D module allows users to make the trade-
off of conversion speed to resolution. Regardless of
the resolution required, the acquisition time is the
same. To speed up the conversion, the A/D module
may be halted by clearing the GO/DONE bit after the
desired number of bits in the result have been con-
verted. Once the GO/DONE bit has been cleared, all
of the remaining A/D result bits are ‘0’. The equation
to determine the time before the GO/DONE bit can be
switched is as follows:
Conversion time = (N+1)TAD
Where: N = number of bits of resolution required,
and 1TAD is the amplifier settling time.
Since TAD is based from the device oscillator, the user
must us e so me meth od (a tim er, software loop, etc .) to
determine when the A/D GO/DONE bit may be
cleared. Ta bl e 1 1 - 4 shows a comparison of time
required for a conversion with 4 bits of resolution, ver-
sus the normal 12-bit resolution conversion. The
example is for devices operating at 20 MHz. The A/D
clock is programmed for 32 TOSC.
EXAMPLE 11-4: 4-BIT vs. 12-BIT
CONVERSION TIME
Example
4-Bit Example:
Conversion Time = (N + 1) TAD
= (4 + 1) TAD
= (5)(1.6 S)
= 8 S
12-Bit Example:
Conversion Time = (N + 1) TAD
= (12 + 1) TAD
= (13)(1.6 S)
= 20.8 S
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11.10 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clo ck source be c onfigured for RC
(ADCS<1:0> = 11b). With the RC clock source
selected, when the GO/DONE bit is set the A/D mo dule
waits one instruction cycle before starting the conver-
sion cycle. This allows the SLEEP instructio n to be ex e-
cuted, which eliminates all digital switching noise
during the sample and conversion. When the conver-
sion cycle is completed the GO/DONE bit is cleared,
and the result loaded into the ADRESH and ADRESL
registers. If the A/D inte rrupt is enabled , the dev ic e wil l
wake-up from SLEEP. If the A/D interrupt is not
enabled, the A/D module will then be turned off,
although the ADON bit will remain set.
When the A/D clock sour ce is anoth er clock optio n (not
RC), a SLEEP instruction causes the present conver-
sion to be aborted and the A/D module is turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D mo du le in it s low est
current consumption state.
11.11 Connection Considerations
Since the analog inputs employ ESD protection, they
have diodes to VDD and VSS. This requires that the
analog input mus t be bet ween VDD and V SS. If the input
volt age exce eds this range by greater th an 0.3V (eith er
direction), one of the diodes becomes forward biased
and it may da mage the device if the inp ut curren t spec-
ification is exceeded.
An external RC f ilt er i s so metimes added for ant i-al ias -
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept un der the 2.5 k recommended sp ecifi cation . I t is
recommended that any external components con-
nected to an analog input pin (capacitor, zener diode,
etc.) have very little leakage current.
TABLE 11-2: SUMMARY OF A/D REGISTERS
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be configured to
RC (ADCS<1:0> = 11).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ----
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 0000 ----
05h PORTA PORTA Data Latch when written: PORTA pins when read 000x 0000 000u 0000
06h PORTB PORT B Data Latch when written: PORTB pins when read xxxx xx11 uuuu uu11
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
9Dh ANSEL — — ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
17h CCP1CON — — — — 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Sha ded cells are not used for A/D conversion.
1999-2013 Microchip Technology Inc. DS41120C-page 117
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12.0 SPECIAL FEATURES OF THE
CPU
These d evices have a host of features intended to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
operating modes an d offer code protecti on. These are:
• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Low-vo lt a