1999-2013 Microchip Technology Inc. DS41120C-page 1
PIC16C717/770/771
18/20-Pin, 8-Bit CMOS Microcont rollers with 10/12-Bit A/D
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Interrupt capability (up to 10 internal/external
inter rupt so urc es)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Pow er- on Reset (POR )
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscilla tor f or relia ble opera tion
• Selectable oscillator options:
- INTRC - Internal RC, dual speed (4 MHz and
37 kHz nominal) dynamic ally s witc hable for
power savings
- ER - External resistor, dual speed (user
selectable frequency and 37 kHz nominal)
dynamically switchable for power savings
- EC - External clock
- HS - High speed crystal/resonator
- XT - Crystal/re son ator
- LP - Low power crystal
• Low power, high speed CMOS EPROM
technology
• In-Circuit Serial Programming™(ICSP™
• Wide operating voltage range: 2.5V to 5.5V
• 15 I/O pins with individual control for:
- Direction (15 pins)
- Digital/Analog input (6 pins)
- PORTB interrupt on change (8 pins)
- PORTB weak pull-up (8 pins)
- High voltage open drain (1 pin)
• Commercial and Industrial temperature ranges
• Low power consumption:
- < 2 mA @ 4V, 4 MHz
-11 A typical @ 2.5V, 37 kHz
-< 1 A typical standby current
Pin Diagr am
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be increm ent ed duri ng SLEEP via extern al
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Enhanced Capture, Compare, PWM (ECCP)
module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
- Enhanced PWM:
- Single, Half-Bridge and Full-Bridge Output
modes
- D ig it a lly pr ogra mmable deadband del ay
• Analog-to-Digital converter:
- PIC16C770/771 12-bit resolution
- PIC16C717 10- bit r esolution
• On-chip absolute bandgap voltage reference
generator
• Programmable Brown-out Reset (PBOR)
circuitry
• Programmable Low-Voltage Detection (PLVD)
circuitry
• Master Synchronous Serial Port (MSSP) with two
modes of opera tion:
- 3-wire SPI™ (supports all 4 SPI modes)
-I
2C™ compatible including Master mode
support
• Program Memory Read (PMR) capability for look-
up table, character string storage and checksum
calculation purposes
Device Memory Pins A/D
Resolution A/D
Channels
Program
x14 Data
x8
PIC16C717 2K 256 18, 20 10 bits 6
PIC16C770 2K 256 20 12 bits 6
PIC16C771 4K 256 20 12 bits 6
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
AVDD
AVSS
10 11
PIC16C770/771
20-Pin PDIP, SOIC, SSOP
PIC16C717/770/771
DS41120C-page 2 1999-2013 Microchip Technology Inc.
Pin Diagram s
18-Pin PDIP, SOIC
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PIC16C717
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD(2)
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS(1)
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
PIC16C717
VDD(2)
VSS(1)
10 11
20-Pin SSOP
Note 1: VSS pins 5 and 6 must be tied together.
2: VDD pins 15 and 16 must be tied together.
Key Features
PICmicroTM Mid-Range MCU Family
Reference Manual, (DS33023) PIC16C717 PIC16C770 PIC16C771
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR, MCLR,
WDT (PWRT, OST) POR, BOR, MCLR,
WDT (PWRT, OST) POR, BOR, MCLR,
WDT (PWRT, OST)
Program Memory (14-bit words) 2K 2K 4K
Data Memory (bytes) 256 256 256
Interrupts 10 10 10
I/O Ports Ports A,B Ports A,B Ports A , B
Timers 333
Enhanced Capture/Compare/PWM (ECCP)
modules 111
Serial Communications MSSP MSSP MSSP
12-bit Analog-to-Digital Module –6 input channels 6 input channels
10-bit Analog-to-Digital Module 6 input channels ––
Instruction Set 35 Instructions 35 Instructions 35 Instructions
1999-2013 Microchip Technology Inc. DS41120C-page 3
PIC16C717/770/771
Table of Contents
1.0 Device Overview......................................................................................................................................................5
2.0 Memory Organization...............................................................................................................................................9
3.0 I/O Ports.................................................................................................................................................................25
4.0 Program Memory Read (PMR) ..............................................................................................................................41
5.0 Timer0 Module.......................................................................................................................................................45
6.0 Timer1 Module.......................................................................................................................................................47
7.0 Timer2 Module.......................................................................................................................................................51
8.0 Enhanced Capture/Compare/PWM (ECCP) Modules............................................................................................53
9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................65
10.0 Voltage Reference Module and Low-voltage Detect..........................................................................................101
11.0 Analog-to-Digital Converter (A/D) Module..........................................................................................................105
12.0 Special Features of the CPU .............................................................................................................................117
13.0 Instruction Set Summary....................................................................................................................................133
14.0 Development Support ........................................................................................................................................141
15.0 Electrical Characteristics....................................................................................................................................147
16.0 DC and AC Characteristics Graphs and Tables................................................................................................. 179
17.0 Packaging Information .......................................................................................................................................197
APPENDIX A: Revision History ............................................. ...... ..... ...... ...................... ...... ..... ................................207
APPENDIX B: Device Differences ... ..... ...... ..... ...... ...... ...................... ...... ..... ....................... ..... ................................208
Index ..........................................................................................................................................................................209
On-Line Support..........................................................................................................................................................215
Reader Response.......................................................................................................................................................216
PIC16C717/770/771 Product Identification System....................................................................................................217
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PIC16C717/770/771
DS41120C-page 4 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS41120C-page 5
PIC16C717/770/771
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicroTM
Mid-Range MCU Family Reference Manual,
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip website. The Reference Manual should
be considered a complementary document to this data
sheet, and is highly recommended reading for a better
understanding o f the device arc hi tec ture a nd operatio n
of the peripheral modules.
There are thr ee devices (PIC16C7 17, P IC16C770 and
PIC16C771) covered by this data sheet. The
PIC16C717 device comes in 18/20-pin packages and
the PIC1 6C770/771 dev ices come in 2 0-p in packages.
The following two figures are device block diagrams of
the PIC16C717 and the PIC16C770/771.
FIGURE 1-1: PIC16C717 BLOCK DIAGRAM
EPROM
Program
Memory
2K x 14
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
256 x 8
Direct Addr 7
Addr(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
PORTA
PORTB
RA4/T0CKI
RB0/AN4/INT
RB4/SDI/SDA
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register .
Enhanced CCP Master
Timer0 Timer1 Timer2
Synchronous
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1/LVDIN
RA0/AN0
8
3
Timing
Generation
10-bit
ADC
RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
Internal
4 MHz, 37 kHz
and ER mode
(ECCP) Serial Port (MSSP)
B andgap
Reference Low-voltage
Detect
RAM
Program Memory
Read (PMR)
PIC16C717/770/771
DS41120C-page 6 1999-2013 Microchip Technology Inc.
FIGURE 1-2: PIC16C770/771 BLOC K DIAGRAM
EPROM
Program
Memory(2)
13 Data B us 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
256 x 8
Direct Addr 7
Addr(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
PORTA
PORTB
RA4/T0CKI
RB0/AN4/INT
RB4/SDI/SDA
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
2: Program memory for PIC16C770 is 2K x 14. Program memory for PIC16C771 is 4K x 14.
Enhanc ed C CP Master
Timer0 Timer1 Timer2
Synchronous
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1/LVDIN
RA0/AN0
8
3
Timing
Generation
12-bit
ADC
RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
Internal
4 MHz, 37 kHz
and ER mode
(ECCP) Serial Po rt (MSSP)
Bandgap
Reference Low-voltage
Detect
RAM
Program Memory
Read (PMR)
AVDD
AVSS
1999-2013 Microchip Technology Inc. DS41120C-page 7
PIC16C717/770/771
TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0 RA0 ST CMOS Bi-directional I/O
AN0 AN A/D input
RA1/AN1/LVDIN
RA1 ST CMOS Bi-directional I/O
AN1 AN A/D input
LVDIN AN LVD input reference
RA2/AN2/VREF-/VRL
RA2 ST CMOS Bi-directional I/O
AN2 AN A/D input
VREF- AN Negative analog reference input
VRL AN Internal voltage reference low output
RA3/AN3/VREF+/VRH
RA3 ST CMOS Bi-directional I/O
AN3 AN A/D input
VREF+ AN Positive analog reference input
VRH AN Internal voltage reference high output
RA4/T0CKI RA4 ST OD Bi-d irectional I/O
T0CKI ST TMR0 clock input
RA5/MCLR/VPP
RA5 ST Input port
MCLR ST Master clear
VPP Power Programming voltage
RA6/OSC2/CLKOUT
RA6 ST CMOS Bi-directional I/O
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
RA7/OSC1/CLKIN
RA7 ST CMOS Bi-directional I/O
OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/ER resistor connection
RB0/AN4/INT
RB0 TTL CMOS Bi-directional I/O(1)
AN4 AN A/D input
INT ST Interrupt input
RB1/AN5/SS
RB1 TTL CMOS Bi-directional I/O(1)
AN5 AN A/D input
SS ST SSP slave select input
RB2/SCK/SCL
RB2 TTL CMOS Bi-directional I/O(1)
SCK ST CMOS S erial clock I/O for SPI
SCL ST OD Serial clock I/O for I2C
RB3/CCP1/P1A
RB3 TTL CMOS Bi-directional I/O(1)
CCP1 ST CMOS Capture 1 input/Compare 1 output
P1A CMOS PWM P1A output
RB4/SDI/SDA
RB4 TTL CMOS Bi-directional I/O(1)
SDI ST Serial data in for SP I
SDA ST OD Serial data I/O for I2C
RB5/SDO/P1B
RB5 TTL CMOS Bi-directional I/O(1)
SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.
PIC16C717/770/771
DS41120C-page 8 1999-2013 Microchip Technology Inc.
RB6/T1OSO/T1CKI/P1C
RB6 TTL CMOS Bi-directional I/O(1)
T1OSO XTAL Crystal/Resonator
T1CKI CMOS TMR1 clock input
P1C CMOS PWM P1C output
RB7/T1OSI/P1D
RB7 TTL CMOS Bi-directional I/O(1)
T1OSI XTAL TMR1 crystal/resonator
P1D CMOS PWM P1D output
VSS VSS Power Ground reference for logic and I/O pins
VDD VDD Power Positive supply for logic and I/O pins
AVSS(2) AVSS Power Ground reference for analog
AVDD(2) AVDD Pow er Positive supply for analog
TABLE 1-1: PIC16C717/770/771 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.
1999-2013 Microchip Technology Inc. DS41120C-page 9
PIC16C717/770/771
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these PIC®
microcontrollers. Each block (Program Memory and
Data Memory) has its own bus, so that concurrent
access can occur.
Addit ional informat ion on devi ce memory may be found
in the PICmicro Mid-Range MCU Family Reference
Manual, (DS33023).
2.1 Program Memory Organization
The PIC16C717/770/771 devices have a 13-bit pro-
gram counter capable of addressing an 8K x 14 pro-
gram memory space. The PIC16C717 and the
PIC16C770 have 2K x 14 words of program memory.
The PIC16C771 has 4K x 14 words of program mem-
ory. Accessing a location above the physically imple-
mented address will cause a wrap-around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK OF THE
PIC16C717 AND PIC16C770
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK OF THE
PIC16C771
2.2 Data Memory Organization
The data memory is partitioned into multiple banks,
whic h contain th e General Pu rpose Re gisters a nd the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00 Bank0
= 01 Bank1
= 10 Bank2
= 11 Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some frequently used special func-
tion registers from one bank are mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The registe r file can be accesse d either dire ctly , or ind i-
rectly, through the File Select Register FSR.
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Program
Memory Page 0 07FFh
3FFFh
RP1 RP0 (STATUS<6:5>)
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
3FFFh
PIC16C717/770/771
DS41120C-page 10 1999-2013 Microchip Technology Inc.
FIGURE 2-3: REGISTER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Indirect addr.(*)
ADRESL
PIR2 PIE2
ADRESH
ADCON0 ADCON1
General
Purpose
Register
General
Purpose
Register
EFh
F0h
accesses
70h-7Fh
96 Bytes
80 Bytes
LVDCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
17Fh
Bank 2
16Fh
170h
File
Address
PCL
STATUS
FSR
PCLATH
INTCON
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
1FFh
Bank 3
Indirect addr.(*)
OPTION_REG
1EFh
1F0h
accesses
70h - 7Fh
TRISB
PCL
STATUS
FSR
PCLATH
INTCON
Indirect addr.(*)
TMR0
General
Purpose
Register
accesses
70h - 7Fh
PORTB
80 Bytes
File
Address
File
Address
File
Address
REFCON
SSPCON2
WPUB
IOCB
ANSEL
P1DEL
PMDATL
PMADRL
PMDATH
PMADRH
PMCON1
1999-2013 Microchip Technology Inc. DS41120C-page 11
PIC16C717/770/771
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The spec ial function regi sters can be clas sified into two
sets ; core (CPU) and pe riphera l. Thos e regis ters a sso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Bank 0
00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
01h TMR0 Timer0 module’s register xxxx xxxx 45
02h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
03h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
04h(3) FSR Indirect data memory address pointer xxxx xxxx 23
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 25
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xx11 33
07h —Unimplemented — —
08h —Unimplemented — —
09h —Unimplemented — —
0Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
0Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
0Ch PIR1 —ADIF—— SSPIF CCP1IF TMR2IF TMR1IF -0---0000 18
0Dh PIR2 LVDIF — — —BCLIF— — — 0--- 0--- 20
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx 47
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx 47
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 47
11h TMR2 Timer2 module’s reg ister 0000 0000 51
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 51
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 70
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 67
15h CC PR1L Capture/Co mpare/PWM Register1 (LSB) xxxx xxxx 54
16h CC PR1H Capture/C ompare/PWM Register1 (MSB) xxxx xxxx 54
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53
18h —Unimplemented — —
19h —Unimplemented — —
1Ah —Unimplemented — —
1Bh —Unimplemented — —
1Ch —Unimplemented — —
1Dh —Unimplemented — —
1Eh ADRESH A/D High Byte Result Register xxxx xxxx 107
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 107
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
PIC16C717/770/771
DS41120C-page 12 1999-2013 Microchip Technology Inc.
Bank 1
80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15
82h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
83h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
84h(3) FSR Indirect data memory address pointer xxxx xxxx 23
85h TRISA PORTA Data Direction Register 1111 1111 25
86h TRISB POR TB Data Direction Register 1111 1111 33
87h —Unimplemented — —
88h —Unimplemented — —
89h —Unimplemented — —
8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
8Ch PIE1 —ADIE—— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 17
8Dh PIE2 LVDIE — — —BCLIE— — — 0--- 0--- 19
8Eh PCON — — — —OSCF—PORBOR ---- 1-qq 21
8Fh —Unimplemented — —
90h —Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 69
92h PR2 Timer2 Period Register 1111 1111 52
93h SSPADD Synch ro no us Serial Port (I2C mode) Address Regist er 0000 0000 76
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 66
95h WPUB PORTB Weak Pull-up Control 1111 1111 34
96h IOCB PORTB Interr upt on C han ge Contro l 1111 0000 34
97h P1DEL PWM 1 Delay value 0000 0000 62
98h —Unimplemented — —
99h —Unimplemented — —
9Ah —Unimplemented — —
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 102
9Ch LVDCON —— BGST LVDEN LVV3 LVV2 LVV1 LVV0 --00 0101 101
9Dh ANSEL — — Analog Channel Select --11 1111 25
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx 107
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 107
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
1999-2013 Microchip Technology Inc. DS41120C-page 13
PIC16C717/770/771
Bank 2
100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
101h TMR0 Timer0 module’s register xxxx xxxx 45
102h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
103h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
104h(3) FSR Indirect data memory address pointer xxxx xxxx 23
105h —Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx11 33
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
10Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
10Ch PMDATL Program memory read data low xxxx xxxx
10Dh PMADRL Program memory read address low xxxx xxxx
10Eh PMDATH —— Program memory read data high --xx xxxx
10Fh PMADRH — — — — Program memory read address high ---- xxxx
110h-
11Fh —Unimplemented — —
Bank 3
180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 15
182h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 22
183h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 14
184h(3) FSR Indirect data memory address pointer xxxx xxxx 23
185h —Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 33
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 22
18Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 16
18Ch PMCON1 Reserved — — — — — —RD1--- ---0
18Dh-
18Fh —Unimplemented — —
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the pro gram counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
PIC16C717/770/771
DS41120C-page 14 1999-2013 Microchip Technology Inc.
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the ar ithmetic st atus of th e ALU, the RESET st atus and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set t he Z bit. T his leav es the STA T US regist er
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affe ct the Z, C or D C bits from th e ST ATUS register. For
other instructions not affecting any status bits, see the
"Instruction Set Summary."
REGISTER 2-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Regist er Bank Select bit (used for indire ct add ressing)
1 = Bank 2, 3 ( 100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instru cti on
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF in st ruct ion s) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 15
PIC16C717/770/771
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register, which cont ains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able re gister known a lso as the pres caler), t he Ext ernal
INT Int errupt, T MR0 and the w eak pul l-up s on POR TB.
REGISTER 2-2: OPTION REGISTER (OPTION_REG: 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit(1)
1 = PORTB weak pull-ups are disabled
0 = PORTB weak pull-ups are enabled by the WPUB register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit
1 = Transition on RA4/T0 CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: Individua l w ea k pul l-u p on R B pin s ca n be enab led/disable d from the w ea k pu ll-u p
PORTB Register (WPUB).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C717/770/771
DS41120C-page 16 1999-2013 Microchip Technology Inc.
2.2.2.3 INTCON REGISTER
The INTCO N Register is a read able and writ able regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interru pt fla g bit s get se t when an in terru pt
conditi on occ urs , re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all int erru pts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR 0 interr upt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit(1)
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 regist er has overfl owed (must be clear ed in softw are)
0 = TMR0 reg i ster did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cl eared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB<7:0> pins changed state (must be cleared in software)
0 = None of the RB<7:0> pins have changed state
Note 1: Individual RB pin interrupt-on-change can be enabled/disabled from the
Interrupt-on-Change PORTB register (IOCB).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS41120C-page 17
PIC16C717/770/771
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1: 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE—— SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 Unimplemented: Read as ’0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D inte rru pt
bit 5-4 Unimplemented: Read as ’0’
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP inte rru pt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrup t
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown
PIC16C717/770/771
DS41120C-page 18 1999-2013 Microchip Technology Inc.
2.2.2.5 PIR1 REGISTE R
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5: PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch)
Note: Interru pt fla g bit s get se t when an in terru pt
conditi on occ urs , re gardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIF—— SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’.
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ’0’
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interru pt condition ha s occurred, and must be c leared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI A transmission/reception has taken place.
I2 C Slave / Master
A transmission/reception has taken place.
I2 C Master
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was IDLE (Multi-master system).
A STOP condition occurred while the SSP module was IDLE (Multi-master system).
0 = No SSP interrupt condition has occurred.
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR 1 register capture occurred (must be cleared in softw are)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 reg i ster did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown