ADS1231IDR - Texas Instruments - Datasheet.Directory

24-Bit

ADCDS

VREFP VREFN

CAP DVDD

GND

AINP

AINN SCLK

SPEED

DRDY/DOUT

PDWN

AVDD

Internal

Oscillator

G=128

CAP

CLKIN

EMI

Filter

ADS1231

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SBAS414C –JULY 2009–REVISED DECEMBER 2010

24-Bit Analog-to-Digital Converter

for Bridge Sensors

1FEATURES DESCRIPTION

2• Complete Front-End for Bridge Sensors The ADS1231 is a precision, 24-bit analog-to-digital

converter (ADC). With an onboard low-noise

• Internal Amplifier, Gain of 128 amplifier, onboard oscillator, precision third-order

• Internal Oscillator 24-bit delta-sigma (ΔΣ) modulator, and bridge power

• Low-Side Power Switch for Bridge Sensor switch, the ADS1231 provides a complete front-end

• Low Noise: 35nVrms solution for bridge sensor applications including

weigh scales, strain gauges, and load cells.

• Selectable Data Rates: 10SPS or 80SPS The low-noise amplifier has a gain of 128, supporting

• Simultaneous 50Hz and 60Hz Rejection at a full-scale differential input of ±19.5mV. The ΔΣ ADC

10SPS has 24-bit resolution and is comprised of a third-order

• Input EMI Filter modulator and fourth-order digital filter. Two data

• External Voltage Reference up to 5V for rates are supported: 10SPS (with both 50Hz and

Ratiometric Measurements 60Hz rejection) and 80SPS. The ADS1231 can be

put in a low-power standby mode or shut off

• Simple, Pin-Driven Control completely in power-down mode.

• Two-Wire Serial Digital Interface The ADS1231 is controlled by dedicated pins; there

• Supply Range: 3V to 5.3V are no digital registers to program. Data are output

• Package: SOIC-16 over an easily-isolated serial interface that connects

• Temperature Range: –40°C to +85°C directly to the MSP430 and other microcontrollers.

The ADS1231 is available in an SO-16 package and

APPLICATIONS is specified from –40°C to +85°C.

• Weigh Scales

• Strain Gauges

• Load Cells

• Industrial Process Control

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS1231

SBAS414C –JULY 2009–REVISED DECEMBER 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or visit the device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range, unless otherwise noted. ADS1231 UNIT

AVDD to GND –0.3 to +6 V

DVDD to GND –0.3 to +6 V

100, momentary mA

Input current 10, continuous mA

Analog input voltage to GND –0.3 to AVDD + 0.3 V

Digital input voltage to GND –0.3 to DVDD + 0.3 V

Human body model (HBM) ±2000 V

JEDEC standard 22, test method A114-C.01, all pins

ESD(2) Charged device model (CDM) ±500 V

JEDEC standard 22, test method C101, all pins

Maximum junction temperature +150 °C

Operating temperature range –40 to +85 °C

Storage temperature range –60 to +150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) CAUTION: ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

THERMAL INFORMATION ADS1231

THERMAL METRIC(1) SOIC (D) UNITS

16 PINS

qJA Junction-to-ambient thermal resistance 79.5

qJCtop Junction-to-case (top) thermal resistance 37.5

qJB Junction-to-board thermal resistance 37.1 °C/W

yJT Junction-to-top characterization parameter 5.6

yJB Junction-to-board characterization parameter 36.7

qJCbot Junction-to-case (bottom) thermal resistance n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

ADS1231

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SBAS414C –JULY 2009–REVISED DECEMBER 2010

ELECTRICAL CHARACTERISTICS

Minimum/maximum limit specifications apply from –40°C to +85°C. Typical specifications at +25°C.

All specifications at AVDD = DVDD = VREFP = +5V, VCM = 2.5V and VREFN = GND, unless otherwise noted.

ADS1231

PARAMETER CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

±0.5VREF/128 V

Full-scale input voltage (AINP – AINN) VREF = AVDD = 5V ±19.5 mV

VREF = AVDD = 3V ±11.7 mV

Common-mode input range GND + 1.5 AVDD – 1.5 V

Differential input current ±2 nA

LOW-SIDE POWER SWITCH

AVDD = 5V, ISW = 30mA 3.5 5 Ω

On-resistance (RON)AVDD = 3V, ISW = 30mA 4 7 Ω

Current through switch 30 mA

SYSTEM PERFORMANCE

Resolution No missing codes 24 Bits

Internal oscillator, SPEED = high 80 SPS

Internal oscillator, SPEED = low 10 SPS

Data rate External oscillator, SPEED = high fCLK/61, 440 SPS

External oscillator, SPEED = low fCLK/491, 520 SPS

Digital filter settling time Full settling 4 Conversions

Integral nonlinearity (INL) Differential input, end-point fit ±8 ppm

Input offset error 10 mV

Input offset drift ±20 nV/°C

Gain error 1 %

Gain drift ±2 ppm/°C

fIN = 50Hz or 60Hz ±1Hz, fDATA = 10SPS, 80 100 dB

internal oscillator

Normal-mode rejection(1) fIN = 50Hz or 60Hz ±1Hz, fDATA = 10SPS, 90 110 dB

external oscillator(2)

Common-mode rejection At dc 110 dB

fDATA = 10SPS, AVDD = VREF = 5V 35 nV, rms

fDATA = 80SPS, AVDD = VREF = 5V 102 nV, rms

Noise fDATA = 10SPS, AVDD = VREF = 5V 232 nV, P-P

fDATA = 80SPS, AVDD = VREF = 5V 622 nV, P-P

Power-supply rejection At dc 90 100 dB

VOLTAGE REFERENCE INPUT

Voltage reference input (VREF) VREF = VREFP – VREFN 1.5 AVDD AVDD + 0.1 V

Negative reference input (VREFN) AGND – 0.1 VREFP – 1.5 V

Positive reference input (VREFP) VREFN + 1.5 AVDD + 0.1 V

Voltage reference input current 10 nA

DIGITAL INPUT/OUTPUT (DVDD = 3V to 5.3V)

VIH 0.8 DVDD DVDD + 0.1 V

VIL GND 0.2 DVDD V

Logic levels VOH IOH = 500mA DVDD – 0.4 V

VOL IOL = 500mA 0.2 DVDD V

Input leakage 0 < VDIGITAL INPUT < DVDD ±10 mA

Serial clock input frequency (fSCLK) 5 MHz

(1) Specification is assured by the combination of design and final test.

(2) External oscillator = 4.9152MHz.

ADS1231

SBAS414C –JULY 2009–REVISED DECEMBER 2010

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum limit specifications apply from –40°C to +85°C. Typical specifications at +25°C.

All specifications at AVDD = DVDD = VREFP = +5V, VCM = 2.5V and VREFN = GND, unless otherwise noted.

ADS1231

PARAMETER CONDITIONS MIN TYP MAX UNIT

POWER SUPPLY

Power-supply voltage (AVDD, DVDD) 3 5.3 V

Normal mode, AVDD = 3V 900 mA

Normal mode, AVDD = 5V 900 mA

Analog supply current Standby mode 0.1 mA

Power-down 0.1 mA

Normal mode, DVDD = 3V 60 mA

Normal mode, DVDD = 5V 95 mA

Digital supply current Standby mode, SCLK = high, DVDD = 3V 45 mA

Standby mode, SCLK = high, DVDD = 5V 65 mA

Power-down 0.2 mA

Normal mode, AVDD = DVDD = 3V 2.9 mW

Power dissipation, total Normal mode, AVDD = DVDD = 5V 5 mW

TEMPERATURE

Operating temperature range –40 +85 °C

Specified temperature range –40 +85 °C

DVDD

GND

CLKIN

SPEED

CAP

AINP

AINN

DRDY/DOUT

SCLK

PDWN

AVDD

PSW

GND

VREFP

VREFN

ADS1231

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SBAS414C –JULY 2009–REVISED DECEMBER 2010

PIN CONFIGURATION

D PACKAGE

SO-16

(TOP VIEW)

PIN DESCRIPTIONS

ANALOG/DIGITAL

NAME TERMINAL INPUT/OUTPUT DESCRIPTION

DVDD 1 Digital Digital power supply

GND 2 Supply Ground for digital and analog supplies

CLKIN 3 Digital input External clock input: typically 4.9152MHz. Tie low to activate internal oscillator.

Data rate select:

SPEED DATA RATE

SPEED 4 Digital input 0 10SPS

1 80SPS

CAP 5 Analog Gain amplifier bypass capacitor connection

CAP 6 Analog Gain amplifier bypass capacitor connection

AINP 7 Analog input Positive analog input

AINN 8 Analog input Negative analog input

VREFN 9 Analog input Negative reference input

VREFP 10 Analog input Positive reference input

GND 11 Supply Ground for digital and analog supplies

PSW 12 Analog Low-side power switch

AVDD 13 Supply Analog power supply

PDWN 14 Digital input Power-down: holding this pin low powers down the entire converter and resets the ADC.

Serial clock: clock out data on the rising edge. Also used to initiate Standby mode. See the Standby

SCLK 15 Digital input Mode section for more details.

Dual-purpose output:

DRDY/DOUT 16 Digital output Data ready: indicates valid data by going low.

Data output: outputs data, MSB first, on the first rising edge of SCLK.

ADS1231

SBAS414C –JULY 2009–REVISED DECEMBER 2010

www.ti.com

NOISE PERFORMANCE

The ADS1231 offers outstanding noise performance. Table 1 summarizes the typical noise performance with

inputs shorted externally for different data rates and voltage reference values.

The RMS and Peak-to-Peak noise are referred to the input. The effective number of bits (ENOB) is defined as:

ENOB = ln (FSR/RMS noise)/ln(2)

The Noise-Free Bits are defined as:

Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2)

Where:

FSR (Full-Scale Range) = VREF/Gain.

Table 1. Noise Performance

AVDD and VREF RMS NOISE(1) PEAK-TO-PEAK NOISE(1) ENOB

DATA RATE (V) (nV) (nV) (RMS) NOISE-FREE BITS

5 35.2 231.9 20.1 17.4

10 3 33.5 199.2 19.4 16.8

5 102.1 622.1 18.5 15.9

80 3 80.3 549.6 18.2 15.4

(1) Noise specifications are based on direct measurement of 1024 consecutive samples.

−300

−250

−200

−150

−100

−50

100

150

200

250

300

0 200 400 600 800 1000

Time (Reading Number)

Conversion Data (nV)

Data Rate = 10SPS

−300

−250

−200

−150

−100

−50

100

150

200

250

300

0 200 400 600 800 1000

Time (Reading Number)

Conversion Data (nV)

Data Rate = 80SPS

−40−35−30−25−20−15−10−5 0 5 10 15 20 25 30 35 40

100

150

200

250

300

350

400

450

500

−40−35−30−25−20−15−10−5 0 5 10 15 20 25 30 35 40

24−bit LSBs

# of Occurrences

Data Rate = 10SPS

−40−35−30−25−20−15−10−5 0 5 10 15 20 25 30 35 40

100

125

150

175

200

225

250

−40−35−30−25−20−15−10−5 0 5 10 15 20 25 30 35 40

24−bit LSBs

# of Occurrences

Data Rate = 80SPS

100

125

150

−20 −15 −10 −5 0 5 10 15 20

Input Voltage (mV)

RMS Noise (nV)

Data Rate = 10SPS

100

125

150

−20 −15 −10 −5 0 5 10 15 20

Input Voltage (mV)

RMS Noise (nV)

Data Rate = 80SPS

ADS1231

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SBAS414C –JULY 2009–REVISED DECEMBER 2010

TYPICAL CHARACTERISTICS

At TA= +25°C, AVDD = DVDD = REFP = 5V, REFN = AGND, and VCM = 2.5V unless otherwise noted.

NOISE vs TIME NOISE vs TIME

Figure 1. Figure 2.

NOISE HISTOGRAM NOISE HISTOGRAM

Figure 3. Figure 4.

NOISE vs SIGNAL NOISE vs SIGNAL

Figure 5. Figure 6.

2000

1500

1000

500

1000

1500

2000

85603522.510-2.5-40

Offset(nV)

Temperature( C)°

-15-27.5 72.547.5

0.02

0.015

0.01

0.005

0.01

0.015

0.02

85603522.510-2.5-40

GainError(%)

Temperature( C)°

-15-27.5 72.547.5

201050-5-20

IntegralNonlinearity(ppm)

V (mV)

-10-15 15

- °20 C

-40 C°

+25 C°

+70 C°

9.8

9.85

9.9

9.95

10.05

10.1

10.15

10.2

−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85

Temperature (°C)

Data Rate (SPS)

Data Rate = 10SPS

1200

1000

800

600

400

200

85603522.510-2.5-40

AnalogCurrent( A)m

Temperature( C)°

-15-27.5 72.547.5

120

115

110

105

100

85603522.510-2.5-40

DigitalCurrent( A)m

Temperature( C)°

-15-27.5 72.547.5

ADS1231

SBAS414C –JULY 2009–REVISED DECEMBER 2010

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TYPICAL CHARACTERISTICS (continued)

At TA= +25°C, AVDD = DVDD = REFP = 5V, REFN = AGND, and VCM = 2.5V unless otherwise noted.

OFFSET DRIFT vs TEMPERATURE GAIN ERROR vs TEMPERATURE

Figure 7. Figure 8.

INL vs INPUT SIGNAL DATA RATE vs TEMPERATURE

Figure 9. Figure 10.

ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE

Figure 11. Figure 12.

RINT

RF1

R1RF2

ADC

Gain=1

CAP

AINP

CAP

AINN

EMI

Filter

EMI

Filter

ADS1231

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SBAS414C –JULY 2009–REVISED DECEMBER 2010

OVERVIEW

The ADS1231 is a precision, 24-bit ADC that includes

a low-noise PGA, internal oscillator, third-order

delta-sigma (ΔΣ) modulator, and fourth-order digital

filter. The ADS1231 provides a complete front-end

solution for bridge sensor applications such as weigh

scales, strain gauges, and pressure sensors.

Data can be output at 10SPS for excellent 50Hz and

60Hz rejection, or at 80SPS when higher speeds are

needed. The ADS1231 is easy to configure, and all

digital control is accomplished through dedicated

pins; there are no registers to program. A simple

two-wire serial interface retrieves the data.

ANALOG INPUTS (AINP, AINN)

The input signal to be measured is applied to the

input pins AINP and AINN. The ADS1231 accepts

differential input signals, but can also measure Figure 13. Simplified Diagram of the Amplifier

unipolar signals.

LOW-NOISE AMPLIFIER External Capacitor

The ADS1231 features a low-drift, low-noise amplifier An external capacitor (CEXT) across the two ADS1231

that provides a complete front-end solution for bridge CAP pins combines with the internal resistor RINT

sensors. A simplified diagram of the amplifier is (on-chip) to create a low-pass filter. The

shown in Figure 13. It consists of two recommended value for CEXT is 0.1mF which provides

chopper-stabilized amplifiers (A1 and A2) and three a corner frequency of 720Hz. This low-pass filter

accurately matched resistors (R1, RF1, and RF2) that serves two purposes. First, the input signal is

construct a differential front-end stage with a gain of bandlimited to prevent aliasing by the ADC and to

128, followed by gain stage A3 (Gain = 1). The inputs filter out the high-frequency noise. Second, it

are equipped with an EMI filter, as shown in attenuates the chopping residue from the amplifier to

Figure 13. The cutoff frequency of the EMI filter is improve temperature drift performance. NPO or C0G

20MHz. By using AVDD as the reference input, the capacitors are recommended. For optimal

bipolar input ranges from –19.5mV to +19.5mV. The performance, place the external capacitor very close

inputs of the ADS1231 are protected with internal to the CAP pins.

diodes connected to the power-supply rails. These

diodes clamp the applied signal to prevent it from

damaging the input circuitry.

Z =500MW

EFF

AVDD

Z =500MW

EFF

VREFP VREFN

AVDD

ESD

Protection

CBUF

Bridge

Sensor

+VDD

AINP

AINN

VREFN

GND

ADS1231

VREFP

ADS1231

SBAS414C –JULY 2009–REVISED DECEMBER 2010

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VOLTAGE REFERENCE INPUTS LOW-SIDE POWER SWITCH (SW)

(VREFP, VREFN) The ADS1231 incorporates an internal switch for use

The voltage reference used by the modulator is with an external bridge sensor, as shown in

generated from the voltage difference between Figure 15. The switch can be used in a return path for

VREFP and VREFN: VREF = VREFP – VREFN. The the bridge power. By opening the switch, power

reference inputs use a structure similar to that of the dissipation in the bridge is eliminated.

analog inputs. In order to increase the reference input The switch is controlled by the ADS1231 conversion

impedance, switching buffer circuitry is used to status. During normal conversions, the switch is

reduce the input equivalent capacitance. The closed (the SW pin is connected to GND). During

reference drift and noise impact ADC performance. In standby or power-down modes, the switch is opened

order to achieve best results, pay close attention to (the SW pin is high impedance). When using the

the reference noise and drift specifications. A switch, it is recommended that the negative reference

simplified diagram of the circuitry on the reference input (VREFN) be connected directly to the bridge

inputs is shown in Figure 14. The switches and ground terminal, as shown in Figure 15 for best

capacitors can be modeled approximately using an performance.

effective impedance of:

Figure 14. Simplified Reference Input Circuitry

ESD diodes protect the reference inputs. To prevent

these diodes from turning on, make sure the voltages Figure 15. Low-Side Power Switch

on the reference pins do not go below GND by more

than 100mV, and likewise, do not exceed AVDD by

100mV: CLOCK SOURCE

GND – 100mV < (VREFP or VREFN) < AVDD + The ADS1231 uses an internal oscillator. No external

100mV clock circuitry is required.

Frequency(Hz)

Gain(dB)

-50

-100

-150

0 10 20 30 40 50 60 70 80 90 100

(a)

Frequency(Hz)

(b)

Gain(dB)

-50

-100

-150

494846 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

DataRate=10SPS

ADS1231

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SBAS414C –JULY 2009–REVISED DECEMBER 2010

FREQUENCY RESPONSE

The ADS1231 uses a sinc4digital filter with the

frequency response. The frequency response repeats

at multiples of the modulator sampling frequency of

76.8kHz. The overall response is that of a low-pass

filter with a –3dB cutoff frequency of 3.32Hz with the

SPEED pin tied low (10SPS data rate) and 11.64Hz

with the SPEED pin tied high (80SPS data rate).

To help see the response at lower frequencies,

Figure 16(a) illustrates the nominal response out to

100Hz, when the data rate = 10SPS. Notice that

signals at multiples of 10Hz are rejected, and

therefore simultaneous rejection of 50Hz and 60Hz is

achieved.

The benefit of using a sinc4filter is that every

frequency notch has four zeros on the same location.

This response, combined with the low drift internal

oscillator, provides an excellent normal-mode

rejection of line-cycle interference.

Figure 16(b) zooms in on the 50Hz and 60Hz notches

with the SPEED pin tied low (10SPS data rate).

Figure 16. Nominal Frequency Response Out To

100Hz

AbruptChangeinExternalVIN

VIN

DRDY/DOUT

Startof

Conversion

including

unsettledV .

1stConversion;

V settled,but

digitalfilter

unsettled.

2ndConversion;

V settled,but

digitalfilter

unsettled.

3rdConversion;

V settled,but

digitalfilter

unsettled.

4thConversion;

V settled,but

digitalfilter

unsettled.

Conversion

Time

ADS1231

SBAS414C –JULY 2009–REVISED DECEMBER 2010

www.ti.com

Table 2. Data Rate Settings

SETTLING TIME

SPEED PIN DATA RATE

Fast changes in the input signal require time to settle. 0 10SPS

For example, an external multiplexer in front of the

ADS1231 can generate abrupt changes in input 1 80SPS

voltage by simply switching the multiplexer input

channels. These sorts of changes in the input require DATA FORMAT

four data conversion cycles to settle. When The ADS1231 outputs 24 bits of data in binary twos

continuously converting, five readings may be complement format. The least significant bit (LSB)

necessary in order to settle the data. If the change in has a weight of (0.5VREF/128)(223 – 1). The positive

input occurs in the middle of the first conversion, four full-scale input produces an output code of 7FFFFFh

more full conversions of the fully-settled input are and the negative full-scale input produces an output

required to obtain fully-settled data. Discard the first code of 800000h. The output clips at these codes for

four readings because they contain only signals exceeding full-scale. Table 3 summarizes the

partially-settled data. Figure 17 illustrates the settling ideal output codes for different input signals.

time for the ADS1231.

Table 3. Ideal Output Code vs Input Signal

DATA RATE

INPUT SIGNAL VIN

The ADS1231 data rate is set by the SPEED pin, as (AINP – AINN) IDEAL OUTPUT

shown in Table 2. When SPEED is low, the data rate ≥+0.5VREF/128 7FFFFFh

is nominally 10SPS. This data rate provides the 000001h

(+0.5VREF/128)/(223 – 1)

lowest noise, and also has excellent rejection of both 0 000000h

50Hz and 60Hz line-cycle interference. For

applications requiring fast data rates, setting SPEED FFFFFFh

(–0.5VREF/128)/(223 – 1)

high selects a data rate of nominally 80SPS. ≤–0.5VREF/128 800000h

1. Excludes effects of noise, INL, offset, and gain

errors.

Figure 17. Settling Time in Continuous Conversion Mode

DRDY/DOUT 23 22 21

1 24

LSBMSB

Data

DataReady

SCLK

tDS

tCONV

tSCLK

tPD

NewDataReady

tSCLK

tHT

tUPDATE

ADS1231

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SBAS414C –JULY 2009–REVISED DECEMBER 2010

DATA READY/DATA OUTPUT (DRDY/DOUT) DATA RETRIEVAL

This digital output pin serves two purposes. First, it The ADS1231 continuously converts the analog input

indicates when new data are ready by going low. signal. To retrieve data, wait until DRDY/DOUT goes

Afterwards, on the first rising edge of SCLK, the low, as shown in Figure 18. After DRDY/DOUT goes

DRDY/DOUT pin changes function and begins low, begin shifting out the data by applying SCLKs.

outputting the conversion data, most significant bit Data are shifted out MSB first. It is not required to

(MSB) first. Data are shifted out on each subsequent shift out all 24 bits of data, but the data must be

SCLK rising edge. After all 24 bits have been retrieved before new data are updated (within tCONV)

retrieved, the pin can be forced high with an or else the data will be overwritten. Avoid data

additional SCLK. It then stays high until new data are retrieval during the update period (tUPDATE). If only 24

ready. This configuration is useful when polling on the SCLKs have been applied, DRDY/DOUT remains at

status of DRDY/DOUT to determine when to begin the state of the last bit shifted out until it is taken high

data retrieval. (see tUPDATE), indicating that new data are being

updated. To avoid having DRDY/DOUT remain in the

state of the last bit, the 25th SCLK can be applied to

SERIAL CLOCK INPUT (SCLK) force DRDY/DOUT high, as shown in Figure 19. This

This digital input shifts serial data out with each rising technique is useful when a host controlling the device

edge. This input has built-in hysteresis, but care is polling DRDY/DOUT to determine when data are

should still be taken to ensure a clean signal. Glitches ready.

or slow-rising signals can cause unwanted additional

shifting. For this reason, it is best to make sure the

rise and fall times of SCLK are both less than 50ns.

Figure 18. 24-Bit Data Retrieval Timing

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tDS DRDY/DOUT low to first SCLK rising edge 0 ns

tSCLK SCLK positive or negative pulse width 100 ns

tPD (1) SCLK rising edge to new data bit valid: propagation delay 50 ns

tHT (1) SCLK rising edge to old data bit valid: hold time 20 ns

tUPDATE Data updating: no readback allowed 90 ms

SPEED = 1 12.5 ms

tCONV Conversion time (1/data rate) SPEED = 0 100 ms

(1) Minimum required from simulation.

1 24 25

22 21 0

Data

25thSCLKtoForce /DOUTHighDRDY

DataReady NewDataReady

DRDY/DOUT

SCLK

DRDY/DOUT 23 22 21

1 24

0 23

SCLK

StandbyMode DataReady

tDSS tSTANDBY tS_RDY

StartConversion

ADS1231

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STANDBY MODE When tSTANDBY has passed with SCLK held high,

Standby mode activates. DRDY/DOUT stays high

Standby mode dramatically reduces power when Standby mode begins. SCLK must remain high

consumption by shutting down most of the circuitry. to stay in Standby mode. To exit Standby mode

To enter Standby mode, simply hold SCLK high after (wakeup), set SCLK low. The first data after exiting

DRDY/DOUT goes low; see Figure 20. Standby mode Standby mode are valid.

can be initiated at any time during readback; it is not

necessary to retrieve all 24 bits of data beforehand.

Figure 19. Data Retrieval with DRDY/DOUT Forced High Afterwards

Figure 20. Standby Mode Timing (Can be used for single conversions)

SYMBOL DESCRIPTION MIN TYP MAX UNITS

SCLK high after DRDY/DOUT SPEED = 1 12.44 ms

tDSS (1) goes low to activate Standby SPEED = 0 99.94 ms

mode SPEED = 1 12.5 ms

tSTANDBY Standby mode activation time SPEED = 0 100 ms

SPEED = 1 52.6 ms

Data ready after exiting Standby

tS_RDY (1) mode SPEED = 0 401.8 ms

(1) Based on an ideal internal oscillator.

AVDD

DVDD

PDWN

³ m10 s

DataReady

Start

Conversion

DRDY/DOUT

SCLK

CLKSource

Wakeup

Power-DownMode

PDWN

tWAKEUP tTS_RDY

tPDWN

ADS1231

www.ti.com

SBAS414C –JULY 2009–REVISED DECEMBER 2010

POWER-DOWN MODE

Power-Down mode shuts down the entire ADC

circuitry and reduces the total power consumption

close to zero. To enter Power-Down mode, simply

hold the PDWN pin low. Power-Down mode also

resets the entire circuitry. Power-Down mode can be

initiated at any time during readback; it is not

necessary to retrieve all 24 bits of data beforehand. Figure 21. Power-Up Timing Sequence

Figure 22 shows the wake-up timing from

Power-Down mode.

Figure 22. Wake-Up Timing from Power-Down Mode

SYMBOL DESCRIPTION MIN TYP UNITS

tWAKEUP(1)(2) Wake-up time after Power-Down mode 7.95 ms

tPDWN(1) PDWN pulse width 26 ms

(1) Based on an ideal internal oscillator.

(2) Typical required from simulation.

ADS1231

VREFP

CAP

AINP

AINN

AVDD DVDD

GND

DRDY/DOUT

SCLK

PDWN

SPEED

1 Fm(1)

0.1 Fm(2)

2,3,11

12 1

MSP430x4xx

VDD

GND

3Vto5.3V 3V

1 Fm(1)

VREFN

Load

Cell

ADS1231

SBAS414C –JULY 2009–REVISED DECEMBER 2010

www.ti.com

APPLICATION EXAMPLE

Weigh Scale System

Figure 23 shows a typical ADS1231 application as part of a weigh scale system.

(1) Place a 0.1mF or higher capacitor as close as possible on both AVDD and DVDD.

(2) Place capacitor very close to the ADS1231 CAP pins for optimal performance.

Figure 23. Weigh Scale Example

PACKAGE OPTION ADDENDUM

www.ti.com 10-Jan-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS1231ID ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples

ADS1231IDR ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS1231IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jan-2011

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS1231IDR SOIC D 16 2500 333.2 345.9 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jan-2011

Pack Materials-Page 2

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