MXT3020-C - Maker Communications, Inc.

MXT3020

reference manual

version 4.0

Order Number: 100107-04

Revision C of the MXT3020

July 1999

Printed in the United States of America.

The information in this document is believed to be correct, however, the

information can change without notice. Maker Communications, Inc. disclaims

any responsibility for any consequences resulting from the use of the information

contained in this document.

The hardware, software, and the related documentation is provided with

RESTRICTED RIGHTS. Use, duplication, or disclosure by the U.S. Government

is subject to restrictions as set forth in subparagraph (c)(1) (ii) of The Rights in

Technical Data and Computer Program Product clause at DFARS 252.227-7013

or subparagraphs (c)(1) and (2) of the Commercial Computer Software-

Restricted Rights at 48 CFR 52.227-19, as applicable.

Contractor/manufacturer is:

Maker Communications, Inc.

73 Mount Wayte Avenue, Framin gham, MA 01702

CellMaker and BridgeMaker are registered trad emarks of Maker

Communicat ions , In c. Acces s Maker, High -In te nsit y C ommu nicat ions Processor ,

High-Intensity Communications Processing, PortMaker, Octave, and SimMaker

are trademarks of Maker Communications, Inc.

All other trademarks are owned by their respective companies.

This manual supercedes and obsoletes the following Maker Communications

publication:

100107-03 - MXT3020 Reference Manual, dated July 1998

100350-01 - MXT3020 Reference Manual, errata sheet, Sept/Oct 1998

MXT3020 Reference Manual  Version 4.0 i
CONTENTS
Preface xi
Maker Products xii
Traffic Stream Processing Solutions xii
ATM Cell Processing Solutions xiii
Using this Manual xiv
Add itional Document Re ferences xiv
Organization of this  man ual xvii
CHAPTER 1 Device Overview 1
Circ uit Interface 4
The Data Mover (Scatter/Gather) Units 5
Scatter and Gather Memory Interfaces 6
Port2 Interface 7
CHAPTER 2 Circuit Interface 9
Circuit Interface registers 11
Per-Link registers 11
Global registers 11
Link Configuration register 12
Added detail: Bits 12-10 – clock source control 15
Added detail: Bit 6 – link pair mode 19
Added detail: BSCE pin 21
Link Buffer Address counters 23

ii  Versio n 4.0 MXT3020 Reference Manual
Link R x Buffer Address counter 23
Link Tx Buffer Address counter 24
Details of the Link Tx/Rx Buffer Address counters 25
Link Tri-state Control Address counter 27
An example of the tri-stat e cont rol pr o c ess 27
The tri- state enable control map 28
Summary of tri-stat e control operation 32
Link se rvice clock genera tion registers 33
Link Service Clock N register 34
Link Service Clock K register 35
Link Service Clock L count er 35
Link FTC counter 36
Link SRTS Value register 36
CI Tri-state C ontrol Base Address register 37
 CI Configuration register 37
MAXDS0, MAXTBS, and MAXRBS and buffer sizing 40
CI Quiet Frame Base Address register 42
Quiet L ogi c 43
CI SRTS FTC register 45
CI SRTS Valid Stat us register 45
CI Status register 46
Interface Pins 47
CHAPTER 3 Data Mover Units and Task Buffer 
RAMs 49
Lists and Task s 50
Activating the Data Mover Unit 51
Loadin g list blo cks 51
Loading the Task Buffer RAM 53
Data Mover Unit Instruction Set 54
Task Buffer Format 55
Channel Map Pointer 56
List Size 57
Fra m e N um ber 57
SAR Size 57
SAR Offset 57
Register 06 (write) - Addition al con trol bits 58
Register 06 (read) - Additional status bits 60
Data Mover Unit Registers 61

MXT3020 Reference Manual  Version 4. 0 iii
Channel Map Pointer (CMP) 62
Instructio n Poin ter (IP) 63
Frame Counter (FC) 63
Transfer Counter (TC) 63
CRC Function Code (FNC) 63
HSCT Control Flags 63
Instructio n Segme n t (ISEG) 64
Immediate (CONST) 64
Command (CMD) 64
Task T imer   (TKT) 65
Status (STA T) 65
MAPD and Fill 65
TT register 66
TVR register 66
CRC-10 [9:0] 66
Start of CRC-10 [5:0] 6 6
Address Generation 67
List Block Address Generation 67
List RAM Address Generation 6 7
Scatter/Gather Memory Address Generation 68
Task Buffer RAM Address Generation 71
Interface Pins 71
Examples of Scatter and Gather Operations 72
Scatter 72
Gather 73
Multicast 74
CHAPTER 4 Scatter and Gather Memory Interfaces 75
Scatter Memory Controller 76
 Gather Memory Controller 77
Determining Scatter and Gath er Memory requirements 78
Scatter Memory 78
Gather Memory 78
Interface Pins 79
CHAPTER 5 Port2 Interf ace 81
MXT3020 addressing 82
MXT3020 address space 83

iv  Version 4.0 MXT3020 Reference Manual
Interface Pins 86
CHAPTER 6 Register Reference 87
Channel Map Pointer (TBR and DMU) 89
CI Configuration register 90
CI Quiet Frame Base Address register 92
CI SRTS FTC register 93
CI SRTS Valid Status register 94
CI Status register 95
CI Tri-state C ontrol Base Address register 96
Command register 97
CRC-10 regis t er 98
Immediate and Control Flags register (TBR and DMU) 99
Instruction Pointer and Frame Counter 102
Link Configuration register 103
Link FTC counter 105
Link Rx Buffer Address counter 106
Link Service Clock K register 107
Link Se rvice Clock L counter 108
Link Service Clock N register 109
Link SRTS Value register 110
Link Tri-state Control Address counter 111
Link Tx Buffer Address counter 112
List Size and Frame Number 113
MAPD and FILL registers 114
SAR SDU registers 115
SAR Size and SAR Offset 116
TT and TVR registers 117
Status register 118
Task Timer register 119
Transfer Counter and Task Buffer Offset registers 120
CHAPTER 7 Interfacing Guidelines 123
Interfacing to Scatter/Gather Memory 124
Interfacing the MXT3020 to the MXT3010 126

MXT3020 Reference Manual  Version 4. 0 v
Port2 Burst and Non -Burst Operat ion 127
The DMA2 instructions 128
Multiple MXT3020 implementation 1 30
Device selection code example 132
Scatter/Gather Task Buffer Busy flags 134
Quad  MXT3020 layout cons id e r ations 135
Timing analysis of quad MXT3 020 on Port 2 136
PCB Design Concerns for quad MXT3020 137
Clock tree distribution 138
CHAPTER 8 Timing 139
MXT3020 ti ming - general informatio n 139
Definition of switching levels 139
Input clock details 140
Timing 141
Circ uit Interface 142
Port2 Interface timing 144
Scatter/Gather Memory Interface 149
Status Interface 153
SCSA Bus Timing 154
MVIP Bus Timing 157
MXT3020 As sistan ce to Non-burst Device s 158
MXT3020 reset timing 159
CHAPTER 9 Pin Information 161
MXT3020 pinout 162
MXT3020 si gnal descrip tions 163
JTA G /PLL Miscellaneous pin terminations 170
Pin Listing 171
CHAPTER 10 Electrical Parameters 177
MXT3020 maximum ratings and op eratin g conditions 178
DC electrica l characteristics 179
MXT3020 power sequencing 179
MXT3020 PLL conside ration s 180

vi  Version 4.0 MXT3020 Re ference Manual
Overview 180
VDD_PLLVCC decoupling 180
General decoupling 181
Reference clock jitter 182
CHAPTER 11 Mechanical and Thermal Information 185
MXT3020 mechanical/thermal information 186
Storage co nditions 187
APPENDIX A Acronyms 189
APPENDIX B Registered Decoder PAL Source Code 191

MXT3020 Reference Manual Version 4.0 vii
List of Figures
Figure 1  T1/E1/ATM Interface Using the MXT3010 and MXT3020 2
Figure 2  Block diagram of the MXT3020 3
Figure 3  Link Configuration register bit assignments 12
Figure 4  SRTS support hardware 14
Figure 5  Configuration Uni-1 17
Figure 6  Configuration Uni-2 17
Figure 7  Configuration Uni-3 18
Figure 8  Configuration Uni-4 18
Figure 9  Configuration Bi-1 18
Figure 10  Configuration Bi-2 19
Figure 11  Configuration Bi-3 19
Figure 12  MXT3020 operating modes - eight link pairs 20
Figure 13  MXT3020 operating modes - ASER and BSER 21
Figure 14  Tri-state enable for the ASER pins 28
Figure 15  ASER and BSER tri-state enable bit usage (bidirectional) 29
Figure 16  ASER and BSER tri-state enable bit usage (unidirectional) 31
Figure 17  Link service clock generation registers 33
Figure 18  Quiet Frame Allocation Map 44
Figure 19  Pre-Scatter/Gather Task Buffer Register Format 55
Figure 20  Post-Scatter/Gather Task Buffer Register Format 56
Figure 21  DMU register set organization 62
Figure 22  Creation of 19-Bit Address (Uni) When DS0 = 24 or 32 69
Figure 23  Creation of 19-Bit Address (Uni) When DS0 = 64 69
Figure 24  Creation of 19-Bit Address (Uni) When DS0 = 96 or 128 69
Figure 25  Creation of 19-Bit Address (Bi) When DS0 = 24 or 32 70
Figure 26  Creation of 19-Bit Address (Bi) When DS0 = 64 70
Figure 27  Creation of 19-Bit Address (Bi) When DS0 = 96 or 128 70
Figure 28  Example of a Scatter Operation 72
Figure 29  Example of a Gather Operation 73
Figure 30  Example of an Mcast Operation 74
Figure 31  MXT3020 address space 83
Figure 32  Scatter Data Mover Unit  Register Map 84
Figure 33  Gather Data Mover Unit  Register Map 84
Figure 34  Circuit Interface per-link registers 85
Figure 35  Circuit Interface global and SRTS value registers  86
Figure 36  Schematic of MXT3020C to Scatter/Gather Memories 124
Figure 37  MXT3020 to MXT3010 interconnection schematic 126
Figure 38  Diagram of Port2 burst DMA instruction bits 128
Figure 39  Diagram of Port2 non-burst DMA instruction bits 129
Figure 40  Sche matic of circuit for interfac i ng quad  MXT3020’s 131

viii Version 4.0 MXT3020 Refer ence Manual
Figure 41 Quad MXT3020 interconnect topology #1 135
Figure 42 Quad MXT3020 interconnect topology #2 135
Figure  43 Clock Distribution Circuit 138
Figure 44 Switching level voltages 139
Figure 45 Input clock waveform (pin FN) 1 40
Figure 46 Receive timing in unidirectional mode 143
Figure 47 Transmit timing in unidirectional mode 143
Figure 48 Receive/Transmit timing in bidirectional mode 143
Figure 49 Port2 burst write timing (1 halfword) 145
Figure 50 Port2 burst write timing (4 halfwords) 146
Figure 51 Port2 burst read timing (1 halfword) 147
Figure 52 Port2 burst read timing (2 halfwords) 148
Figure 53 Scatter/Gather Memory Halfword Write Timing 150
Figure 54 Scatter/Gather Memory Burst Write (Byte) Timing 151
Figure 55 Scatter/Gather Memory Burst Read (Byte/Halfword) Timing 152
Figure 56 Status interface timing 153
Figure 57 Computer telephony interface reference circuit 154
Figure 58 SCSA Bus Timing 155
Figure 59 SCSA Bus Timing  156
Figure 60 MVIP BUS Timing (2/4 MHz)  157
Figure 61 Timing for MXT3020 Assistance to Non-Burst Devices  158
Figure 62 MXT3020 Reset Timing  159
Figure 63 MXT3020 package/pin diagram 162
Figure 64 Ge nerat i ng a quie t VDD_PLLVCC 181
Figure 65 MXT3020 decoupling capacitor location 182
Figure 66 MXT3020 package/pin diagram - top view 186
Figure 67 MXT3020 package/pin diagram - side view 187

MXT3020 Reference Manual Version 4.0 ix
List of Tables
Table 1 Circuit Interface registers (for each link) 11
Table 2 Circuit Interface registers (global) 11
Table 3 Configurations for ACLK and BCLK 16
Table 4 MXT3020 link interface pins and signals 20
Table 5 Buffer size allocation 25
Table 6 Fram e Counte r / DS0 Counter 26
Table 7 Relation of buffer size to variable y 26
Table 8 Circuit Interface pins, per link 47
Table 9 Circuit Interface pins, common to all links 47
Table 10 Data Mover Unit Instructions 54
Table 11 Data Mover Unit Registers 61
Table 12 Relation of ISEG register to address ranges 64
Table 13 Data Mover Unit and Task Buffer RAM interface pins 71
Table 14 Scatter and Gather Memory Interface Pins 79
Table 15 Port2 Interface pins 86
Table 16 Scatter/Gather Memory control connections 125
Table 17 Port2 burst DMA instruction bit mapping 129
Table 18 Port2 non-burst DMA instruction bit mapping 129
Table 19 Scatter and Gather Task Buffer Busy flag wiring 134
Table 20 Synopsis of MXT3020 and MXT3010 timing requirements 136
Table 21 Simulated interconnect delay 136
Table 22 Input clock timing parameters (in nanoseconds) 140
Table 23 Circuit Interface timing 142
Table 24 Port2 Interface timing 144
Table 25 Scatter/Gather Memory Interface Timing Table 149
Table 26 Status interface timing table 153
Table 27 MXT3020 SCSA Bus Timing (2/4 MHz) 155
Table 28 MXT3020 SCSA Bus Timing (8 MHz) 156
Table 29 MXT3020 MVIP Bus Timing (2/4 MHz) 157
Table 30 MXT3020 Reset Timing 159
Table 31 Port 2 Interface Signal Description 164
Table 32 Scatter/Gather Memory Interface signal description 165
Table 33 Circuit Interface signal description 166
Table 34 Miscellaneous clock, control, and test signal descriptions 167
Table 35 Power and Ground pin descriptions 168
Table 36 Unused pin termination - specific pins 170
Table 37 U nused pin term ination - general pins 170
Table 38 Pin Listing 171
Table 39 Pin Type Descriptions 175
Table 40 Absolute maximum ratings (VSS = 0V) 178

x Version 4.0 MXT3020 Refer ence Manual

Table 41 Recommended operating conditions 178

Table 42 DC Electrical characteristics 179

Table 43 MXT3020 package summary 187

MXT3020 Reference Ma nu al Version 4.0 xi

Preface

Maker Communications designs, develops, and markets a complete line of programmable,

High-Intensity Communications Processors™, software solutions, and development tools.

These products are designed to be adapted quickly and effectively to an extensive range of

netw orking applications.

xii Versio n 4. 0 MXT3 02 0 Reference Manual

Preface

Maker Products

Maker Communications’s product line includes:

• Traffic Stream Pr oces sing S olut i ons

• ATM Cell Processing Solutions

Traffic Stream Processing Solutions

Integrated Circuit

The MXT4400 Traffic Stream Processor is Maker Comm unications’s very high-

performance communications processing engine . Equally adept at supporting pack-

ets and ATM cells, this device re sides in the data path of net working systems and pro-

vides wire-speed, programmable internetworking and traffic management. It is the

first of a pr oduct f amily tha t suppor ts OC-1 2 and OC-48 tr af fic loads. This pr ogram-

mable chip is adapted for a number of different applic ations using either Maker's

firmware packages or customer developed applications.

Software Solutions

Executi ng on the MXT4400, PortMaker™ empl oys a modul ar arch itectur e built on

a common kernel to deliver standard inter-domain services. These services include

ATM Adaptation Layer 5 (AAL5) Segmentation and Reassembly (SAR) at 622 Mb/

s and support for Packet over SONET.

Development Tools

Maker Communications offers a full suite of development tools for the MXT4400

T raffi c Stream Processor . These include a Verilog model of the chip, the TSP Assem-

bler, the MXT4400 simulat ed t est benc h (ESIM), and the gr aphical versio n the reof

(GESIM). The TSP Assembler assembles, links, and creates a program image that is

downloaded to the MXT4400 during device initialization. ESIM is a Verilog-based

simulat or t ha t pr ovi des a tightly cont rolled and fully o bse rva b le en vir onment to test

and debug both processor applications and external host programs before running

them on th e target hardware. ESIM is complemented with a graphical post processor ,

GESIM.

MXT3020 Reference Ma nu al Version 4.0 xiii

Maker Products

ATM Cell Processing Solutions

Integrated Circuits

Maker Communications delivers a wide range of ATM solutions based on the

MXT3010 cell processing engine and the MXT3020 circuit interface coprocess or.

The MXT3010 is a high-performance programmable cell processor engine specifi-

cally de signed t o hand le ATM cell mani pulat ion and t ransmis sion at data rates up to

622 Mb/s . The MXT3020 is an ATM circuit in terface coprocess or for the MXT3010

cell pr ocessor . It provides fle xible interwo rking between T ime Divi sion Multiplexed

(TDM) links and the ATM network.

Software Solutions

The MXT3010 and MXT3020 are complemented with a series of software applica-

tions that provi de s tandar d ce ll p rocess ing f uncti onali ty. CellMaker®-155 and Cell-

Maker®-622 execute on an MXT3010 and provide ATM Adaptation Layer 5

(AAL5) Segment ation and Reassembl y (SAR) at data rat es of 155 Mb/s and 622 Mb/

s, respec tively. AccessMake r™ executes on an MXT3010 with up to four attached

MXT3020 coprocessors. It provides cell processing functions for both packet and cir-

cuit int erworking to suppor t multipl e services concurre ntly including AAL1, AAL5,

IMA, and cell relay.

Development Tools

Maker Communications offers a full suite of development tools for the MXT3010

Cell Processor including Verilog models of the chips, the AS3010 assembler, Cell-

Maker Simulator (CSIM), and Graphical CellMaker Simulator (GCSIM). The

AS3010 assembles, links, and creates a program image that is downloaded to the

MXT3010 during device initialization. CSIM is a Verilog-based simulator that pro-

vides a tightly controlled and fully observable environment to execute and debug

both processor applications and external host programs before running them on the

target hardware. Maker also provides two development boards. CSIM is comple-

mented wit h a graphical post processor , GCSIM. The MXT3016 is a 32-bit, PCI bus-

based deve lopment board used to te st 622Mb/s applications. Th e MXT3025 is a 32-

bit, PCI bus-based evaluation board used to test OC-3 ATM (MXT3010) and T1

(MXT3020) applications.

xiv Version 4. 0 MXT3 02 0 Refere nc e Manua l

Preface

Using this Manual

This manual is a reference document intended to assist in the design of communica-

tions systems. This manual is product specific and should be used in conjunction with

other Maker product documentation to develop systems. For a complete listing of

Maker documentation refer to the web site at http://www.maker.com/support.

Additional Document References

The information provided in Maker documentation assumes some reader familiarity with the

following do cuments:

• ATM Forum’s UTOPIA Specification, Level 2, Version 1.0, af-phy-0039.000,

dated June 1995

• PCI Spec ification

Terminology

The glossary contained in this manual defines Maker terminology as well as networking/

communications terminology applicable to Maker products.

Notes and Cautions

The manual uses these conventions:

Notes contain information that is incidental to the current subject matter.

Cautions warn of the risk of unfortunate system damage or loss of data.

MXT3 0 20 Refe rence Ma nual Versio n 4.0 xv

Using this Manual

Typographical Conventions

This document uses the following typographical conventions:

• API commands appear in mixed case, for example Open_Channel.

• Simulator commands appear in lower case, for example cdl_dump.

• Instruction mnemonics and registers appear in uppercase, for example the

R_TSSCFG register.

• User input appears in bold monospace font.

• System output and code examples appear in monospace font.

• Variables that accompany commands or configuration switches appear in <ital-

ics and in brackets>, for example sim <14000>

• Text references to locations off of the current page appear in italics. For exam-

ple, see Maker Products on page xi.

• For on-line viewers using ADOBE Acrobat PDF readers, all hypertext links

appear in blue.

Change bars

Change bars are provided to indicate revisions made since the publication of the manual.

xvi Version 4.0 MXT3020 Refer e nc e Man ual

Preface

Contacting Support Services

Maker Communications h as the following forums for getting in formation, communicatin g

ideas, and reporting problems:

• Sales and customer support: 508-628-0622

• Customer support: support@maker.com

• Produc t inquiries: info@maker.com

• Facsimile: 508-628-0256

• Web: www.maker.com

MXT3020 Reference Ma nu al Version 4.0 xvii

Organiza tio n of this manual

Organization of this manual

This refe rence manual includes three sections: Subsystems, Register Reference , and

Signal Descriptions and Electrical Characteristics. Also included are Appendix A,

Acronyms, and Appendix B, Registered Decoder PAL Source Code.

The Subsystems section is a general tutorial on the organization and features of the

MXT3020. Inten ded for r eader s unfamil iar wi th the chip, th is sect ion in cludes info r-

mation on the:

• Circuit Interface

• Data Mover (Scatter/Gather) Units with List RAMs and Task Buffer RAMs

• Scatter and Gather Memory Interfaces

• Port 2 Int erface

Section 2, Register Refe rence, is intended for experienced users of the MXT3020.

This section condenses the material provided in the Subsystems section into tabular

form, and pr ovides the bit assignments and functions for all MXT3020 registers,

which are listed in alphabetical order.

Section 3, Signal Des criptions and Electrical Chara cteristic s, section includes inf or-

mation on:

• Timing information

• Pin out and pin listing

• Signal descriptions

• Electrical para meters

• Thermal characteristics

• Mechanical information

xviii Version 4. 0 MXT3 02 0 Refere nc e Man ua l

Preface

MXT3020 Reference Manual Version 4. 0

Section 1 Subsystems

This section is compos ed of five chapt er s. It provides an o ver view of the MXT3020

ATM circuit interface coprocessor and its major functional subsystems.

Version 4.0 MXT3020 Reference Manual

MXT3020 Reference Manual Version 4. 0 1

CHAPTER 1 Device Overview

The MXT30 20 is a TDM cir cuit inte rface copr ocesso r for buil ding syste ms that in te-

grate ATM, packets , and TDM – including voice-ov er-ATM products . T og ether with

the MXT3010, the MXT3020 delivers the performance and features to support mul-

tiple s ervices concurrentl y, including stru ctured and unstruct ured AAL1 circui t emu-

lation, ATM User-Network Interface (UNI), Inverse Multiplexing for ATM (IMA),

AAL2, and TM4.0 compli ant AAL5. With up to four MXT3020s connect ed to a sin -

gle MXT3010, systems can be developed that support any combination of up to 32

T1, E1, or J2 links through standard framers, or up to 64 bidirectional links (up to 8

Mb/s each) supporting SCSA and MVIP computer telephony buses.

MXT3020 applications include:

• Circuit emulation service for converting TDM data into AAL1 cells in both

Structured Data Transfer (SDT) and Unstructured Data Transfer (UDT) modes.

• ATM User-Network Interface support and inverse multiplexing over TDM cir-

cuits including T1, E1, and J2.

Key features of the MXT3020 include:

• A g lue le ss con nect i on t o t he MXT3010. The MXT30 10’s SWAN process or pro-

grams and contro ls the MXT3020.

• Support for structur ed and unstructured data transf er modes on 16 bidirectional

TDM wires that directly support SCSA and MVIP telephony busses, or 8 unidi-

rectional TDM wire pairs that connect to T1, E1, or J2 framers.

2 Version 4.0 MXT3020 Reference Manual

Device Overview

• Data Mover Units that sup port f ull y arbitrary mapping of DS0 s to cell payloads

including cross link mapping for use in tr unking applications. The Data Mover

Units contain cell delineation, Header Error Control (HEC) generation and

checking, plus cell payload scrambling and descrambling hardware to support

T1 and E1 User-Network Interfaces.

• Su ppor t f or Nx64 mode with up to 2048 DS0's of tr affic with up t o 10 24 vi rtual

circuits.

• Internal cloc k recovery using Synchronous Resi dual Ti me Stamp (SRTS) or

Adaptive techniques.

Figure 1 shows a block diagram of a possible application using the MXT3020 as a

coprocessor for the MXT3010 to provide an interface between ATM and T1/E1 facil-

ities.

FIGURE 1. T1/E1/ATM Interface Using the MXT3010 and MXT3020

MXT3010

Framers

ATM Facility

Scatter

Memory

Eight T1 or E1 Lines

Gather

Memory

MXT3020

Scatter

Memory

Eight T1 or E1 Lines

Gather

Memory

MXT3020

Port2 Bus

Framers

Eight T1 or E1 Lines

MXT3020

Eight T1 or E1 Lines

MXT3020 Gather

Memory

Gather

Memory

Scatter

Memory Scatter

Memory

MXT3020 Reference Manual Version 4.0 3

Figure 2 shows a block diagram of the MXT3020.

FIGURE 2. Block diagram of the MXT3020

The m ajor sect ions of the MXT3020 are the:

• Circuit Interface

• Data Mover (Scatter/Gather) Units with List RAMs and Task Buffer RAMs

• Scatter and Gather Memory Interfaces

• Port 2 Int erface

Port 2 Interface

Circuit Interface

Scatter MemGather Mem

Links 0-7

Port2 Bus

Interface Interface

Scatter

Task Buffer

RAMs

SDU Scatter Unit

Scatter List RAM

Gather

Ta sk Buffer

RAMs

SDU Gather Unit

Gather List RAM

4 Version 4.0 MXT3020 Reference Manual

Device Overview

CIRCUIT INTERFACE

The C ircuit In terface receives an d transmits TDM serial da ta over eight se rial link

pairs.

• Each link pair supports structured and unstructured data transfer (SD T and

UDT) modes, and is independent with its own clocks and unidirect ional mode

frame sync hronization.

• Each link pair can be configured in a unidirectional mode suitable for use with

framers or in a bidirectional mode compatible with telephony busses. When

configured in unidirectional mode, each link pair implements one receive line

and one transmit line. When configured in bidirectional mode, each link of the

pair implements an independent bidirectional line.

• For each link, a tri-state control map is provided. The MXT3020 steps through

the tri-state control map as each DS0 occurs, enabling or disabling the tri-state

output en able on the link as directed by the co ntrol bits in the map.

• Rece ived TDM frames are wr itten into buffers in Gather Memory. Transmi t

TDM frames are read from buffers in Scatter memory.

Port 2 Interface

Circuit Interface

Scatter MemGather Mem

Links 0-7

Port2 Bus

Interface Interface

Scatter

Task Buffer

RAMs

SDU Scatter Unit

Scatter List RAM

Gather

Ta sk Buffer

RAMs

SDU Gather Unit

Gather List RAM

MXT3020 Reference Manual Version 4.0 5

The Data Mover (Sca tter/Gather) Units

THE DATA MOVER (SCATTER/GATHER) UNITS

The Data Mover Units (DMUs) are specialized scatter/gather machines. One DMU

disasse mbles SAR Se rvice Dat a Units (SDUs) fr om ATM cel ls and prepares data f or

transmission over TDM links. Simultaneously, the other DMU receives data from

TDM links and assembles it into ATM SAR SDUs. The Data Mover Units are pro-

grammed by the MXT3010, which lo ads li sts of i nstru ction s for con troll ing th e data

transf er proce ss into a designat ed area of Gather Memory. The MXT3010 the n loads

control information and data into the T a sk Buffer RAM of the scatter machine or con-

trol information into the Task Buffer RAM of the gather machine.

Port 2 Interface

Circuit Interface

Scatter MemGather Mem

Links 0-7

Port2 Bus

Interface Interface

Scatter

Task Buffer

RAMs

SDU Scatter Unit

Scatter List RAM

Gather

Ta sk Buffer

RAMs

SDU Gather Unit

Gather List RAM

6 Version 4.0 MXT3020 Reference Manual

Device Overview

SCATTER AND GATHER MEMORY INTERFACES

The Scatter and Gather Memory interf aces are each 16-bits wide and support up to

512 Kbytes of pipelined synchronous SRAM. Each port can accept accesses from

any of the on-chip masters (Circuit Interface, Data Mover Units, or Port2 Interface).

Because the Scatter and Gather Memory ports are independent, operations to these

ports can occur simultaneously.

Port 2 Interface

Circuit Interf ace

Scatter MemGather Mem

Links 0-7

Port2 Bus

Interface Interface

Scatter

Task Buffer

RAMs

SDU Scatter U nit

Scatter List RAM

Gather

Task Buffer

RAMs

SDU Gather Unit

Gather List RAM

MXT3020 Reference Manual Version 4.0 7

Port2 Interface

PORT2 INTERFACE

The Port2 Inte rface is t he MXT3020’s co nnection to the MXT3010 device . Throug h

the Port2 Interface, the MXT3010 can read and write Scatter and Gather memory , the

Task Buffer RAMs, List RAMs, and all internal registers. See “MXT3020 address

space” on page 83. Once a Port2 transfer begins, the MXT3020's Port2 Interface

demultiplexes the Port2 bus and decodes the address. If the address maps to this chip,

the MXT3020 performs the read or write operation to the register or RAM selected

by the address. The MXT3020 address space is accessible only in burst transfer

mode.

An MXT3020 occupi es 1 Mbyte of Port2 addr ess space. Two MXT3020s can resi de

on a Port 2 bus without th e need fo r additi onal devi ce selec tion log ic. The P2A20 pin

of one MXT3020 is strapped low to decode Port2 bus address space 0x000000 to

0x0FFFFF while the P2A20 pin of the other MXT3020 is strapped high to decode

Port2 a ddress space 0x100000 to 0x1FFFFF. Alternative ly , multiple MXT3020’ s can

be supported with the addition of a devi ce selection PAL. See “Multiple MXT3020

implementation” on pa ge 130.

Port 2 Interface

Circuit Interface

Scatter MemGather Mem

Links 0-7

Port2 Bus

Interface Interface

Scatter

Task Buffer

RAMs

SDU Scatter Unit

Scatter List RAM

Gather

Task Buffer

RAMs

SDU Gather Unit

Gather List RAM

8 Version 4.0 MXT3020 Reference Manual

Device Overview

MXT3020 Reference Manual Version 4. 0 9

CHAPTER 2 Cir cuit Interface

The Circuit Interface logic receives and transmits TDM serial data. The Circuit Inter-

face supports eight serial link pairs.

• Each link pair supports structured and unstructured data transfer (SDT and

UDT) modes.

• Each link pair is compl et ely i ndependent with its own cl ock s and unidirectional

mode frame synchronization.

• TDM serial data rates supported are 1.544, 2.048, 4.096, 6.144, or 8.192 Mhz.

Port 2 Interface

Circuit Interface

Scatter MemGather Mem

Links 0-7

Port2 Bus

Interface Interface

Scatter

Task Buffer

RAMs

SDU Scatter Unit

Scatter List RAM

Gather

Ta sk Buffer

RAMs

SDU Gather Unit

Gather List RAM

10 Version 4.0 MXT3020 Reference Manual

Circuit Interface

• Each link pair can be configured in a unidirectional or a bidirectional mode. In

unidirectional mode, each link pair is configured as one 2-wire port with a dedi-

cated receive and transmit line, and can connect to T1, E1, and J2 framers. In

bidire ction al mode, each li nk pair is configur ed as two singl e-wir e bidirect ional

links, and can directly support SCSA and MVIP telephony busses.

• A tri-state control map for each link can be stored in a section of the Gather

Memory re served for contro l purposes. The si ze of the tri-s tate control map for a

link is det er m ine d by t h e number of DS0s o ccurring in each fr ame, as a tri-stat e

control bit is provided for each DS0 on the link. Synchronized by Frame Sync

on the li nk, the MXT3020 steps through the tri-state control map as each DS0

occurs, enabling or disabling the tri-state output enable on the link as directed

by the tr i-state control bits in the map. In bidirectional mode, each wire is indi-

vidually tri-statable on a DS0 by DS0 basis. In unidirectional mode, each trans-

mit wire is individually tri-statable on a DS0 by DS0 basis.

• Serial da ta receive d by the links is packed into h alfwo rds and wri tten to buffers

in Gather Memory. Data to be transmitted is read fr om Scatter Memory and

shif ted out onto the tr ansmi t links . The Circui t Inter face m ainta in s all nece ssary

pointers to Scatter/Gather Memory to support constant-bit-rate data with mini-

mal intervention from the SWAN processor in the MXT3010.

MXT3020 Reference Manual Version 4.0 11
Circuit Interface r e gi st ers
CIRCUIT INTERFACE REGISTERS
Per-Link registers
Each of the eight link pairs has a configuration register, three address counters, and 
five l in k s ervice clock and  Sync hronous Residual Time Stamp (SRTS)  cont rol regis-
ters:
TABLE 1. Circuit Interface registers (for each link)
Global registe rs
In additi on t o the ei ght register s pr ovi ded for each link, the Circuit  Int er fa ce has  six  
global configuration/status re gisters: 
TABLE 2. Cir c uit Interface r egisters (global)
Register Function
Link Configuration register See “Link Config ur ation register” on page 12.
Link Tx Buffer Address counter See “Link Buffer Address counters” on page 23.
Link Rx Buffer Address counter
Link Tri-state Control Address 
counter  See “Link Tri-sta te Control Address counter” on page 27.
Link service clock control registers: 
N register, K register,
L counter, FTC counter,
Link SRTS Value register
See “Link service clock generation registers” on page 33.
Register Function
CI Tri-state Control Base Address 
register See “CI Tri-state Control Base Address register”  on page 37.
CI Configuration register See “CI Configuration register” on page 3 7.
CI Quiet Frame Base Address reg-
ister See “CI Quiet Frame Base Address register” on page 42.
CI SRTS FTC register  See “CI SRTS FTC register” on page 45.
CI SRTS Valid Status register See “CI SRT S Valid Status register” on page 45.
CI Status register See “CI Status register” on page 46.

12 Version 4.0 MXT3020 Reference Manual

Circuit Interface

LINK CONFIGURATION REGISTER

The Link Conf iguration register controls the operating mode of each link. There is

one of t hese read/write re gisters for each li nk. The bit map is shown i n Figure 3 and

the bit fun ctions ar e described in the paragraphs which follow.

FIGURE 3 Link Configuration register bit assignments

D_FCNT (bit 13)

The Link Buffer Address counters (page 23) are 15 bits long and consist of a DS0

portion and a frame count portion. The number of bits used in the DS0 portion

depends up on the number of DS0’s in the fra me (MAXDS0 in the “CI Conf iguration

regist er ” on page 37). The bits n o t u sed for the DS0 portion are t he f ra m e co unt por -

tion. The D_FCNT bit enables/disables incrementing the frame count portion. Set-

ting this bit to one (1) disables incrementing the frame count portion, causing

programs used in special applications to repeatedly use a single portion of frame

buffer storage. Clearing this bit to zero (0) enables incrementing the frame count por-

tion. This latter choic e is used by most pr ograms.

TxCLKS (bits 12 and 11)

These bits select the link transmitter clock source (SRTS, BCLK, ACLK). See

“Added detail: Bits 12-10 – clock source control” on page 15..

1514131211109876543210

D_FCNT

TxCLKS

ACLK_MD

ACTDS0 BI DTM D_DELAY

LSB_1ST

SRTS_MD

LkRSET

Bit 12 Bit 11 Clock Source

0 0 Internal SRTS Clock

0 1 External BCLK inpu t

1 0 External ACLK input

1 1 Reserved

MXT3020 Reference Manual Version 4.0 13

Link Config ura tio n register

ACLK_MD (bit 10)

This bit sel ects the ACLK pin I/O dir ect io n. W hen t hi s bi t is one (1), the ACLK pin

is an ou tpu t. Whe n t his bit is zero (0), the ACLK pi n i s a n i nput . See “Added detail:

Bits 12-10 – clock source control” on page 15.

ACTDS0 (bits 9, 8, and 7)

These bits indicate the actual number of DS0's per frame. This information is used by

the tri -s tat e en abl e control map (see “The tri-state enable cont rol map” on page 28).

BI (bit 6)

This bit controls t he mode of a link pa ir. When this bit is one (1) , the link ope rates in

bidirectional mode. When this bit is zero (0), the link operates in unidirectional mode.

These modes ar e described in greate r detail in “Adde d detail : Bit 6 – link pair mode”

on page 19.

DTM (bit 5)

This bit se lects the Data Transf er M ode of t h e li nk pair. When th is bi t is one (1), th e

link operates in Structured Data Transfer (SDT) mode. When this bit is zero (0), the

link operates in Unstructur ed Data Transfer (UDT) mode.

Bit 9 Bit 8 Bit 7 Actual number of DS0’s per frame

00024

00132

01064

01196

100128

101 through 111 Reserved

14 Version 4.0 MXT3020 Reference Manual

Circuit Interface

D_DELAY (bits 4 and 3)

These bits control the position of Frame Sync relative to the first bit of a frame.

LSB_1ST (bit 2)

This bit controls the direction of the link shift registers. When this bit is one (1), the

link sh ift regis ters operat e in LSB mode, sh ifting the least sig nificant bit of each byte

onto the ser ial lin e firs t. When this bit is z ero (0), the link sh ift reg ister s operate in

MSB mode, shifting the most significant bit of each byte onto the serial line first.

SRTS_MD (bit 1)

This bit contro ls the mode of the SRTS value gener ator. Figure 4 shows a simpli fied

diagram of the SRTS support hardware.

FIGURE 4 SRTS support hardware

When this bit is one (1), the SRTS value generator operates in maste r mode. In this

mode, the value generator uses the external ly supplied TDM service clock (BCLK

pin) to generate SRTS values for transmission over the ATM link with the data.

Bit 4 Bit 3 Frame Sync to first data delay

0 0 1 cycle

0 1 2 cycles

1 0 3 cycles

1 1 Reserved

Numerically

Controlled

Oscillator 0

Regenerated

service clock

Divide

by 3008

(Settable)

SRTS

value

SRTS

4-bit up-

counter

SRTS

Value

Latch

FNET

BCLK

N Value

K Value

MXT3020 Clock (FN) SRTS_MD

SRTS value generator

L Value

3-bit

divider in

N register

MXT3020 Reference Manual Version 4.0 15

Link Config ura tio n register

When the SRTS_MD bit is zero (0), the SRTS value generator operates in slave

mode. In slave mode, the SR TS value generator measures the service clock generated

by the numerically controlled oscillator within the MXT3020. When SRTS is used

for cl ock recover y , the SR TS v alues thus generated are used by software t o adjust t he

values of N and K and lock the regenerated TDM service clock to the remote TDM

service clock.

LkRESET (bit 0)

This bit c ontrols the re set state of a link pa ir . Setti ng this bit to one (1) plac es the link

in the reset state. Clearing this bit to zero (0) removes the link from the reset state.

Added detail: Bits 12-10 – clock source control

ACLK pin

In addition to the ASER and BSER pins, an ACLK pin is provided. The state of bit

10 (ACLK_MD) in the Link Configuration register determines whether this pin is

used as an input or as an output:

• If ACLK_M D is cl ear (0) , th e ACL K pin fu nct io ns as an input and functions as

the Transmit Input Clock in both the bidirectional (bus) and unidirectional

(frame r) modes.

• If ACLK_MD is set (1), the ACLK pin functions as an output and functions as

the Transmit Link (Output) Clock in the unidirectional (framer) mode. In bidi-

recti onal (b us) mode, the tr i-st ate co ntrol that is bei ng used t o cont rol th e ASER

line is presented on the ACLK pin and can be used to control external output-

enabled devi ce s.

BCLK pin

The BCLK pin provides t he Receive Cloc k signals for both ASER and BSER in both

the unidirectional and bidirect ional modes.

16  Version 4.0 MXT3020 Reference Manual
Circuit Interface
Table 3 shows four configur ations using ACLK and BCLK to provide clocking in 
unidirectional mode. Table 3 also shows three configurations using ACLK and 
BCLK to provide clocking in bidirectional mode. The figures cited in the table pro-
vide additional information about the clocking configurations.
Note:While sixteen configurations are theoretically possible (four bits are used), only the seven 
show n  in the figures  a re functiona l. O t h er c onfigurat ion s  a r e n on - functional an d m us t  not be 
used.
TABLE 3. Configurations for ACLK and BCLK 
Bits 
12,11,10,6 Description Figure
0100  (Unidirectional mode)  An external clock on the BCL K pin pro-
vides the  clocking for both the  link logic  transmitter and receiv er . 
The ACLK pin is unused .
Figure 5, 
“Config uratio n Uni-
1,” on page 17
1000  (Unidirectional mode)  An external clock on the ACLK pin pro-
vides  clocki ng for  the link log ic tran smitter. An extern al clock  on 
the BCLK pin provi des clock ing for the link l ogic receiver.  
Figure 6, 
“Config uratio n Uni-
2,” on page 17
0010  (Unidirectional mode)  The internal SRTS clock provide s  clock-
ing for the link logic transmitter and outputs this clock on the 
ACLK pin. An external clock on the B CLK pin provides clock-
ing for the link logic receiver.
Figure 7, 
“Config uratio n Uni-
3,” on page 18
0110  (Unidirectional mode)  An external clock on the BCL K pin pro-
vides  the   c lock ing  fo r both the link  lo g i c tra n smit ter  a nd   rece iv er 
and provides the same clock signal as an output on the ACLK 
pin.
Figure 8, 
“Config uratio n Uni-
4,” on page 18
0101  (Bidi rectional mode) An extern al clock on the BCLK pi n pro-
vides the  clocking for both the  link logic  transmitter and receiv er . 
The ACLK pin is unused . 
Figure 9, 
“Configuration Bi-
1,” on page 18
1001  (Bidi rectional mode) An extern al clock on the ACLK pi n pro-
vides  clocki ng for  the link log ic tran smitter. An extern al clock  on 
the BCLK pin provi des clock ing for the link l ogic receiver.  
Figure 10, 
“Configuration Bi-
2,” on page 19
0111  (Bidi rectional mode) An extern al clock on the BCLK pi n pro-
vides the  clocking for both the  link logic  transmitter and receiv er . 
The tri-state  control that is being us ed to control the ASER line  is 
presen ted on  the ACLK pin and can be used to cont rol ex terna l 
output -enab led devices.
Figure 11, 
“Configuration Bi-
3,” on page 19

MXT3020 Reference Manual Version 4.0 17

Link Config ura tio n register

FIGURE 5 Configuration Un i-1

FIGURE 6 Configuration Un i-2

Internal SRTS Clock 00

Link Confi guration bit 12 11

ACLK pin

BCLK pin

ASER pin

BSER pin

Link Pa ir Serial iz e /

Deseriali z e Logic

Rclk

Tclk

UNI

Tri-state control A

0 1 00

Sign al on BC LK pin pr o vi de s all clo ck ing

Internal SRTS Clock 00

Link Confi guration bit 12 11

ACLK pin

BCLK pin

ASER pin

BSER pin

Link Pa ir Serial iz e /

Deseriali z e Logic

Rclk

Tclk

UNI

Tri-state control A

1 0 00

Signal on BCLK pin provides receiver clocking

Signal on ACLK pin provides transmitter clocking

18 Version 4.0 MXT3020 Reference Manual

Circuit Interface

FIGURE 7 Configuration Un i-3

FIGURE 8 Configuration Un i-4

FIGURE 9 Configuration Bi-1

Inter na l SRTS Cloc k 00

Link Confi guration bit 12 11

ACLK pin

BCLK pin

ASER pin

BSER pin

Link Pa ir Serial iz e /

Deseriali z e Logic

Rclk

Tclk

UNI

Tri-state control A

0 0 01

Sign al on BCLK pin provide s receiver clock ing

Internal SRTS provides transmit clocking and output on ACLK

Internal SRTS Clock 00

Link Config urat ion bit 12 11

ACLK pin

BCLK pin

ASER pin

BSER pin

Link Pair Seri alize /

Deseriali z e Logic

Rclk

Tclk

UNI

Tri-state control A

0 1 01

Signal on BCLK pin pr o vides all clocking and outp ut on AC LK

Internal SRTS Clock 00

Link Config urat ion bit 12 11

ACLK pin

BCLK pin

ASER pin

BSER pin

Link Pair Seri alize /

Deseriali z e Logic

Rclk

Tclk

UNI

Tri-state control A

0 1 10

Sign al on BC LK pin pr o vi de s all clo ck ing

Tri-state gating

Tri-state control B

MXT3020 Reference Manual Version 4.0 19

Link Config ura tio n register

FIGURE 10 Configuration Bi-2

FIGURE 11 Configuration Bi-3

Added detail : Bit 6 – li nk pair mode

The MXT3020 circuit interface can be operated in either bidirectional or unidirec-

tional mode. The BI bit (bit [6]) in the Link Configuration register selects the mode

of operation. Bidirectional mode is typically used with telephony busses, and unidi-

recti onal mode is ty pically us ed with TDM framers . Figure 12 sho ws the two modes.

Internal SRTS Clock 00

Link Config urat ion bit 12 11

ACLK pin

BCLK pin

ASER pin

BSER pin

Link Pair Seri alize /

Deseriali z e Logic

Rclk

Tclk

UNI

Tri-state control A

1 0 10

Sign al on BC LK pin pr ovide s r e ce iv e r cl oc king

Tri-sta te ga ti ng

Sign al on AC L K pin provides transm it te r cloc k i ng

Tri-state con trol B

Internal SRTS Clock 00

Link Config urat ion bit 12 11

ACLK pin

BCLK pin

ASER pin

BSER pin

Link Pair Seri alize /

Deseriali z e Logic

Rclk

Tclk

uni

Tri-state control A

0 1 11

Sign al on BC LK pin pr o vi de s all clo ck ing

Tri-sta te ga ti ng

Tri-state control for external gating is provided on ACLK pin

Tri-state con trol B

20 Version 4.0 MXT3020 Reference Manual

Circuit Interface

FIGURE 12 MXT3020 operat in g modes - eight lin k pairs

As indicated in the figure, the MXT3020 treats the TDM links as eight link pairs,

regardless of operating mode. Thus, the two operating modes can be compared by

analyzing a single link pair.

Pins associated with a link pair

There are fi ve pins associat ed with each li nk pair . Dependi ng upon the confi guration

of the link, these pins may be connected to a variety of diff erent signals within the

MXT3020. Table 4 summarizes the connection possibilities, and the paragraphs

which follow discuss each pin and its configuration alternatives in greater detail.

TABLE 4. MXT3020 link interface pins and signals

Pin Signals carried in unidirectional mode Signals carried in bidirectional mode

ASER TxData (“A Serial”) for link nTx/RxData for link n

BSER RxData (“B Serial”) for link nTx/RxData for link n + 8

ACLK

(output)

(input) Tx Link Clk for ASER

Tx Input Clk for ASER/BSER Copy of tri-state enable for ASER

Tx Input Clk for ASER/BSER

BCLK RxCLK for ASER/BSER RxCLK for ASER/BSER

BSCE Frame Sync Copy of tri-state enable for BSER

Link Pair 0/8

Link Pair 1/9

Link Pair 2/10

Link Pair 3/11

Link Pair 4/12

Link Pair 5/13

Link Pair 6/14

Link Pair 7/15

Link Pair 0

Link Pair 1

Link Pair 2

Link Pair 3

Link Pair 4

Link Pair 5

Link Pair 6

Link Pair 7

Unidirectional Mode

Bidirection al Mode

Link 0

Link 8

Link 1

Link 9

Link 2

Link 10

Link 3

Link 11

Link 4

Link 12

Link 5

Link 13

Link 6

Link 14

Link 7

Link 15

MXT3020 Reference Manual Version 4.0 21

Link Config ura tio n register

ASER and BSER pins

Figure 13 shows the ASER (A serial) and BSER (B serial) pins. As indicated in Table

4, in the unidirectional mode, ASER and BSER are TxData and RxData respec tively .

In bidirectional mode, ASER and BSER carry Tx/RxData. Since ASER and BSER

are bidirectional busses in that mode, the transmit functions of ASER and BSER need

to be di sable d when rece ived da ta is arri ving. Enablin g and di sabli ng of the t ransmit

function are accomplished by tri-state enable circuitry described in “Link Tri-state

Control Address counter” on page 27.

FIGURE 13 MXT3020 operating modes - ASER and BSER

Added detail: BSCE pin

As indi cated in Table 4 o n page 20, the BSCE pin can be use d either as a Frame Sync

pin, or as a copy of the tri-state enable for the BSER pin. Usage of the BSCE pin

depends upon the MXT3020 operating mode and is explained below.

BSCE usage in unidirectional mode

When the MXT3020 is used in unidirectional mode , it is typically c onnected to TDM

framers that provide Frame Sync signals. T wo methods of wiri ng the Frame Sync s ig-

nal are availa ble:

• If a single Fr ame Sync sign al is used , it can be connected t o the FSYNC pin (pin

160) of the MXT3020. In addition, the FS_MODE bit (bit [0] of the CI Config-

uration register) should be cleared to zero (0) to indicate that a Frame Sync sig-

nal common to all links is being supplied on the FSYNC pin.

Link Pair 0/8 Link Pair 0

Unidirectional Mode

Bidirection al Mode

BSER

ASER ASER

BSER

Link 0

Link 8

22 Version 4.0 MXT3020 Reference Manual

Circuit Interface

• If the application calls for different link pairs to use different Frame Sync sig-

nals, Frame Sync signals ca n be wired to the BSCE pin s of individu al link pairs.

In addition, the FS_MODE bit (bit [0] of the CI Configuration register) should

be set to one ( 1) to indicate tha t Fram e Sync signa l s for each link pai r are being

provided on their respective BSCE pins.

In addition to the actions listed above, bits [4:3] of the Link Configuration register

and bit [10] of the CI Configuration register are used to control the use of Frame Sync

in various applications.

BSCE usage in bidirectional mode

Bidirectional mode is used with telephony busses, where per-link Frame Sync signals

are not required. The refore, the BSCE pin is not used for Fr ame Sync in bidirectional

mode. In bidirectional mode, the tri-state control that is being used to control the

BSER line is presented on the BSCE pin and can be used to control external output-

enabled devi ce s.

MXT3020 Reference Manual Version 4.0 23

Link Buffer Address counters

LINK BUFFER ADDRESS COUNTERS

Link Rx Buffer Address counter

This register indicates where the next data received on this TDM link pair will be

stored in the Gather Memory. The contents of this counter combined with the link

number provide an 18-bit pointer to a halfword-aligned circular queue in Gather

Memory where received data can be written by the Circuit Interface logic. Every link

pair has a separate queue for re cei ved dat a, t hus each li nk pa ir has one of these read/

write registers. The counters are initializ ed by the SWAN processor i n the MXT3010

and are incremented automatically by the link hardware during data transfers.

Restriction on Link Rx Buffer Address co unter

Values in this regist er can only b e modifi ed when the link i s in the reset state . This restrictio n

does not affect the automatic incrementing that the MXT3020 performs during data transfers.

1514131211109876543210

Rx (Gather) Address counter 0

24 Version 4.0 MXT3020 Reference Manual

Circuit Interface

Link Tx Buffer Address counter

This register indicates the location in Scatter Memory from which the next data to be

transmitted on the TDM link will be taken. The contents of this counter combined

with the li nk number provi de an 18- bi t poi nte r to a hal fwor d- ali gne d circul ar queue

in Scatter Memory where transmit link data can be read by the Circuit Interface logic.

There is a separate transmit data queue for every link pair; thus, there is one of these

read/wr ite r egist ers fo r eac h link pair. The counter s are init iali zed by the SWAN pro-

cessor i n the MXT3010 and are increme nted automat ically by the l ink hardwar e dur-

ing data transfers.

Restrictions on Link Tx Buffer Address counter

Values written to this register must be 4 higher than those written to the Link Rx Buffer

Address counter. Values in this register can only be modified when the link is in the reset

state. These restri ct ions do not affect the automat ic incrementing that t he MXT3020 per-

forms during data transfers.

1514131211109876543210

Tx (Scatter) Address counter] 0

MXT3020 Reference Manual Version 4.0 25

Link Buffer Address counters

Details of the Link Tx/Rx Buffer Address counters

Each address counter is composed of a frame counter (FC) and a DS0 counter. The

DS0 counter wraps based upon the settings of the ACTDS0 field in the “Link Con-

figuration register” on page 12 . The frame counter wraps based on the MAXDS0 and

MAXTBS/MAXRBS fields in the “CI Configuration register” on page 37.

The MAXDS0 and MAXTBS/MAXRBS settings determine the buffer size allocated

to each link. This is shown in Table 5.

TABLE 5. Buffer size allocation

MAXDS0 MAXTBS/MAXRBS Buffer size (Wrap boundary)

24 or 32 64 frames 2K

64 64 frames 4K

96 or 128 64 frames 8K

24 or 32 128 fr a mes 4K

64 128 fr a mes 8K

96 or 128 128 frames 16K

24 or 32 256 fr a mes 8K

64 256 fr a mes 16K

96 or 128 256 frames 32K

24 or 32 512 fr a mes 16K

64 512 fr a mes 32K

96 or 128 512 frames 64Ka

a. The 64K bu ffer size is not supported in bidirectional mode.

26 Version 4.0 MXT3020 Reference Manual

Circuit Interface

The positions of the frame counter and DS0 counter portions of the Link TX/RX

Buff er Address counters are shown in Table 6.

In Table 6, vari able y repre sen ts the highes t orde r bit used by the f rame counte r. The

value of y depends upon the buffer size, as shown in Table 7.

TABLE 6. Frame Counter / DS0 Counter

Unidirectional mode Bidirectional mode

MAXDS0 Frame counter DS0 counter Frame counter DS0 counter

24 or 32 [y:5] [4:0] [y:6] [5:1]

64 [y:6] [5:0] [y:7] [6:1]

96 or 128 [y:7] [6:0] [y:8] [7:1]

TABLE 7. Relation of buffer size to variable y

Buffer size Unidirectional mode, y= Bidirectional mode, y=

2K 10 11

4K 11 12

8K 12 13

16K 13 14

32K 14 15

64K 15 Not supported

MXT3020 Reference Manual Version 4.0 27

Link Tri-stat e Control Address count er

LINK TRI-STATE CONTROL ADDRESS COUNTER

The contents of the Tri-state Control (TSC) Address counter are combined with the

Tri-state Control Base Address register and the Link ID number (LID) to create an

18-bit p oin ter t o a ha lfword -alig ned e ntry i n Gather Memo ry c ontai ning th e tr i-st ate

control map for the link. The format of the Tri-state Con trol Address coun ter is

shown below. The format of the complete pointer is shown in “Creation of the tri-

state control map pointer” on page 28.

An example of the tri-state control pro cess

The MXT3020 provides tri-state control of ASER [7:0] and BSER [7:0] when oper-

ating in bidirectional mode. The MXT3020 also provides tri-state control of ASER

[7:0] when operating in unidirectional mode. Tri-state control is provided by tri-state

control maps located in Gather Memory.

Figure 14 shows, in simplified form, the fundamentals of tri-state control. To sim-

plify the figure, only the tri-state control of ASER [0], operating in bidirectional

mode, is shown.

1514131211109876543210

0TSCNT0

28 Version 4.0 MXT3020 Reference Manual

Circuit Interface

FIGURE 14 Tri-state enable for the ASER pins

In the exa mple shown, data is bei ng generated i n T1 format. That is, a byte o f data is

presented for a 64 Kbps channel (DS0); then a byte of data is presented for the next

DS0. When data has been pre sented for 24 DS0’ s, a new frame begins and a new byte

of data for the first DS0 is presented. The data being presented is only enabled onto

the ASER[0 ] pin if the bit in the tr i-state m ap for this lin k indicate s that enablin g dur-

ing the time period of this DS0 is permitted. Specifically, a zero (0) in the tri-state

map indicates that the data should be enabled onto the ASER [0] pin. Thus, in the

example, data is being applied to DS0 #0 and DS0 #1, but not to DS0 #23.

If one thinks of the registers shown in Figure 14 as shift registers, it is important to

note that the tri-state map “shifts” at one-eighth the rate of the data registers, as a bit

in the tri-state map controls the enabling or disabling of an entire byte of data. For

each byte time (at a DS0 rate) on each link, the MXT3020 provides two tri-state

enable bi ts, on e for ASER and on e for BSER.

The tri-state enable control map

Creation of the tri-state control map pointer

The contents of the Tri-state Control Address counter (page 27) are combined with

the Tri-sta te Cont rol Base Address regist er (p age 37) and the Link ID number ( LID)

to create an 18-bit pointer to a halfword-aligned entry in Gather Memory containing

the tri-state co ntrol map for the link. The pointer has the following format:

ASER [0]

MXT3020 serial data being transmitted on the ASER pin of link pair 0

MXT3020 tri-state map for link pair 0

Data traversing the bus line connected to ASER [0] pin

00001 1 11

Data byte for DS0 #0

Data byte

DS0 #0 Data byte

DS0 #23 Data by te

DS0 #1

Tim e slo t

DS0 #0 Time slot

DS0 #23 Time slot

DS0 #1

010

Time slot for DS0 #0

Enabling

Gate

MXT3020 Reference Manual Version 4.0 29

Link Tri-stat e Control Address count er

Bidirectional mode

The tri-state control map pointer identifies eight buffers (LID [7:5]) in memory, one

buf fer for ea ch link pair. Each buf fer consist s of 16 halfword s (TSCNT [4:1]) or 256

bits. For each link pair , duri ng each DS0 data by te, the MXT3020 read s two of these

tri-s tate enable bits, one for ASER an d one for BSER. F igure 15 sh ows the sequ ence

in wh ich th ese enable bits are used.

FIGURE 15 ASER and BSER tri-state enable bit usage1 (bidirectional)

Figure 15 shows a tri-state map that would be sufficient for 24 DS0’ s on one link pair .

By changing the value of LID and using the same three values for TSCNT, similar

maps could be loaded into memor y to control 24 DS0’ s on each of th e eight link pairs

served by the MXT3020.

The tri-state control map shown in Figure 15 serves 24 DS0’s and uses 48 bits. The

MXT3020 can acc ommodate t ri-sta te control maps wit h as many a s 128 DS0’s (256

bits) for each link pair.

18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

TSC_BASE LID TSCNT

1. In all MXT3020 figures, memory addressing is Big Endian.

15 0

BSER[0] during DS0 #1

BSER[0] during DS0 #0

ASER[0] du ring DS0 #1

ASER[0] du ring DS0 #0

TSCNT[4:1] = 00000

15 07

BSER[0] during DS0 #9

BSER[0] during DS0 #8

ASER[0] du ring DS0 #9

ASER[0] du ring DS0 #8

TSCNT[4:1] = 00001

0x---00

0x---02

15 0

BSER[0] during DS0 #17

BSER[0] during DS0 #16

ASER[0] during DS0 #1 7

ASER[0] during DS0 #1 6

TSCNT[4:1] = 00010

0x---04

Memory

Address Tri-State c ounter

30 Version 4.0 MXT3020 Reference Manual

Circuit Interface

If the actual number of DS0s is less than 128, there is no requirement that the tri-state

control map be filled with 256 bits, as the Tri-state Control Address counter wraps

based up on the actual number of DS0s indicated in t he ACTDS0 bits in the Link Con-

figuration register. The wrap boundaries for the Tri-state Address counter are indi-

cated in the following table:

Unidirectional mode

The contents of the Tri-state Control Address counter (page 27) are combined with

the Tri-sta te Cont rol Base Address regist er (p age 37) and the Link ID number ( LID)

to create an 18-bit pointer to a halfword-aligned entry in Gather Memory containing

the tri-state co ntrol map for the link.

The tri-state control map pointer (page 28) identifies eigh t buffer s (LID [7:5]) in

memory, one buffer for each link pair. Each buffer consists of eight halfwords

(TSCNT [3:1])1 or 128 bits. For each link pair, during each DS0 data byte, the

MXT3020 reads one of the se tri- state ena ble bits to contro l the ena bling of da ta onto

the ASER pin. Figure 16 shows the sequence in which these enable bits are used.

Mode ACTDS0 Wrap Boundary

Bidirectio na l 24 6 bytes

Bidirectio na l 32 8 bytes

Bidirectional 64 16 bytes

Bidirectional 96 24 bytes

Bidirectional 128 32 by tes

1. TSCNT[4] is not used in unidirectional mode.

MXT3020 Reference Manual Version 4.0 31

Link Tri-stat e Control Address count er

FIGURE 16 ASER and BSER tri-state enable bit usage (unidirectional)

Figure 16 shows a tri-state map that would be sufficient for 32 DS0’ s (E1) on one link

pair . By changing the value of LID and using the same two values for TSCNT , similar

maps could be loaded into memory to c ontrol 32 DS0’ s on each of the eigh t link pairs

served by the MXT3020.

The tri-state control map shown in Figure 16 serves 32 DS0’s and uses 32 bits. The

MXT3020 can acc ommodate t ri-sta te control maps wit h as many a s 128 DS0’s (128

bits) for each link pair.

If the actual numbe r of DS0s is less than 128, ther e is no requirement that the tri-state

control map be filled with 128 bits, as the Tri-state Control Address counter wraps

based upo n the act ual numb er of DS0s. The actua l number of DS0s is de termined b y

the ACTDS0 b its in the Link Configurat ion regist er , and the wrap bounda ries fo r the

Tri-state Address counter are indicated in the following table:

Mode ACTDS0 Wrap Boundary

Unidirectional 24 4 bytes

Unidirectional 32 4 bytes

Unidirectional 64 8 bytes

Unidirectional 96 12 bytes

Unidirectional 128 16 by tes

15 07

ASER[0] during DS0 #0

ASER[0] during DS0 #1

ASER[0] during DS0 #8

ASER[0] during DS0 #9

TSCNT[4:1] = 00000

15 07

ASER[0] during DS0 #16

ASER[0] during DS0 #17

ASER[0] during DS0 #24

ASER[0] during DS0 #25

TSCNT[4:1] = 00001

0x---00

0x---02

Memory

Address Tri-State c ounter

32 Version 4.0 MXT3020 Reference Manual

Circuit Interface

Summary of tri-state control operation

The MXT3020 provides tri-state control of ASER [7:0] and BSER [7:0] when oper-

ating in bidirectional mode. The MXT3020 also provides tri-state control of ASER

when operating in unidirectional mode. To set up a tri-state map, software selects a

TSC Base Address, and for each link pair (LID) provides up to 16 (bidirectional

mode) or 8 (Unidirectional mode) halfwords specifying the tri-state enable map.

During operation, the MXT3020 services each link pair sequentially. For each link,

the MXT3020 maint ains a Tri-st ate Contr ol Addre ss count er (TSCNT) ba sed on the

receipt of Frame Sync by the link. Thus, for each link (LID), the MXT3020 has an

indicat ion (TSCNT) of whi ch DS0 is being handled by t hat link. The MXT302 0 uses

this information (LID and TSCNT), in conjunction with the TSC Base Address, to

obta in t he tri-state control map appropriate to the DS0 bei ng s erviced by that li nk at

that time. In bidirecti onal m ode, tw o tri- state enable bits from t he map are us ed to

control the gating of bytes of DS0 data onto the ASER and BSER pins respectively

(see Fi gur e 14 a nd Figure 15). In uni dir ec tional mode, a tri -s tate en abl e b it f rom the

map is use d to control the gating of a byte of DS0 data onto the ASER pin (see Figure

14 and Figure 16).

MXT3020 Reference Manual Version 4.0 33

Link service clock generation registers

LINK SERVICE CLOCK GENERATION REGISTERS

For each link, there are five registers used for link service clock generation:

• Link Service Clock N register

• Link Service Clock K register

• Link Service Clock L register

• Link FTC counter

• Link SRTS Value register

Figure 17 shows the relationship of these registers and counters to the link service

clock circuitry.

FIGURE 17 Link service clock generation registers

Three of the r egisters (N, K, L) control a numeric ally co ntrolled oscillat or which has

an inte ger por tion N a nd a fr actio nal por tion, K/L. Th e equat ion for the ou tput c lock

is shown below:

Numerically

Controlled

Oscillator 0

Regenerated

SRTS

value

BCLK

N register

K register

FN SRTS_MD

L register

FTC register

3008

CI SRTS Valid

Status register

1-bit “ready” flag

service clock

Circuitry provided for each link (8 copies) Shared by all

links (1 copy)

Link SRTS

Value register

Link FTC

counter

SRTS

4-bit up-

counter

FNET 3-bit

divider in

N register

Link Service Clock period NK

----





System clock period×=

34 Version 4.0 MXT3020 Reference Manual

Circuit Interface

Link Service Clock N register

The LSC_N value in the Link Service Clock N register represents the integer multi-

ple of system c lock per iods use d to gene rate t he link service clock. T his is the coar se

setting of the numerically controlled oscillator used to generate the service cl ock.

Setting bit 7 of this register to one (1) enables the SRTS counters. There is one of

these registers for each link.

Bits 15-13 of this register provide a pr ogrammable divider for the network clock

(FNET) (s ee Figure 17 on page 3 3). The table below shows t he division pr ovided for

various settings of bits 15-13. In addition, t he table sho ws the setti ngs that s hould be

used to support common TDM service clock frequencies when an FNET clock of

19.44 MHz is used.

1514131211109876543210

FNET_DIV Reserved

EN_CNT

LSC_N

Bits 15-13 Divide by Divider output frequencies for

FNET = 19.44 MHz TDM service clock frequencies

for FNET= 19.44 MHz

0 1 19 .4 4 MH z

1 2 9.72 MHz 8.192 MHz

2 3 6.48 MHz

3 4 4.86 MHz 4.096 MHz

4 5 3. 88 8 MH z

5 6 3.24 MHz

6 7 2. 77 7 MH z

7 8 2.43 MHz 2.048 MHz and 1.544 MHz

Restriction on FNET_DIV bits

Bits [15:8] of this register are write only and read back as all zeroes. All bits in this register

are cleared t o zeroes by Reset. Th us, the FNET_D IV bi ts are write-only and are cleared to

zeroes by Reset.

MXT3020 Reference Manual Version 4.0 35

Link service clock generation registers

Link Service Clock K register

The valu e in the Link Service Clock K regist er repr esents the frac tion control numer -

ator us ed to generat e the link ser vice clock. Th is is the f ine settin g of the numeri cally

controlled oscillator used to generate the service clock.There is one of these read/

write registers for each link.

Link Service Clock L counter

The value i n the Link Servi ce Clock L counte r represent s the fraction c ontrol denom-

inator us ed to generate the link service cl oc k. Thi s is a free run n in g co unt er that can

be read and written for di agnostic purposes and can be seeded with an initial value.

However, the value loa ded int o this co unter do es not al ter t he ef fec tive de nominat or

value, which is always 65,536 (216). This counter advances once for each service

clock cycle generated. There is one of these counters for each link.

1514131211109876543210

LSC_K

1514131211109876543210

LSC_L

36 Version 4.0 MXT3020 Reference Manual

Circuit Interface

Link FTC counter

The SRTS value generator for each link creates an SRTS value by using an FTC

counter to count a designated number (Frequency Terminal Count) of service clock

periods. A register common to all links (see “CI SRTS FTC register” on page 45)

establ ishes the number of servi ce cloc k perio ds to be co unted. Thi s number i s gener -

ally 3008 (decimal). There is one readable Link FTC counter for each link (see “Link

FTC read back” entries in “Circuit Interface per-link registers” on page 85). To

change the count used by the Link FTC counter, write the CI SRTS FTC register

(page 45).

Link SRTS Value register

Each link has a single SRTS generat or con trolled by the SRTS_M D bit f or tha t link

(see “L ink Configura tion register ” on page 12). A 4-bit val ue is latch ed into the local

SR TS value each time the FTC counter expires (see “Link FTC counter” on page 36).

There is one of these read/write registers for each link.

1514131211109876543210

0 LINK_SRTS_FTC

1514131211109876543210

0 SRTS_VALUE [3:0]

MXT3020 Reference Manual Version 4.0 37

CI Tri-state Contr ol Base Address register

CI TRI-STATE CONTROL BASE ADDRESS REGISTER

The value in this register defines the base address of the Tri-state Control table in

Gather Memory. The contents of this register and the Tri-state Control Address

counter are combined wit h the Link ID numbe r (LID) to cre ate an 18-bi t pointer to a

halfword-aligned entry in Gather Memory containing the tri-state control map for the

link. See “Creation of the tri-state control map pointer” on page 28.. There is only one

CI Tri-state Control Base Address register; it is a read/write register.

CI CONFIGURATION REGISTER

This register controls the operating mode of the Circuit Interface. There is only one

CI Configuration register; it is a read/write register.

FS_POL (Bit 15)

This bit contr ols the inter pret ation of the p olari ty o f the Frame Sy nc input . If t his bi t

is set to one (1), FSYNC active level is zero (0). If this bit is cleared to zero (0),

FSYNC active level is one (1).

Snap Shot Period (Bits 14-12)

These bi ts should be wri tt en as 010 and igno re d o n r eads. W i th this setti ng, the max-

imum unidirectional-mode link speed is 8 MHz and the maximum bidirectional-

mode link speed is 4, 6, or 8 MHz f or System Clock s peeds of 33 MHz, 40 MHz, a nd

50 MHz respectively.

1514131211109876543210

0 TSC_BASE

1514131211109876543210

FS_POL

SS_PER LP_BK FS_EN MAXRBS MAXTBS MAXDS0

FS_MODE

38 Version 4.0 MXT3020 Reference Manual

Circuit Interface

LP_BK (B it 11)

This bi t enables l ink loopback mode. If th is bit is s et to one ( 1), the li nk pair is pla ced

in loopba ck mode. In unidi rection al mode, all l inks loop th eir ASER trans mit output

back to BSER receive input. In bidirectional mode, the ASER transmit output is

looped back to the ASER receive input, and the BSER transmit output i s looped back

to the BSER receive input. If this bit is cleared to zero (0), the link pair is placed in

normal operating mode.

When a link pair is in loopback mode, no data is presented to the ASER or BSER

pins. Clock signals are not affected by loopback. During loopback mode, cl ocking

and Frame Sync must be suppli ed in t he same fa shion as for nor mal oper ating mode.

FS_EN (Bit 10)

This bit enables/disables Frame Sync detection. When asserted, this global bit per-

mits all SDT mode li nks to acquire Frame Sy nc simultaneously. If this bit is set to

one (1), Frame Sync detection is enabled, enabling all SDT mode links that have their

LkRESET bits1 clear (0). If this bit is clea red to zero (0), Frame Sync det ection is dis-

abled, di sab li ng a ll SDT mode l ink s. Thi s bi t o nly appl ie s t o SDT mode l in ks. UDT

mode links ignore this bit.

MAXRBS (Bits 9-7)

These bit s specify th e maximum amount of TDM to ATM receive frame s torage allo -

cated for any link in the system.

1. LkRESET bits are in the Link Configurati on registers for each link. See “LkRESET (bit 0)” on

page 15.

Bit 6 Bit 5 Bit 4 Maximum TDM to ATM receive frame storage

00064 frames

001128 frames

010256 frames

011512 frames

100 through 111 Reserved

MXT3020 Reference Manual Version 4.0 39

CI Configuratio n register

MAXTBS (Bits 6-4)

These bits specify the maximum amount of ATM to TDM transmit frame storage

allocated for any link in the system.

MAXDS0 (Bits 3-1)

These bits specify the maximum number of DS0’s per frame for any link in the

system.

FS_MODE (bit 0)

This bit determines the frame sync source for all of the links. If this bit is set to one

(1), each link receiv es its fra me sync (or an equ ivalent signal) fr om that l ink’s BSCE

pin. If this bit is cleared to ze ro (0), all l inks re ceive fr ame sync (or an equival ent sig -

nal) from the chip Frame Sync pin. This bit must be cleared to zero (0) when any links

are in the bidirectional mode.

Bit 9 Bit 8 Bit 7 Maximum ATM to TDM transmit frame

storage

00064 frames

001128 frames

010256 frames

011512 frames

100 through 111 Reserved

Bit 3 Bit 2 Bit 1 Maximum DS0’s per frame

00 0 24

00 1 32

01 0 64

01 1 96

10 0 128

101 through 111 Reserved

40 Version 4.0 MXT3020 Reference Manual

Circuit Interface

MAXDS0, MAXTBS, and MAXRBS and buffer sizing

The MAXDS0, MAXTBS, and MAXRBS bit s def i ne a c ommon buffer size in Sc at -

ter/Gather memory for all of the TDM links. The common buffer size for all links is

the maximum required by any link being served. The following examples are pro-

vided:

Example #1:

If thre e act ive transmit links have a MAXRBS = 128 frames and a MAXDS0 = 128

DS0s, each link buffer is 16 Kbytes (128 x 128).

DSOs 31 63 127

Frames

0 <---------------------------------- 128 DS0s ---------------- ----------------- ------->

2TX0 BUFFER

-16 Kbytes

127

0 <---------------------------------- 128 DS0s ---------------- ----------------- ------->

2TX1 BUFFER

-16 Kbytes

127

0 <---------------------------------- 128 DS0s ---------------- ----------------- ------->

2TX2 BUFFER

-16 Kbytes

127

MXT3020 Reference Manual Version 4.0 41

CI Configuratio n register

Example #2:

If there are t hree active transmit links with a MAXRBS = 128 frames and MAXDS0s

of 128, 32, and 64 DS0s per frame, all three buff ers are the 16 Kbytes (128 x 128)

required by the link wi th the largest buf fering requirement. Utilization of the three 16

Kbyte buffers is shown in the figure.

DSOs 31 63 127

Frames

0 <------------------------------------ 128 DS0s -------------------------------------->

2 TX0 BUFFER

-16 Kbytes

127

0 <----32 DS0s---->

2 TX1 BUFFER NOT USED

-4 Kbytes 12 Kbytes

127

0 <----------------64 DS0s--------------->

2 TX2 BUFFER NOT USED

-8 Kbytes 8 Kbytes

127

42 Version 4.0 MXT3020 Reference Manual

Circuit Interface

CI QUIET FRAME BASE ADDRESS REGISTER

An 11-bit value in this register defines the base address of the Quiet Frame in Gather

Memory. Additional bits indicate the type of Scatter and Gather SRAM used, control

access t o the high memory s pace (FE000 - FFC00), an d enable the quie t logic. There

is only one CI Quiet Fram e Base Address register; it is a read/write register.

QUIET_FRAME (Bits 15-5)

These bits define the base address of the Quiet Frame in Gather Memory.

RESERVED (Bit 4)

This bit is reserved. It should be written as a zero and ignored on reads.

GATH_4M (Bit 3)

Set this bit to one (1 ) if the Gather Me mory is implement ed with a si ngle 256 K x 16

(4 Mb) SRAM. Set this bit to zero (0) if smaller parts are used. This bit controls the

Gather Memory address decoding and asserts GATH_OE_[0] when any Gather

Memory location is read. GATH_OE_[0] connects to the SRAM output enable pin.

SCAT_4M (Bit 2)

Set this bit t o one (1) if the Scatte r Memory is implement ed wit h a singl e 25 6K x 16

(4 Mb) SRAM. Set this bit to zero (0) if smaller parts are used. This bit controls the

Scatter Memory address decoding and asserts SCAT_OE_[0] when any Scatter

Memory location is read. SCAT_OE_ [0] connects to the SRAM output enable pin.

1514131211109876543210

QUIET_FRAME 0

GATH_4M

SCAT_4M

EN_HMEM

EN_QUIET

MXT3020 Reference Manual Version 4.0 43

CI Quiet Frame Base Address register

EN_HMEM (Bit 1)

This bit enables MXT3020 response to Port 2 access in the co-processor high mem-

ory space (i.e. FE000 - FFC00). I f this bit i s set to one (1), the MXT3020 responds to

high memory addresses. If this bit is cleared to zero (0), the MXT3020 does not

respond to high memory addresses.

When two MXT3020s are present on the sa me P2 bus, all 2 Mbytes of available

address space are assigne d. However, the MXT3020 defau lts at power -up to not use

a small window of space between FE000 and FC000. If a designer wishes , these

addresses can be used for a CAM or similar burst mode device. If, however, it is

desired to use this space for additional Gather Memory, programs utilizing the

MXT3020 should set EN_HMEM to one (1).

EN_QUIET (Bit 0)

This bit ena bles th e quiet l ogic. If this bit is set to one (1), the qui et logi c is enabl ed.

If this bit is cleared to zero (0), the quiet logic is disabled.

Quiet Logi c

The Circui t Interf ace contai ns the quiet logic. For e ach transmit link, a dummy quie t

frame exists in Gather Memory with the proper quiet value for each DS0 in the frame.

The quiet logic copies these quiet frames into the Transmit Link buffers as soon as

the data in the buffers has been shifted out onto the TDM lines. The quiet frames

reside in the T ransmit Link buffers until replaced by data arriving from the ATM link.

In this way, the MXT3020 ensures that in the event of an ATM link underflow, the

correct quiet values (rather than stale data) are transmitted on the TDM links.

The quiet logic reads the quiet values from predefined quiet frames in Gather Mem-

ory and writes them into the TDM transmit frame buffers in Scatter Memory. There

must be one quie t frame for every ac tive TDM tr ansmit ter. The logic reads bur sts of

eight hal fwords from the Gat her Memory and then arbi trates for , and writes, the half-

words into Scatter Memory. This process continues until one frame in each TDM

transmit buffer is overwritten.

44 Version 4.0 MXT3020 Reference Manual

Circuit Interface

To be efficient, and to reduce t he overhead required for this op eration, the controllers

use the Link Reset and Data Transfer Mode bits of the Link Configuration registers

to skip links that are unused or are setup for unstructured data transfer mode. The

quiet f ram e area ca n b e a maxi mum size of 16 frames with 128 by tes pe r fr ame, or 2

Kbytes in s ize. The 2-Kbyte ar ea can b e locat ed anywher e in Gath er Memory abo ve

the TDM Link receive buffers, which always begin at Port2 address 0x80000. The

Quiet Fra me Base Addr ess r egist er loc ates t he qui et fr ame area and must be set up at

initializatio n. Bit [0] of this regi ster enables/disables the quiet logic .

Although each quiet frame has storage for 128 quiet DS0 values, only the actual num-

ber of quiet DS0’s need to be initialized for each frame. For example, if only three

links were transmitting, links 0, 1, and 2, and they supported 128, 32 and 64 DS0’s

respect ivel y, then t he al locat ion map for th e qui et f rame area would lo ok li ke the fol -

lowing:

FIGURE 18 Quiet Frame Allocation Map

31 63 127

0 <------------------------------------ 128 DS0s ----------------------------------------->

1 <-32 DS0s-> Not Used

2 <----------------64 DS0s----------------> Not Used

15 Not Used

MXT3020 Reference Manual Version 4.0 45

CI SRTS FTC register

CI SRTS FTC REGISTER

The value in the CI SR TS FTC register represents the number of service clock1 peri-

ods betwee n updates of the Link SRTS Value register (see “Link FTC counter” on

page 36 a nd “Link SRTS Value register ” on page 36 ). Whenever a Link FTC c ounter

counts down to zero, it is reloaded from the CI SRTS FTC regist er, whi ch is typic ally

set to 3008. There is only one CI SRTS FTC register; it is a read/write register.

CI SRTS VALID STATUS REGISTER

This stat us regi ster i ndicat es whethe r a link has a valid SRTS value latched . When a

link’s SRTS value is read by the SWAN processor in the MXT3010, its respective

valid b it is clea red. There is onl y one CI SRTS Valid St atus reg ister; it i s a re ad-onl y

SRTS_VALID (Bits 7-0)

These bit s indica te, on a bit -per -link ba sis, whether t he link co rresp onding to that bit

has a valid SRTS value latched . If bit n is a one (1), a valid SR TS value for link n has

been latch ed. If bit n is a zero (0), a valid SR TS value for link n has not be en lat ched.

1. The service clock rate for a T1 facility is 1.544 MHz.

1514131211109876543210

0 CI_SRTS_FC

1514131211109876543210

0SRTS

VALID

SRTS

VALID

SRTS

VALID

SRTS

VALID

SRTS

VALID

SRTS

VALID

SRTS

VALID

SRTS

VALID

46 Version 4.0 MXT3020 Reference Manual

Circuit Interface

CI STATUS REGISTER

Bits in this register indicate, for ea ch link, whether that link has acquired Frame Sync

or has lost Frame Sync. There is only one CI S tatus re gister; it i s a read-only reg ister.

ACQ n

These bits indicate whether link n has acquired Frame Sync. If an ACQ bit is a one

(1), link n has acquired Frame Sync. If an ACQ bit is a zero (0), Link n has not

acquired Frame Sync or has lost Frame Sync.

LOST n

These bits indicate whether link n has lost Frame Sync. If a LOST bit is a one (1),

link n has lost Frame Sync after acquiring it. When this bit sets, the corresponding

ACQ bit is cleared. This bit i s cle ar ed by Link Reset or Chip Rese t. If a LOST bit is

a zero (0), link n has not lost Frame Sync.

1514131211109876543210

ACQ7 LOST7 ACQ6 LOST6 ACQ5 LOST5 ACQ4 LOST4 ACQ3 LOST3 ACQ2 LOST2 ACQ1 LOST1 ACQ0 LOST0

MXT3020 Reference Manual Version 4.0 47

Interface Pins

INTERFACE PINS

There are five pins associated with each of the eight link pairs. The modes are con-

trol led by the L ink Config uration r egisters .

Note: y represents the link number, where

In addition, the FSYNC and FNET interface pins are common to all of the links in

the Circuit Interface.

TABLE 8. Circuit Interface pins, per link

Pin Mode Function Drive

ASER (y) Unidirectional

Bidirectional Transmit Data

T ransmit/Receive Data (A) Output

I/O

BSER (y) Unidirectional

Bidirectional Receive Data

T ransmit/Receive Data (B) Input

I/O

ACLK (y) Unidirectional

ACLK_MD = 1 Transmit Link Clock Output

ACLK_MD = 0 Transmi t Input Clock Input

Bidirectional

ACLK_MD = 1 ASER (y) Tri-state Enable Output

ACLK_MD = 0 Transmi t Input Clock Input

BCLK (y) All Receive Clock

(for A and B) Input

BSCE (y) Unidire ctional Link Frame Sync Input

Bidirectional BSER (y) Tri-state Enable Output

TABLE 9. Circuit Interface pins, common to all links

Pin Name Function Drive

FSYNC Frame Sync Comm on Frame Sync input for all

links when FS_MODE bit is 0. Input

FNET Network Clock Network clock used for SRTS (refer-

ence input) Input

0y7.≤≤

48 Version 4.0 MXT3020 Reference Manual

Circuit Interface

MXT3020 Reference Manual Version 4. 0 49

CHAPTER 3 Data Mover Units and Task

Buffer RAMs