LTC1665/LTC1660
1
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BLOCK DIAGRAM
FEATURES DESCRIPTION
Micropower Octal
8-Bit and 10-Bit DACs
The 8-bit LTC
®
1665 and 10-bit LTC1660 integrate eight
accurate, serially addressable digital-to-analog convert-
ers (DACs) in tiny 16-pin narrow SSOP packages. Each
buffered DAC draws just 56μA total supply current, yet
is capable of supplying DC output currents in excess
of 5mA and reliably driving capacitive loads to 1000pF.
Sleep mode further reduces total supply current to 1μA.
Linear Technology’s proprietary, inherently monotonic volt-
age interpolation architecture provides excellent linearity
while allowing for an exceptionally small external form factor.
Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1665 and LTC1660
ideal for battery-powered applications, while their ease
of use, high performance and wide supply range make
them excellent choices as general purpose converters.
LTC1665 Differential Nonlinearity (DNL)
LTC1660 Differential Nonlinearity (DNL)
APPLICATIONS
n Tiny: 8 DACs in the Board Space of an SO-8
n Micropower: 56μA per DAC Plus
1μA Sleep Mode for Extended Battery Life
n Pin Compatible 8-Bit LTC1665 and 10-Bit LTC1660
n Wide 2.7V to 5.5V Supply Range
n Rail-to-Rail Voltage Outputs Drive 1000pF
n Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
n Reference Input Impedance is Constant—
Eliminates External Buffer
n Mobile Communications
n Remote Industrial Devices
n Automatic Calibration for Manufacturing
n Portable Battery-Powered Instruments
n Trim/Adjust Applications L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
215
1GND
VOUT A
VOUT B
VOUT C
VOUT D
REF
CS/LD
SCK
VCC
VOUT H
VOUT G
VOUT F
VOUT E
CLR
DOUT
DIN
166560 BD
16
DAC A DAC H
3 14
DAC B DAC G
4 13
DAC C DAC F
5
7
6
8
10
11
9
12
DAC D DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
CODE
0 64 128 192 255
LSB
166560 G09
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
VCC = 5V
VREF = 4.096V
CODE
0 256 512 768 1023
LSB
166560 G13
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
VCC = 5V
VREF = 4.096V
LTC1665/LTC1660
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1
2
3
4
5
6
7
8
TOP VIEW
GN PACKAGE
16-LEAD PLASTIC SSOP
N PACKAGE
16-LEAD PDIP
16
15
14
13
12
11
10
9
GND
VOUT A
VOUT B
VOUT C
VOUT D
REF
CS/LD
SCK
VCC
VOUT H
VOUT G
VOUT F
VOUT E
CLR
DOUT
DIN
TJMAX = 125°C, θJA = 150°C/W (GN)
TJMAX = 125°C, θJA = 100°C/W (N)
ABSOLUTE MAXIMUM RATINGS
VCC to GND ............................................... –0.2V to 7.5V
Logic Inputs to GND ................................. –0.2V to 7.5V
VOUT A, VOUT B, VOUT H,
REF to GND .................................–0.2V to (VCC + 0.2V)
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC1665C/LTC1660C .............................. 0°C to 70°C
LTC1665I/LTC1660I ............................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Note 1)
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1665CGN#PBF LTC1665CGN#PBF 1665 16-Lead Plastic SSOP 0°C to 70°C
LTC1665IGN#PBF LTC1665IGN#PBF 1665I 16-Lead Plastic SSOP –40°C to 85°C
LTC1660CGN#PBF LTC1660CGN#PBF 1660 16-Lead Plastic SSOP 0°C to 70°C
LTC1660IGN#PBF LTC1660IGN#PBF 1660I 16-Lead Plastic SSOP –40°C to 85°C
LTC1665CN#PBF LTC1665CN#PBF LTC1665CN 16-Lead Plastic PDIP 0°C to 70°C
LTC1665IN#PBF LTC1665IN#PBF LTC1665IN 16-Lead Plastic PDIP –40°C to 85°C
LTC1660CN#PBF LTC1660CN#PBF LTC1660CN 16-Lead Plastic PDIP 0°C to 70°C
LTC1660IN#PBF LTC1660IN#PBF LTC1660IN 16-Lead Plastic PDIP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC1665/LTC1660
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ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
LTC1665 LTC1660
UNITSMIN TYP MAX MIN TYP MAX
Accuracy
Resolution l8 10 Bits
Monotonicity VREF ≤ VCC – 0.1V (Note 2) l8 10 Bits
DNL Differential Nonlinearity VREF ≤ VCC – 0.1V (Note 2) l±0.1 ±0.5 ±0.2 ±0.75 LSB
INL Integral Nonlinearity VREF ≤ VCC – 0.1V (Note 2) l±0.2 ±1.0 ±0.6 ±2.5 LSB
VOS Offset Error (Note 7) l±10 ±30 ±10 ±30 mV
VOS Temperature Coefficient l±15 ±15 μV/°C
FSE Full-Scale Error VCC = 5V, VREF = 4.096V l±1 ±4 ±3 ±15 LSB
Full-Scale Error Temperature Coefficient l±30 ±30 μV/°C
PSR Power Supply Rejection VREF = 2.5V 0.045 0.18 LSB/V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Input
Input Voltage Range l0V
CC V
Resistance Not in Sleep Mode l35 65 kΩ
Capacitance (Note 6) 15 pF
IREF Reference Current Sleep Mode l0.001 1 μA
Power Supply
VCC Positive Supply Voltage For Specified Performance l2.7 5.5 V
ICC Supply Current VCC = 5V (Note 3)
VCC = 3V (Note 3)
Sleep Mode (Note 3)
l
l
l
450
340
1
730
530
3
μA
μA
μA
DC Performance
Short-Circuit Current Low VOUT = 0V, VCC = 5.5V, VREF = 5.1V, Code = Full
Scale
l10 30 100 mA
Short-Circuit Current High VOUT = VCC = 5.5V, VREF = 5.1V, Code = 0 l10 27 120 mA
AC Performance
Voltage Output Slew Rate Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.60
0.25
V/μs
V/μs
Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) 30 μs
Capacitive Load Driving 1000 pF
Digital I/O
VIH Digital Input High Voltage VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
l
l
2.4
2.0
V
V
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
l
l
0.8
0.6
V
V
VOH Digital Output High Voltage IOUT = –1mA, DOUT Only lVCC – 1 V
VOL Digital Output Low Voltage IOUT = 1mA, DOUT Only l0.4 V
ILK Digital Input Leakage VIN = GND to VCC l±10 μA
CIN Digital Input Capacitance (Note 6) l10 pF
LTC1665/LTC1660
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TIMING CHARACTERISTICS
The l denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 4.5V to 5.5V
t1DIN Valid to SCK Setup l40 ns
t2DIN Valid to SCK Hold l0ns
t3SCK High Time (Note 6) l30 ns
t4SCK Low Time (Note 6) l30 ns
t5CS/LD Pulse Width (Note 6) l80 ns
t6LSB SCK High to CS/LD High (Note 6) l30 ns
t7CS/LD Low to SCK High (Note 6) l80 ns
t8DOUT Propagation Delay CLOAD = 15pF (Note 6) l580ns
t9SCK Low to CS/LD Low (Note 6) l20 ns
t10 CLR Pulse Width (Note 6) l100 ns
t11 CS/LD High to SCK Positive Edge (Note 6) l30 ns
SCK Frequency Continuous Square Wave (Note 6)
Continuous 23% Duty Cycle Pulse (Note 6)
Gated Square Wave (Note 6)
l
l
l
5.00
7.69
16.7
MHz
MHz
MHz
VCC = 2.7V to 5.5V
t1DIN Valid to SCK Setup (Note 6) l60 ns
t2DIN Valid to SCK Hold (Note 6) l0ns
t3SCK High Time (Note 6) l50 ns
t4SCK Low Time (Note 6) l50 ns
t5CS/LD Pulse Width (Note 6) l100 ns
t6LSB SCK High to CS/LD High (Note 6) l50 ns
t7CS/LD Low to SCK High (Note 6) l100 ns
t8DOUT Propagation Delay CLOAD = 15pF (Note 6) l5 150 ns
t9SCK Low to CS/LD Low (Note 6) l30 ns
t10 CLR Pulse Width (Note 6) l120 ns
t11 CS/LD High to SCK Positive Edge (Note 6) l30 ns
SCK Frequency Continuous Square Wave (Note 6)
Continuous 28% Duty Cycle Pulse
Gated Square Wave
l
l
l
3.85
5.55
10
MHz
MHz
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined from code 4 to code
255 for the LTC1665 and from code 20 to code 1023 for the LTC1660.
See Applications Information.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes 26 and 230 for the LTC1665 or codes 102 and 922 for the
LTC1660.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured at code 4 for the LTC1665 and code 20 for the
LTC1660.
LTC1665/LTC1660
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TYPICAL PERFORMANCE CHARACTERISTICS
Minimum VOUT
vs Load Current (Output Sinking) Large-Signal Step Response
Supply Current vs Temperature
Supply Current
vs Logic Input Voltage
Midscale Output Voltage
vs Load Current
Midscale Output Voltage
vs Load Current
Minimum Supply Headroom
vs Load Current (Output Sourcing)
(LTC1665/LTC1660)
IOUT (mA)
–30 –20 –10 0 10 20 30
VOUT (V)
166560 G01
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
VCC = 4.5V
VCC = 5V
VCC = 5.5V
VREF = VCC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
SINKSOURCE
IOUT (mA)
–15 –4–8–12 0 4 8 12 15
VOUT (V)
166560 G02
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
VCC = 2.7V
VCC = 3V
VCC = 3.6V
VREF = VCC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
SINKSOURCE
0246810
VCC – VOUT (mV)
166560 G03
1400
1200
1000
800
600
400
200
0
–55°C
25°C
125°C
VREF = 4.096V
ΔVOUT < 1LSB
CODE = 255 (LTC1665)
CODE = 1023 (LTC1660)
|
IOUT
|
(mA) (SOURCING)
|
IOUT
|
(mA) (SINKING)
0246810
VOUT (mV)
166560 G04
1400
1200
1000
800
600
400
200
0
–55°C
25°C
125°C
VCC = 5V
CODE = 0
TIME (μs)
0 20406080100
VOUT (V)
166560 G05
5
4
3
2
1
0
10% TO
90% STEP
VCC = VREF = 5V
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
SUPPLY CURRENT (μA)
166560 G06
500
480
460
440
420
400
380
360
340
320
300
VCC = 5.5V
VCC = 4.5V
VCC = 3.6V
VCC = 2.7V
LOGIC INPUT VOLTAGE (V)
012345
SUPPLY CURRENT (mA)
166560 G07
2
1.6
1.2
0.8
0.4
0
ALL DIGITAL INPUTS
SHORTED TOGETHER
LTC1665/LTC1660
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Load Regulation vs Output Current Load Regulation vs Output Current
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1665)
CODE
0 64 128 192 255
LSB
1665/60 G08
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
VCC = 5V
VREF = 4.096V
CODE
0 64 128 192 255
LSB
166560 G09
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
VCC = 5V
VREF = 4.096V
IOUT (mA)
–2 –1 0 1 2
ΔVOUT (LSB)
0.5
0.25
0
–0.25
–0.5
166560 G10
VCC = VREF = 5V
CODE = 128
SINKSOURCE
IOUT (μA)
–500 0 500
ΔVOUT (LSB)
0.5
0.25
0
–0.25
–0.5
166560 G11
SINKSOURCE
VCC = VREF = 3V
CODE = 128
LTC1665/LTC1660
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Load Regulation vs Output Current Load Regulation vs Output Current
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1660)
CODE
0 256 512 768 1023
LSB
166560 G12
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
VCC = 5V
VREF = 4.096V
CODE
0 256 512 768 1023
LSB
166560 G13
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
VCC = 5V
VREF = 4.096V
IOUT (mA)
–2 –1 0 1 2
ΔVOUT (LSB)
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
166560 G14
VCC = VREF = 5V
CODE = 512
SINKSOURCE
IOUT (μA)
–500 0 500
ΔVOUT (LSB)
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
166560 G15
SINKSOURCE
VCC = VREF = 3V
CODE = 512
LTC1665/LTC1660
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BLOCK DIAGRAM
PIN FUNCTIONS
GND (Pin 1): System Ground.
VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Volt-
age Outputs. The output range is
0to 255
256
⎛
⎝
⎜⎞
⎠
⎟VREF for the LTC1665
0to 1023
1024
⎛
⎝
⎜⎞
⎠
⎟VREF for the LTC1660
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
DIN into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 9): Serial Interface Data Input. Data on the DIN
pin is shifted into the 16-bit register on the rising edge of
SCK. CMOS and TTL compatible.
DOUT (Pin 10): Serial Interface Data Output. Data appears
on DOUT 16 positive SCK edges after being applied to DIN.
May be tied to DIN of another LTC1665/LTC1660 for daisy-
chain operation. CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
(LTC1665/LTC1660)
215
1GND
VOUT A
VOUT B
VOUT C
VOUT D
REF
CS/LD
SCK
VCC
VOUT H
VOUT G
VOUT F
VOUT E
CLR
DOUT
DIN
166560 BD
16
DAC A DAC H
3 14
DAC B DAC G
4 13
DAC C DAC F
5
7
6
8
10
11
9
12
DAC D DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
LTC1665/LTC1660
9
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TIMING DIAGRAM
DIN
DOUT
C
S/LD
SCK
A3 A3
A3 A2
A2 X1A1 X0
166560 F01
A1 X1 X0
t2
t8
t9t11
t5t7
t6
t1
t3t4
Figure 1
OPERATION
Transfer Function
The transfer function is:
VOUT(IDEAL) =k
256
⎛
⎝
⎜⎞
⎠
⎟VREF for theLTC1665
VOUT(IDEAL) =k
1024
⎛
⎝
⎜⎞
⎠
⎟VREF for theLTC1660
where k is the decimal equivalent of the binary DAC input
code and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent
and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.2V ≤ VREF ≤ VCC + 0.2V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
Serial Interface
Referring to Figure 2a (2b): With CS/LD held low, data
on the DIN input is shifted into the 16-bit shift register on
the positive edge of
SCK
. The 4-bit DAC address, A3-A0,
is loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word
and causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note:
SCK
must be low before CS/LD is pulled low.
The buffered serial output of the shift register is available
on the DOUT pin, which swings from GND to VCC. Data
appears on DOUT 16 positive SCK edges after being ap-
plied to DIN.
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, DIN and
CS
/LD) by
using the included “daisy-chain” facility. A series of m
chips is configured by connecting each DOUT (except the
last) to DIN of the next chip, forming a single 16m-bit
shift register. The SCK and
CS
/LD signals are common
to all chips in the chain. In use,
CS
/LD is held low while m
16-bit words are clocked to DIN of the first chip;
CS
/LD
is then pulled high, updating all of them simultaneously.
LTC1665/LTC1660
10
166560fa
OPERATION
Sleep Mode
DAC address 1110b is reserved for the special Sleep instruc-
tion (see Table 2). In this mode, the digital interface stays
active while the analog circuits are disabled; static power
consumption is thus virtually eliminated. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
DIN
DOUT
SCK
C
S/LD
A3 A2
INPUT WORD W0
INPUT CODE
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0 A3
166560 F02a
16151413121110987654321
(ENABLE CLK) (UPDATE OUTPUT)
ADDRESS/CONTROL DON’T CARE
INPUT WORD W0
INPUT WORD W–1
DIN
DOUT
SCK
C
S/LD
A3 A2
INPUT WORD W0
INPUT CODE DON’T CARE
A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 A3
166560 F02b
16151413121110987654321
(ENABLE CLK) (UPDATE OUTPUT)
ADDRESS/CONTROL
INPUT WORD W0
INPUT WORD W–1
Figure 2a. LTC1665 Register Loading Sequence
Figure 2b. LTC1660 Register Loading Sequence
Table 1a. LTC1665 Input Word
Table 1b. LTC1660 Input Word
A3 A2 A1
ADDRESS/CONTROL
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 X1 X0D0
INPUT CODE DON’T
CARE
A3 A2 A1
ADDRESS/CONTROL
A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X1 X0X2
DON’T CAREINPUT CODE
LTC1665/LTC1660
11
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OPERATION
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL
DAC STATUS SLEEP STATUSA3 A2 A1 A0
0 0 0 0 No Change Wake
0 0 0 1 Load DAC A Wake
0 0 1 0 Load DAC B Wake
0011Load DAC C Wake
0100Load DAC D Wake
0101Load DAC E Wake
0110Load DAC F Wake
0111Load DAC G Wake
1000Load DAC H Wake
1001 No Change Wake
1010 No Change Wake
1011 No Change Wake
1100 No Change Wake
1101 No Change Wake
1110 No Change Sleep
1111Load ALL DACs
with Same
8/10-Bit Code
Wake
Sleep mode is initiated by performing a load sequence
to address 1110b (the DAC input word D7-D0 [D9-D0]
is ignored). Once in Sleep mode, a load sequence to any
other address (including “No Change” addresses 0000b
and 1001-1101b) causes the LTC1665/LTC1660 to Wake.
It is possible to keep one or more chips of a daisy chain
in continuous Sleep mode by giving the Sleep instruction
to these chips each time the active chips in the chain are
updated.
Voltage Outputs
Each of the eight rail-to-rail output amplifiers contained
in these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85Ω
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1μF
load can be successfully driven by inserting a 20Ω resis-
tor; a 2.2μF load needs only a 10Ω resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
Rail-to-Rail Output Considerations
In any rail-to-rail output voltage DAC, the output is limited
to voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at VCC as shown in Figure 3c. No full-scale limiting can
occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
LTC1665/LTC1660
12
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OPERATION
166560 F03
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
1280 255
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
LTC1665/LTC1660
13
166560fa
TYPICAL APPLICATIONS
A Low Power Quad Trim Circuit with Coarse/Fine Adjustment
VOUT4
VOUT1
VOUT3
VOUT2
R1
COARSE
R1
COARSE
0.1μF
0.1μF
R1
4
1
2
3
11
3.3V 3.3V
R1
COARSE
R1 R2
R2
R2
FINE
R2
FINE
R2
FINE
R1
COARSE
R2
FINE
166560 TA01
215
1
GND
VOUT A
VOUT B
VOUT C
VOUT D
REF
CS/LD
SCK
3-WIRE
SERIAL
INTERFACE
VCC
VOUT H
VOUT G
VOUT F
VOUT E
CLR
TO OTHER
LTC1665s
DOUT
DIN
16
DAC A DAC H
3 14
DAC B DAC G
4 13
DAC C DAC F
5
7
6
8
11
9
12
DAC D DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
0.1μF
0.1μF
3.3V
1
4
2
U1
LTC1665
–
+
U2A
LT®1491
7
6
5
–
+
U2B
LT1491
LTC1258-2.5
0.1μF
0.1μF
R1
14
13
12
R2
–
+
U2D
LT1491
0.1μF
R1
8
9
10
R2
–
+
U2C
LT1491
R2 >> R1
VOUT 1 = VOUT A +
Example: For R1 = 110Ω and R2 = 11k,
VOUT 1 = VOUT A + 0.01 VOUT B
R1
R2 VOUT B
Similarly VOUT 2, VOUT 3, VOUT 4
10
LTC1665/LTC1660
14
166560fa
TYPICAL APPLICATIONS
An 8-Channel Bipolar Output Voltage Circuit Configuration
VOUT D´
±5V
5V
RR
166560 TA04
215
1
GND
VOUT A
VOUT B
VOUT C
VOUT D
REF
CS/LD
CLK
3-WIRE
SERIAL
INTERFACE
VCC
VOUT H
VOUT G
VOUT F
VOUT E
CLR
DOUT
DIN
16
DAC A DAC H
3 14
DAC B DAC G
4 13
DAC C DAC F
5
7
6
8
10
11
9
12
DAC D DAC E
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
U1
LTC1660
14
13
12
–
+
U2D
LT1491
VOUT C´
±5V
RR
8
9
10
–
+
U2C
LT1491
VOUT B´
±5V
RR
7
6
5
–
+
U2B
LT1491
VOUT A´
±5V
R
0.1μF
0.1μF
VS+
VS–
R
1
2
4
11
3
–
+
U2A
LT1491
0.1μF
VOUT E´
±5V
14
13
12
–
+
U3D
LT1491
VOUT F´
±5V
8
9
10
–
+
U3C
LT1491
VOUT G´
±5V
7
6
5
–
+
U3B
LT1491
VOUT H´
±5V
R
0.1μF
0.1μF
VS+
VS–
R
RR
RR
RR
1
24
11
3
–
+
U3A
LT1491
CODE
0
512
1023
VOUT X
–5V
0V
+4.99V
LTC1665/LTC1660
15
166560fa
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG #05-08-1641)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) w 45s
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LTC1665/LTC1660
16
166560fa
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
N16 REV I 0711
.255 ± .015*
(6.477 ± 0.381)
.770*
(19.558)
MAX
16
12345678
910
11
12
13
14
15
.020
(0.508)
MIN
.120
(3.048)
MIN
.130 ± .005
(3.302 ± 0.127)
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.018 ± .003
(0.457 ± 0.076)
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
LTC1665/LTC1660
17
166560fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 1/12 Removed Typical values in Timing Characteristics 3, 4
LTC1665/LTC1660
18
166560fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1999
LT 0112 REV A • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC1661 Dual 10-Bit VOUT DAC in 8-Lead MSOP Package VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output
LTC1663 Single 10-Bit VOUT DAC in SOT-23 Package VCC = 2.7V to 5.5V, Internal Reference, 60μA
LTC1446/
LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448 Dual 12-Bit VOUT DAC in SO-8 Package VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454/
LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458/
LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1590 Dual 12-Bit IOUT DAC in SO-16 Package VCC = 4.5V to 5.5V, 4-Quadrant Multiplication
LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package
VCC: 2.7V to 5.5V
Low Power Multiplying VOUT DAC. Output Swings from GND to
REF. REF Input Can Be Tied to VCC
LT1460 Micropower Precision Series Reference, 2.5V, 5V, 10V Versions 0.075% Max, 10ppm/°C Max, Only 130μA Supply Current
2
61611
DAC A
CLR VCC REF
5V
U1 LTC1660
0.1μF
0.1μF
0.1μF
VA3
VH´ = VH + ΔVH
VL´ = VL + VL
VL´
1
2
VH
(FROM MAIN DAC)
VL
(FROM MAIN DAC)
10V
–5V
RG
50k
RF
5k
VB
VC
VD
GND
166560 TA03
3
DAC B
0.1μF
RG
50k
RG
50k
RG
50k
–
+U2A
LT1369
QUAD
0.1μF
5
7
6
RF
5k
RF
5k
RF
5k
LOGIC
DRIVE
PIN DRIVER
(1 OF 2)
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
CS/LD
SCK
DIN
4
5
8
1
9
7
–
+U2B
LT1369
QUAD
VLVOUT
VH
CODE A
512
512
512
CODE B
1023
512
0
ΔVH, ΔVL
–250mV
0
+250mV
VA = VC = 2.5V
For Resistor Values Shown:
Adjustment Range = 250mV
Adjustment Step Size = 500μV
Note: DACs E Through H Can Be
Configured for a Second Pin Driver
With U2C and U2D of the LT1369
VH´ = VH + (VA – VB)
RF
RG
VL´ = VL + (VC – VD)
RF
RG
VH´
A Pin Driver VH and VL Adjustment Circuit for ATE Applications
