TDA9984AHW/15/C181 - NXP Semiconductors

1. General description

The TDA9984A is a HDMI transmitter (which also supports DVI) which allows mixing a

3×8-bit RGB or Y-CB-CRvideo stream with a pixel rate up to 150 MHz together with up to

4 S/PDIF or I2S-bus audio streams with an audio sampling rate up to 192 kHz.

A programmable upscaling block allows creating a 1080p output from a standard deﬁnition

input. An intraﬁeld deinterlacer is included in the scaler.

In order to be compatible with most applications, and thanks to the integration of a fully

programmable input formatter and color space conversion block, the video input formats

accepted also include Y-CB-CR4:4:4(upto3×8-bit), Y-CB-CR4:2:2semi-planar (up

to 2 × 12-bit) and Y-CB-CR 4:2:2 compliant with ITU656 (up to 1 ×12-bit). In case of

ITU656-like format, the input pixel clock can be made active on both edges.

The TDA9984A includes a HDCP 1.2 compliant cipher block. The HDCP key set can be

stored internally in a non-volatile OTP memory for maximum security.

The TDA9984A includes a true I2C-bus master interface for DDC communication for EDID

purpose and HDCP purpose.

The TDA9984A can be controlled by an I2C-bus interface.

2. Features

n3× 8-bit video data input buses; CMOS and LV-TTL compatible

nHorizontal synchronization, vertical synchronization and data enable inputs or VREF,

HREF and FREF inputs which can be used for synchronization

nPixel rate clock input can be made active on one or both edges; selectable via I2C-bus

n4 I2S-bus audio input channels, 1 S/PDIF channel; audio data rate up to 192 kHz per

input for both standards

n250 MHz to 1.50 GHz TMDS transmitter operation

nProgrammable input formatter and upsampler/interpolator allows input of any of the

4:4:4 or 4:2:2 semi-planar and 4 :2:2 ITU656-like formats

nProgrammable color space converter allows to input RGB video data and to output

RGB or Y-CB-CR 4 : 2 : 2 HDMI video data, or to input Y-CB-CR video data and to

output RGB or Y-CB-CR 4:2:2 HDMI video data; converter can be passed

nUpscaler allows creating a 1080p output from a standard deﬁnition input by using

intelligent edge interpolation

nRepetition of video samples as required by the HDMI standard

nInsertion of HDMI additional information such as InfoFrames

TDA9984A

HDMI transmitter with 1080p upscaler embedded

Rev. 03 — 10 April 2008 Product data sheet

Product data sheet Rev. 03 — 10 April 2008 2 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

nDownstream availability using hot plug detection (HPD input) and receiver detection

(RxSense circuit)

nMaster DDC interface

nDeals with multiple levels of HDCP receivers and repeaters

nInternal SHA-1 calculation

nControllable via I2C-bus

nLow power dissipation

n1.8 V and 3.3 V power supplies

nPower-down mode

nHard reset

nPin-to-pin compatible with TDA9983A/B and TDA9981A/B

nSoftware compatible with TDA9983A/B and TDA9981A/B

3. Applications

nSet-top box

nDVD player

nDVD recorder

nAV receiver

nHome theater

nDigital video camera

nDigital still camera

nPersonal video recorder

nMedia center PCs, graphic cards

nSwitches

Product data sheet Rev. 03 — 10 April 2008 3 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

4. Quick reference data

[1] Video format:

a) Input 480p, ITU656 embedded sync, 48 kHz S/PDIF 2 channels

b) Output 1080p, Y-CB-CR 4 : 2 : 2, 48 kHz S/PDIF

[2] Video format:

a) Input 1080p, Y-CB-CR 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels

b) Output 1080p, Y-CB-CR 4 : 2 : 2, 48 kHz S/PDIF

5. Ordering information

[1] A lead-free package is required to comply with the new legislation.

Table 1. Quick reference data

DD(3V3)

= 3.3 V; V

DD(1V8)

= 1.8 V; V

= 0 V; T

amb

Cto70

C; unless otherwise speciﬁed.

Typical values are measured at T

amb

= 25

C and f

clk

= 150 MHz.

Symbol Parameter Conditions Min Typ Max Unit

VPP programming voltage 5.0 5.25 5.5 V

VDDA(FRO)(3V3) free running oscillator analog supply

voltage (3.3 V) 3.0 3.3 3.6 V

VDDA(PLL)(3V3) PLL analog supply voltage (3.3 V) 3.0 3.3 3.6 V

VDDD(3V3) digital supply voltage (3.3 V) 3.0 3.3 3.6 V

VDDH(3V3) HDMI supply voltage (3.3 V) 3.0 3.3 3.6 V

VDDC(1V8) core supply voltage (1.8 V) 1.65 1.8 1.95 V

Pcons power consumption input 480p, output 1080p [1] - 500 630 mW

input 1080p, output 1080p [2] - 320 400 mW

Ptot total power dissipation TMDS output current added

input 480p, output 1080p [1] - 630 770 mW

input 1080p, output 1080p [2] - 450 540 mW

Ppd power dissipation in power-down

mode - 3040mW

Table 2. Ordering information

Type number Package[1]

Name Description Version

TDA9984AHW HTQFP80 plastic thermal enhanced thin quad ﬂat package;

80 leads; body 12 ×12 ×1 mm; exposed die pad SOT841-4

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xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

Product data sheet Rev. 03 — 10 April 2008 4 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

6. Block diagram

The device can handle HDCP based on 1.2 features.

Fig 1. Block diagram

001aag595

2 × 12-bit Y-CB-CR 4 : 2 : 2 semi-planar

1 × 12-bit Y-CB-CR 4 : 2 : 2 ITU656

3 × 8-bit RGB or Y-CB-CR 4 : 4 : 4

2 × 12-bit Y-CB-CR 4 : 2 : 2 semi-planar

1 × 12-bit Y-CB-CR 4 : 2 : 2 ITU656

TDA9984AHW

DOWN-

SAMPLER

4 : 4 : 4

4 : 2 : 2

VIDEO

INPUT

PROCESSOR

COLOR

SPACE

CONVERTER

RGB to Y-CB-CR

Y-CB-CR to RGB

UPSAMPLER

4 : 2 : 2

4 : 4 : 4

UPSCALER

4 : 2 : 2

AUDIO

PROCESSING

CLOCK

MANAGMENT

AUDIO

FIFO

CTS/N

AUDIO CONTENT

AUDIO INFO-FRAME

ACR

VIDEO INFO-FRAME

OTHER INFO-FRAME

HPD

MANAGEMENT

RxSENSE

INT

HPD

INTERRUPT

GENERATION

DATA

ISLAND

PACKET

INSERTION

VHREF GENERATOR

TMDS

SERIALIZER

26 TXC−

27 TXC+

29 TX0−

30 TX0+

32 TX1−

33 TX1+

35 TX2−

36 TX2+

I2C-BUS REGISTERS

I2C-BUS

SLAVE

HDCP

PROCESSING

OTP

MEMORY

KEYS

I2C_SCL I2C_SDA DDC_SDA DDC_SCL

43 44 19 20

4140

HARD

RESET

RST_N

VPP VDDD(3V3) VDDA(FRO)(3V3)

VDDH(3V3) VDDA(PLL)(3V3)

313, 48, 71

VSSD

14, 47,

VSSC

15, 60,

VSSA(FRO)(3V3)

VSSA(PLL)(1V8)

VSSH

25, 31,

VSSA(PLL)(3V3)

VDDC(1V8)

16, 45,

59, 74 23

28, 34 38

VPA[7:0]

VPB[7:0]

VPC[7:0]

VSYNC/VREF

HSYNC/HREF

DE/FREF

68 to 70

75 to 79

57, 58

61 to 65,

49 to 56

VCLK

AP0 to AP7 4 to 11

TM 21

ACLK 12

DDC BUS

MASTER

EXT_SWING

Product data sheet Rev. 03 — 10 April 2008 5 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

7. Pinning information

7.1 Pin description

Fig 2. Pin conﬁguration

TDA9984AHW

HSYNC/HREF VSSC

VSYNC/VREF VDDC(1V8)

VPP VPB[6]

AP7 VPB[7]

AP6 VPC[0]

AP5 VPC[1]

AP4 VPC[2]

AP3 VPC[3]

AP2 VPC[4]

AP1 VPC[5]

AP0 VPC[6]

ACLK VPC[7]

VDDD(3V3) VDDD(3V3)

VSSD VSSD

VSSC VSSA(PLL)(1V8)

VDDC(1V8) VDDC(1V8)

INT I2C_SDA

HPD I2C_SCL

DDC_SDA RST_N

DDC_SCL A0

TM DE/FREF

VSSA(FRO)(3V3) VPA[0]

VDDA(FRO)(3V3) VPA[1]

EXT_SWING VPA[2]

VSSH VPA[3]

TXC−VPA[4]

TXC+ VDDC(1V8)

VDDH(3V3) VSSC

TX0−VSSD

TX0+ VDDD(3V3)

VSSH VPA[5]

TX1−VPA[6]

TX1+ VPA[7]

VDDH(3V3) VPB[0]

TX2−VCLK

TX2+ VPB[1]

VSSH VPB[2]

VDDA(PLL)(3V3) VPB[3]

VSSA(PLL)(3V3) VPB[4]

A1 VPB[5]

001aag597

Table 3. Pin description

Symbol Pin Type[1] Description

HSYNC/HREF 1 I horizontal synchronization or reference input

VSYNC/VREF 2 I vertical synchronization or reference input

VPP 3 P programming voltage for OTP memory; connect to

ground for digital core in normal operation

AP7 4 I audio port 7 input

AP6 5 I audio port 6 input

AP5 6 I audio port 5 input

AP4 7 I audio port 4 input

AP3 8 I audio port 3 input

Product data sheet Rev. 03 — 10 April 2008 6 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

AP2 9 I audio port 2 input

AP1 10 I audio port 1 input

AP0 11 I audio port 0 input

ACLK 12 I audio clock input

VDDD(3V3) 13 P digital supply voltage for I/O ports (3.3 V)

VSSD 14 G digital ground for I/O ports

VSSC 15 G ground for digital core

VDDC(1V8) 16 P supply voltage for digital core (1.8 V)

INT 17 O interrupt output; warns the external microprocessor that

a special event has occurred

HPD 18 I hot plug detect input; 5 V tolerant

DDC_SDA 19 I/O DDC bus data input/output; 5 V tolerant

DDC_SCL 20 I DDC bus clock input; 5 V tolerant

TM 21 I internal test mode input; connect to ground

VSSA(FRO)(3V3) 22 G analog ground for free running oscillator

VDDA(FRO)(3V3) 23 P analog supply voltage for free running oscillator (3.3 V)

EXT_SWING 24 I swing adjust input for TMDS output; a ﬁxed resistor must

be connected to VDDH(3V3)

VSSH 25 G ground for TMDS (HDMI) transmitter

TXC−26 O negative clock channel for TMDS output

TXC+ 27 O positive clock channel for TMDS output

VDDH(3V3) 28 P supply voltage for TMDS (HDMI) transmitter (3.3 V)

TX0−29 O negative data channel 0 for TMDS output

TX0+ 30 O positive data channel 0 for TMDS output

VSSH 31 G ground for TMDS (HDMI) transmitter

TX1−32 O negative data channel 1 for TMDS output

TX1+ 33 O positive data channel 1 for TMDS output

VDDH(3V3) 34 P supply voltage for TMDS (HDMI) transmitter (3.3 V)

TX2−35 O negative data channel 2 for TMDS output

TX2+ 36 O positive data channel 2 for TMDS output

VSSH 37 G ground for TMDS (HDMI) transmitter

VDDA(PLL)(3V3) 38 P analog supply voltage for PLL (3.3 V)

VSSA(PLL)(3V3) 39 G analog ground for PLL

A1 40 I I2C-bus slave address bit 1 input

A0 41 I I2C-bus slave address bit 0 input

RST_N 42 I hard reset input; active LOW

I2C_SCL 43 I I2C-bus clock input

I2C_SDA 44 I/O I2C-bus data input/output

VDDC(1V8) 45 P supply voltage for digital core (1.8 V)

VSSA(PLL)(1V8) 46 G analog ground for PLL

VSSD 47 G digital ground for I/O ports

Table 3. Pin description

…continued

Symbol Pin Type[1] Description

Product data sheet Rev. 03 — 10 April 2008 7 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

[1] P = Power supply; G = Ground; I = Input; O = Output.

VDDD(3V3) 48 P digital supply voltage for I/O ports (3.3 V)

VPC[7] 49 I video port C input bit 7 (MSB)

VPC[6] 50 I video port C input bit 6

VPC[5] 51 I video port C input bit 5

VPC[4] 52 I video port C input bit 4

VPC[3] 53 I video port C input bit 3

VPC[2] 54 I video port C input bit 2

VPC[1] 55 I video port C input bit 1

VPC[0] 56 I video port C input bit 0 (LSB)

VPB[7] 57 I video port B input bit 7 (MSB)

VPB[6] 58 I video port B input bit 6

VDDC(1V8) 59 P supply voltage for digital core (1.8 V)

VSSC 60 G ground for digital core

VPB[5] 61 I video port B input bit 5

VPB[4] 62 I video port B input bit 4

VPB[3] 63 I video port B input bit 3

VPB[2] 64 I video port B input bit 2

VPB[1] 65 I video port B input bit 1

VCLK 66 I video pixel clock input

VPB[0] 67 I video port B input bit 0 (LSB)

VPA[7] 68 I video port A input bit 7 (MSB)

VPA[6] 69 I video port A input bit 6

VPA[5] 70 I video port A input bit 5

VDDD(3V3) 71 P digital supply voltage for I/O ports (3.3 V)

VSSD 72 G digital ground for I/O ports

VSSC 73 G ground for digital core

VDDC(1V8) 74 P supply voltage for digital core (1.8 V)

VPA[4] 75 I video port A input bit 4

VPA[3] 76 I video port A input bit 3

VPA[2] 77 I video port A input bit 2

VPA[1] 78 I video port A input bit 1

VPA[0] 79 I video port A input bit 0

DE/FREF 80 I video data enable or ﬁeld reference input

Table 3. Pin description

…continued

Symbol Pin Type[1] Description

Product data sheet Rev. 03 — 10 April 2008 8 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8. Functional description

The TDA9984A is designed to convert digital data (video and audio) provided by a

Set-Top Box or DVD into an HDMI output, which could be used in TV with HDMI or DVI

input.

The TDA9984A is able to output HDMI with the formats:

•RGB

•Y-CB-CR 4 : 4 : 4

•Y-CB-CR 4 : 2 : 2

The video data input formats are:

•RGB

•Y-CB-CR 4 : 4 : 4

•Y-CB-CR 4 : 2 : 2 semi-planar

•Y-CB-CR 4 : 2 : 2 ITU656-like

It can also handle audio formats:

•4 I2S-bus channels

•1 S/PDIF channel

8.1 Video processing

The TDA9984A has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0] and can

handle any of the following video input modes:

•RGB with 8-bit for each component

•Y-CB-CR 4 : 4 : 4 with 8-bit for each component

•Y-CB-CR 4 : 2 : 2 semi-planar with up to 12-bit for each component (Y, CB and CR)

•Y-CB-CR 4 : 2 : 2 ITU656 with up to 12-bit data depth

The TDA9984A can be set to latch data at either the rising or the falling edge.

8.1.1 Internal assignment

The aim of the video input processor is to map internally the incoming data to the

corresponding mode, which can be handled by the video processing. The device expects

to have a big endian digital stream at its input. The internal signal name VP[23:0] is

assigned depending on the input mode as deﬁned in Figure 3.

Fig 3. Internal assignment of VP[23:0]

VIDEO

INPUT

PROCESSOR

001aag599

VPA[7:0]

VPB[7:0] VP[23:0]

VPC[7:0]

Product data sheet Rev. 03 — 10 April 2008 9 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

The device can swap and invert (in case of a little endian stream) the incoming video data

via the I2C-bus registers VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 (page 00h)

to match the expectation of the video processing block; see Table 4.

When input ports are not used, it is possible to map them to internal ground via the

I2C-bus registers ENA_VP_0, ENA_VP_1, ENA_VP_2, GND_VP_0, GND_VP_1 and

GND_VP_2 (page 00h).

8.1.2 Input format mappings

See Table 5 for more information concerning input format supported.

Table 4. Internal assignment

Internal port RGB Y-CB-CR

4 : 4 : 4 4 : 2 : 2 semi-planar 4 : 2 : 2 ITU656-like

VP[23] G[7] Y[7] Y[11] Y-CB-CR[11]

VP[22] G[6] Y[6] Y[10] Y-CB-CR[10]

VP[21] G[5] Y[5] Y[9] Y-CB-CR[9]

VP[20] G[4] Y[4] Y[8] Y-CB-CR[8]

VP[19] G[3] Y[3] Y[7] Y-CB-CR[7]

VP[18] G[2] Y[2] Y[6] Y-CB-CR[6]

VP[17] G[1] Y[1] Y[5] Y-CB-CR[5]

VP[16] G[0] Y[0] Y[4] Y-CB-CR4]

VP[15] B[7] CB[7] Y[3] Y-CB-CR[3]

VP[14] B[6] CB[6] Y[2] Y-CB-CR[2

VP[13] B[5] CB[5] Y[1] Y-CB-CR[1]

VP[12] B[4] CB[4] Y[0] Y-CB-CR[0]

VP[11] B[3] CB[3] CB-CR[11] -

VP[10] B[2] CB[2] CB-CR[10] -

VP[9] B[1] CB[1] CB-CR[9] -

VP[8] B[0] CB[0] CB-CR[8] -

VP[7] R[7] CR[7] CB-CR[7] -

VP[6] R[6] CR[6] CB-CR[6] -

VP[5] R[5] CR[5] CB-CR[5] -

VP[4] R[4] CR[4] CB-CR[4] -

VP[3] R[3] CR[3] CB-CR[3] -

VP[2] R[2] CR[2] CB-CR[2] -

VP[1] R[1] CR[7] CB-CR[1] -

VP[0] R[0] CR[0] CB-CR[0] -

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 03 — 10 April 2008 10 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

[1] Double edge means both rising and falling edges.

Table 5. Inputs of video input formatter

Space color Format Channels Sync Rising

edge Falling

edge Double

edge[1] Transmission

input format Pixel clock

(MHz) Maximum

input format Reference

RGB 4:4:4 3× 8-bit external X - 150 MHz - Section 8.1.2.1

X - 150 MHz -

embedded X - 150 MHz -

X - 150 MHz -

Y-CB-CR4:4:4 3× 8-bit external X - 150 MHz - Section 8.1.2.2

X - 150 MHz -

embedded X - 150 MHz -

X - 150 MHz -

Y-CB-CR4 : 2 : 2 up to 1 ×12-bit

semi-planar external X ITU656-like 54.054 MHz 480p/576p Section 8.1.2.3

X ITU656-like 54.054 MHz 480p/576p

X ITU656-like 27.027 MHz 480p/576p Section 8.1.2.4

embedded X ITU656-like 54.054 MHz 480p/576p Section 8.1.2.5

X ITU656-like 54.054 MHz 480p/576p

X ITU656-like 27.027 MHz 480p/576p Section 8.1.2.6

up to 2 ×12-bit

semi-planar external X SMPTE293M 148.5 MHz 1080p Section 8.1.2.7

X SMPTE293M 148.5 MHz 1080p

embedded X SMPTE293M 148.5 MHz 1080p Section 8.1.2.8

X SMPTE293M 148.5 MHz 1080p

Product data sheet Rev. 03 — 10 April 2008 11 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.2.1 RGB 4:4:4 external sync input (rising edge)

Table 6. RGB 4 :4:4 mapping

Video port A Video port B Video port C Control

Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4 Pin RGB 4 :4:4

VPA[0] B0 VPB[0] G0 VPC[0] R0 HSYNC/HREF used

VPA[1] B1 VPB[1] G1 VPC[1] R1 VSYNC/VREF used

VPA[2] B2 VPB[2] G2 VPC[2] R2 DE/FREF used

VPA[3] B3 VPB[3] G3 VPC[3] R3

VPA[4] B4 VPB[4] G4 VPC[4] R4

VPA[5] B5 VPB[5] G5 VPC[5] R5

VPA[6] B6 VPB[6] G6 VPC[6] R6

VPA[7] B7 VPB[7] G7 VPC[7] R7

DE could also be generated from HSYNC/HREF and VSYNC/VREF

Fig 4. Pixel encoding RGB 4 : 4 : 4 external sync input (rising edge)

001aag380

Bxxx Bxxx...B3B2B1B0

HSYNC/HREF

VSYNC/VREF

DE/FREF

Gxxx Gxxx...G3G2G1G0

Rxxx Rxxx...R3R2R1R0

CONTROL

INPUTS

VPA[7:0]

VCLK

VPB[7:0]

VPC[7:0]

Product data sheet Rev. 03 — 10 April 2008 12 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.2.2 Y-CB-CR 4:4:4 external sync input (rising edge)

Table 7. Y-CB-CR 4 : 4 : 4 mapping

Video port A Video port B Video port C Control

Pin Y-CB-CR 4:4:4 Pin Y-CB-CR 4:4:4 Pin Y-CB-CR 4:4:4 Pin Y-CB-CR 4:4:4

VPA[0] CB0 VPB[0] Y0 VPC[0] CR0 HSYNC/HREF used

VPA[1] CB1 VPB[1] Y1 VPC[1] CR1 VSYNC/VREF used

VPA[2] CB2 VPB[2] Y2 VPC[2] CR2 DE/FREF used

VPA[3] CB3 VPB[3] Y3 VPC[3] CR3

VPA[4] CB4 VPB[4] Y4 VPC[4] CR4

VPA[5] CB5 VPB[5] Y5 VPC[5] CR5

VPA[6] CB6 VPB[6] Y6 VPC[6] CR6

VPA[7] CB7 VPB[7] Y7 VPC[7] CR7

DE could also be generated from HSYNC/HREF and VSYNC/VREF

Fig 5. Pixel encoding Y-CB-CR 4 : 4 : 4 external sync input (rising edge)

001aag381

CBxxx CBxxx...CB3CB2CB1CB0

HSYNC/HREF

VSYNC/VREF

DE/FREF

Yxxx Yxxx...Y3Y2Y1Y0

CRxxx CRxxx...CR3CR2CR1CR0

CONTROL

INPUTS

VPA[7:0]

VCLK

VPB[7:0]

VPC[7:0]

Product data sheet Rev. 03 — 10 April 2008 13 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.2.3 Y-CB-CR 4:2:2 ITU656-like external sync input (rising edge)

Table 8. Y-CB-CR 4 : 2 : 2 ITU656-like rising edge mapping

Video port A Video port B Control

Pin Y-CB-CR4:2:2(ITU656-like) Pin Y-CB-CR4:2:2(ITU656-like) Pin Y-CB-CR 4:2:2

VPA[0] CB0Y

00C

R0Y

10 VPB[0] CB4Y

04C

R4Y

14 HSYNC/HREF used

VPA[1] CB1Y

01C

R1Y

11 VPB[1] CB5Y

05C

R5Y

15 VSYNC/VREF used

VPA[2] CB2Y

02C

R2Y

12 VPB[2] CB6Y

06C

R6Y

16 DE/FREF used

VPA[3] CB3Y

03C

R3Y

13 VPB[3] CB7Y

07C

R7Y

VPA[4] - - - - VPB[4] CB8Y

08C

R8Y

VPA[5] - - - - VPB[5] CB9Y

09C

R9Y

VPA[6] - - - - VPB[6] CB10 Y010 CR10 Y110

VPA[7] - - - - VPB[7] CB11 Y011 CR11 Y111

Fig 6. Pixel encoding Y-CB-CR 4 : 2 : 2 ITU656-like external sync input (rising edge)

001aag383

CRxxx Yxxx...Y1CR0Y0CB0

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPB[7:0]; VPA[3:0]

VCLK

Product data sheet Rev. 03 — 10 April 2008 14 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.2.4 Y-CB-CR 4:2:2 ITU656-like external sync input (rising and falling)

Table 9. Y-CB-CR 4 : 2 : 2 ITU656-like double edge mapping

Video port A Video port B Control

Pin Y-CB-CR 4:2:2

(ITU656-like) Pin Y-CB-CR 4:2:2

VPA[0] CB0Y

00C

R0Y

10 VPB[0] CB4Y

04C

R4Y

14 HSYNC/HREF used

VPA[1] CB1Y

01C

R1Y

11 VPB[1] CB5Y

05C

R5Y

15 VSYNC/VREF used

VPA[2] CB2Y

02C

R2Y

12 VPB[2] CB6Y

06C

R6Y

16 DE/FREF used

VPA[3] CB3Y

03C

R3Y

13 VPB[3] CB7Y

07C

R7Y

VPA[4] ---- VPB[4] CB8Y

08C

R8Y

VPA[5] ---- VPB[5] CB9Y

09C

R9Y

VPA[6] ---- VPB[6] CB10 Y010 CR10 Y110

VPA[7] ---- VPB[7] CB11 Y011 CR11 Y111

Fig 7. Pixel encoding Y-CB-CR 4 : 2 : 2 ITU656-like external sync input (rising and falling)

001aag382

CRxxx Yxxx...Y1CR0Y0CB0

HSYNC/HREF

VSYNC/VREF

DE/FREF

VPB[7:0]; VPA[3:0]

VCLK

CONTROL

INPUTS

Product data sheet Rev. 03 — 10 April 2008 15 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.2.5 Y-CB-CR 4:2:2 ITU656-like embedded sync input (rising edge)

Table 10. Y-CB-CR 4 : 2 : 2 ITU656-like embedded rising edge mapping

Video port A Video port B Control

Pin Y-CB-CR 4:2:2

(ITU656-like) Pin Y-CB-CR 4:2:2

VPA[0] CB0Y

00C

R0Y

10 VPB[0] CB4Y

04C

R4Y

14 HSYNC/HREF not used

VPA[1] CB1Y

01C

R1Y

11 VPB[1] CB5Y

05C

R5Y

15 VSYNC/VREF not used

VPA[2] CB2Y

02C

R2Y

12 VPB[2] CB6Y

06C

R6Y

16 DE/FREF not used

VPA[3] CB3Y

03C

R3Y

13 VPB[3] CB7Y

07C

R7Y

VPA[4] ---- VPB[4] CB8Y

08C

R8Y

VPA[5] ---- VPB[5] CB9Y

09C

R9Y

VPA[6] ---- VPB[6] CB10 Y010 CR10 Y110

VPA[7] ---- VPB[7] CB11 Y011 CR11 Y111

Fig 8. Pixel encoding Y-CB-CR 4 : 2 : 2 ITU656-like embedded sync input (rising edge)

001aag385

CRxxx Yxxx...Y1CR0Y0CB0VPB[7:0]; VPA[3:0]

VCLK

Product data sheet Rev. 03 — 10 April 2008 16 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.2.6 Y-CB-CR 4:2:2 ITU656-like embedded sync input (rising and falling)

Table 11. Y-CB-CR 4 : 2 : 2 ITU656-like embedded double edge mappings

Video port A Video port B Control

Pin Y-CB-CR 4:2:2

(ITU656-like) Pin Y-CB-CR 4:2:2

VPA[0] CB0Y

00C

R0Y

10 VPB[0] CB4Y

04C

R4Y

14 HSYNC/HREF not used

VPA[1] CB1Y

01C

R1Y

11 VPB[1] CB5Y

05C

R5Y

15 VSYNC/VREF not used

VPA[2] CB2Y

02C

R2Y

12 VPB[2] CB6Y

06C

R6Y

16 DE/FREF not used

VPA[3] CB3Y

03C

R3Y

13 VPB[3] CB7Y

07C

R7Y

VPA[4] ---- VPB[4] CB8Y

08C

R8Y

VPA[5] ---- VPB[5] CB9Y

09C

R9Y

VPA[6] ---- VPB[6] CB10 Y010 CR10 Y110

VPA[7] ---- VPB[7] CB11 Y011 CR11 Y111

Fig 9. Pixel encoding Y-CB-CR 4 : 2 : 2 ITU656-like embedded sync input (rising and falling)

001aag384

CRxxx Yxxx...Y1CR0Y0CB0VPB[7:0]; VPA[3:0]

VCLK

Product data sheet Rev. 03 — 10 April 2008 17 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.2.7 Y-CB-CR 4:2:2 semi-planar external input (rising edge)

Table 12. Y-CB-CR 4 : 2 : 2 semi-planar rising edge mapping

Video port A Video port B Video port C Control

Pin Y-CB-CR 4:2:2

semi-planar Pin Y-CB-CR 4:2:2

semi-planar Pin Y-CB-CR

4:2:2

VPA[0] Y00Y

10 VPB[0] Y04Y

14 VPC[0] CB4C

R4 HSYNC/HREF used

VPA[1] Y01Y

11 VPB[1] Y05Y

15 VPC[1] CB5C

R5 VSYNC/VREF used

VPA[2] Y02Y

12 VPB[2] Y06Y

16 VPC[2] CB6C

R6 DE/FREF used

VPA[3] Y03Y

13 VPB[3] Y07Y

17 VPC[3] CB7C

VPA[4] CB0C

R0 VPB[4] Y08Y

18 VPC[4] CB8C

VPA[5] CB1C

R1 VPB[5] Y09Y

19 VPC[5] CB9C

VPA[6] CB2C

R2 VPB[6] Y010 Y110 VPC[6] CB10 CR10

VPA[7] CB3C

R3 VPB[7] Y011 Y111 VPC[7] CB11 CR11

Fig 10. Pixel encoding Y-CB-CR 4 : 2 : 2 semi-planar external input (rising edge)

001aag386

Y5 ...Y4Y3Y2Y1Y0

HSYNC/HREF

VSYNC/VREF

DE/FREF

CR4 ...CB4CR2CB2CR0CB0

CONTROL

INPUTS

VPB[7:0]; VPA[3:0]

VCLK

VPC[7:0]; VPA[7:4]

Product data sheet Rev. 03 — 10 April 2008 18 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.2.8 Y-CB-CR 4:2:2 semi-planar embedded sync input (rising edge)

Table 13. Y-CB-CR 4 : 2 : 2 semi-planar embedded rising edge mapping

Video port A Video port B Video port C Control

Pin Y-CB-CR 4:2:2

semi-planar Pin Y-CB-CR 4:2:2

semi-planar Pin Y-CB-CR

4:2:2

VPA[0] Y00Y

10 VPB[0] Y04Y

14 VPC[0] CB4C

R4 HSYNC/HREF not used

VPA[1] Y01Y

11 VPB[1] Y05Y

15 VPC[1] CB5C

R5 VSYNC/VREF not used

VPA[2] Y02Y

12 VPB[2] Y06Y

16 VPC[2] CB6C

R6 DE/FREF not used

VPA[3] Y03Y

13 VPB[3] Y07Y

17 VPC[3] CB7C

VPA[4] CB0C

R0 VPB[4] Y08Y

18 VPC[4] CB8C

VPA[5] CB1C

R1 VPB[5] Y09Y

19 VPC[5] CB9C

VPA[6] CB2C

R2 VPB[6] Y010 Y110 VPC[6] CB10 CR10

VPA[7] CB3C

R3 VPB[7] Y011 Y111 VPC[7] CB11 CR11

Fig 11. Pixel encoding Y-CB-CR 4 : 2 : 2 semi-planar embedded sync input (rising edge)

001aag387

Y5 ...Y4Y3Y2Y1Y0

CR4 ...CB4CR2CB2CR0CB0

VPB[7:0]; VPA[3:0]

VCLK

VPC[7:0]; VPA[7:4]

Product data sheet Rev. 03 — 10 April 2008 19 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.3 Synchronization

The TDA9984A can be synchronized with external input signals HSYNC and VSYNC or

with extraction of the sync information from embedded sync codes (SAV/EAV) inside the

video.

8.1.3.1 Timing extraction generator

This block can extract the synchronization signals HREF, VREF and FREF from SAV and

EAV in case of embedded synchronization in the data stream.

Synchronization signals can be embedded in Y-CB-CR 4 : 2 : 2 ITU656 (up to 1 ×12-bit)

and semi-planar (up to 2 ×12-bit).

8.1.3.2 Data enable generator

TDA9984A contains a Data Enable (DE) generator. This circuit generates an internal DE

signal for a system which does not provide one. The DE generator is controlled via the

I2C-bus register.

8.1.4 Input and output video format

Due to the ﬂexible video input formatter, the TDA9984A can accept a large range of inputs

formats. This ﬂexibility allows the TDA9984A to be compatible with the maximum number

of MPEG decoders. Moreover, these input formats may be changed in many ways (space

color converter, upsampler and scaler) to be transmitted across the HDMI link.

Table 14 gives the possible inputs and outputs.

8.1.5 Scaler unit

8.1.5.1 Scaler features

The scaler unit has the following features:

•Up-scaling only: to expand input image horizontally and vertically

•Deinterlacer embedded (no need of output memory)

•Data processing: 12-bit data width

Table 14. Inputs and outputs capability

Input Scaler Output

Space color Format Channels Space color Format Channels

RGB 4 : 4 : 4 3 × 8-bit no scaling RGB 4 : 4 : 4 3 × 8-bit

Y-CB-CR4 : 4 : 4 3 × 8-bit

Y-CB-CR4 : 2 : 2 2 × 12-bit

Y-CB-CR4 : 4 : 4 3 × 8-bit no scaling RGB 4 : 4 : 4 3 × 8-bit

Y-CB-CR4 : 4 : 4 3 × 8-bit

Y-CB-CR4 : 2 : 2 2 × 12-bit

Y-CB-CR4 : 2 : 2 upto 1×12-bit

semi-planar scaling RGB 4 : 4 : 4 3 × 8-bit

Y-CB-CR4 : 4 : 4 3 × 8-bit

Y-CB-CR4 : 2 : 2 2 × 12-bit

upto2×12-bit

semi-planar scaling RGB 4 : 4 : 4 3 × 8-bit

Y-CB-CR4 : 4 : 4 3 × 8-bit

Y-CB-CR4 : 2 : 2 2 × 12-bit

Product data sheet Rev. 03 — 10 April 2008 20 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

•Maximum output operating frequency is 148.5 MHz; HDTV supported 1080p both PAL

and NTSC

•Input video standards Y-CB-CR 4:2:2 semi-planar and ITU656 (no RGB, nor

Y-CB-CR4:4:4)

8.1.5.2 Input and output video scaler

The scaler will convert the standard deﬁnition (high deﬁnition respectively) video signals

(480i/576i, 480p/576p and 720p, 1080i respectively) into 1080p as described in Figure 12.

Remark: All 4:2:2 input video formats can be by passed, as well as all RGB and

Y-CB-CR4 : 4 : 4 input data, which will be directly fed to the color space converter.

8.1.6 Upsampler

The incoming Y-CB-CR 4:2:2 (2×12-bit) data stream format can be upsampled into an

8-bit Y-CB-CR 4:4:4 (3×8-bit) data stream by repeating or linearly interpolating the

chrominance pixels.

All upscaling modes are available only for Y-CB-CR 4 : 2 : 2 input format.

(1) Pass through

(2) Upscaling

(3) Upscaling and interlacing

(4) Deinterlacing

(5) Deinterlacing and upscaling

(6) Deinterlacing, upscaling and interlacing

Fig 12. Input and output video scaler

001aag603

720

1280

1920

720

1920

480p

720p

1080i

480i

1080p

2, 3

6, 7 (NTSC)

720

1280

1920

720

1920

576p

720p

1080i

576i

1080p

720

1280

1920

720

1920

480p

720p

1080i

480i

1080p

720

1280

1920

720

1920

576p

720p

1080i

576i

1080p

17, 18

21, 22 (PAL)

2, 3

6, 7 (NTSC)

17, 18

21, 22 (PAL)

VIDEO STANDARD OUTPUT

VIDEO STANDARD INPUT

FORMAT

861B

FORMAT

861B

(1)

(2) (2)

(2)

(4)

(5)

(2)

(3)

(3) (2)

(2)

(4)

(5)

(1)

(6)

(5)

(4)

(1)

Product data sheet Rev. 03 — 10 April 2008 21 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.1.7 Color space converter

The color-space converter is used to convert input video data from one type to another

color space (e.g. RGB to Y-CB-CRand Y-CB-CRto RGB). This block can be by passed and

each coefﬁcient is programmable by the I2C-bus registers.

8.1.8 Downsampler

This block works only with Y-CB-CRinput format. These ﬁlters downsample the CBand CR

signals by a factor of 2. A delay is added on the G/Y channel, which corresponds to the

pipeline delay of the ﬁlters, to put the Y channel in phase with the CB and CR channel.

8.2 Audio processing

The TDA9984A is compatible with audio features as per

HDMI speciﬁcation, Rev. 1.2a

•S/PDIF

•I2S-bus up to 4 channels

S/PDIF or I2S-bus can be selected via the I2C-bus. Only one audio format can be used at

a same time. Table 15 shows the audio port allocation.

All audio ports are LV-TTL compatible.

It is possible to map internally an unused port to internal ground via the I2C-bus registers

ENA_APx and GND_APx on page 00h (both audio inputs and clock input as well).

8.2.1 S/PDIF

The audio port AP6 is used for this feature. In this format, the TDA9984A supports

2-channel uncompressed PCM data (IEC 60958) layout 0, or compressed bit stream up to

8 multi-channels (Dolby Digital, DTS, AC3, etc.) layout 1.

CRR

CBB

C11 C12 C13

C21 C22 C23

C31 C32 C33

RCR

BCB

OinGY

OinRCR

OinBCB







OoutYG

OoutCRR

OoutCBB

Table 15. Audio port conﬁguration

Audio port Format

S/PDIF I2S-bus

AP0 - WS (word select)

AP1 - I2S-bus channel 0

AP2 - I2S-bus channel 1

AP3 - I2S-bus channel 2

AP4 - I2S-bus channel 3

AP5 MCLK -

AP6 S/PDIF input -

AP7 AUX (internal test) AUX (internal test)

ACLK - SCK

Product data sheet Rev. 03 — 10 April 2008 22 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

The TDA9984A is able to recover the original clock from the S/PDIF signal (no need of

external clock). In addition, it can also use an external clock to decode the S/PDIF signal.

8.2.2 I2S-bus

There are 4 I2S-bus stereo inputs channels (AP1, AP2, AP3 and AP4) which allow

carrying 8 uncompressed audio channels. The I2S-bus input interface receives an I2S-bus

signal including serial data in, word select and serial clock. Various I2S-bus formats are

supported and can be selected by setting the appropriate bits of the register. Typical

waveforms for the I2S-bus signals at 64fs are given in Figure 13.

The I2S-bus input interface can receive up to 24-bit wide audio samples via the serial data

input with a clock frequency of at least 32 times the input sample frequency fs. Audio

samples with a precision better than 24 bits are truncated to 24-bit format.

a. Philips format

b. Left justiﬁed format

c. Right justiﬁed format

Fig 13. I2S-bus formats

001aag607

DATA

MSB LSB24-bits audio sample word 0 0 0

ACLK(64fs)

LEFT CHANNEL

(n−1) RIGHT CHANNEL

(n−1) LEFT CHANNEL

(n) RIGHT CHANNEL

(n) LEFT CHANNEL

(n+1) RIGHT CHANNEL

(n+1)

001aag608

DATA

MSB LSB24-bits audio sample word 0 0 0

ACLK(64fs)

LEFT CHANNEL

(n−1) RIGHT CHANNEL

(n−1) LEFT CHANNEL

(n) RIGHT CHANNEL

(n) LEFT CHANNEL

(n+1) RIGHT CHANNEL

(n+1)

001aag609

DATA

MSB LSB24-bits audio sample word0 0 0

ACLK(64fs)

LEFT CHANNEL

(n−1) RIGHT CHANNEL

(n−1) LEFT CHANNEL

(n) RIGHT CHANNEL

(n) LEFT CHANNEL

(n+1) RIGHT CHANNEL

(n+1)

Product data sheet Rev. 03 — 10 April 2008 23 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

If the input clock has a frequency of 32fs, only 16-bit audio samples can be received. If the

input clock has a frequency of 64fs, the audio word is truncated to 24-bit format and

padded with zeros.

The word select signal WS indicates whether left or right channel information is

transferred over the serial data.

8.3 HDCP processing

8.3.1 High-bandwidth digital content protection

The HDMI transmitter contains an HDCP function, which encrypts the transmitted stream

content (both video and audio). This function can be enabled and disabled via the I2C-bus.

The keys can be stored internally in OTP non-volatile memory or can be loaded via the

I2C-bus. As the keys are stored internally, the security is maximized.

8.3.1.1 Repeater function

The TDA9984A can be used in a repeater device according to the

HDCP speciﬁcation,

Rev 1.2

. The TDA9984A is able to store the KSV list of a maximum of 127 devices in a

8.3.1.2 SHA-1

To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the

downstream repeater. For security purposes and in order to relieve the microcontroller,

the SHA-1 has been implemented within the TDA9984A.

This calculation is worked out after the transmitter has loaded the KSV list (see

HDCP

speciﬁcation, Rev 1.2

). If SHA-1 calculated by transmitter equals the SHA-1 calculated by

repeater, then an interrupt is sent.

8.4 TMDS serializer

8.4.1 RxSense detection

The TDA9984A has the capability to sense the receiver connectivity and working

behavior. This feature detects the presence of the 50 Ω pull-up resistor RT on the

downstream site onto the TMDS clock channel.

Fig 14. Receiver sensitivity detection

TRANSMITTER

RECEIVER

VDDA

001aag601

Product data sheet Rev. 03 — 10 April 2008 24 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

As long as the receiver is connected to the transmitter and powered up, bit RXS_FIL is set

to logic 1 (see register INT_FLAGS_3, page 00h, address 12h).

As soon as the cable is unplugged or the receiver site is powered off (assuming in this

case that VDD is switched off), the RxSense generates an interrupt inside the TDA9984A,

changing the value of bit RXS_FIL to logic 0. This allows the application to stop sending

unnecessary video content.

This feature is very useful when the receiver has been recovered from an off-state and

does not generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case,

RxSense will generate an interrupt so that the TDA9984A restarts sending video.

Remark: According to the HDMI speciﬁcation, only the HPD interrupt allows the

application to read the EDID. RxSense is not mandatory to initialize the EDID reading

procedure.

8.4.2 TMDS output buffers

The TMDS output amplitude can be adjusted via an external resistor connected between

pins EXT_SWING and VDDH(3V3); see Figure 15.

It is strongly recommended to use REXT_SWING = 610 Ω± 1 % to get a nominal swing of

500 mV. By doing so, the TDA9984A shall meet the minimum low-level output voltage as

per

HDMI speciﬁcation, Rev 1.2a

, table 4-12.

8.4.3 Pixel repetition

To transmit video formats with pixel rates below 25 Msample/s or to increase the number

of audio sample packets in each frame, the TDA9984A uses pixel repetition to increase

the number of pixels sent by the frame. The pixel clock is multiplied by the same factor as

given in Table 16.

(1) Swing character data

(2) Upper limit (600 mV)

(3) Lower limit (400 mV)

Fig 15. TMDS single-ended output swing as a function of external resistor REXT_SWING

001aag602

REXT_SWING (Ω)

500 800700600

450

550

650

Vo(se)

(mV)

350

(1)

(2)

(3)

Product data sheet Rev. 03 — 10 April 2008 25 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.5 Control blocks

8.5.1 Clock management

The system clock is composed of a series of 3 PLLs, which will generates different clocks

in the system taking into account the double edge, the scaling ratio and the serialization.

Here is described brieﬂy the clock system architecture:

•PLL double edge: generates a clock at twice the VCLK input frequency to capture

correctly the data at the video formatter input

•PLL scaling: creates a new video processing scaled clock taking into account the

scaling ratio programmed in the scaler

•PLL serializer: a system clock generator, which enables the stream produced by the

encoder to be transmitted on the TMDS data channel at ten times or above the

sampling rate; see Section 8.4.3

Each PLL can be bypassed via the I2C-bus and then external clock VCLK can be provided

independently to each block.

8.5.2 Interrupt controller

Pin INT is used to alert the microcontroller that a critical event concerning the HDMI has

occurred. Some of theses interrupts are maskable. See Table 17 for the interrupt types

generated by the TDA9984A.

Table 16. Pixel repetition

PR[3:0] Pixel repetition factor

0000 no repetition: pixel sent once

0001 2 times: pixel repeated once

0010 3 times

0011 4 times

0100 5 times

0101 6 times

0110 7 times

0111 8 times

1000 9 times

1001 10 times

Others reserved

Product data sheet Rev. 03 — 10 April 2008 26 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

8.5.3 Hot plug detection

Pin HPD is the hot plug detect pin; it is 5 V input tolerant. When asserted, the hot plug

detect signal tells the transmitter that the receiver is connected. When changing from

LOW to HIGH, the TDA9984A has to read EDID to match the video format to the format

the receiver can handle.

8.5.4 Initialization

After power-up, the TDA9984A is activated by a hard reset. Pin RST_N can be used to

activate the TDA9984A in a known state.

The device also offers the possibility to perform a soft reset that will affect a certain

number of I2C-bus registers, but not all of them. This soft reset is also mandatory for a

proper initialization of the device.

8.5.5 Power management

The TDA9984A can be powered down via the I2C-bus register. In this mode, all PLLs are

switched off and the biasing structure of the output stage is disconnected (all activity is

reduced). Therefore, the TDA9984A has a very low power consumption which is suitable

for portable applications.

8.6 DDC interface

8.6.1 DDC channel

The DDC pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at standard mode

(100 kHz) and fast mode (400 kHz). The DDC is used as a master interface in case of

EDID reading, and while proceeding for HDCP. It is recommended not going beyond

100 kHz for EDID as claimed by the HDMI speciﬁcation. This frequency is linked to the

internal free running oscillator whose nominal frequency is 30 MHz as:

Table 17. Interrupts

Interrupt Deﬁnition Maskable

feature

Domain Interrupt name

HDCP r0 R0 = R’0 check done maskable

pj Pj = P’j check fails

sha-1 V = V’ check success

bstatus Bstatus available

bcaps Bcaps available

t0 HDCP goes to initial state

security HDCP encryption is off or blue

screen removed not maskable

HPD hpd transition on HPD input maskable

RxSense rx_sense transition on RxSense

EDID edid_block_rd EDID block read ﬁnished

Interrupt sw_intsoftware test purpose

fDDC fFRO

32N

clk div–

----------------------------------

Product data sheet Rev. 03 — 10 April 2008 27 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

Where:

fFRO = free running oscillator frequency

Nclk-div = value set by register

Then for convenience, it is recommended to keep the same frequency for HDCP purpose.

8.6.2 E-EDID

8.6.2.1 E-EDID reading

As a master interface for the EDID process, the DDC is compliant to the

C-bus

speciﬁcation

and has the possibility of the repeat and start condition to enable quick

access to the EDID content, as well as the large EDID reading possibility (with the use of

a segment pointer).

The TDA9984A has a full I2C-bus page (page 09h) dedicated to the EDID where 1 block

can be stored. The block can be read by the microprocessor to determine the supported

video and audio format of the downstream site.

Remark: When the block is read by the TDA9984A, it generates an interrupt to warn the

main processor that the TDA9984A is ready to transmit the content. Once the content is

read-out by the microprocessor, it can allow reading other blocks if required.

8.6.2.2 HDMI and DVI receiver discrimination

This information is located in the E-EDID receiver part, more exactly in the ‘Vendor

Speciﬁc Data block within the ﬁrst CEA EDID timing extension.

If the 24-bit IEEE Registration Identiﬁer contains the value 00 0C03h, then the receiver will

support HDMI; otherwise the device shall be treated as a DVI device.

However, even though the TDA9984A have directly access to that information, this is the

task of the microcontroller to ask to switch from DVI to HDMI mode.

8.7 I2C-bus interface

The I2C-bus pins I2C_SDA and I2C_SDL are 5 V tolerant. Pin I2C_SCL is only an input

pin. Both fast mode (400 kHz) and standard mode (100 kHz) are supported. The registers

of the TDA9984A can be accessed via the I2C-bus. All registers are R/W except some,

which cannot be read for conﬁdentiality.

The TDA9984A is used as a slave I2C-bus device. Bits A0 and A1 of the I2C-bus device

address are externally selected by pins A0 and A1 (see Table 18).

The I2C-bus access format is shown in Figure 16.

Firstly, the master writes the TDA9984A address and the subaddress to access the

speciﬁc register, and then the data.

Table 18. Device address

Device address W/R

A6 A5 A4 A3 A2 A1 A0 -

11100pin A1 pin A0 0/1

Product data sheet Rev. 03 — 10 April 2008 28 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

9. I2C-bus registers deﬁnitions

9.1 Memory page management

The I2C-bus memory is split into several pages and the selection between pages is made

with common register CURPAGE_ADR. It is only necessary to write in this register once

to change the current page. So multiple read or write operations in the same page need a

write register CURPAGE_ADR once at the beginning.

9.2 ID version

The ID-version readable via I2C-bus is deﬁned as follows:

•TDA9984AHW will have the value 1000 XXXX

The 4 LSBs are used for indicating the die version.

Fig 16. I2C-bus access

001aaf292

123456789123456789123456789

SLAVE ADDRESS SUBADDRESS

SCL

SDA

DATA STOP

Table 19. Memory pages

Page address Memory page description

00h general control

01h scaler and PLL scaling

02h PLL settings

09h EDID control page

10h InfoFrames and packets

11h audio settings and content info packets

12h HDCP and OTP

Product data sheet Rev. 03 — 10 April 2008 29 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

10. Limiting values

11. Thermal characteristics

Table 20. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD(3V3) supply voltage (3.3 V) −0.5 +4.6 V

VDD(1V8) supply voltage (1.8 V) −0.5 +2.5 V

∆VDD supply voltage difference −0.5 +0.5 V

Tstg storage temperature −55 +150 °C

Tamb ambient temperature 0 70 °C

Tjjunction temperature - 125 °C

Vesd electrostatic discharge voltage human body model - ±2000 V

Table 21. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from

junction to ambient in free air 26.5 K/W

Product data sheet Rev. 03 — 10 April 2008 30 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

12. Static characteristics

[1] Video format:

a) Input 480p, ITU656 embedded sync, 48 kHz S/PDIF 2 channels

b) Output 1080p, Y-CB-CR 4 : 2 : 2, 48 kHz S/PDIF

[2] Video format:

a) Input 1080p, Y-CB-CR 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels

b) Output 1080p, Y-CB-CR 4 : 2 : 2, 48 kHz S/PDIF

Table 22. Supplies

DD(3V3)

= 3.3 V; V

DD(1V8)

= 1.8 V; V

= 0 V; T

amb

Cto70

C; unless otherwise speciﬁed.

Typical values are measured at T

amb

= 25

C and f

clk

= 150 MHz.

Symbol Parameter Conditions Min Typ Max Unit

VPP programming voltage 5.0 5.25 5.5 V

VDDA(FRO)(3V3) free running oscillator analog

supply voltage (3.3 V) 3.0 3.3 3.6 V

VDDA(PLL)(3V3) PLL analog supply voltage (3.3 V) 3.0 3.3 3.6 V

VDDD(3V3) digital supply voltage (3.3 V) 3.0 3.3 3.6 V

VDDH(3V3) HDMI supply voltage (3.3 V) 3.0 3.3 3.6 V

VDDC(1V8) core supply voltage (1.8 V) 1.65 1.8 1.95 V

IDDA(FRO)(3V3) free running oscillator analog

supply current (3.3 V) - 0.1 1 mA

IDDA(PLL)(3V3) PLL analog supply current (3.3 V) - 4 6 mA

IDDD(3V3) digital supply current (3.3 V) - - 5 mA

IDDH(3V3) HDMI supply current (3.3 V) - 14 15 mA

IDDC(1V8) core supply current (1.8 V) - 235 275 mA

Pcons power consumption input 480p, output 1080p [1] - 500 630 mW

input 1080p, output 1080p [2] - 320 400 mW

Ptot total power dissipation TMDS output current added

input 480p, output 1080p [1] - 630 770 mW

input 1080p, output 1080p [2] - 450 540 mW

Ppd power dissipation in power-down

mode - 3040mW

Table 23. LV-TTL digital inputs

DD(3V3)

= 3.3 V; V

DD(1V8)

= 1.8 V; V

= 0 V; T

amb

Cto70

C; typical values are measured at T

amb

= 25

C; unless

otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE

and RST_N

VIL LOW-level input voltage - - 0.8 V

VIH HIGH-level input voltage 2.0 - - V

5 V tolerant input: pin HPD

VIL LOW-level input voltage - - 0.8 V

VIH HIGH-level input voltage 2.0 - - V

Product data sheet Rev. 03 — 10 April 2008 31 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

13. Dynamic characteristics

[1] In case of MCLK is required, this frequency has to be coherent with S/PDIF input.

Output: pin INT

VOL LOW-level output voltage CL = 10 pF; IOL = 2 mA - - 0.4 V

VOH HIGH-level output voltage CL = 10 pF; IOH =−2 mA 2.4 - - V

Table 23. LV-TTL digital inputs

…continued

DD(3V3)

= 3.3 V; V

DD(1V8)

= 1.8 V; V

= 0 V; T

amb

Cto70

C; typical values are measured at T

amb

= 25

C; unless

otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Table 24. TMDS outputs

DD(3V3)

= 3.3 V; V

DD(1V8)

= 1.8 V; V

= 0 V; T

amb

Cto70

C; typical values are measured at T

amb

= 25

C; unless

otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+

VO(dif) differential output voltage REXT_SWING = 610 Ω(1 % tolerance);

RL=50Ω480 525 560 mV

Table 25. Timing characteristics

DD(3V3)

= 3.3 V; V

DD(1V8)

= 1.8 V; V

= 0 V; T

amb

Cto70

C; typical values are measured at T

amb

= 25

C; unless

otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Video inputs; see Figure 17

fclk(max) maximum clock frequency pin VCLK 150 - - MHz

δclk clock duty cycle pin VCLK 40 50 60 %

tsu(D) data input set-up time 1.0 - - ns

th(D) data input hold time 0.8 - - ns

Audio input

S/PDIF mode

fssampling frequency 2 channels 32 - 192 kHz

fclk clock frequency pin AP5 (MCLK) [1] --75MHz

Tclk clock period pin AP5 (MCLK) [1] 13.3 - - ns

δclk clock duty cycle 40 - 60 %

I2S-bus mode

fssampling frequency 32 - 192 kHz

TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+

fclk(max) maximum clock frequency 150 - - MHz

DDC I2C-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL

fSCL SCL clock frequency standard mode - - 100 kHz

fast mode - - 400 kHz

I2C-bus; 5 V tolerant; slave bus: pins I2C_SDA and I2C_SCL

fSCL SCL clock frequency standard mode - - 100 kHz

fast mode - - 400 kHz

Product data sheet Rev. 03 — 10 April 2008 32 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

a. Sync on rising edge

b. Sync on falling edge

c. Sync on rising and falling (double) edge

Data is not allowed to change in the shaded area.

Fig 17. Set-up and hold time for various clock modes

001aag604

VCLK

tsu(D)

VPA[7:0]

VPB[7:0]

VPC[7:0]

DE, HSYNC, VSYNC th(D)

001aag605

VCLK

tsu(D)

VPA[7:0]

VPB[7:0]

VPC[7:0]

DE, HSYNC, VSYNC th(D)

VCLK

VPA[7:0]

VPB[7:0]

VPC[7:0]

DE, HSYNC, VSYNC

001aag606

tsu(D) th(D)

Product data sheet Rev. 03 — 10 April 2008 33 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

13.1 Input format

Mapping of the video ports:

•Port VPA has been mapped to CB for Y-CB-CR space and B for RGB color space

•Port VPB has been mapped to Y for Y-CB-CR space and G for RGB color space

•Port VPC has been mapped to CR for Y-CB-CR space and R for RGB color space

[1] L stands for tying to LOW voltage recommendation, e.g. ground.

Table 26. Input format

Input pins Signal RGB Y-CB-CR

4:4:4 4:4:4 4:2:2 (semi-planar) 4:2:2 (ITU656-like)[1]

Video port A

VPA[0] CB0/B0 B0 CB0Y

00Y

10C

B0Y

00C

R0Y

VPA[1] CB1/B1 B1 CB1Y

01Y

11C

B1Y

01C

R1Y

VPA[2] CB2/B2 B2 CB2Y

02Y

12C

B2Y

02C

R2Y

VPA[3] CB3/B3 B3 CB3Y

03Y

13C

B3Y

03C

R3Y

VPA[4] CB4/B4 B4 CB4C

B0C

R0LLLL

VPA[5] CB5/B5 B5 CB5C

B1C

R1LLLL

VPA[6] CB6/B6 B6 CB6C

B2C

R2LLLL

VPA[7] CB7/B7 B7 CB7C

B3C

R3LLLL

Video port B

VPB[0] Y0/G0 G0 Y0 Y04Y

14C

B4Y

04C

R4Y

VPB[1] Y1/G1 G1 Y1 Y05Y

15C

B5Y

05C

R5Y

VPB[2] Y2/G2 G2 Y2 Y06Y

16C

B6Y

06C

R6Y

VPB[3] Y3/G3 G3 Y3 Y07Y

17C

B7Y

07C

R7Y

VPB[4] Y4/G4 G4 Y4 Y08Y

18C

B8Y

08C

R8Y

VPB[5] Y5/G5 G5 Y5 Y09Y

19C

B9Y

09C

R9Y

VPB[6] Y6/G6 G6 Y6 Y010 Y110 CB10 Y010 CR10 Y110

VPB[7] Y7/G7 G7 Y7 Y011 Y111 CB11 Y011 CR11 Y111

Video port C

VPC[0] CR0/R0 R0 CR0C

B4C

R4LLLL

VPC[1] CR1/R1 R1 CR1C

B5C

R5LLLL

VPC[2] CR2/R2 R2 CR2C

B6C

R6LLLL

VPC[3] CR3/R3 R3 CR3C

B7C

R7LLLL

VPC[4] CR4/R4 R4 CR4C

B8C

R8LLLL

VPC[5] CR5/R5 R5 CR5C

B9C

R9LLLL

VPC[6] CR6/R6 R6 CR6C

B10 CR10 L L L L

VPC[7] CR7/R7 R7 CR7C

B11 CR11 L L L L

Product data sheet Rev. 03 — 10 April 2008 34 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

13.2 Timing parameters for supported video

The TDA9984A supports all EIA/CEA-861B standards and ATSC video input formats.

Table 27. Timing parameters for EIA/CEA-861B

Format Format V frequency

(Hz) H total V total H frequency

(kHz) Pixel frequency

(MHz) Pixel

repetition Scaler

59.94 Hz systems

1 (VGA) 640 × 480p 59.9401 800 525 31.469 25.175 1 -

2, 3 720 × 480p 59.9401 858 525 31.469 27.000 1 X

4 1280 × 720p 59.9401 1650 750 44.955 74.175 1 X

5 1920 × 1080i 59.9401 2200 1125 33.716 74.175 1 X

6, 7 (NTSC) 1440 × 480i 59.9401 1716 525 15.734 27.000 2 X

8, 9 1440 × 240p 59.9401 1716 262 15.734 27.000 2 -

8, 9 1440 × 240p 59.9401 1716 263 15.734 27.000 2 -

10, 11 2880 × 480i 59.9401 3452 525 15.734 54.000 4[1] -

12, 13 2880 × 240p 59.9401 3452 262 15.734 54.000 4[1] -

12, 13 2880 × 240p 59.9401 3452 263 15.734 54.000 4[1] -

14, 15 1440 × 480p 59.9401 1716 525 31.469 54.000 2 -

16 1920 × 1080p 59.9401 2200 1125 67.432 148.350 1 -

60 Hz systems

1 (VGA) 640 × 480p 60.000 800 525 31.500 25.200 1 -

2, 3 720 × 480p 60.000 858 525 31.500 27.027 1 X

4 1280 × 720p 60.000 1650 750 45.000 74.250 1 X

5 1920 × 1080i 60.000 2200 1125 33.750 74.250 1 X

6, 7 (NTSC) 1440 × 480i 60.000 1716 525 15.750 27.027 2 X

8, 9 1440 × 240p 60.000 1716 262 15.750 27.027 2 -

8, 9 1440 × 240p 60.000 1716 263 15.750 27.027 2 -

10, 11 2880 × 480i 60.000 3452 525 15.750 54.054 4[1] -

12, 13 2880 × 240p 60.000 3452 262 15.750 54.054 4[1] -

12, 13 2880 × 240p 60.000 3452 263 15.750 54.054 4[1] -

14, 15 1440 × 480p 60.000 1716 525 31.500 54.054 2 -

16 1920 × 1080p 60.000 2200 1125 67.500 148.50 1 -

50 Hz systems

17, 18 720 × 576p 50.000 864 625 31.250 27.000 1 X

19 1280 × 720p 50.000 1980 750 37.500 74.250 1 X

20 1920 × 1080i 50.000 2640 1125 28.125 74.250 1 X

21, 22 (PAL) 1440 × 576i 50.000 1728 625 15.625 27.000 1 X

23, 24 1440 × 288p 50.000 1728 312 15.625 27.000 2 -

23, 24 1440 × 288p 50.000 1728 313 15.625 27.000 2 -

23, 24 1440 × 288p 50.000 1728 314 15.625 27.000 2 -

25, 26 2880 × 576i 50.000 3456 625 15.625 54.000 4[1] -

27, 28 2880 × 288p 50.000 3456 312 15.625 54.000 4[1] -

27, 28 2880 × 288p 50.000 3456 313 15.625 54.000 4[1] -

Product data sheet Rev. 03 — 10 April 2008 35 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

[1] The format can also be deﬁned with a repetition factor of up to 10.

27, 28 720 × 288p 50.000 3456 314 15.625 54.000 4 -

29, 30 1440 × 576p 50.000 1728 625 31.250 54.000 2 -

31 1920 × 1080p 50.000 2640 1125 56.250 148.50 1 -

Table 27. Timing parameters for EIA/CEA-861B

…continued

Format Format V frequency

(Hz) H total V total H frequency

(kHz) Pixel frequency

(MHz) Pixel

repetition Scaler

Table 28. Timing parameters for ATSC DTV standards, which are not deﬁned in EIA/CEA-861B

Standard Format V frequency

(Hz) H total V total H frequency

(kHz) Pixel frequency

(MHz) Pixel

repetition Scaler

SMPTE-296M 1280 × 720p 30.000 3300 750 22.500 74.250 1 -

29.970 3300 750 22.478 74.175 1 -

25.000 3960 750 18.750 74.250 1 -

23.976 4125 750 17.982 74.175 1 -

Table 29. Timing parameters for PC standards below 165 MHz

Standard Format V frequency

(Hz) H total V total H frequency

(kHz) Pixel frequency

(MHz) Pixel

repetition Scaler

640 × 350p 85.080 832 445 37.861 31.500 1 -

640 × 400p 85.080 832 445 37.861 31.500 1 -

720 × 400p 85.039 936 446 37.937 35.500 1 -

VGA 640 × 480p 59.9401 800 525 31.469 25.175 1 -

72.809 832 525 37.861 31.500 1 -

75.000 840 500 37.500 31.500 1 -

85.008 832 520 43.269 36.000 1 -

SVGA 800 × 600p 56.250 1024 625 35.156 36.000 1 -

60.317 1056 628 37.879 40.000 1 -

72.188 1040 666 48.077 50.000 1 -

75.000 1056 625 46.875 49.500 1 -

85.061 1048 631 53.673 56.250 1 -

XGA 1024 × 768p 60.004 1344 806 48.362 65.000 1 -

70.069 1328 806 56.476 75.000 1 -

75.029 1312 800 60.023 78.750 1 -

84.997 1376 808 68.677 94.500 1 -

1024 × 768i 86.957 1264 817 35.522 44.900 1 -

1152 × 864p 75.000 1600 900 67.500 108.000 1 -

85.000 1576 907 77.094 121.500 1 -

1280 × 960p 60.000 1800 1000 60.000 108.000 1 -

85.002 1728 1011 85.937 148.450 1 -

SXGA 1280 × 1024p 60.002 1688 1066 63.981 108.000 1 -

75.025 1688 1066 79.977 135.000 1 -

Product data sheet Rev. 03 — 10 April 2008 36 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

14. Package outline

Fig 18. Package outline SOT841-4 (HTQFP80)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT841-4 MS-026

SOT841-4

06-04-25

06-06-20

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included

UNIT A

max

mm 1.2 0.15

0.05 1.05

0.95 0.27

0.17 0.20

0.09 12.1

11.9 12.1

11.9 14.15

13.85 14.15

13.85 0.75

0.45 1.45

1.05 1.45

1.05

DIMENSIONS (mm are the original dimensions)

HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad

80 21

61 40

120

60 41

pin 1 index

exposed die pad X

detail X L

(A3)

0 5 10 mm

scale

A2A3

0.25

bpc D(1) E(1) e

0.5

4.79

4.69

4.79

4.69

EhHEL

Lpv

0.2

0.08

0.1

ZD(1) ZE(1) θ

7°

0°

Product data sheet Rev. 03 — 10 April 2008 37 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

15. Abbreviations

Table 30. Abbreviations

Acronym Description

AV Audio Video

CMOS Complimentary Metal-Oxide Semiconductor

DDC Display Data Channel

DE Data Enable

DTS Digital Transmission System

DVD Digital Versatile Disc

DVI Digital Visual Interface

EAV End Active Video

EDID Extended Display Identiﬁcation Data

E-EDID Enhanced Extended Display Identiﬁcation Data

HD High Deﬁnition

HDCP High-bandwidth Digital Content Protection

HDMI High-Deﬁnition Multimedia Interface

HDTV High-Deﬁnition Television

KSV Key Selection Vector

LSB Least Signiﬁcant Bit

LV-TTL Low Voltage Transistor-Transistor Logic

MSB Most Signiﬁcant Bit

OTP One Time Programming

PCM Pulse Code Modulation

PLL Phase-Locked Loop

SAV Start Active Video

SHA-1 Secure Hash Algorithm 1

S/PDIF Sony/Philips Digital Interface

TMDS Transition Minimized Differential Signalling

Y-CB-CRY = luminance, CB = chroma component blue, CR = chroma component red

Product data sheet Rev. 03 — 10 April 2008 38 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

16. Revision history

Table 31. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TDA9984A_3 20080410 Product data sheet - TDA9984A_2

Modiﬁcations: •Table 22: supply currents added

•Removed ﬁgure Set-up and hold time for I2S-bus mode

TDA9984A_2 20080115 Preliminary data sheet - TDA9984_1

TDA9984_1 20070723 Objective data sheet - -

Product data sheet Rev. 03 — 10 April 2008 39 of 40

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors TDA9984A

HDMI transmitter with 1080p upscaler embedded

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 April 2008

Document identifier: TDA9984A_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

5 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Functional description . . . . . . . . . . . . . . . . . . . 8

8.1 Video processing . . . . . . . . . . . . . . . . . . . . . . . 8

8.1.1 Internal assignment . . . . . . . . . . . . . . . . . . . . . 8

8.1.2 Input format mappings . . . . . . . . . . . . . . . . . . . 9

8.1.2.1 RGB 4:4:4 external sync input (rising edge) 11

8.1.2.2 Y-CB-CR 4 : 4 : 4 external sync input

(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8.1.2.3 Y-CB-CR 4 : 2 : 2 ITU656-like external sync

input (rising edge). . . . . . . . . . . . . . . . . . . . . . 13

8.1.2.4 Y-CB-CR 4 : 2 : 2 ITU656-like external sync

input (rising and falling). . . . . . . . . . . . . . . . . . 14

8.1.2.5 Y-CB-CR 4 : 2 : 2 ITU656-like embedded

sync input (rising edge) . . . . . . . . . . . . . . . . . 15

8.1.2.6 Y-CB-CR 4 : 2 : 2 ITU656-like embedded

sync input (rising and falling) . . . . . . . . . . . . . 16

8.1.2.7 Y-CB-CR 4 : 2 : 2 semi-planar external input

(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.1.2.8 Y-CB-CR 4 : 2 : 2 semi-planar embedded sync

input (rising edge). . . . . . . . . . . . . . . . . . . . . . 18

8.1.3 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 19

8.1.3.1 Timing extraction generator . . . . . . . . . . . . . . 19

8.1.3.2 Data enable generator . . . . . . . . . . . . . . . . . . 19

8.1.4 Input and output video format. . . . . . . . . . . . . 19

8.1.5 Scaler unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.1.5.1 Scaler features . . . . . . . . . . . . . . . . . . . . . . . . 19

8.1.5.2 Input and output video scaler . . . . . . . . . . . . . 20

8.1.6 Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.1.7 Color space converter. . . . . . . . . . . . . . . . . . . 21

8.1.8 Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.2 Audio processing . . . . . . . . . . . . . . . . . . . . . . 21

8.2.1 S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.2.2 I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.3 HDCP processing. . . . . . . . . . . . . . . . . . . . . . 23

8.3.1 High-bandwidth digital content protection. . . . 23

8.3.1.1 Repeater function . . . . . . . . . . . . . . . . . . . . . . 23

8.3.1.2 SHA-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.4 TMDS serializer . . . . . . . . . . . . . . . . . . . . . . . 23

8.4.1 RxSense detection . . . . . . . . . . . . . . . . . . . . . 23

8.4.2 TMDS output buffers. . . . . . . . . . . . . . . . . . . . 24

8.4.3 Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 24

8.5 Control blocks. . . . . . . . . . . . . . . . . . . . . . . . . 25

8.5.1 Clock management . . . . . . . . . . . . . . . . . . . . 25

8.5.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 25

8.5.3 Hot plug detection . . . . . . . . . . . . . . . . . . . . . 26

8.5.4 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.5.5 Power management . . . . . . . . . . . . . . . . . . . . 26

8.6 DDC interface. . . . . . . . . . . . . . . . . . . . . . . . . 26

8.6.1 DDC channel . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.6.2 E-EDID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.6.2.1 E-EDID reading . . . . . . . . . . . . . . . . . . . . . . . 27

8.6.2.2 HDMI and DVI receiver discrimination . . . . . . 27

8.7 I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 27

2C-bus registers deﬁnitions . . . . . . . . . . . . . 28

9.1 Memory page management. . . . . . . . . . . . . . 28

9.2 ID version. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29

11 Thermal characteristics . . . . . . . . . . . . . . . . . 29

12 Static characteristics . . . . . . . . . . . . . . . . . . . 30

13 Dynamic characteristics. . . . . . . . . . . . . . . . . 31

13.1 Input format . . . . . . . . . . . . . . . . . . . . . . . . . . 33

13.2 Timing parameters for supported video . . . . . 34

14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 36

15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 38

17 Legal information . . . . . . . . . . . . . . . . . . . . . . 39

17.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 39

17.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 39

17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 39

18 Contact information . . . . . . . . . . . . . . . . . . . . 39

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40