LT4256-3
1
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The LT
®
4256-3 is a high voltage Hot Swap
TM
controller that
allows a board to be safely inserted and removed from a
live backplane. An internal driver controls the high side
N-channel MOSFET gate for supply voltages ranging from
10.8V to 80V. The part features an open-circuit detect
(OPEN) output that indicates abnormally low load current
conditions.
The LT4256-3 also features an adjustable analog foldback
current limit. If the supply remains in current limit for more
than a programmable time, the N-channel MOSFET shuts
off, the PWRGD output asserts low and the LT4256-3
either automatically restarts after a time-out delay or
latches off until the UV pin is cycled low (depending on the
status of the RETRY pin).
The PWRGD output indicates when the output voltage
rises above a programmed level. An external resistor
string from V
CC
provides programmable undervoltage and
overvoltage protection.
The LT4256-3 is available in a 16-lead SSOP package.
■
Hot Board Insertion
■
Electronic Circuit Breaker/Power Bussing
■
Industrial High Side Switch/Circuit Breaker
■
24V/48V Industrial/Alarm Systems
■
Ideally Suited for 12V, 24V and 48V Distributed
Power Systems
■
48V Telecom Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Allows Safe Board Insertion and Removal from a
Live Backplane
■
Controls Supply Voltage from 10.8V to 80V
■
Foldback Current Limiting
■
Open Circuit and Overcurrent Fault Detect
■
Drives an External N-Channel MOSFET
■
Automatic Retry or Latched Off Operation
After Overcurrent Fault
■
Programmable Supply Voltage Power-Up Rate
■
Open MOSFET Detection
■
1% Over and Undervoltage Detection Accuracy
■
Available in a 16-Lead SSOP Package
Positive High Voltage
Hot Swap Controller
with Open-Circuit Detect
4256 TA01
0.020Ω
LT4256-3
SENSEVCC
GATE
FB
VOUT
PWRGD
RETRY
UV
OV
TIMER GND
VIN
48V
GND
(SHORT PIN)
IRF540
CMPZ5241BS
11V
4.02k
4.02k
64.9k
100Ω
4.02k
10Ω36.5k
PWRGD
VOUT
48V
2A
51k
CL
33nF
0.01µF
10nF
OPEN
SMAT70A
UV = 36V
OV = 73V
PWRGD = 40V
+
48V, 2A Hot Swap Controller
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
LT4256-3 Start-Up Behavior
Hot Swap is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
V
IN
50V/DIV
V
OUT
50V/DIV
PWRGD
50V/DIV
2.5ms/DIV
C
L
= 225µF
42563 TA02
INRUSH
CURRENT
500mA/DIV
CONTACT BOUNCE
LT4256-3
2
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(Note 1)
Supply Voltage (V
CC
) ................................ –0.3 to 100V
SENSE, PWRGD ....................................... – 0.3 to 100V
GATE Voltage (Note 2) .................... – 0.3V to V
CC
+ 10V
GATE Maximum Current ..................................... 200µA
V
OUT
.......................................................... –3V to 100V
FB, UV, OPEN ............................................. – 0.3 to 44V
OV .............................................................. –0.3 to 18V
RETRY ........................................................ – 0.3 to 15V
TIMER Voltage ......................................... –0.3V to 4.3V
Maximum Input Current (TIMER) ....................... 100µA
Operating Temperature
LT4256-3C ............................................. 0°C to 70°C
LT4256-3I ......................................... –40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ABSOLUTE AXI U RATI GS
W
WW
U
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Note: NC is a pin that is “Not Connected.”
PACKAGE/ORDER I FOR ATIO
UUW
ORDER PART
NUMBER
GN PART MARKING
42563
42563I
LT4256-3CGN
LT4256-3IGN
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Operating Voltage ●10.8 80 V
I
CC
Operating Current 1.8 3.9 mA
V
UVLH
Undervoltage Threshold V
CC
Low-to-High Transition ●3.96 4 4.04 V
V
UVHYS
Hysteresis 0.25 0.4 0.55 V
I
INUV
UV Input Current UV ≥ 1.2V –0.1 –1 µA
UV = 0V –1.5 –3 µA
V
UVRTH
Fault Latch Reset Threshold Voltage ●0.4 0.85 1.2 V
V
OVLH
Overvoltage Threshold V
CC
Low-to-High Transition ●3.96 4 4.04 V
V
OVHYS
Hysteresis 0.25 0.4 0.55 V
I
INOV
OV Input Current 0V ≤ OV < 7V 0.1 1 µA
V
OPEN
Open-Circuit Voltage Threshold (V
CC
– V
SENSE
)●1.5 3 6.5 mV
V
OLOPEN
OPEN Output Low Voltage I
O
= 2mA 0.20 0.5 V
I
O
= 5mA 0.75 1.3 V
I
INOPEN
Leakage Current V
OPEN
= 5V 0.1 1 µA
V
SENSETRIP
SENSE Pin Trip Voltage (V
CC
– V
SENSE
) FB = 0V ●71422 mV
FB ≥ 2V ●45 55 65 mV
I
INSNS
SENSE Pin Input Current V
SENSE
= V
CC
40 70 µA
I
PU
GATE Pull-Up Current Charge Pump On, ∆V
GATE
= 7V ●–16 –32 –63 µA
I
PD
GATE Pull-Down Current Any Fault, V
GATE
> V
OUT
40 62 80 mA
I
PDL
V
OUT
Pull-Down Current, Fault Condition Any Fault, V
GATE
= V
OUT
+
∆V
GATEL
, 130 µA
V
OUT
= 48V
∆V
GATE
External N-Channel Gate Drive (Note 2) V
GATE
– V
OUT
, 10.8V ≤ V
CC
≤ 20V ●4.5 8.8 12.5 V
20V ≤ V
CC
≤ 80V ●10 11.6 12.8 V
∆V
GATEL
External N-Channel Gate Drive, Fault Condition V
GATE
– V
OUT
, V
OUT
= 48V –2 V
1
2
3
4
5
6
7
8
TOP VIEW
GN PACKAGE
16-LEAD PLASTIC SSOP
16
15
14
13
12
11
10
9
UV
OV
NC
OPEN
PWRGD
NC
RETRY
GND
V
CC
SENSE
NC
GATE
V
OUT
NC
FB
TIMER
T
JMAX
= 125°C, θ
JA
= 130°C/W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LT4256-3
3
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V
FB
FB Voltage Threshold FB High-to-Low Transition ●3.95 3.99 4.03 V
FB Low-to-High Transition ●4.20 4.45 4.65 V
V
FBHYS
FB Hysteresis Voltage 0.3 0.45 0.60 V
V
OLPGD
PWRGD Output Low Voltage I
O
= 1.6mA 0.25 0.4 V
I
O
= 5mA 0.60 1.0 V
I
PWRGD
PWRGD Pin Leakage Current V
PWRGD
= 80V 0.1 1 µA
I
INFB
FB Input Current FB = 4.5V –0.1 –1 µA
I
TIMERPU
TIMER Pull-Up Current TIMER = 3V, During Fault ●– 63 – 105 –147 µA
I
TIMERPD
TIMER Pull-Down Current TIMER = 3V ●1.5 3 5 µA
V
THTIMER
TIMER Shutdown Threshold C
TIMER
= 10nF ●4.3 4.65 5 V
D
TIMER
Duty Cycle (RETRY Mode) ●1.5 3 4.5 %
V
RETRYTH
RETRY Threshold ●0.4 0.85 1.2 V
I
INRTR
RETRY Input Current RETRY = GND –87 –130 µA
t
PHLUV
UV Low to GATE Low C
GATE
= 100pF 1.7 3 µs
t
PLHUV
UV High to GATE High C
GATE
= 100pF 6 9 µs
t
PHLFB
FB Low to PWRGD Low 0.8 2 µs
t
PLHFB
FB High to PWRGD High 3.2 5 µs
t
PHLSENSE
(V
CC
– V
SENSE
) High to GATE Low V
CC
– V
SENSE
= 275mV 1 3 µs
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: An internal clamp limits the GATE pin to a minimum of 10V above
V
CC
. Driving this pin to a voltage beyond the clamp voltage may damage
the part.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ICC vs Temperature
SENSE Regulation Voltage
vs Temperature ICC vs VCC
TEMPERATURE (°C)
–50
10
SENSE REGULATION VOLTAGE (mV)
15
20
48
58
–25 02550
42563 G01
75 100
53
FB = 0V
FB > 2V
V
CC
(V)
10
2.0
2.5
3.5
40 60
42563 G02
1.5
1.0
20 30 50 70 80
0.5
0
3.0
I
CC
(mA)
TEMPERATURE (°C)
–50
0
ICC (mA)
0.5
1.0
1.5
2.5
–25 02550
42563 G03
75 100
2.0
VCC = 48V
Specifications are at TA = 25°C unless otherwise noted.
LT4256-3
4
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TYPICAL PERFOR A CE CHARACTERISTICS
UW
GATE Pull-Up Current
vs Temperature
GATE Pull-Down Current
vs Temperature
TIMER Currents vs VCC
TIMER Currents vs Temperature
TEMPERATURE (°C)
–50
–40
GATE PULL-UP CURRENT (µA)
–35
–30
–20
0
–25 02550
42563 G04
75 100
–10
–25
–5
–15
32µA @ 25°C
TEMPERATURE (°C)
–50
56
GATE PULL-DOWN CURRENT (mA)
57
58
60
63
–25 02550
42563 G05
75 100
62
59
61
VGATE – VOUT Voltage
vs Temperature
TEMPERATURE (°C)
–50
10.0
VGATE – VOUT VOLTAGE (V)
10.5
11.0
12.0
14.0
–25 02550
42563 G07
75 100
13.0
13.5
11.5
12.5
VCC = 80V VCC = 48V
VCC = 20V
V
CC
(V)
10
I
TIMER
(µA)
0
2.5
5.0
40 60
42563 G09
–80
–100
20 30 50 70 80
–120
–140
PULL-UP CURRENT
PULL-DOWN CURRENT
TIMER Shutdown Threshold
vs Temperature
TEMPERATURE (°C)
–50
0
TIMER SHUTDOWN THRESHOLD (V)
4.2
4.4
4.8
5.4
–25 02550
42563 G10
75 100
5.2
4.6
5.0
Specifications are at TA = 25°C unless otherwise noted.
GATE Pull-Down Capability vs VCC
Below Minimum Operating Voltage
VCC (V)
0
0
IGATE (mA )
10
20
30
40
60
2468
42563 G17
10 12
50
VGATE – VOUT Voltage
vs Temperature
TEMPERATURE (°C)
–50
0
VGATE – VOUT VOLTAGE (V)
2
4
8
14
–25 02550
42563 G06
75 100
12
6
10
VCC = 10.8V
VCC = 12V
VCC = 18V
UV Current vs UV Voltage
V
UV
(V)
01234
–1.4
I
UV
(µA)
–1.2
–0.8
–0.6
–0.4
40
0.4
42563 G18
–1.0
10 20 30 50
–0.2
0
0.2
TEMPERATURE (°C)
–50
–140
–120
ITIMER (µA)
–100
–80
0
5.0
–25 02550
42563 G08
75 100
2.5
PULL-UP CURRENT
PULL-DOWN CURRENT
LT4256-3
5
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FB Thresholds vs Temperature
OPEN Output Voltage vs IOPEN
FB Current vs FB Voltage
OPEN Threshold Voltage
vs Temperature
PWRGD Output Voltage
vs IPWRGD
OV Current vs OV Voltage
IOPEN (mA)
0
0
VOPEN (V)
2
4
6
2468
42563 G13
10
8
10
1
3
5
7
9
12
TEMPERATURE (°C)
–50
0
0.5
OPEN THRESHOLD VOLTAGE (mV)
1.5
2.5
3.5
5.0
–25 02550
42563 G14
75 100
4.5
1.0
2.0
3.0
4.0
VCC – VSENSE
IPWRGD (mA)
0
0
VPWRGD (V)
1
2
3
4
6
2468
42563 G15
10 12
5
TEMPERATURE (°C)
–50
3.9
4.0
FB THRESHOLDS (V)
4.1
4.2
4.3
4.5
–25 02550
42563 G16
75 100
4.4
H-L THRESHOLD
L-H THRESHOLD
V
OV
(V)
0
–50
I
OV
(µA)
0
50
100
150
200
250
5101520
42563 G19
V
FB
(V)
0
–0.4
I
FB
(µA)
–0.3
–0.2
–0.1
0
0.1
0.2
10 20 30 40
42563 G20
50
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Specifications are at TA = 25°C unless otherwise noted.
UV Thresholds vs Temperature
TEMPERATURE (°C)
–50
3.5
3.6
UV THRESHOLDS (V)
3.7
3.8
3.9
4.1
–25 02550
42563 G11
75 100
4.0
H-L THRESHOLD
L-H THRESHOLD
OV Thresholds vs Temperature
TEMPERATURE (°C)
–50
3.5
3.6
OV THRESHOLDS (V)
3.7
3.8
3.9
4.1
–25 02550
42563 G12
75 100
4.0
H-L THRESHOLD
L-H THRESHOLD
LT4256-3
6
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PI FU CTIO S
UUU
UV (Pin 1): Undervoltage Sense Input. UV is an input that
enables the output voltage. When UV is driven above 4V,
GATE will start charging and the output turns on. When
UV goes below 3.6V, GATE discharges and the output
shuts off.
Pulsing UV to below 0.4V for at least 5µs after a current
limit fault cycle resets the fault latch (when RETRY pin is
low, commanding latch off operation) and allows the part
to turn back on. This command is only accepted after
TIMER is discharged below 0.65V. To disable UV sensing,
connect the pin to a voltage between 5V and 44V.
OV (Pin 2): Overvoltage Sense Input. OV is an input that
disables the output voltage. If OV ever goes above 4V,
GATE is discharged and the output shuts off. When OV
goes below 3.6V, GATE starts charging and the output
turns back on. To disable overvoltage sensing, connect pin
to ground.
NC (Pins 3, 6, 11, 14): No Connect. Not connected to any
internal circuitry.
OPEN (Pin 4): Open Circuit Detect Output. This pin is an
open collector output that releases and is pulled high
through an external resistor if the load current is less than
(3mV)/R5.
PWRGD (Pin 5): Power Good Output. PWRGD is pulled
low whenever the voltage on FB falls below the high-to-low
threshold voltage. It goes into a high impedance state
when the voltage on FB exceeds the low-to-high threshold
voltage. An external pull-up resistor can pull PWRGD to a
voltage higher or lower than V
CC
.
RETRY (Pin 7): Current Fault Retry Input. RETRY com-
mands the operational mode of the current limit. If RETRY
is floating, the LT4256-3 automatically restarts after a
current fault. If it is connected to a voltage below 0.4V, it
will latch off after a current fault (which requires that UV be
cycled low in order to start normal operation again).
GND (Pin 8): Device Ground. This pin must be tied to a
ground plane for best performance.
TIMER (Pin 9): Timing Input. An external timing capacitor
from TIMER to GND programs the maximum time the part
is allowed to remain in current limit. When the part goes
into current limit, a 105µA pull-up current source starts to
charge the timing capacitor. When the voltage on TIMER
reaches 4.65V (typ), GATE is pulled low; the TIMER pull-
up current will be turned off and the capacitor is discharged
by a 3µA pull-down current. When TIMER falls below 0.65V
(typ), GATE turns on again if RETRY is high (if RETRY is
low, UV must be pulsed low to reset the internal fault latch
before GATE will turn on). If RETRY is grounded and UV is
not cycled low, GATE remains latched off and TIMER will
be discharged to near ground. UV must be cycled low after
TIMER has discharged below 0.65V (typ) to reset the part.
If RETRY is floating or connected to a voltage above its
1.2V threshold, the LT4256-3 automatically restarts after
a current fault. Under an output short-circuit condition, the
LT4256-3 cycles on and off with a 3% on-time duty cycle.
FB (Pin 10): Power Good Comparator Input. FB monitors
the output voltage through an external resistive divider.
When the voltage on FB is lower than the high-to-low
threshold of 3.99V, PWRGD is pulled low and released
when FB is pulled above the 4.45V low-to-high threshold.
The voltage present on FB affects foldback current limit
(see Figure 8 and related discussion).
V
OUT
(Pin 12): Output Voltage Sense Input. This pin
should be connected to the source of the external MOSFET.
It is used to sense when the MOSFET is shut off (during any
fault mode) and to reduce the pull-down current on GATE.
This protects the LT4256-3 from excessive power dissipa-
tion when large output capacitors are used.
LT4256-3
7
42563fa
PI FU CTIO S
UUU
GATE (Pin 13): High Side Gate Drive for the External
N-Channel MOSFET. An internal charge pump guarantees
at least 10V of gate drive for V
CC
supply voltages above
20V and 4.5V of gate drive for V
CC
supply voltages
between 10.8V and 20V. The rising slope of the voltage on
GATE is set by an external capacitor connected from GATE
to GND and an internal 32µA pull-up current source from
the charge pump output.
If the current limit is reached, the GATE voltage is adjusted
to maintain a constant voltage across the sense resistor
while the timing capacitor starts to charge. If the TIMER
voltage ever exceeds 4.65V, GATE is pulled low.
GATE is also pulled to GND whenever UV is pulled low; the
V
CC
supply voltage drops below the externally programmed
undervoltage threshold, above the overvoltage threshold
or below the internal UVLO threshold (9.8V).
GATE is clamped internally to a maximum voltage of
11.6V (typ) above VOUT under normal operating condi-
tions. Driving this pin beyond the clamp voltage may
damage the part. GATE is also clamped to 2V (typ) below
VOUT. When the gate is commanded off due to a fault
condition, it is discharged quickly by a 62mA (typ)
capable switch until GATE is 2V (typ) below VOUT. When
GATE is below VOUT by 2V, the 62mA is reduced to 130µA
to protect the LT4256-3 against damage if VOUT has large
capacitance. A Zener diode is needed between the gate
and source of the external MOSFET to protect its gate
oxide under instantaneous short-circuit conditions. See
Applications Information.
SENSE (Pin 15): Current Limit Sense Input. A sense
resistor is placed in the supply path between VCC and
SENSE. The current limit circuit regulates the voltage
across the sense resistor (VCC – SENSE) to 55mV while in
current limit when FB is 2V or higher. If FB drops below
2V, the regulated voltage across the sense resistor de-
creases linearly and stops at 14mV when FB is 0V. The
OPEN output also uses SENSE to detect when the output
current is less than (3mV)/R5.
To defeat current limit, connect SENSE to V
CC
.
V
CC
(Pin 16): Input Supply Voltage. The positive supply
input ranges from 10.8V to 80V for normal operation. I
CC
is typically 1.8mA. An internal circuit disables the LT4256-3
for inputs less than 9.8V (typ).
LT4256-3
8
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BLOCK DIAGRA
W
+
–
–
+
–
+
108µA
VP
VP
3mV
LOGIC
2V
14mV TO 55mV
9.8V 4V
4V
VCC
INTERNAL
UV
TIMER LOW
TIMER HIGH
GND
0.65V
4.65V
–
+
–
+
3.99V3.99V
7V
100k
PWRGD
TIMER
4256 BD
V
CC
SENSE
V
P
GEN
FB
OV
3µA
UV
RETRY
GATE
V
OUT
OPEN
+
–
+
–
+
–
CHARGE
PUMP
AND
GATE
DRIVER
+
–
REF GEN
16 15
OPEN
CIRCUIT 4
12
13
5
9
8
CURRENT
LIMIT
FOLDBACK
10
7
1
2
UV
OV
LT4256-3
9
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TEST CIRCUIT
TI I G DIAGRA S
WUW
Figure 2. UV to GATE Timing
Figure 3. VOUT to PWRGD Timing
Figure 4. SENSE to GATE Timing
Figure 1
V
CC
SENSE
GATE
V
OUT
TIMER
RETRY
PWRGD
OPEN
FB
OV
UV
48V
GND
3V
3V
4256 F01
100pF
+–
+–
+–
48V
+–
UV
4256 F02
GATE VOUT +2V
tPLHUV
4V
VOUT +2V
tPHLUV
3.6V
V
CC
– SENSE
4256 F04
GATE
V
CC
t
PHLSENSE
55mV
FB
4256 F03
PWRGD 1V
tPLHFB
4.45V
1V
tPHLFB
3.99V
LT4256-3
10
42563fa
APPLICATIO S I FOR ATIO
WUUU
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge.
The transient currents can permanently damage the con-
nector pins and glitch the system supply, causing other
boards in the system to reset.
The LT4256-3 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The
device also provides undervoltage and overvoltage as well
as overcurrent protection while a power good output
signal indicates when the output supply voltage is ready
with a high output.
Power-Up Sequence
An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control the power up of the
supply voltage (Figure 5). Resistor R5 provides current
detection and capacitor C1 controls the GATE slew rate.
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
When the power pins first make contact, transistor Q1 is
held off. If the voltage on V
CC
is between the externally
programmed undervoltage and overvoltage thresholds,
V
CC
is above 9.8V and the voltage on TIMER is less than
4.65V (typ), transistor Q1 will be turned on (Figure 6). The
voltage on GATE rises with a slope equal to 32µA/C1 and
the supply inrush current is set at:
I
INRUSH
= C
L
• 32µA/C1 (1)
where C
L
is the total load capacitance.
Figure 5. 1.6A, 48V Latchoff Application
Figure 6. Start-Up Waveforms
4256 F05
R5
0.025Ω
LT4256-3
SENSE
13
12
10
5
7
8
16 15
1
2
4
9
VCC
GATE
VOUT
FB
PWRGD
RETRY
UV
OV
TIMER GND
VIN
48V
GND
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
PWRGD
VOUT
48V
1.6A
R4
51k
CL
C2
33nF
C3
0.01µFC1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
D2
SMAT70A
+
IOUT
500mA/DIV
VOUT
50V/DIV
5ms/DIV
4256 F06
PWRGD
50V/DIV
GATE
50V/DIV CL = 125µF
LT4256-3
11
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APPLICATIO S I FOR ATIO
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To reduce inrush current, increase C1 or decrease load
capacitance. If the voltage across the current sense resis-
tor R5 reaches V
SENSETRIP
, the inrush current will be lim-
ited by the internal current limit circuitry. The voltage on
GATE is adjusted to maintain a constant voltage across the
sense resistor and TIMER begins to charge.
When the FB voltage goes above the low-to-high V
FB
threshold, PWRGD goes high.
Undervoltage and Overvoltage Detection
The LT4256-3 uses UV and OV to monitor the V
CC
voltage
to determine when it is safe to turn on the load and allow
the user the greatest flexibility for setting the operational
thresholds. UV and OV are internally connected to an
analog window comparator. Any time that UV goes below
3.6V or OV goes above 4V, GATE will be pulled low until the
UV/OV voltages return to the normal operation voltage
window (4V and 3.6V, respectively).
The UV threshold should never be set below the internal
UVLO threshold (9.8V typically) because the benefit of the
UV’s hysteresis will be lost, making the LT4256-3 more
susceptible to noise (V
CC
must be at least 9.8V when UV
is at its 3.6V threshold). UV is filtered with C3 to prevent
noise spikes and capacitively coupled glitches from shut-
ting down the LT4256-3 output erroneously.
To calculate UV and OV thresholds, use the following
equations:
4256 F07
R5
0.010Ω
LT4256-3
SENSE
13
10
5
7
8
16
D2
SMAT70A
15
1
2
4
9
VCC
GATE
FB
12
VOUT
PWRGD
RETRY
UV
OV
TIMER GND
VCC
48V
(SHORT PIN)
Q1
IRF540
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
Q2
VN2222
R1
64.9k
R7
100Ω
R9
4.02k
R6
10ΩR8
36.5k
VOUT
48V
4A
R4
51k
CL
C2
33nF
C3
0.01µF
OFF SIGNAL
FROM MPU
C1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
GND
+
Figure 7. How to Use a Logic Signal to Control the LT4256-3 Turn On/Off
RRR
V
Va
RRR
Vb
kRRR k
VV
R
RR
VV
RR
R
THUVLH
THOVLH
THUVHL
THOVHL
123 412
312
41
2
20 1 2 3 200 3
36 1 1
23 4
36 1 12
3
=+
()
⎛
⎝
⎜⎞
⎠
⎟
()
=+
()
Ω≤ ++ ≤Ω
()
=+
+
⎛
⎝
⎜⎞
⎠
⎟
()
=+
+
⎛
⎝
⎜⎞
⎠
⎟
–
–
.;
.
where V
THULH
and V
THOVLH
are the desired UV and OV
threshold voltages when V
CC
is rising (L – H).
Figure 7 shows how the LT4256-3 is commanded to shut
off with a logic signal. This is accomplished by pulling the
gate of the open-drain MOSFET, Q2, (tied to UV) high.
LT4256-3
12
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APPLICATIO S I FOR ATIO
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Short-Circuit Protection
The LT4256-3 features a programmable foldback current
limit with an electronic circuit breaker that protects against
short circuits or excessive load currents. The current limit
is set by placing a sense resistor (R5) between V
CC
and
SENSE. The current limit threshold is calculated as:
I
LIMIT
= 55mV/R5 (5)
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
back as a function of the output voltage, which is sensed
internally on FB.
If the LT4256-3 goes into current limit when the voltage on
FB is 0V, the current limit circuit drives GATE to force a
constant 14mV drop across the sense resistor. As the
output at FB increases, the voltage across the sense
resistor increases until FB reaches 2V, at which point the
voltage across the sense resistor is held constant at 55mV
(see Figure 8).
For a 0.025Ω sense resistor, the typical current limit is set
at 2200mA and folds back to 560mA when the output is
shorted to ground. Thus, MOSFET peak power dissipation
under short-circuit conditions is reduced from 106W to
27W. See the Layout Considerations section for important
information about board layout to minimize current limit
threshold error.
The LT4256-3 also features a variable overcurrent re-
sponse time. The time required for the part to regulate the
GATE voltage is a function of the voltage across the sense
resistor connected between V
CC
and SENSE. This helps to
eliminate sensitivity to current spikes and transients that
might otherwise unnecessarily trigger a current limit re-
sponse and increase MOSFET dissipation. Figure 9 shows
the response time as a function of the overdrive at SENSE.
Figure 8. Current Limit Sense Voltage vs Feedback Pin Voltage Figure 9. Response Time to Overcurrent
14mV
0V 2V FB
4256 F08
55mV
V
CC
– V
SENSE
50 100 150 200
4256 F09
12
10
8
6
4
2
RESPONSE TIME (µs)
VCC – VSENSE (mV)
0
LT4256-3
13
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APPLICATIO S I FOR ATIO
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TIMER
TIMER provides a method for programming the maximum
time the part is allowed to operate in current limit. When
the current limit circuitry is not active, TIMER is pulled to
GND by a 3µA current source. When the current limit
circuitry becomes active, a 108µA pull-up current source
is connected to TIMER and the voltage will rise with a slope
equal to 105µA/C
TIMER
as long as the circuitry stays active.
Once the desired maximum current limit time is known,
the capacitor value is:
CnF 25•tms; C=105 A
4.65V
[]
=
[]
µ•t
(6)
Whenever TIMER reaches 4.65V (typ), the internal fault
latch is set causing GATE to be pulled low and TIMER to be
discharged to GND by the 3µA current source. The part is
not allowed to turn on again until the voltage on TIMER
falls below 0.65V (typ).
Whenever GATE is commanded off by any fault condition,
it is discharged with a high current, turning off the external
MOSFET. The waveform in Figure 10 shows how the
output latches off following a current fault. The drop
across the sense resistor is held at 55mV as the timer
ramps up. Once TIMER reaches its shutdown threshold
(4.65V typically), the circuit latches off.
Automatic Restart
If RETRY is floating, then the device automatically restarts
after a current overload fault.
When the voltage at TIMER ramps back down to 0.65V
(typ), the LT4256-3 turns on again. If the short-circuit
condition at the output still exists, the cycle will repeat
itself indefinitely. The duty cycle under short-circuit con-
ditions is 3% which prevents Q1 from overheating. Fig-
ure 11 shows representative waveforms during a short
circuit.
Latch Off Operation
If RETRY is grounded, the LT4256-3 will latch off after a
current fault. After the part latches off, it may be com-
manded to start back up. This is accomplished by cycling
UV to ground and then back high (this command can only
be accepted after TIMER discharges below the 0.65V typ
threshold, which prevents overheating transistor Q1).
Figure 10. Latch Off Waveforms Figure 11. RETRY Waveforms
10ms/DIV 4256 F10
I
OUT
500mA/DIV
V
OUT
50V/DIV
TIMER
5V/DIV
GATE
50V/DIV
IOUT
500mA/DIV
VOUT
50V/DIV
TIMER
5V/DIV
GATE
50V/DIV
10ms/DIV
4256 F11
LT4256-3
14
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APPLICATIO S I FOR ATIO
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Therefore, using RETRY only, the LT4256-3 will either
latch off after an overcurrent fault condition or it will go
into a hiccup mode.
Power Good Detection
The LT4256-3 includes a comparator for monitoring the
output voltage. The output voltage is sensed through the
FB pin via an external resistor string. The comparator’s
output (PWRGD) is an open collector capable of operating
from a pull-up as high as 80V.
PWRGD can be used to directly enable/disable a power
module with an active high enable input. Figure 12 shows
how to use PWRGD to control an active low enable input
power module. Signal inversion is accomplished by tran-
sistor Q2 and R10.
The thresholds for the FB pin are 4.45V (low to high) and
3.99V (high to low). To calculate the PWRGD thresholds,
use the following equations:
RV
kRR k
V
8= V• R9, high to low (7)
(8a)
= 4.45V 1+ R8
R9 , low to high (8b)
THPWRGD
THPWRGD
399 1
20 8 9 200
.–
⎛
⎝
⎜⎞
⎠
⎟
Ω≤ +≤Ω
⎛
⎝
⎜⎞
⎠
⎟
OPEN Pin/Open FET Detection
OPEN is an output which signals abnormally low load
currents. When the voltage across the sense resistor is
less than 3mV, the open collector pull-down device is shut
off allowing OPEN to be externally pulled high. OPEN is
always active when V
CC
is above 9.8V. If V
CC
is below 9.8V
(the internal UVLO threshold), OPEN is pulled low.
Open-circuit MOSFETs are detected with the LT4256-3 by
monitoring the voltage across R5 with OPEN while moni-
toring the output voltage with PWRGD. An open FET
condition is signalled when OPEN is high and PWRGD is
low (after the part has completed its start-up cycle).
Figure 12. Active Low Enable PWRGD Application
4256 F12
R5
100mΩ
LT4256-3
SENSE
13
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
FB
12
VOUT
PWRGD
RETRY
UV
OV
TIMER GND
VCC
24V
(SHORT PIN)
Q1
IRFZ34VS
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
R1
32.4k
R7
100Ω
R6
10Ω
VOUT
24V
400mA
VLOGIC
R4
27k
R8
14k
CL
R10
51k
C2
33nF
C3
0.01µFC1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
R9
4.02k
Q2
ZN3904
PWRGD
GND
D2
SMAT70A
+
LT4256-3
15
42563fa
This open FET condition can be falsely signalled during
start-up if the load is not activated until after PWRGD goes
high. To avoid this false indication, OPEN and PWRGD
should not be polled for a period of time, t
STARTUP
, given
by:
tVC
A
STARTUP CC
=µ
31
32
••
(9)
This can be accomplished either by a microcontroller (if
available) or by placing an RC filter as shown in Figure 13.
Once the OPEN voltage exceeds the monitoring logic thresh-
old, V
THRESH
, and PWRGD is low, an open FET condition
is signalled. In order to prevent a false indication, the RC
product should be set with the following equation:
RC VC
AV
VV
CC
LOGIC
LOGIC THRESH
>
µ⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
⎜⎞
⎠
⎟
31
32
••
ln –
(10)
Another condition that can cause a false indication is if the
LT4256-3 goes into current limit during start-up. This will
cause t
STARTUP
to be longer than calculated. Also, if the
LT4256-3 stays in current limit long enough for TIMER to
fully charge up to its threshold, the LT4256-3 will either
latch off (RETRY = 0) or go into the current limit hiccup
mode (RETRY = floating). In either case, an open FET
condition will be falsely signalled. If the LT4256-3 does go
into current limit during start-up, C1 can be increased (see
Power-Up Sequence).
APPLICATIO S I FOR ATIO
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Supply Transient Protection
The LT4256-3 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. However,
voltage transients above 100V may cause permanent
damage. During a short-circuit condition, the large change
in currents flowing through the power supply traces can
cause inductive voltage transients which could exceed
100V. To minimize the voltage transients, the power trace
parasitic inductance should be minimized by using wider
traces or heavier trace plating and a bypass capacitor
should be placed between V
CC
and GND. A surge suppres-
sor (TransZorb
®
) at the input can also prevent damage
from voltage transients.
GATE Pin
A curve of gate drive vs V
CC
is shown in Figure 14. GATE
is clamped to a maximum voltage of 12.8V above V
OUT
.
This clamp is designed to withstand the internal charge
pump current. An external Zener diode must be used as
shown in all applications. At a minimum input supply
voltage of 10.8V, the minimum gate drive voltage is 4.5V.
When the input supply voltage is higher than 20V, the gate
drive voltage is at least 10V and a standard threshold
MOSFET can be used. In applications from 12V to 15V
range, a logic level MOSFET must be used.
Figure 13. Delay Circuit for OPEN FET Detection
4
R
C
4256 F13
OPEN
LT4256-3 TO
MONITORING
LOGIC
V
LOGIC
INTERNAL
OPEN COLLECTOR
PULL-DOWN
Figure 14. ∆VGATE vs VCC
VCC (V)
10
3
∆VGATE (V)
4
6
7
8
13
10
30 50 60
4256 F14
5
11
12
9
20 40 70 80
TransZorb is a registered trademark of General Instruments, GSI.
LT4256-3
16
42563fa
In some applications it may be possible for V
OUT
to ring
below ground (due to the parasitic trace inductance).
Higher current applications, especially where the output
load is physically far away from the LT4256-3 will be more
susceptible to these transients. This is normal and the
LT4256-3 has been designed to allow for some ringing
below ground. However, if the application is such that
V
OUT
can ring more than 3V below ground, damage may
occur to the LT4256-3 and an external diode, D2, from
ground (anode) to V
OUT
(cathode) will have to be added to
the circuit as shown in Figure 15 (it is critical that the
reverse breakdown voltage of the diode be higher than the
highest expected V
CC
voltage). A capacitor placed from
ground to V
OUT
directly at the LT4256-3 pins can help
reduce the amount of ringing on V
OUT
but it may not be
enough for some applications.
During a fault condition, the LT4256-3 pulls down on
GATE with a switch capable of sinking about 62mA. Once
GATE drops below the output voltage by a diode forward
voltage, the external Zener will forward bias and V
OUT
will
also be discharged to GND. In addition to the GATE
capacitance, the output capacitance will be discharged
through the LT4256-3.
In applications utilizing very large external N-channel
MOSFETs, the possibility exists for the MOSFET to turn on
when initially inserted into a live backplane (before the
APPLICATIO S I FOR ATIO
WUUU
LT4256-3 becomes active and pulls down on GATE). This
is due to the MOSFET intrinsic drain to gate capacitance
forcing current into R7 and C1 when the drain voltage
steps up from ground to V
CC
with an extremely fast rise
time. To alleviate this situation, a diode, D3, should be put
across R7 with the cathode connected to C1 as shown in
Figure 16.
Whenever the LT4256-3 turns the MOSFET off, GATE pulls
the MOSFET gate to ground with an open collector capable
of sinking 62mA. If the output is held up by a large
reservoir capacitor, the stored energy is dissipated in the
pull-down transistor via a sneak path through the (now
forward biased) Zener, D1. The LT4256-3 has a propri-
etary feature that reduces on-chip power dissipation by
sensing when the MOSFET is off and reducing the pull-
down current significantly. See V
GATE
Turn-Off for more
information about using this feature.
V
GATE
Turn-Off
The LT4256-3 has a proprietary feature that reduces
power dissipation by sensing when the MOSFET is off and
reducing the pull-down current significantly. As the GATE
pin is discharged during any fault, the LT4256-3 monitors
the GATE pin and V
OUT
pin. When the GATE pin is 2V below
V
OUT
, the pull-down current is reduced from 62mA to
about 130µA.
Figure 15. Negative Output Voltage Protection Diode Application
4256 F14
R5
0.010Ω
LT4256-3
SENSE
13
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
FB
12
V
OUT
PWRGD
RETRY
UV
OV
TIMER GND
V
CC
48V
(SHORT PIN)
Q1
IRF540
D1
CMPZ5241BS
11V
D3
MRA4003T3
R3
4.02k
R2
4.02k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10ΩR8
36.5k
V
OUT
48V
4A
R4
51k
C
L
C2
33nF
C3
0.01µFC1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
GND
D2
SMAT70A
+
LT4256-3
17
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APPLICATIO S I FOR ATIO
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Figure 16. High dV/dt MOSFET Turn-On Protection Circuit
4256 F16
R5
0.033Ω
LT4256-3
SENSE
13
10
12
5
7
8
16 15
1
2
4
9
VCC
GATE
VOUT
FB
PWRGD
RETRY
UV
OV
TIMER GND
VCC
48V
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241BS
11V
D3
1N4148W
R3
4.02k
R2
4.02k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10ΩR8
36.5k
VOUT
48V
1.2A
R4
27k
CL
C2
33nF
C3
0.1µF
C1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
GND
D2
SMAT70A
+
Figure 17. Enhanced Output Pull-Down Circuit
In order to use this feature as designed, a bidirectional
Zener diode is needed for D1. When the LT4256-3 com-
mands the MOSFET off (and a bidirectional Zener is used),
the output discharges very slowly (t
OFF
= (C
LOAD
• V
OUT
)/
130µA). Several variations can be implemented to dis-
charge the output faster. The recommeded method is
shown in Figure 17 and uses an external PNP transistor,
diode and resistor to discharge the output quickly.
4256 F17
R5
0.010Ω
LT4256-3
SENSE
13
R
PROG
Q2
2N4920
D3
1N4148
R
B
18k
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
FB
12
V
OUT
PWRGD
RETRY
UV
OV
TIMER GND
V
CC
48V
(SHORT PIN)
Q1
IRF540
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
R1
64.9k
R7
100Ω
R9
4.02k
R6
1k
R8
36.5k
V
OUT
48V
4A
R4
51k
C
L
C2
33nF
C3
0.01µFC1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
GND
D2
SMAT70A
+
The equation to set the nominal discharge current is:
IRA
DISCHG PROG
=µ
()
5000 130
(11)
where R
PROG
must be less than 1k.
The maximum current equation is:
IRA
MAX PROG
=µ
()
7000 350
(12)
LT4256-3
18
42563fa
APPLICATIO S I FOR ATIO
WUUU
Figure 18. Recommended Component Placement
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
to the current sense resistor (R5 in typical application
circuit) is recommended. Note that 1oz copper exhibits a
sheet resistance of about 530µΩ/❏. Small resistances can
cause large errors in high current applications. Noise
immunity will be improved significantly by locating resis-
tor dividers close to the pins with short V
CC
and GND
traces. The minimum trace width for 1oz copper foil is
0.02" per amp to make sure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Figure 18 shows a layout that meets these requirements.
C1
42563 F18
V
OUT
V
IN
GND
R8
R7
R5
Q1
D1
R6
R9
R3
R1
D2
R2
LT4256-3
LT4256-3
19
42563fa
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LT4256-3
20
42563fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
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© LINEAR TECHNOLOGY CORPORATION 2004
LT/LWI/LT 0705 REV A • PRINTED IN USA
APPLICATIO S I FOR ATIO
WUUU
R5
0.020Ω
LT4256-3
SENSEV
CC
GATE
FB
V
OUT
PWRGD
RETRY
UV
OV
TIMER GND
D3
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
R1
64.9k R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
PWRGD2
V
OUT2
48V
2A
R4
51k
C
L2
33nF
C3
0.01µF
C1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
+
4256 TA03
R5
0.020Ω
LT4256-3
SENSEV
CC
GATE
FB
V
OUT
PWRGD
RETRY
UV
OV
TIMER GND
V
IN
48V
GND
(SHORT PIN)
Q1
IRF540
Q2
IRF540
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
R1
64.9k R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
PWRGD1
V
OUT1
48V
2A
R4
51k
C
L1
C2
33nF
C3
0.01µF
C1
10nF
OPEN
D2
SMAT70A
UV = 36V
OV = 73V
PWRGD = 40V
+
Dual 48V Supply Sequencing Application
VIN
50V/DIV
VOUT1
50V/DIV
VOUT2
50V/DIV
5ms/DIV
4256 TA04
PWRGD1
50V/DIV
CL1 = 200µF
CL2 = 147µF
