DRV602
LEFT
RIGHT
-
+
-
+
DAC
DAC
SOC
DRV602
www.ti.com
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
DirectPath™, Pop-Free 3Vrms Line Driver with Adjustable Gain
Check for Samples: DRV602
Designed using TI's patented DirectPath™
1FEATURES technology, the DRV602 is capable of driving 3Vrms
234• DirectPath™ into a 2.5kΩload with 5V supply voltage. The device
– Eliminates Pop/Clicks has differential inputs and uses external gain setting
resistors, that supports a gain range of ±1V/V to
– Eliminates Output DC-Blocking Capacitors ±10V/V. The use of external gain resistors also allows
– Provides Flat Frequency Response the implementation of a 2nd order low pass filter to
20Hz–20kHz compliment DAC's and SOC converters. The line
• Low Noise and THD output of the DRV602 has ±8kV IEC ESD protection.
The DRV602 (referred to as the '602) has built-in
– SNR > 102 dB shutdown control for pop-free on/off control.
– Typical VN< 15 mVms Using the DRV602 in audio products can reduce
– THD+N < 0.05% 20 Hz–20 kHz component count compared to traditional methods of
• Output Voltage into 2.5-kΩLoad generating a 3Vrms output. The DRV602 doesn't
– 2 Vrms with 3.3-V Supply Voltage require a power supply greater than 5V to generate
its 8.5VPP output, nor does it require a split rail power
– 3 Vrms with 5-V Supply Voltage supply. The DRV602 integrates its own charge pump
• 3Vrms Output Voltage into 2.5 kΩLoad With to generate a negative supply rail that provides a
5V Supply Voltage clean, pop-free ground biased 3Vrms output.
• Differential Input The DRV602 is available in a 14 pin TSSOP
package.
APPLICATIONS If higher SNR, trimmed DC-offset and external
• Set-Top Boxes undervoltage-mute functions are beneficial in the
• PDP / LCD TV application, TI recommends the footprint compatible
• Blu-ray Disc™, DVD-Players DRV603 (SLOS617).
• Home Theater in a Box For a stereo line and stereo HP driver see DRV604
(SLOS659).
DESCRIPTION
The DRV602PW is a 3Vrms pop-free stereo line
driver designed to allow the removal of the output
dc-blocking capacitors for reduced component count
and cost. The device is ideal for single supply
electronics where size and cost are critical design
parameters.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DirectPath, TI FilterPro are trademarks of Texas Instruments.
3Blu-ray Disc is a trademark of Blu-ray Disc Association.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
+INR
2
3
4
-INR
OUTR
SGND
5
6
7 8
EN
PVSS
CN
9
10
11
12
13
14
CP
PVDD
PGND
OUTL
-INL
+INL
ChargePump
NC
a
DRV602
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PW (TSSOP) PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN I/O(1) DESCRIPTION
NAME TSSOP (PW)
+INR 1 I Right channel OPAMP positive input
–INR 2 I Right channel OPAMP negative input
OUTR 3 O Right channel OPAMP output
SGND 4 I Signal ground
EN 5 I Enable input, active high
PVSS 6 O Supply voltage
CN 7 I/O Charge pump flying capacitor negative terminal
CP 8 I/O Charge pump flying capacitor positive terminal
PVDD 9 I Positive supply
PGND 10 I Power ground
NC 11 No internal connection
OUTL 12 O Left channel OPAMP output
–INL 13 I Left channel OPAMP negative input
+INL 14 I Left channel OPAMP positive input
(1) I = input, O = output, P = power
2Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): DRV602
DRV602
www.ti.com
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
ABSOLUTE MAXIMUM RATINGS(1) (2)
over operating free-air temperature range VALUE UNIT
Supply voltage, VDD to GND –0.3 V to 5.5 V
VIInput voltage VSS – 0.3 to VDD + 0.3 V
RLMinimum load impedance > 600 Ω
EN to GND –0.3 to VDD +0.3 V
TJMaximum operating junction temperature range, –40 to 150 °C
Tstg Storage temperature range –40 to 150 °C
ESD IEC Contact ESD Protection per IEC6100-4-2, on output pins measured on DRV602EVM ±8 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
DISSIPATION RATINGS POWER RATING(1) POWER RATING(1)
PACKAGE qJC (°/W) qJA (°/W) AT TA≤25°C AT TA≤70°C
TSSOP-14 (PW) 35 115(2) 870mW 348mW
(1) Power rating is determined with a junction temperature of 125°C. This is the point where performance starts to degrade and long-term
reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C
for best performance and reliability.
(2) These data were taken with the JEDEC High-K test printed circuit board (PCB). For the JEDEC low-K test PCB, the qJA is 185°C.
ORDERING INFORMATION
TAPACKAGE(1) DESCRIPTION
-40°C to 85°C DRV602PW 14-Pin TSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
VDD Supply voltage, DC Supply Voltage 3 3.3 5.5 V
VIH High-level input voltage EN 60 % of VDD
VIL Low-level input voltage EN 40 % of VDD
TAOperating free-air temperature –40 85 °C
ELECTRICAL CHARACTERISTICS
TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage VDD = 3 V to 5 V, Voltage follower - gain = 1 5 mV
PSRR Supply Rejection Ratio VDD = 3.3 V to 5 V 88 dB
VOH High-level output voltage VDD = 3.3 V, RL= 2.5 kΩ3.10 V
VOL Low-level output voltage VDD = 3.3 V, RL= 2.5 kΩ–3.05 V
|IIH| High-level input current (EN) VDD = 5 V, VI= VDD 1 µA
|IIL| Low-level input current (EN) VDD = 5 V, VI= 0 V 1 µA
VDD = 3.3 V, No load, EN = VDD 8 11 mA
IDD Supply Current VDD = 5 V, No load, EN = VDD 12.5 20
Shutdown mode, Vdd = 3 V to 5 V 2 mA
Copyright © 2008–2010, Texas Instruments Incorporated 3
Product Folder Link(s): DRV602
R3
C2
RIGHT
INPUT
+
-
LEFT
INPUT
LEFT
OUTPUT
RIGHT
OUTPUT
3.3V
supply
C1
C2
R3
R2
R2
R1
R1
R3
+
-
C1 R3R1
R1
R2 C2
R2
C3 1 Fm
DRV602
1 Fm
1 Fm
Clickand Pop
Suppression
ShortCircuit
Protection
SGND
Bias
Circuitry
PVSS
CN CP
PVDD
-INL
+INL
OUTR
-INR
OUTL
+INR
EN PGND
NC
Line
Driver
Line
Driver
C2
ENABLE
C3
C3
C3
DRV602
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
www.ti.com
OPERATING CHARACTERISTICS
VDD = 3.3 V , TA= 25°C, RL= 2.5kΩ, C(PUMP) = C(PVSS) = 1 µF , CIN = 1 µF, RIN = 33 kΩ, Rfb = 68kΩ(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THD = 1%, VDD = 3.3 V, f = 1 kHz 2.05
VOOutput Voltage (Outputs In Phase) Vrms
THD = 1%, VDD = 5 V, f = 1 kHz 3.01
VO= 2 Vrms, f = 1 kHz 0.01%
THD+N Total harmonic distortion plus noise VO= 2 Vrms, f = 6.8 kHz 0.05%
Crosstalk VO= 2 Vrms, f = 1 kHz –100 dB
IOOutput current limit VDD = 3.3 V 20 mA
RIN Input resistor range 1 10 47 kΩ
Rfb Feedback resistor range 4.7 20 100 kΩ
Slew rate 4.5 V/ms
Maximum capacitive load 220 pF
VNNoise output voltage A-weighted, BW 20Hz–22kHz 15 mVrms
VO= 2 Vrms, THD+N = 0.1%, 22 kHz BW,
SNR Signal to noise ratio 102 dB
A-weighted
GBW Unity Gain Bandwidth 8 MHz
AVO Open-loop voltage gain 150 dB
Fcp Charge Pump frequency 225 450 675 kHz
APPLICATION CIRCUIT
R1 = 33kΩ, R2 = 68kΩ, R3 = 100kΩ, C1 = 150pF, C2 = 15pF, C3 = 1 mF
Differential input, single ended output, 2nd order filter. 40kHz –3dB frequency, Gain 2.06.
4Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): DRV602
0.0001
10
0.001
0.01
0.1
1
5
100m 5200m 500m 800m 2 3 4
V -OutputVoltage-Vrms
O
THD+N-TotalHarmonicDistortion+Noise-%
20Hz
1kHz
6.7kHz
20 20k50 100 200 500 1k 2k 5k
0.0001
10
0.001
0.01
0.1
1
5
THD+N-TotalHarmonicDistortion+Noise-%
f-Frequency-Hz
200mVrms
2Vrms
14m
12m
10m
8m
6m
4m
2m
0
-0 +1 +2 +3 +4 +5
QuiescentCurrent- A
V -SupplyVoltage-V
DD
NoLoad,
V =0V
I
+0
-20
-40
-60
-80
-100
-120
-140
05k 10k 20k15k
V = 2Vrms
O
FFT - dBr
f - Frequency - Hz
DRV602
www.ti.com
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS
VDD = 3.3V , TA= 25°C, C(PUMP) = C(PVSS) = 1 µF , CIN = 1 µF, RIN = 33 kΩ, Rfb = 68 kΩ, RL= 2.5 kΩ(unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT VOLTAGE FREQUENCY
Figure 1. Figure 2.
FFT QUIESCENT SUPPLY CURRENT
vs vs
FREQUENCY SUPPLY VOLTAGE
Figure 3. Figure 4.
Copyright © 2008–2010, Texas Instruments Incorporated 5
Product Folder Link(s): DRV602
OPAMP
Co
MuteCircuit
Output
Enable
+
+
+
-
ConventionalSolution
DRV602 Output
Enable
+
-
DVR602Solution
VDD
VSS
GND
VDD
VDD/2
GND
DirectPath
9-12V
5V
DRV602
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
www.ti.com
APPLICATION INFORMATION
Line Driver Amplifiers
Single-supply line driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 5 illustrates
the conventional line driver amplifier connection to the load and output signal.
DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click &
pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can reduce
the fidelity of the audio output signal.
Figure 5. Conventional and DirectPath Line Driver
The DirectPath™ amplifier architecture operates from a single supply, but makes use of an internal charge pump
to provide a negative voltage rail.
Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what
is effectively a split supply mode.
The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail.
The DirectPath amplifier requires no output dc blocking capacitors.
The bottom block diagram and waveform of Figure 5 illustrate the ground-referenced Line Driver architecture.
This is the architecture of the DRV602.
6Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): DRV602
Rfb
Rfb
+
-
Differential
Input
-In
+In
CIN RIN
RIN
CIN
RIN
CIN
+In
Rfb
Rx
+
-
Cx
Non
Inverting
DRV602
www.ti.com
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
Charge Pump Flying Capacitor and PVSS Capacitor
The charge pump flying capacitor, CPUMP, serves to transfer charge during the generation of the negative supply
voltage. The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum
charge transfer. Low ESR capacitors are an ideal selection, and a value of 1µF is typical. Capacitor values that
are smaller than 1µF can be used, but the maximum output voltage may be reduced and the device may not
operate to specifications.
Decoupling Capacitors
The DRV602 is a DirectPath Line Driver amplifier that require adequate power supply decoupling to ensure that
the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 1µF, placed as close as possible to the device PVDD lead works best. Placing this decoupling
capacitor close to the DRV602 is important for the performance of the amplifier. For filtering lower frequency
noise signals, a 10-µF or greater capacitor placed near the audio power amplifier would also help, but it is not
required in most applications because of the high PSRR of this device.
Gain setting resistors ranges
The gain setting resistors, RIN and Rfb, must be chosen so that noise, stability and input capacitor size of the
DRV602 is kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN . Selecting values that are too
high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different gain
settings.
Table 1. Recommended Resistor Values
INPUT RESISTOR FEEDBACK RESISTOR DIFFERENTIAL INPUT INVERTING INPUT GAIN NON INVERTING INPUT
VALUE, RIN VALUE, Rfb GAIN GAIN
22 kΩ22 kΩ1.0 V/V –1.0 V/V 2.0 V/V
15 kΩ30 kΩ1.5 V/V –1.5 V/V 2.5 V/V
33 kΩ68 kΩ2.1 V/V –2.1 V/V 3.1 V/V
10 kΩ100 kΩ10.0 V/V –10.0 V/V 11.0 V/V
Figure 6. Differential Input Figure 7. Inverting
Figure 8. Non-Inverting
Copyright © 2008–2010, Texas Instruments Incorporated 7
Product Folder Link(s): DRV602
fcIN +1
2pRIN CIN CIN +1
2pfcIN RIN
or
- In
DifferentialInput InvertingInput
DRV602
R1
R2
+
-
C3 R3 C1
C2
+ In
- In
R1
R2
+
-
C3 R3 C1
C2
C3 R1 R3 C1
R2
DRV602
DRV602
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
www.ti.com
Input-Blocking Capacitors
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the
DRV602. These capacitors block the DC portion of the audio source and allow the DRV602 inputs to be properly
biased to provide maximum performance. The input blocking capacitors also limit the DC gain to 1, limiting the
DC-offset voltage at the output.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using
Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the
input resistor chosen from Table 1, then the frequency and/or capacitance can be determined when one of the
two values are given.
(1)
Using the DRV602 as 2nd Order Filter
Several audio DACs used today require an external low-pass filter to remove out of band noise. This is possible
with the DRV602 as it can be used like a standard OPAMP.
Several filter topologies can be implemented both single ended and differential. In Figure 9, a Multi FeedBack -
MFB, with differential input and single ended input is shown.
An ac-coupling capacitor to remove dc-content from the source is shown, it serves to block any dc content from
the source and lowers the dc-gain to 1 helping reducing the output dc-offset to minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI website
at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
Figure 9. 2nd Order Active Low Pass Filter
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to
get a small size ac-coupling cap. With the proposed values, 33k, 68k, 100k, a DNR of 102dB can be achieved
with a small 1mF input ac-coupling capacitor.
8Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): DRV602
Supplyramp
Supply
EN
Timeforac-coupling
capacitorstocharge
DRV602
www.ti.com
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
Pop-Free Power Up
Pop-free power up is ensured by keeping the EN (enable pin) low during power supply ramp up and down. The
EN pin should be kept low until the input ac-coupling capacitors are fully charged before asserting the EN pin
high; this way, proper precharge of the ac-coupling is performed, and pop-free power-up is achieved. Figure 10
illustrates the preferred sequence.
Figure 10. Power-Up Sequence
Capacitive Load
The DRV602 has the ability to drive a high capacitive load up to 220pF directly, higher capacitive loads can be
accepted by adding a series resistor of 10Ωor larger.
Layout Recommendations
A proposed layout for the DRV602 can be seen in the DRV602EVM user's guide (SLOU248) and the Gerber files
can be downloaded on www.ti.com, open the DRV602 product folder and look in the Tools and Software folder.
The gain setting resistors, RIN and Rfb , must be placed close to the input pins to minimize the capacitive loading
on these input pins and to ensure maximum stability of the DRV602. For the recommended PCB layout, see the
DRV602EVM user's guide.
Copyright © 2008–2010, Texas Instruments Incorporated 9
Product Folder Link(s): DRV602
DRV602
SLOS572D –DECEMBER 2008–REVISED OCTOBER 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.
Changes from Revision A (December 2008) to Revision B Page
• Changed crosstalk spec from -80dB to -100dB .................................................................................................................... 4
Changes from Revision B (October 2009) to Revision C Page
• Added "Pop-Free" to title and changed "pop-less" to "pop-free in description text strings. ................................................. 1
• Added Output Voltage Feature bullet: "3Vrms With 5-V Supply Voltage" ............................................................................ 1
• Changed "2Vrms" to "3Vrms" in Description Section ........................................................................................................... 1
• Changed "5VPP" to "8.5VPP" in Description Section .............................................................................................................. 1
• Changed Recommended Operating Conditions TArange from "0 to 70 °C" to "–40 to 85°C" ............................................. 3
• Changed Electrical Characteristics Test Conditions VDD from "4.5 V" to "5 V" .................................................................... 3
• Added "VO" spec. for "VDD = 5 V" to Operating Characteristics table ................................................................................... 4
Changes from Revision May 2010 (C) to Revision D Page
• Changed Abs Max Table (TJ) From: -40°C to 85°C to -40°C to 150 .................................................................................... 3
• Changed RIGHT INPUT From: + / - To: - / + in the Application Circuit ................................................................................ 4
• Added RL= 2.5 kΩto the TYPICAL CHARACTERISTICS conditions statement ................................................................ 5
• Added , CPUMP, to the first sentence of the Charge Pump Flying Capacitor and PVSS Capacitor section .......................... 7
• Changed VDD To: PVDD in Decoupling Capacitors section ................................................................................................... 7
• Changed SD (shutdown pin) to EN (enable pin) in the Pop-Free Power Up section ........................................................... 9
• Deleted last sentence in the Capacitive Load section .......................................................................................................... 9
10 Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): DRV602
PACKAGE OPTION ADDENDUM
www.ti.com 9-Oct-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DRV602PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
DRV602PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DRV602PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DRV602PWR TSSOP PW 14 2000 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV602PWR TSSOP PW 14 2000 367.0 367.0 35.0
DRV602PWR TSSOP PW 14 2000 355.0 350.0 50.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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