W9864G6IH-6I - Winbond Electronics Corporation America

W9864G6IH

1M × 4BANKS × 16BITS SDRAM

Publication Release Date: Mar. 22, 2010

- 1 - Revision A11

Table of Contents-

1. GENERAL DESCRIPTION ......................................................................................................... 3

2. FEATURES ................................................................................................................................. 3

3. AVAILABLE PART NUMBER ..................................................................................................... 4

4. PIN CONFIGURATION...............................................................................................................4

5. PIN DESCRIPTION..................................................................................................................... 5

6. BLOCK DIAGRAM ...................................................................................................................... 6

7. FUNCTIONAL DESCRIPTION ................................................................................................... 7

7.1 Power Up and Initialization ............................................................................................. 7

7.2 Programming Mode Register Set command .................................................................. 7

7.3 Bank Activate Command ................................................................................................ 7

7.4 Read and Write Access Modes ...................................................................................... 7

7.5 Burst Read Command .................................................................................................... 8

7.6 Burst Command.............................................................................................................. 8

7.7 Read Interrupted by a Read ........................................................................................... 8

7.8 Read Interrupted by a Write............................................................................................ 8

7.9 Write Interrupted by a Write............................................................................................ 8

7.10 Write Interrupted by a Read............................................................................................ 8

7.11 Burst Stop Command ..................................................................................................... 9

7.12 Addressing Sequence of Sequential Mode .................................................................... 9

7.13 Addressing Sequence of Interleave Mode ..................................................................... 9

7.14 Auto-precharge Command ........................................................................................... 10

7.15 Precharge Command.................................................................................................... 10

7.16 Self Refresh Command ................................................................................................ 10

7.17 Power Down Mode ....................................................................................................... 11

7.18 No Operation Command............................................................................................... 11

7.19 Deselect Command ...................................................................................................... 11

7.20 Clock Suspend Mode.................................................................................................... 11

8. OPERATION MODE ................................................................................................................. 12

9. ELECTRICAL CHARACTERISTICS......................................................................................... 13

9.1 Absolute Maximum Ratings .......................................................................................... 13

9.2 Recommended DC Operating Conditions .................................................................... 13

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 2 - Revision A11

9.3 Capacitance.................................................................................................................. 13

9.4 DC Characteristics........................................................................................................ 14

9.5 AC Characteristics and Operating Condition................................................................ 15

10. TIMING WAVEFORMS ............................................................................................................. 18

10.1 Command Input Timing ................................................................................................ 18

10.2 Read Timing.................................................................................................................. 19

10.3 Control Timing of Input/Output Data............................................................................. 20

10.4 Mode Register Set Cycle .............................................................................................. 21

11. OPERATINOPERATING TIMING EXAMPLE........................................................................... 22

11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 22

11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 23

11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 24

11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 25

11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 26

11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 27

11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 28

11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)..................................... 29

11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 30

11.10 Auto-precharge Write (Burst Length = 4) .................................................................... 31

11.11 Auto Refresh Cycle ..................................................................................................... 32

11.12 Self Refresh Cycle....................................................................................................... 33

11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)............................. 34

11.14 Power down Mode....................................................................................................... 35

11.15 Auto-precharge Timing (Write Cycle).......................................................................... 36

11.16 Auto-precharge Timing (Read Cycle) ......................................................................... 37

11.17 Timing Chart of Read to Write Cycle........................................................................... 38

11.18 Timing Chart of Write to Read Cycle........................................................................... 38

11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39

11.20 Timing Chart of Burst Stop Cycle (Precharge Command).......................................... 39

11.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 40

11.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 41

12. PACKAGE SPECIFICATION .................................................................................................... 42

12.1 54L TSOP (II)-400 mil................................................................................................... 42

13. REVISION HISTORY ................................................................................................................43

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 3 - Revision A11

1. GENERAL DESCRIPTION

W9864G6IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as

1M words × 4 banks × 16 bits. W9864G6IH delivers a data bandwidth of up to 200M words per second.

For different application, W9864G6IH is sorted into the following speed grades: -5/-6/-6I/-6A/-7 and -

7S. The -5 parts can run up to 200MHz/CL3. The -6/-6I/-6A parts can run up to 166MHz/CL3 (the -6I

industrial grade, -6A automotive grade which is guaranteed to support -40°C ~ 85°C). The -7/-7S parts

can run up to 143MHz/CL3 and with tRP = 18nS.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE

command. Column addresses are automatically generated by the SDRAM internal counter in burst

operation. Random column read is also possible by providing its address at each clock cycle.

The multiple bank nature enables interleaving among internal banks to hide the precharging time.By

having a programmable Mode Register, the system can change burst length, latency cycle, interleave

or sequential burst to maximize its performance. W9864G6IH is ideal for main memory in high

performance applications.

2. FEATURES

• 3.3V± 0.3V for -5/-6/-6I/-6A speed grades power supply

• 2. 7V~3.6V for -7/-7S speed grades power supply

• 1,048,576 words × 4 banks × 16 bits organization

• Self Refresh Current: Standard and Low Power

• CAS Latency: 2 & 3

• Burst Length: 1, 2, 4, 8 and full page

• Sequential and Interleave Burst

• Byte data controlled by LDQM, UDQM

• Auto-precharge and controlled precharge

• Burst read, single write operation

• 4K refresh cycles/64mS

• Interface: LVTTL

• Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS compliant

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 4 - Revision A11

3. AVAILABLE PART NUMBER

PART NUMBER SPEED SELF REFRESH

CURRENT (MAX.)

OPERATING

TEMPERATURE

W9864G6IH-5 200MHz/CL3 2 mA 0°C ~ 70°C

W9864G6IH-6 166MHz/CL3 2 mA 0°C ~ 70°C

W9864G6IH-6I 166MHz/CL3 2 mA -40°C ~ 85°C

W9864G6IH-6A 166MHz/CL3 2 mA -40°C ~ 85°C

W9864G6IH-7 143MHz/CL3 2 mA 0°C ~ 70°C

W9864G6IH-7S 143MHz/CL3 2 mA 0°C ~ 70°C

4. PIN CONFIGURATION

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

LDQM

CAS

RAS

BS0

BS1

A10/AP

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

UDQM

CLK

CKE

A11

VDDQ

VSSQ

VDD

VSS

VSSQ

VDDQ

VSS

VDD

VDDQ

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 5 - Revision A11

5. PIN DESCRIPTION

PIN NUMBER PIN NAME FUNCTION DESCRIPTION

23 ~ 26, 22,

29 ~35 A0−A11 Address

Multiplexed pins for row and column address.

Row address: A0−A11. Column address: A0−A7.

A10 is sampled during a precharge command to

determine if all banks are to be precharged or bank

selected by BS0, BS1.

20, 21 BS0, BS1 Bank Select Select bank to activate during row address latch time,

or bank to read/write during address latch time.

2, 4, 5, 7, 8, 10,

11, 13, 42, 44,

45, 47, 48, 50,

51, 53

DQ0−DQ15 Data

Input/ Output Multiplexed pins for data output and input.

19 CS Chip Select

Disable or enable the command decoder. When

command decoder is disabled, new command is

ignored and previous operation continues.

18 RAS Row Address

Strobe

Command input. When sampled at the rising edge of

the clock RAS , CAS and WE define the

operation to be executed.

17 CAS Column

Address Strobe Referred to RAS

16 WE Write Enable Referred to RAS

39, 15 UDQM

LDQM

Input/output

mask

The output buffer is placed at Hi-Z (with latency of 2)

when DQM is sampled high in read cycle. In write

cycle, sampling DQM high will block the write

operation with zero latency.

38 CLK Clock Inputs

System clock used to sample inputs on the rising

edge of clock.

37 CKE Clock Enable

CKE controls the clock activation and deactivation.

When CKE is low, Power Down mode, Suspend

mode, or Self Refresh mode is entered.

1, 14, 27 VDD Power Power for input buffers and logic circuit inside DRAM.

28, 41, 54 VSS Ground

Ground for input buffers and logic circuit inside

DRAM.

3, 9, 43, 49 VDDQ Power for I/O

buffer

Separated power from VDD, to improve DQ noise

immunity.

6, 12, 46, 52 VSSQ Ground for I/O

buffer

Separated ground from VSS, to improve DQ noise

immunity.

36, 40 NC No Connection No connection.

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 6 - Revision A11

6. BLOCK DIAGRAM

DQ0

DQ15

UDQM

LDQM

CLK

CKE

A10

CLOCK

BUFFER

COMMAND

DECODER

ADDRESS

BUFFER

REFRESH

COUNTER

COLUMN

COUNTER

CONTROL

SIGNAL

GENERATOR

MODE

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #2

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #0

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #3

DATA CONTROL

CIRCUIT

BUFFER

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #1

NOTE:

The cell array configuration is 4096 * 256 * 16

ROW DECODER ROW DECODER

ROW DECODERROW DECODER

BS0

BS1

RAS

CAS

A11

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 7 - Revision A11

7. FUNCTIONAL DESCRIPTION

7.1 Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and

initialization sequence need to be followed to guarantee the device being preconditioned to each user

specific needs.

During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage

when the input signals are held in the "NOP" state. The power up voltage must not exceed VDD + 0.3V

on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required

followed by a precharge of all banks using the precharge command. To prevent data contention on the

DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial

pause period. Once all banks have been precharged, the Mode Register Set Command must be

issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required

before or after programming the Mode Register to ensure proper subsequent operation.

7.2 Programming Mode Register Set command

After initial power up, the Mode Register Set Command must be issued for proper device operation.

All banks must be in a precharged state and CKE must be high at least one cycle before the Mode

signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data

during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A

new command may be issued following the mode register set command once a delay equal to tRSC

has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

7.3 Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.

The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS

to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive

Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice

versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is

specified as tRAS (max.).

7.4 Read and Write Access Modes

After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting

RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level

defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The

address inputs determine the starting column address. Reading or writing to a different row within an

activated bank requires the bank be precharged and a new Bank Activate command be issued. When

more than one bank is activated, interleaved bank Read or Write operations are possible. By using the

programmed burst length and alternating the access and precharge operations between multiple

banks, seamless data access operation among many different pages can be realized. Read or Write

Commands can also be issued to the same bank or between active banks on every clock cycle.

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 8 - Revision A11

7.5 Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding

RAS and WE high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst

length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page

explain the address sequence of interleave mode and sequence mode.

7.6 Burst Command

The Burst Write command is initiated by applying logic low level to CS , CAS and WE while

holding RAS high at the rising edge of the clock. The address inputs determine the starting column

address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle

that the Write Command is issued. The remaining data inputs must be supplied on each subsequent

rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes

will be ignored.

7.7 Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,

the remaining addresses are overridden by the new read address with the full burst length. The data

from the first Read Command continues to appear on the outputs until the CAS Latency from the

interrupting Read Command the is satisfied.

7.8 Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output

drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will

issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the

DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM

masking is no longer needed.

7.9 Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the

previous burst is interrupted, the remaining addresses are overridden by the new address and data

will be written into the device until the programmed burst length is satisfied.

7.10 Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read

Command is activated. The DQs must be in the high impedance state at least one cycle before the

new read data appears on the outputs to avoid data contention. When the Read Command is

activated, any residual data from the burst write cycle will be ignored.

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 9 - Revision A11

7.11 Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank

open for future Read or Write Commands to the same page of the active bank, if the burst length is full

page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop

Command is defined by having RAS and CAS high with CS and WE low at the rising edge of

the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS

Latency in a burst read cycle, interrupted by Burst Stop.

7.12 Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to

the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 n BL = 2 (disturb address is A0)

Data 1 n + 1 No address carry from A0 to A1

Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)

Data 3 n + 3 No address carry from A1 to A2

Data 4 n + 4

Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)

Data 6 n + 6 No address carry from A2 to A3

Data 7 n + 7

7.13 Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit

in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2

Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 4

Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 8

Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 10 - Revision A11

7.14 Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is

entered. During auto-precharge, a Read Command will execute as normal with the exception that the

active bank will begin to precharge automatically before all burst read cycles have been completed.

Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by CAS Latency.

A Read or Write Command with auto-precharge cannot be interrupted before the entire burst

operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is

prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started,

the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-

Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write

Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically

enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred

to as write tWR. The bank undergoing auto-precharge cannot be reactivated until tWR and tRP are

satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-

precharge Command, the interval between the Bank Activate Command and the beginning of the

internal precharge operation must satisfy tRAS (min).

7.15 Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The

Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising

edge of the clock. The Precharge Command can be used to precharge each bank separately or all

banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to

be precharged when the command is issued. After the Precharge Command is issued, the precharged

bank must be reactivated before a new read or write access can be executed. The delay between the

Precharge Command and the Activate Command must be greater than or equal to the Precharge time

(tRP).

7.16 Self Refresh Command

The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE

high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.

Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.

When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are

disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will

exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after

tXSR from the end of Self Refresh Command.

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly

distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and

just after exiting the self refresh mode.

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 11 - Revision A11

7.17 Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are

gated off to reduce the power. The Power Down mode does not perform any refresh operations,

therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the

device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation

Command is required on the next rising clock edge, depending on tCK. The input buffers need to be

enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).

7.18 No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to

prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of

the clock. A No Operation Command will not terminate a previous operation that is still executing,

such as a burst read or write cycle.

7.19 Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect

Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't Care.

7.20 Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low

while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode

deactivates the internal clock and suspends any clocked operation that was currently being executed.

There is a one clock delay between the registration of CKE low and the time at which the SDRAM

operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are

issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay

from when CKE returns high to when Clock Suspend mode is exited.

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 12 - Revision A11

8. OPERATION MODE

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 1 shows the truth table for the operation commands.

Table 1 Truth Table (Note (1), (2))

COMMAND DEVICE

STATE CKEn-1 CKEn DQM BS0, 1 A10 A0-A9,

A11 CS RAS CAS WE

Bank Active Idle H x x v v V L L H H

Bank Precharge Any H x x v L x L L H L

Precharge All Any H x x x H x L L H L

Write Active

(3) H x x v L v L H L L

Write with Auto-precharge Active (3) H x x v H v L H L L

Read Active

(3) H x x v L v L H L H

Read with Auto-precharge Active (3) H x x v H v L H L H

Mode Register Set Idle H x x v v v L L L L

No-Operation Any H x x x x x L H H H

Burst Stop Active (4) H x x x x x L H H L

Device Deselect Any H x x x x x H x x x

Auto-Refresh Idle H H x x x x L L L H

Self-Refresh Entry Idle H L x x x x L L L H

Self Refresh Exit idle

(S.R)

Clock suspend Mode

Entry Active H L x x x x x x x x

Power Down Mode Entry Idle

Active (5)

Clock Suspend Mode Exit Active L H x x x x x x x X

Power Down Mode Exit

Any

(Power

Down)

Data write/Output Enable Active H x L x x x x x x x

Data write/Output Disable Active H x H x x x x x x x

Notes:

(1) v = valid, x = Don't care, L = Low Level, H = High Level

(2) CKEn signal is input leve l when commands are provided.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 13 - Revision A11

9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings

PARAMETER SYMBOL RATING UNIT NOTES

Input, Output Voltage VIN, VOUT -0.5 ~ VDD + 0.5 (≤ 4.6V max.) V 1

Power Supply Voltage VDD, VDDQ -0.5 ~ 4.6 V 1

Operating Temperature (-5/-6/-7/-7S) TOPR 0 ~ 70 °C 1

Operating Temperature (-6I/-6A) TOPR -40 ~ 85 °C 1

Storage Temperature TSTG -55 ~ 150 °C 1

Soldering Temperature (10s) TSOLDER 260 °C 1

Power Dissipation PD 1 W 1

Short Circuit Output Current IOUT 50 mA 1

NOTE:

1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of

the device.

9.2 Recommended DC Operating Conditions

(TA = 0 to 70°C for -5/-6/-7/-7S, TA = -40 to 85°C for -6I/-6A)

PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES

Power Supply Voltage for -5/-6/-6I/-6A VDD 3.0 3.3 3.6 V 2

Power Supply Voltage for -7/-7S VDD 2.7 - 3.6 V 2

Power Supply Voltage (I/O Buffer) for -5/-6/-6I/-6A VDDQ 3.0 3.3 3.6 V 2

Power Supply Voltage (I/O Buffer) for -7/-7S VDDQ 2.7 - 3.6 V 2

Input High Voltage VIH 2.0 - VDD + 0.3 V 2

Input Low Voltage VIL -0.3 - 0.8 V 2

Note: VIH(max) = VDD/ VDDQ+1.5V for pulse width < 5 nS

IL(min) = VSS/ VSSQ-1.5V for pulse width < 5 nS

9.3 Capacitance

(VDD =3V±0.3V for-5/-6/-6I/-6A, VDD = 2.7V-3.6V for -7/-7S , TA = 25 °C, f = 1 MHz)

PARAMETER SYM. MIN. MAX. UNIT

Input Capacitance

(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , CKE)

Ci1 2.5 4 pf

Input Capacitance (CLK) CCLK 2.5 4 pf

Input/Output Capacitance (DQ0−DQ15) Co 4 6.5 pf

Input Capacitance DQM Ci2 3.0 5.5 pf

Note: These parameters are periodically sampled and not 100% tested

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 14 - Revision A11

9.4 DC Characteristics

(VDD = 3V±0.3V for-5/-6 ,VDD = 2.7V-3.6V for -7/-7S on TA = 0 to 70°C, VDD =3V±0.3V for -6I/-6A on TA = -40 to 85°C)

MAX.

PARAMETER SYM.

-5 -6/-6I/-6A -7/-7S

UNIT NOTES

Operating Current

tCK = min., tRC = min.

Active precharge command

cycling without burst operation

1 Bank Operation

IDD1 100 90 80 3

Standby Current

tCK = min., CS = VIH

VIH/L = VIH (min.)/VIL (max.)

CKE = VIH IDD2 40 35 30 3

Bank: Inactive State CKE = VIL

(Power Down mode) IDD2P 2 2 2 3

Standby Current

CLK = VIL, CS = VIH

VIH/L=VIH (min.)/VIL (max.)

CKE = VIH IDD2S 15 15 15

Bank: Inactive State CKE = VIL

(Power Down mode) IDD2PS 2 2 2 mA

No Operating Current

tCK = min., CS = VIH (min.) CKE = VIH IDD3 65 60 55

Bank: Active State (4 Banks) CKE = VIL

(Power Down mode) IDD3P 15 15 15

Burst Operating Current

(tCK = min.)

Read/Write command cycling

IDD4 180 165 145 3, 4

Auto Refresh Current

(tCK = min.)

Auto refresh command cycling

IDD5 160 140 120 3

Self Refresh Current

Self refresh mode

(CKE = 0.2V)

IDD6 2 2 2

PARAMETER SYMBOL MIN. MAX. UNIT NOTES

Input Leakage Current

(0V ≤ VIN ≤ VDD, all other pins not under test = 0V) II(L) -5 5 µA

Output Leakage Current

(Output disable, 0V ≤ VOUT ≤ VDDQ) lO(L) -5 5 µA

LVTTL Output “H” Level Voltage

(IOUT = -2 mA) VOH 2.4 - V

LVTTL Output “L” Level Voltage

(IOUT = 2 mA) VOL - 0.4 V

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 15 - Revision A11

9.5 AC Characteristics and Operating Condition

(VDD = 3V±0.3V for-5/-6, VDD = 2.7V-3.6V for -7/-7S on TA = 0 to 70°C, VDD = 3V±0.3V for -6I/-6A on TA = -40 to 85°C)

(Notes: 5, 6)

-5 -6/-6I/-6A -7/-7S

PARAMETER SYM.

MIN. MAX. MIN. MAX. MIN. MAX.

UNIT NOTES

Ref/Active to Ref/Active Command

Period tRC 55 60 65

Active to precharge Command Period tRAS 40 100000 42 100000 45 100000 nS

Active to Read/Write Command Delay

Time tRCD 15 15 20

Read/Write(a) to Read/Write(b)

Command Period tCCD 1 1 1 tCK

Precharge to Active Command Period tRP 15 15 18

Active(a) to Active(b) Command Period tRRD 10 12 14 nS

CL* = 2 2 2 2

Write Recovery Time CL* = 3 tWR 2 2 2 tCK

CL* = 2 10 1000 7.5 1000 10 1000

CLK Cycle Time CL* = 3 tCK 5 1000 6 1000 7 1000

CLK High Level Width tCH 2 2 2 9

CLK Low Level Width tCL 2 2 2 9

CL* = 2 - 6 6 10

Access Time from CLK CL* = 3 tAC 4.5 5 5.5 10

Output Data Hold Time tOH 2 2 2 10

Output Data High Impedance Time tHZ 2 5 2 6 2 7 7

Output Data Low Impedance Time tLZ 0 0 0 10

Power Down Mode Entry Time tSB 0 5 0 6 0 7 nS

Transition Time of CLK (Rise and Fall) tT 1 1 1

Data-in Set-up Time tDS 1.5 1.5 1.5 9

Data-in Hold Time tDH 1 1 1 9

Address Set-up Time tAS 1.5 1.5 1.5 9

Address Hold Time tAH 1 1 1 9

CKE Set-up Time tCKS 1.5 1.5 1.5 9

CKE Hold Time tCKH 1 1 1 9

Command Set-up Time tCMS 1.5 1.5 1.5 9

Command Hold Time tCMH 1 1 1 9

Refresh Time tREF 64 64 64 mS

Mode register Set Cycle Time tRSC 2 2 2 tCK

Exit self refresh to ACTIVE command tXSR 70 72 75 nS

*CL = CAS Latency

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 16 - Revision A11

Notes:

1.Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.

2. All voltages are referenced to VSS

‧2.7V~3.6V power supply for -7/-7S speed grade.

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the

minimum values of tCK and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with

output open.

5. Power up sequence please refer to "Functional Description" section described before.

6. AC Test Load diagram.

50 ohms

1.4 V

AC TEST LOAD

Z = 50 ohmsoutput

30pF

7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to

output level.

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 17 - Revision A11

8. These parameters account for the number of clock cycles and depend on the operating frequency

of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count

fractions as whole number)

(1)tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).

tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).

(2)A.C Latency Characteristics

CKE to clock disable (CKE Latency) 1 tCK

DQM to output to HI-Z (Read DQM Latency) 2

DQM to output to HI-Z (Write DQM Latency) 0

Write command to input data (Write Data Latency) 0

CS to Command input ( CS Latency) 0

Precharge to DQ Hi-Z Lead time CL = 2 2

CL = 3 3

Precharge to Last Valid data out CL = 2 1

CL = 3 2

Bust Stop Command to DQ Hi-Z Lead time CL = 2 2

CL = 3 3

Bust Stop Command to Last Valid Data out CL = 2 1

CL = 3 2

Read with Auto-precharge Command to Active/Ref Command CL = 2 BL + tRP tCK + nS

CL = 3 BL + tRP

Write with Auto-precharge Command to Active/Ref Command CL = 2 (BL+1) + tRP

CL = 3 (BL+1) + tRP

9. Assumed input rise and fall time (tT ) = 1nS.

If tr & tf is longer than 1nS, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]nS should be added to the parameter

( The tT maximum can’t be more than 10nS for low frequency application. )

10. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 18 - Revision A11

10. TIMING WAVEFORMS

10.1 Command Input Timing

CLK

A0-A11

BS0,1

VIH

VIL

tCMH tCMS

tCHtCL

tTtT

tCKS tCKH

tCKH

tCKStCKS tCKH

RAS

CAS

CKE

tCMS tCMH

tAS tAH

tCK

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 19 - Revision A11

10.2 Read Timing

Read CAS Latency

tAC

tLZ

tAC

tOH

tHZ

tOH

Burst Length

Read Command

CLK

RAS

CAS

A0-A11

BS0,1

DQ Valid

Data-Out

Valid

Data-Out

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 20 - Revision A11

10.3 Control Timing of Input/Output Data

tCMH tCMS tCMH tCMS

tDS tDH tDS tDH tDS tDH tDS tDH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

tCKH tCKS tCKH tCKS

tDS tDH tDS tDH tDH

tDS tDS tDH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

tCMH tCMS tCMH tCMS

tOH

tAC

tOH

tAC

tOH

tHZ

OPEN

tLZ

tAC

tOH

tAC

tCKH tCKS tCKH tCKS

tOH

tAC

tOH

tAC

tOH

tAC

tOH

tAC

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

CLK

DQM

DQ0~15

(Word Mask)

(Clock Mask)

CLK

CKE

DQ0~15

CLK

Control Timing of Input Data

Control Timing of Output Data

(Output Enable)

(Clock Mask)

DQM

DQ0~15

CKE

CLK

DQ0~15

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 21 - Revision A11

10.4 Mode Register Set Cycle

A3 Addressing Mode

0Sequential

1Interleave

A0A9 Single Write Mode

0Burst read and Burst write

1Burst read and single write

A0A2 A1 A0

A00 0 0

0 0 1

A00 1 0

A00 1 1

A01 0 0

1 0 1

1 1 0

1 1 1

Burst Length

Sequential Interleave

1 1

2 2

4 4

8 8

Reserved Reserved

Full Page

CAS Latency

Reserved

A0A6 A5 A4

A00 0 0

0 1 0

A00 1 1

A01 0 0

A00 0 1

* "Reserved" should stay "0" during MRS cycle.

tRSC

tCMS tCMH

tAS tAH

CLK

RAS

CAS

A0-A11

BS0,1

set data

command

Burst Length

Addressing Mode

CAS Latency

(Test Mode)

A9 A0Write Mode

A10

BS0

A0A11

"0"

Reserved

BS1 "0"

Reserved

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 22 - Revision A11

11. OPERATINOPERATING TIMING EXAMPLE

11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CKE

DQM

A0-A9,

A11

A10

tRC tRC

tRAS tRP tRAS tRP

tRPtRAS tRAS

tRCD tRCD tRCD tRCD

tAC tAC tAC tAC

tRRD tRRD tRRD tRRD

Active Read

Active

Read

Precharge

RAa RBb RAc RBd RAe

RAa CAw RBb CBx RAc CAy RBd CBz RAe

aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3

RAS

CAS

BS1

BS0

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 23 - Revision A11

11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CKE

DQM

A0-A9,

A11

A10

BS1

CAS

RAS

BS0

tRC tRC

tRC

tRAS tRP tRAS tRP

tRAS tRP

tRCD tRCD tRCD

tAC tAC tAC tAC

tRRD tRRD tRRD tRRD

Active Read

Active

Read

tRC

RAa RAc RBd RAe

DQ aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0

* AP is the internal precharge start timing

AP* AP*

RAa CAw RBb CBx RAc CAy RBd RAe

CBz

RBb

AP*

tRCD

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 24 - Revision A11

11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)

012345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC

tRAS tRP

tRP tRAS

tRCD tRCD tRCD

tRRD tRRD

RAa

RAa CAx

RBb

RBb CBy

RAc

RAc CAz

ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0

CLK

CKE

DQM

A0-A9,

A11

A10

BS1

CAS

RAS

Active Read

Precharge Active Read

Precharge Active

tAC tAC

Read

Precharge

tAC

BS0

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 25 - Revision A11

11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)

A0-A9,

A11

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC

tRAS tRP

tRAS

tRCD tRCD tRCD

tRRD tRRD

ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0

RAa

CAx

RBb

RBb CBy

RAc

RAc CAz

* AP is the internal precharge start timing

Active Read

Active

Active Read

tAC tAC

tAC

CLK

CKE

DQM

A10

CAS

RAS

Read

AP*

BS1

BS0

tRAS

tRP

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 26 - Revision A11

11.5 Interleaved Bank Write (Burst Length = 8)

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC

tRAS tRP

tRAS

tRCD tRCD tRCD

tRRD tRRD

RAa

RAa CAx

RBb

RBb CBy

RAc

RAc CAz

ax0 ax1 by4 by5 by6 by7 CZ0 CZ1 CZ2

Write

Precharge

Active

Active Write

Precharge

Active Write

CLK

CKE

DQM

A0-A9,

A11

A10

BS1

CAS

RAS

Idle

Bank #0

Bank #1

Bank #2

Bank #3

BS0

ax4 ax5 ax6 ax7 by0 by1 by2 by3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 27 - Revision A11

11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC

tRAS tRP

tRAS

tRCD tRCD tRCD

tRRD tRRD

RAa

RAa CAx

RBb

RBb CBy

RAb

RAc

ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2

CAz

* AP is the internal precharge start timing

CLK

CKE

DQM

A0-A9,

A11

A10

BS1

CAS

RAS

Active Write Write

Active

Bank #0

Idle

Bank #1

Bank #2

Bank #3

AP*

Active Write AP*

BS0

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 28 - Revision A11

11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

tCCD tCCD tCCD

tRAS

tRCD tRCD

tRRD

RAa

RAa CAI

RBb

RBb CBx CAy CAm CBz

a0 a1 a2 a3 bx0 bx1 Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3

* AP is the internal precharge start timing

CLK

CKE

DQM

A0-A9,

A11

A10

BS1

CAS

RAS

Active Read

Read Read

Read

Precharge

tAC

Bank #0

Idle

Bank #1

Bank #2

Bank #3

AP*

BS0

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 29 - Revision A11

11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

tRAS

tRCD

tWR

RAa

RAa CAx CAy

ax0 ax1 ax2 ax3 ax4 ax5 ay1

ay0 ay2 ay4ay3

QQ Q Q Q Q DDD

CLK

CKE

DQM

A0-A9,

A11

A10

BS1

CAS

RAS

Active Read Write Precharge

tAC

Bank #0

Idle

Bank #1

Bank #2

Bank #3

BS0

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 30 - Revision A11

11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CKE

DQM

A0-A9,

A11

A10

CAS

RAS

BS1

tRC

tRAS tRP tRAS

tRCD tRCD

tAC tAC

Active Read AP* Active Read AP*

RAa RAb

RAa CAw RAb CAx

aw0 aw1 aw2 aw3

* AP is the internal precharge start timing

Bank #0

Idle

Bank #1

Bank #2

Bank #3

BS0

bx0 bx2

bx1 bx3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 31 - Revision A11

11.10 Auto-precharge Write (Burst Length = 4)

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

CKE

DQM

A0-A9,

A11

A10

CAS

RAS

BS1

tRC tRC

tRP tRAS tRP

RAa

tRCD tRCD

RAb RAc

RAa RAb CAx RAc

bx0 bx1 bx2 bx3

Active

Active Write AP* Active Write AP*

* AP is the internal precharge start timing

Bank #0

Idle

Bank #1

Bank #2

Bank #3

tRAS

BS0

CAw

aw0 aw1 aw2 aw3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 32 - Revision A11

11.11 Auto Refresh Cycle

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

All Banks

Prechage

Auto

Refresh Auto Refresh (Arbitrary Cycle)

tRCtRP tRC

CLK

CKE

DQM

A0-A9,

A11

A10

CAS

RAS

BS0,1

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 33 - Revision A11

11.12 Self Refresh Cycle

CLK

CKE

DQM

A0-A9,

A11

A10

BS0,1

CAS

RAS

tCKS

tSB tCKS

All Banks

Precharge

Self Refresh

Entry

Arbitrary Cycle

tRP

Self Refresh Cycle

tXSR

No Operation / Command Inhibit

Self Refresh

Exit

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 34 - Revision A11

11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

RAS

CAS

BS1

BS0

A10

A0-A9,

A11

DQM

CKE

tRCD

RBa

RBa CBv CBw CBx CBy CBz

av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3

QQ Q Q D DDQQQQ

tAC tAC

Read Read

Single WriteActive

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 35 - Revision A11

11.14 Power down Mode

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23

RAa CAa RAa CAx

RAa RAa

ax0 ax1 ax2 ax3

tSB

tCKS tCKS tCKS

tSB

tCKS

Active Standby

Power Down mode

Precharge Standby

Power Down mode

Active NOP Precharge NOP Active

Note: The Power Down Mode is entered by asserting CKE "low".

All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.

When CKE goes high, command input must be No operation at next CLK rising edge.

Violating refresh requirements during power-down may result in a loss of data.

CLK

CKE

DQM

A0-A9,

A11

A10

CAS

RAS

Read

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 36 - Revision A11

11.15 Auto-precharge Timing (Write Cycle)

Act

01 32

(1) CAS Latency = 2

(a) burst length = 1

45 76891110

Write

ActAP

Command

(b) burst length = 2

Write

ActAP

Command

tRP

Write

ActAP

Command

tRP

(d) burst length = 8

Write

ActAP

Command

tRP

D2 D3

D2 D3 D4 D5 D6 D7

(2) CAS Latency = 3

(a) burst length = 1

Write

ActAP

Command

(b) burst length = 2

Write

ActAP

Command

tRP

Write

ActAP

Command

tRP

(d) burst length = 8

Write

Command

tRP

D2 D3

D2 D3 D4 D5 D6 D7

tWR

Act

represents the Write with Auto precharge command.

represents the start of internal precharing.

represents the Bank Active command.

Write

Act

When the /auto precharge command is asserted,the period from Bank Activate

command to the start of intermal precgarging must be at least tRAS (min).

Note )

CLK

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 37 - Revision A11

11.16 Auto-precharge Timing (Read Cycle)

Read AP

0 1110987654321

Read AP Act

Q1 Q2

AP ActRead

Act

(1) CAS Latency=2

Read

Act

When the Auto precharge command is asserted, the period from Bank Activate command to

the start of internal precgarging must be at least t

RAS

(min).

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

Note )

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

Read AP Act

Q1 Q2 Q3

Read AP Act

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

(2) CAS Latency=3

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 38 - Revision A11

11.17 Timing Chart of Read to Write Cycle

Note: The Output data must be masked by DQM to avoid I/O conflict

1110987654321

(1) CAS Latency=2

In the case of Burst Length = 4

Read

Write

( b ) Command

DQM

D0 D1 D2 D3

( a ) Command

(2) CAS Latency=3

Read Write

D0 D1 D2 D3

( a ) Command

DQM

( b ) Command

DQM

D0 D1 D2 D3

11.18 Timing Chart of Write to Read Cycle

ReadWrite

01110987654321

Read

Q1 Q2 Q3

Read

Write

Q0 Q1 Q2 Q3

Write

Q0 Q1 Q2 Q3

D0 D1

( a ) Command

DQM

( b ) Command

DQM

( a ) Command

( b ) Command

DQM

In the case of Burst Length=4

(1) CAS Latency=2

(2) CAS Latency=3

D0 D1

Q0 Q1 Q2 Q3D0

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 39 - Revision A11

11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)

Read BST

0 1110987654321

Q0 Q1 Q2 Q3

BST

( a ) CAS latency =2

Command

( b )CAS latency = 3

(1) Read cycle

(2) Write cycle

Command

Read

Command

Q0 Q1 Q2 Q3 Q4

Write BST

Note: represents the Burst stop command

BST

11.20 Timing Chart of Burst Stop Cycle (Precharge Command)

01 111098765432

(1) Read cycle

(a) CA S latency =2

C om m a nd

Q0 Q1 Q2 Q3 Q4

PRCGRead

(b) CA S latency =3

C om m a nd

Q0 Q1 Q2 Q3 Q4

PRCGRead

(2) Write cycle

Command

Q0 Q1 Q2 Q3 Q4

PRCG

Write

DQM

tW R

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 40 - Revision A11

11.21 CKE/DQM Input Timing (Write Cycle)

5432

CKE MASK

( 1 )

D1 D6D5D3D2

CLK cycle No.

External

Internal

CKE

DQM

5432

( 2 )

D1 D6

D3D2

CLK cycle No.

External

Internal

CKE

DQM

5432

( 3 )

D1 D6D5D4

D3D2

CLK cycle No.

External

CKE

DQM

DQM MASK

DQM MASK CKE MASK

CKE MASK

Internal

CLK

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 41 - Revision A11

11.22 CKE/DQM Input Timing (Read Cycle)

5432

( 1 )

Q1 Q6

Q4Q3Q2

CLK cycle No.

External

Internal

CKE

DQM

Open Open

5432

Q1 Q6

CLK cycle No.

External

Internal

CKE

DQM

Open

( 2 )

765432

Q1 Q6

CLK cycle No.

External

Internal

CKE

DQM

Q5Q4

( 3 )

CLK

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 42 - Revision A11

12. PACKAGE SPECIFICATION

12.1 54L TSOP (II)-400 mil

Controlling Dimension : Millimeters

ZD 0.71

0.002

0.012

MAX.MIN. NOM.

0.30

1.00

0.05

0.45

1.20

0.15

SYMBOL

DIMENSION

(MM)

MAX.

MIN. NOM.

e0.80

L0.40 0.50 0.60

E10.03 10.16 10.29

0.870

D22.2222.09 22.35

0.039

DIMENSION

(INCH)

L1 0.80

11.7611.56 11.96

Y0.1 (*0.08)

SEATING PLANE

127

54 28

0.95 1.05

0.12 0.21

0.037

0.395

0.455

0.016

0.875

0.400

0.463

0.031

0.020

0.031

0.028

0.047

0.006

0.041

0.018

0.0080.005

0.880

0.405

0.471

0.024

0.004 (*0.00315)

Note:｀*＇is only for -7S

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 43 - Revision A11

13. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

A01 Dec. 12, 2007 All Initial formal data sheet

A02 Dec. 24, 2007 3, 4,

13~15 Remove -6I grade parts

Revise overshoot/undershoot pulse width

Before VIH (max.) = VCC/VCCQ +1.2V for pulse width < 5 nS

After VIH (max.) = VCC/VCCQ +1.2V for pulse width < 3 nS

Before VIL (min.) = VSS/VSSQ -1.2V for pulse width < 5 nS

After VIL (min.) = VSS/VSSQ -1.2V for pulse width < 3 nS

A03 Jan. 29, 2008

3, 4, 15 Revise -7/-7S parts AC parameter CLK cycle time of CL2

tCK value from 7nS to 7.5nS

A04 Feb. 26, 2008 15 Revise -6 part AC parameter Access Time from CLK of

CL2 tAC value from 5.5nS to 6nS

Revise overshoot/undershoot pulse width

Before VIH (max.) = VCC/VCCQ +1.2V for pulse width < 3 nS

After VIH (max.) = VCC/VCCQ +1.5V for pulse width < 5 nS

Before VIL (min.) = VSS/VSSQ -1.2V for pulse width < 3 nS

After VIL (min.) = VSS/VSSQ -1.5V for pulse width < 5 nS

A05 Mar. 28, 2008

15 Revise AC parameter CLK cycle time of CL2 tCK value

from 7.5nS to 10nS

A06 Jul. 10, 2008 3, 4,

13~15 Add -6I grade parts

A07 Aug. 01, 2008 42 Update 54L TSOP (II) package drawing and dimensions

A08 Sep. 11, 2008 3, 15 Revise -7 parts AC parameter tRP value from 20nS to 18nS

13 Revise Input/Output Voltage and Power Supply Voltage

spec. in section 9.1 Absolute Maximum Ratings table

A09 Jul. 10, 2009

15 Revise -6 parts tRP and tRCD value from 18nS to 15nS

A10 Aug. 10, 2009 15 Revise -6I parts tRP and tRCD value from 18nS to 15nS

A11 Mar. 22, 2010 3, 4,

13~15 Add -6A Automotive grade parts

W9864G6IH

Publication Release Date: Mar. 22, 2010

- 44 - Revision A11

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.