DATA SH EET
File under Integrated Circuits, IC06 March 1988
INTEGRATED CIRCUITS
FAMILY SPECIFICATIONS
HCMOS family characteristics
March 1988 2
Philips Semiconductors
HCMOS family characteristics FAMILY
SPECIFICATIONS
GENERAL
These family specifications cover the common electrical
ratings and characteristics of the entire HCMOS
74HC/HCT/HCU family, unless otherwise specified in the
individual device data sheet.
INTRODUCTION
The 74HC/HCT/HCU high-speed Si-gate CMOS logic
family combines the low power advantages of the
HE4000B family with the high speed and drive capability of
the low power Schottky TTL (LSTTL).
The family will have the same pin-out as the 74 series and
provide the same circuit functions.
In these families are included several HE4000B family
circuits which do not have TTL counterparts, and some
special circuits.
The basic family of buffered devices, designated as
XX74HCXXXXX, will operate at CMOS input logic levels
for high noise immunity, negligible typical quiescent supply
and input current. It is operated from a power supply of
2to6V.
A subset of the family, designated as XX74HCTXXXXX,
with the same features and functions as the “HC-types”,
will operate at standard TTL power supply voltage
(5 V ±10%) and logic input levels (0.8 to 2.0 V) for use as
pin-to-pin compatible CMOS replacements to reduce
power consumption without loss of speed. These types are
also suitable for converted switching from TTL to CMOS.
Another subset, the XX74HCUXXXXX, consists of
single-stage unbuffered CMOS compatible devices for
application in RC or crystal controlled oscillators and other
types of feedback circuits which operate in the linear
mode.
HANDLING MOS DEVICES
Inputs and outputs are protected against electrostatic
effects in a wide variety of device-handling situations.
However, to be totally safe, it is desirable to take handling
precautions into account
(see also
“HANDLING PRECAUTIONS”
).
RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT
Note
1. For analog switches, e.g. “4016”, “4051 series”, “4351 series”, “4066” and “4067”, the specified maximum operating
supply voltage is 10 V.
SYMBOL PARAMETER 74HC 74HCT UNIT CONDITIONS
min. typ. max. min. typ. max.
VCC DC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIDC input voltage range 0 VCC 0V
CC V
VODC output voltage range 0 VCC 0V
CC V
Tamb operating ambient temperature range −40 +85 −40 +85 °C see DC and AC
CHAR. per device
Tamb operating ambient temperature range −40 +125 −40 +125 °C
tr,t
finput rise and fall times except for
Schmitt-trigger inputs 6.0 1000 6.0 500 ns VCC = 2.0 V
500 VCC = 4.5 V
400 VCC = 6.0 V
March 1988 3
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS FOR 74HCU
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
Note
1. For analog switches, e.g. “4016”, “4051 series”, “4351 series”, “4066” and “4067”, the specified maximum operating
supply voltage is 11 V.
SYMBOL PARAMETER 74HCU UNIT CONDITIONS
min. typ. max.
VCC DC supply voltage 2.0 5.0 6.0 V
VIDC input voltage range 0 VCC V
VODC output voltage range 0 VCC V
Tamb operating ambient temperature range −40 +85 °C see DC and AC
CHAR. per device
Tamb operating ambient temperature range −40 +125 °C
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
VCC DC supply voltage −0.5 +7V
±I
IK DC input diode current 20 mA for VI<−0.5 or VI> VCC +0.5 V
±IOK DC output diode current 20 mA for VO<−0.5 or VO> VCC +0.5 V
±IODC output source or sink
current for −0.5 V <VO<VCC +0.5 V
standard outputs 25 mA
bus driver outputs 35 mA
±ICC;
±IGND
DC VCC or GND current for
types with:
standard outputs 50 mA
bus driver outputs 70 mA
Tstg storage temperature range −65 +150 °C
Ptot power dissipation per package for temperature range: −40 to +125 °C
74HC/HCT/HCU
plastic DIL 750 mW above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K
March 1988 4
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
DC CHARACTERISTICS FOR 74HC
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) VIOTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
VIH HIGH level input
voltage 1.5 1.2 1.5 1.5 V 2.0
3.15 2.4 3.15 3.15 4.5
4.2 3.2 4.2 4.2 6.0
VIL LOW level input
voltage 0.8 0.5 0.5 0.5 V 2.0
2.1 1.35 1.35 1.35 4.5
2.8 1.8 1.8 1.8 6.0
VOH HIGH level output
voltage
all outputs
1.9 2.0 1.9 1.9 V 2.0 VIH
or
VIL
−IO= 20 µA
4.4 4.5 4.4 4.4 4.5 −IO= 20 µA
5.9 6.0 5.9 5.9 6.0 −IO= 20 µA
VOH HIGH level output
voltage
standard outputs
3.98 4.32 3.84 3.7 V 4.5 VIH
or
VIL
−IO= 4.0 mA
5.48 5.81 5.34 5.2 6.0 −IO= 5.2 mA
VOH HIGH level output
voltage
bus driver outputs
3.98 4.32 3.84 3.7 V 4.5 VIH
or
VIL
−IO= 6.0 mA
5.48 5.81 5.34 5.2 6.0 −IO= 7.8 mA
VOL LOW level output
voltage
all outputs
0 0.1 0.1 0.1 V 2.0 VIH
or
VIL
IO= 20 µA
0 0.1 0.1 0.1 4.5 IO= 20 µA
0 0.1 0.1 0.1 6.0 IO= 20 µA
VOL LOW level output
voltage
standard outputs
0.15 0.26 0.33 0.4 V 4.5 VIH
or
VIL
IO= 4.0 mA
0.16 0.26 0.33 0.4 6.0 IO= 5.2 mA
VOL LOW level output
voltage
bus driver outputs
0.15 0.26 0.33 0.4 V 4.5 VIH
or
VIL
IO= 6.0 mA
0.16 0.26 0.33 0.4 6.0 IO= 7.8 mA
±IIinput leakage current 0.1 1.0 1.0 µA 6.0 VCC
or
GND
±IOZ 3-state OFF-state
current 0.5 5.0 10.0 µA 6.0 VIH
or
VIL
VO=V
CC
or GND
ICC quiescent supply
current
SSI 2.0 20.0 40.0 µA 6.0 VCC
or
GND
IO= 0
flip-flops 4.0 40.0 80.0 6.0 IO= 0
MSI 8.0 80.0 160.0 6.0 IO= 0
LSI 50.0 500 1000 6.0 IO= 0
March 1988 5
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) VIOTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
VIH HIGH level input
voltage 2.0 1.6 2.0 2.0 V 4.5
to
5.5
VIL LOW level input
voltage 1.2 0.8 0.8 0.8 V 4.5
to
5.5
VOH HIGH level output
voltage
all outputs
4.4 4.5 4.4 4.4 V 4.5 VIH
or
VIL
−IO= 20 µA
VOH HIGH level output
voltage
standard outputs
3.98 4.32 3.84 3.7 V 4.5 VIH
or
VIL
−IO= 4.0 mA
VOH HIGH level output
voltage
bus driver outputs
3.98 4.32 3.84 3.7 V 4.5 VIH
or
VIL
−IO= 6.0 mA
VOL LOW level output
voltage
all outputs
0 0.1 0.1 0.1 V 4.5 VIH
or
VIL
IO= 20 µA
VOL LOW level output
voltage
standard outputs
0.15 0.26 0.33 0.4 V 4.5 VIH
or
VIL
IO= 4.0 mA
VOL LOW level output
voltage
bus driver outputs
0.16 0.26 0.33 0.4 V 4.5 VIH
or
VIL
IO= 6.0 mA
±IIinput leakage
current 0.1 1.0 1.0 µA 5.5 VCC
or
GND
±IOZ 3-state OFF-state
current 0.5 5.0 10.0 µA 5.5 VIH
or
VIL
VO=V
CC or
GND per input
pin;
other inputs at
VCC or GND;
IO= 0
ICC quiescent supply
current
SSI 2.0 20.0 40.0 µA 5.5 VCC
or
GND
IO= 0
flip-flops 4.0 40.0 80.0 5.5 IO= 0
MSI 8.0 80.0 160.0 5.5 IO= 0
LSI 50.0 500 1000 5.5 IO= 0
March 1988 6
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
Note
1. The additional quiescent supply current per input is determined by the ∆ICC unit load, which has to be multiplied by
the unit load coefficient as given in the individual data sheets. For dual supply systems the theoretical worst-case
(VI= 2.4 V; VCC = 5.5 V) specification is: ∆ICC = 0.65 mA (typical) and 1.8 mA (maximum) across temperature.
∆ICC additional quiescent
supply current per
input pin for unit load
coefficient is 1
(note 1)
100 360 450 490 µA 4.5
to
5.5
VCC
−2.1 V other inputs at
VCC or GND;
IO=0
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) VIOTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
March 1988 7
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
DC CHARACTERISTICS FOR 74HCU
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCU VCC
(V) VIOTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
VIH HIGH level input
voltage 1.7 1.4 1.7 1.7 V 2.0
3.6 2.6 3.6 3.6 4.5
4.8 3.4 4.8 4.8 6.0
VIL LOW level input
voltage 0.6 0.3 0.3 0.3 V 2.0
1.9 0.9 0.9 0.9 4.5
2.6 1.2 1.2 1.2 6.0
VOH HIGH level output
voltage 1.8 2.0 1.8 1.8 V 2.0 VIH
or
VIL
−IO= 20 µA
4.0 4.5 4.0 4.0 4.5 −IO= 20 µA
5.5 6.0 5.5 5.5 6.0 −IO= 20 µA
VOH HIGH level output
voltage 3.98 4.32 3.84 3.7 V 4.5 VCC
or
GND
−IO= 4.0 mA
5.48 5.81 5.34 5.2 6.0 −IO= 5.2 mA
VOL LOW level output
voltage 0 0.2 0.2 0.2 V 2.0 VIH
or
VIL
IO= 20 µA
0 0.5 0.5 0.5 4.5 IO= 20 µA
0 0.5 0.5 0.5 6.0 IO= 20 µA
VOL LOW level output
voltage 0.15 0.26 0.33 0.4 V 4.5 VCC
or
GND
IO= 4.0 mA
0.16 0.26 0.33 0.4 6.0 IO= 5.2 mA
±IIinput leakage current 0.1 1.0 1.0 µA 6.0 VCC
or
GND
ICC quiescent supply
current SSI 2.0 20.0 40.0 µA 6.0 VCC
or
GND
IO=0
March 1988 8
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
AC CHARACTERISTICS FOR 74HCU
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tTHL/ tTLH output transition time
standard outputs 19 75 95 110 ns 2.0 Figs 3 and 4
7 15 19 22 4.5
6 13 16 19 6.0
tTHL/ tTLH output transition time
bus driver outputs 14 60 75 90 ns 2.0 Figs 3 and 4
5 12 15 18 4.5
4 10 13 15 6.0
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCU VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tTHL/ tTLH output transition time 19 75 95 110 ns 2.0 Fig.1
7 15 19 22 4.5
6 13 16 19 6.0
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tTHL/ tTLH output transition time
standard outputs 7 15 19 22 ns 4.5 Figs 8 and 9
tTHL/ tTLH output transition time
bus driver outputs 5 12 15 18 ns 4.5 Figs 8 and 9
March 1988 9
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
HCU TYPES
AC waveforms 74HCU
Test circuit for 74HCU
Fig.1 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
handbook, halfpage
MGK564
10%
90%
90%
50%
50%
INPUT
OUTPUT
trtf
tPHL
tTHL
tPLH
tTLH
10%
GND
VCC
CL= load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
RT= termination resistance should be equal to the output impedance Zoof
the pulse generator.
Fig.2 Test circuit.
handbook, halfpage
MGK565
PULSE
GENERATOR D.U.T
VCC
VIVO
RTCL50 pF
March 1988 10
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
HC TYPES
AC waveforms 74HC
AC waveforms 74HC
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
handbook, halfpage
MGK564
10%
90%
90%
50%
50%
INPUT
OUTPUT
trtf
tPHL
tTHL
tPLH
tTLH
10%
GND
VCC
handbook, full pagewidth
MGK569
10 %
90%
50%
CLOCK
INPUT
VCC
GND
50%
DATA
INPUT
VCC
GND
10%
90%
50%
OUTPUT
tsu
tPHL
tPLH
tsu tTLH tTHL
50%
SET,
RESET,
PRESET
INPUT
VCC
GND
trtf
tWH thth
tWL
trem
1/fmax
Fig.4 Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
(2) For AC measurements: tr=t
f= 6 ns; when measuring fmax, there is no constraint on tr,t
fwith 50% duty factor.
March 1988 11
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
Test circuit for 74HC
AC waveforms 74HC (continued)
CL= load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
RT= termination resistance should be equal to the output impedance Zoof
the pulse generator.
Fig.5 Test circuit.
handbook, halfpage
MGK565
PULSE
GENERATOR D.U.T
VCC
VIVO
RTCL50 pF
Fig.6 Propagation delays of 3-state outputs.
handbook, full pagewidth
MGK562
tPLZ
tPHZ
outputs
disabled outputs
enabled
90%
10%
10%
90%
50%
outputs
enabled
OUTPUT
LOW-to-OFF
OFF-to-LOW
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
OUTPUT
ENABLE
VCC
GND
tPZL
tftr
tPZH
50%
50%
March 1988 12
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
Test circuit for 74HC
HCT TYPES
AC waveforms 74HCT
handbook, full pagewidth
MGK563
D.U.T
VCC VCC
VIVO
RT
RL = 1 kΩ
CL50 pF
PULSE
GENERATOR
Switch position
Note
1. For open-drain N-channel outputs tPLZ and tPZL are applicable.
TEST SWITCH
tPZH
tPZL
tPHZ
tPLZ
GND
VCC
GND
VCC
Fig.7 Test circuit for 3-state outputs.
CL= load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
RT= termination resistance should be equal to the output impedance Zoof
the pulse generator.
Fig.8 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
handbook, halfpage
MGK567
10%
90%
90%
1.3 V
1.3 V
INPUT
OUTPUT
trtf
tPHL
tTHL
tPLH
tTLH
10%
GND
3 V
March 1988 13
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
AC waveforms 74HCT
Test circuit for 74HCT
handbook, full pagewidth
MGK568
10%
90%
1.3 V
CLOCK
INPUT
3 V
GND
1.3 V
DATA
INPUT
3 V
GND
10%
90%
1.3 V
OUTPUT
tsu
tPHL
tPLH
tsu tTLH tTHL
1.3 V
SET,
RESET,
PRESET
INPUT
3 V
GND
trtf
tWH thth
tWL
trem
1/fmax
Fig.9 Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals
(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual
active levels of the forcing signals are specified in the individual device data sheet.
(2) For AC measurements: tr=t
f= 6 ns; when measuring fmax, there is no constraint on tr,t
fwith 50% duty factor.
handbook, halfpage
MGK565
PULSE
GENERATOR D.U.T
VCC
VIVO
RTCL50 pF
CL= load capacitance including jig and probe capacitance (see AC
CHARACTERISTICS for values).
RT= termination resistance should be equal to the output impedance Zoof
the pulse generator.
Fig.10 Test circuit.
March 1988 14
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
AC waveforms 74HCT (continued)
Test circuit for 74HCT
Fig.11 Propagation delays of 3-state outputs.
handbook, full pagewidth
MGK566
tPLZ
tPHZ
outputs
disabled outputs
enabled
90%
10%
10%
90% 1.3 V
outputs
enabled
OUTPUT
LOW-to-OFF
OFF-to-LOW
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
OUTPUT
ENABLE
tPZL
tftr
tPZH
1.3 V
1.3 V
Switch position
Note
1. For open-drain N-channel outputs tPLZ and tPZL are applicable.
TEST SWITCH
tPZH
tPZL
tPHZ
tPLZ
GND
VCC
GND
VCC
Fig.12 Test circuit for 3-state outputs.
CL= load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
RT= termination resistance should be equal to the output impedance Zoof
the pulse generator.
handbook, full pagewidth
MGK563
D.U.T
VCC VCC
VIVO
RT
RL = 1 kΩ
CL50 pF
PULSE
GENERATOR
March 1988 15
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
DATA SHEET SPECIFICATION GUIDE
INTRODUCTION
The 74HCMOS data sheets have been designed for
ease-of-use. A minimum of cross-referencing for more
information is needed.
TYPICAL PROPAGATION DELAY AND FREQUENCY
The typical propagation delays listed at the top of the data
sheets are the average of tPLH and tPHL for the longest data
path through the device with a 15 pF load.
For clocked devices, the maximum frequency of operation
is also given. The typical operating frequency is the
maximum device operating frequency with a 50% duty
factor and no constraints on tr and tf.
LOGIC SYMBOLS
Two logic symbols are given for each device - the
conventional one (Logic Symbol) which explicitly shows
the internal logic (except for complex logic) and the IEC
Logic Symbol as developed by the IEC (International
Electrotechnical Commission).
The IEC has been developing a very powerful symbolic
language that can show the relationship of each input of a
digital logic current to each output without explicitly
showing the internal logic.
Internationally, Working Group 2 of IEC Technical
Committee TC-3 has prepared a new document
(Publication 617-12) which supersedes
Publication 117-15, published in 1972.
RATINGS
The “RATINGS” table (Limiting values in accordance with
the Absolute Maximum System - IEC134) lists the
maximum limits to which the device can be subjected
without damage. This doesn’t imply that the device will
function at these extreme conditions, only that, when these
conditions are removed and the device operated within the
Recommended Operating Conditions, it will still be
functional and its useful life won’t have been shortened.
The maximum rated supply voltage of 7 V is well below the
typical breakdown voltage of 18 V.
RECOMMENDED OPERATING CONDITIONS
The “RECOMMENDED OPERATING CONDITIONS”
table lists the operating ambient temperature and the
conditions under which the limits in the “DC
CHARACTERISTICS” and “AC CHARACTERISTICS”
tables will be met. The table should not be seen as a set of
limits guaranteed by the manufacturer, but as the
conditions used to test the devices and guarantee that
they will then meet the limits in the DC and AC
CHARACTERISTICS tables.
DC CHARACTERISTICS
The “DC CHARACTERISTICS” table reflects the DC limits
used during testing. The values published are guaranteed.
The threshold values of VIH and VIL can be tested by the
user. If VIH and VIL are applied to the inputs, the output
voltages will be those published in the “DC
CHARACTERISTICS” table. There is a tendency, by
some, to use the published VIH and VIL thresholds to test a
device for functionality in a “function-table exercizer”
mode. This frequently causes problems because of the
noise present at the test head of automated test
equipment with cables up to 1 metre. Parametric tests,
such as those used for the output levels under the VIH and
VIL conditions are done fairly slowly, in the order of
milliseconds, so that there is no noise at the inputs when
the outputs are measured. But in functionality testing, the
outputs are measured much faster, so there can be noise
on the inputs, before the device has assumed its final and
correct output state. Thus, never use VIH and VIL to test the
functionality of any HCMOS device type; instead, use input
voltages of VCC (for the HIGH state) and 0 V (for the LOW
state). In no way does this imply that the devices are
noise-sensitive in the final system.
In the data sheets, it may appear strange that the typical
VIL is higher than the maximum VIL. However, this is
because VILmax is the maximum VIL (guaranteed) for all
devices that will be recognized as a logic LOW. However,
typically a higher VIL will also be recognized as a logic
LOW. Conversely, the typical VIH is lower than its minimum
guaranteed level.
For 74HCMOS, unlike TTL, no output HIGH short-circuit
current is specified. The use of this current, for example, to
calculate propagation delays with capacitive loads, is
covered by the HCMOS graphs showing the output drive
capability and those showing the dependence of
propagation delay on load capacitance.
The quiescent supply current ICC is the leakage current of
all the reversed-biased diodes and the OFF-state MOS
transistors. It is measured with the inputs at VCC or GND
and is typically a few nA.
March 1988 16
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HCMOS family characteristics FAMILY SPECIFICATIONS
AC CHARACTERISTICS
The “AC CHARACTERISTICS” table lists the guaranteed
limits when a device is tested under the conditions given in
the AC Test Circuits and Waveforms section.
TEST CIRCUITS
Good high-frequency wiring practices should be used in
test circuits. Capacitor leads should be as short as
possible to minimize ripples on the output waveform
transitions and undershoot. Generous ground metal
(preferably a ground-plane) should be used for the same
reasons. A VCC decoupling capacitor should be provided
at the test socket, also with short leads. Input signals
should have rise and fall times of 6 ns, a signal swing of
0 V to VCC for 74HC and 0 V to 3 V for 74HCT; a 1.0 MHz
square wave is recommended for most propagation delay
tests. The repetition rate must be increased for testing
fmax. Two pulse generators are usually required for testing
such parameters as set-up time, hold time and removal
time. fmax is also tested with 6 ns input rise and fall times,
with a 50% duty factor, but for typical fmax as high as
60 MHz, there are no constraints on rise and fall times.
March 1988 17
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
DEFINITIONS OF SYMBOLS AND TERMS USED IN
HCMOS DATA SHEETS
Currents
Positive current is defined as conventional current flow
into a device.
Negative current is defined as conventional current flow
out of a device.
Voltages
All voltages are referenced to GND (ground), which is
typically 0 V.
ICC Quiescent power supply current; the current
flowing into the VCC supply terminal.
∆ICC Additional quiescent supply current per input
pin at a specified input voltage and VCC.
IGND Quiescent power supply current; the current
flowing into the GND terminal.
IIInput leakage current; the current flowing into a
device at a specified input voltage and VCC.
IIK Input diode current; the current flowing into a
device at a specified input voltage.
IOOutput source or sink current: the current
flowing into a device at a specified output
voltage.
IOK Output diode current; the current flowing into a
device at a specified output voltage.
IOZ OFF-state output current; the leakage current
flowing into the output of a 3-state device in the
OFF-state, when the output is connected to
VCC or GND.
ISAnalog switch leakage current; the current
flowing into an analog switch at a specified
voltage across the switch and VCC.
GND Supply voltage; for a device with a single
negative power supply, the most negative
power supply, used as the reference level for
other voltages; typically ground.
VCC Supply voltage; the most positive potential on
the device.
VEE Supply voltage; one of two (GND and VEE)
negative power supplies.
VHHysteresis voltage; difference between the
trigger levels, when applying a positive and a
negative-going input signal.
VIH HIGH level input voltage; the range of input
voltages that represents a logic HIGH level in
the system.
Analog terms
Capacitances
VIL LOW level input voltage; the range of input
voltages that represents a logic LOW level in
the system.
VOH HIGH level output voltage; the range of
voltages at an output terminal with a specified
output loading and supply voltage. Device
inputs are conditioned to establish a HIGH level
at the output.
VOL LOW level output voltage; the range of voltages
at an output terminal with a specified output
loading and supply voltage. Device inputs are
conditioned to establish a LOW level at the
output.
VT+Trigger threshold voltage; positive-going signal.
VT−Trigger threshold voltage; negative-going
signal.
RON ON-resistance; the effective ON-state
resistance of an analog switch, at a specified
voltage across the switch and output load.
∆RON ∆ON-resistance; the difference in
ON-resistance between any two switches of an
analog device at a specified voltage across the
switch and output load.
CIInput capacitance; the capacitance measured
at a terminal connected to an input of a device.
CI/O Input/Output capacitance; the capacitance
measured at a terminal connected to an I/O-pin
(e.g. a transceiver).
CLOutput load capacitance; the capacitance
connected to an output terminal including jig
and probe capacitance.
CPD Power dissipation capacitance; the capacitance
used to determine the dynamic power
dissipation per logic function, when no extra
load is provided to the device.
CSSwitch capacitance; the capacitance of a
terminal to a switch of an analog device.
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Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
AC switching parameters
fiInput frequency; for combinatorial logic devices
the maximum number of inputs and outputs
switching in accordance with the device
function table. For sequential logic devices the
clock frequency using alternate HIGH and LOW
for data input or using the toggle mode,
whichever is applicable.
foOutput frequency; each output.
fmax Maximum clock frequency; clock input
waveforms should have a 50% duty factor and
be such as to cause the outputs to be switching
from 10%VCC to 90%VCC in accordance with
the device function table.
thHold time; the interval immediately following the
active transition of the timing pulse (usually the
clock pulse) or following the transition of the
control input to its latching level, during which
interval the data to be recognized must be
maintained at the input to ensure their
continued recognition. A negative hold time
indicates that the correct logic level may be
released prior to the timing pulse and still be
recognized.
tr,
tf
Clock input rise and fall times; 10% and 90%
values.
tPHL Propagation delay; the time between the
specified reference points, normally the 50%
points for 74HC and 74HCU devices on the
input and output waveforms and the 1.3 V
points for the 74HCT devices, with the output
changing from the defined HIGH level to the
defined LOW level.
tPLH Propagation delay; the time between the
specified reference points, normally the 50%
points for 74HC and 74HCU devices on the
input and output waveforms and the 1.3 V point
for the 74HCT devices, with the output
changing from the defined LOW level to the
defined HIGH level.
tPHZ 3-state output disable time; the time between
the specified reference points, normally the
50% points for the 74HC and 74HCU devices
and the 1.3 V points for the 74HCT devices on
the output enable input voltage waveform and a
point representing 10% of the output swing on
the output voltage waveform of a 3-state
device, with the output changing from
a HIGH level (VOH) to a high impedance
OFF-state (Z).
tPLZ 3-state output disable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and the 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and a point
representing 10% of the output swing on the
output voltage waveform of a 3-state
device, with the output changing from a LOW
level (VOL) to a high impedance OFF-state (Z).
tPZH 3-state output enable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and the 50%
point on the output voltage waveform of a
3-state device, with the output changing from a
high impedance OFF-state (Z) to a HIGH level
(VOH).
tPZL 3-state output enable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and the 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and the 50%
point on the output voltage waveform of a
3-state device, with the output changing from a
high impedance OFF-state (Z) to a LOW level
(VOL).
trem Removal time; the time between the end of an
overriding asynchronous input, typically a clear
or reset input, and the earliest permissible
beginning of a synchronous control input,
typically a clock input, normally measured at
the 50% points for 74HC devices and the 1.3 V
points for the 74HCT devices on both input
voltage waveforms.
tsu Set-up time; the interval immediately preceding
the active transition of the timing pulse (usually
the clock pulse) or preceding the transition of
the control input to its latching level, during
which interval the data to be recognized must
be maintained at the input to ensure their
recognition. A negative set-up time indicates
that the correct logic level may be initiated
sometime after the active transition of the
timing pulse and still be recognized.
March 1988 19
Philips Semiconductors
HCMOS family characteristics FAMILY SPECIFICATIONS
tTHL Output transition time; the time between two
specified reference points on a waveform,
normally 90% and 10% points, that is changing
from HIGH-to-LOW.
tTHL Output transition time; the time between two
specified reference points on a waveform,
normally 10% and 90% points, that is changing
from LOW-to-HIGH.
tWPulse width; the time between the 50%
amplitude points on the leading and trailing
edges of a pulse for 74HC and 74HCU devices
and at the 1.3 V points for 74HCT devices.
