256K x 4 Stat ic RAM
CY7C106B
CY7C1006B
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05037 Rev. ** Revised August 24, 2001
006B
Features
•High speed
—tAA = 12 ns
•CMOS for optimum speed/power
•Low acti ve pow er
—495 mW
•Low standby pow er
—275 mW
•2.0V data retention (optional)
—100 µW
•Automatic power-down when deselected
•TTL-compatible inputs and outputs
Functional Description
The CY7C106B and CY7C1006B are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and
three-state drivers. These devices have an automatic pow-
er-down feature that reduces power consumption by more
than 65% when the devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and W rite En able (W E) input s L OW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location speci-
fied on the address pins (A0 through A17).
Readi ng from the dev ices is accomp lishe d by takin g Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memo ry l ocatio n spec ified by the add ress pi ns will a ppear
on the four I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106B is available in a standard 400-mil-wide SOJ;
the CY7C1006B is available in a standard 300-mil-wide SOJ.
LogicBlockDiagram Pin Configuration
C106B–1
C106B–2
512 x 512 x 4
ARRAY
A1
A
0
A
10
A
12
A
11
A
13
A
14
COLUMN
DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
OE
INPUTBUFFER
A
15
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A1
A2
A3
A4
A5
A6
A7
A8
A17
VCC
A16
A15
A14
A13
I/O3
I/O2
I/O1
I/O0
A9
A0
A10
CE
OE
NC
A12
A11
WE
WE
CE
I/O0
I/O1
I/O2
I/O3
A2
A3
A4
A6
A7
A8
A9
A5
Selection Guide 7C106B-12
7C1006B-12 7C106B-15
7C1006B-15 7C106B-20
7C1006B-20 7C106B-25
7C1006B-25 7C106B-35
Maximum Access Time (ns) 12 15 20 25 35
Maximum Operating
Current (mA) 90 80 75 70 60
Maximum Sta ndby
Current (mA) 50 30 30 30 25
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 2 of 10
Maximum Ratings
(Above w hi ch the useful life may be impaired. For user g uid e-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z Sta te[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage ..........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –45°C to +85°C
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 3 of 10
Electrical Characteristics Ov er the Op erating Range
Parameter Description Test Conditions
7C106B-12
7C1006B-12 7C106B-15
7C1006B-15 7C106B-20
7C1006B-20
Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+0.3 2.2 VCC
+0.3 2.2 VCC
+0.3 V
VIL Input LOW Vo lta ge[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1+1–1+1–1+1µA
IOZ Output Leakage Current GND < VI < VCC,
Output Disabled –5+5–5+5–5+5µA
IOS Output Short
Circuit Current[3] VCC = Max., VOUT = GND –300 –300 –300 mA
ICC VCC O perating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
90 80 75 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
50 30 30 mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3 V, f=0
Com’l10 10 10mA
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 V CC +
0.3 2.2 VCC +
0.3 V
VIL Input LOW Vo lta ge[1] –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1+1–1+1µA
IOZ Output Leakage Current GND < VI < VCC,
Output Disabled –5+5–5+5µA
IOS Output Short
Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA
ICC VCC O perating
Supply Current VCC = Max. ,
IOUT = 0 mA,
f = fMAX = 1/tRC
70 60 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
30 25 mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
Com’l10 10mA
Notes:
1. VIL (min.) = –2. 0V for pulse durations of less than 20 ns.
2. TA is th e “instant on” case tem perature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 4 of 10
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN: A d d r e s s e s Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 7pF
CIN: Controls 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and W aveforms
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
C106B–3C106B–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AN D
SCOPE
(a) (b)
OUTPUT
R1 480ΩR1 480Ω
R2
255ΩR2
255Ω
167Ω
Equivale nt to: THÉ VENIN EQUIVALENT
1.73V
Rise Time < 1V/ns Fall Time < 1V/ns
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 5 of 10
Switching Characteristics O ver the O perati ng Ran ge[5]
7C106B-12
7C1006B-12 7C106B-15
7C1006B-15 7C106B-20
7C1006B-20 7C106B-25
7C1006B-25 7C106B-35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 12 15 20 25 35 ns
tAA Address to Data Valid 12 15 20 25 35 ns
tOHA Data Hold from Address Change 3 3 3 3 3 ns
tACE CE LOW to Data Valid 12 15 20 25 35 ns
tDOE OE LOW to Data Valid 6 7 8 10 10 ns
tLZOE OE LOW to Low Z 0 0 0 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 6781010ns
tLZCE CE LOW to Low Z[7] 33333ns
tHZCE CE HIGH to High Z[6, 7] 6781010ns
tPU CE LOW to Power-Up 0 0 0 0 0 ns
tPD CE HIGH to Power-Down 12 15 20 25 35 ns
WRITE CYCLE[8, 9]
tWC Write Cycle Time 12 15 20 25 35 ns
tSCE CE LOW to Write End 10 12 15 20 25 ns
tAW Address Set-Up to Write End 10 12 15 20 25 ns
tHA Address Hold from Write End 0 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 0 ns
tPWE WE Pulse Width 10 12 15 20 25 ns
tSD Data Set-Up to Write End 7 8 10 15 20 ns
tHD Data Hold from Write End 0 0 0 0 0 ns
tLZWE WE HIGH to Low Z[7] 23333ns
tHZWE WE LOW to High Z[6, 7 ] 6781010ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and output loading of the specified
IOL/IOH and 30–pF load capaci tance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. T ransit ion is measured ±500 mV fro m steady- state volt age.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less tha n tLZOE, and t HZWE is less than tLZWE for any given devic e.
8. The internal write time of the memory is defined by the overlap of CE an d WE LO W . CE and WE must be LOW to in itiate a write , and the tr ansitio n of either of thes e
signal s can terminate the wri te. The input data set -up and hold timing sh ould be referenc ed to the leading edge of the signal that te rminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE contr olle d, OE LOW) is the sum o f tHZWE and tSD.
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 6 of 10
Data Retention Characteristics Over the Operating Range
Parameter Description Conditions[10] Min. Max. Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0. 3V
250 µA
tCDR[4] Chip Deselect to Data Retention Time 0ns
tR[4] Operation Recovery Time 200 µs
Data Retention Waveform
4.5V4.5V
CE
VCC tCDR
VDR >2V
DATA RETENTION MODE
tR
C106B–5
Switching Waveforms
Read Cycle No.1[11, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Notes:
10. No input may exceed VCC +0.5V .
11. Device is continuously selected, OE and CE = VIL.
12. WE is HIGH for read c ycle.
13. Address v alid prior to or coincident with CE trans ition L OW .
1
PREVIO U S DATA VALI D DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
C106B–6
C106B–7
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE tHZCE
tPD
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 7 of 10
Write Cycle No. 1 (CE Controlled)[14, 15]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
Notes:
14. If CE goe s HIGH simultaneou sly wit h WE going HIGH, the o utput remains i n a h igh-imped ance stat e.
15. Data I/O is high impedance if OE = VIH.
Switching Waveforms (continued)
C106B–8
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA I/O
WE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE C106B–9
ADDRESS
CE
WE
DATA I/O
OE
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 8 of 10
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15]
Switching Waveforms (continued)
DATA VA LID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE C106B–10
ADDRESS
CE
WE
DATA I/O
Truth Table
CE OE WE Input/Output Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selecte d, Ou tpu t s Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12 CY7C106B-12VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1006B-12VC V21 28-Lead (300-Mil) Molded SOJ
15 CY7C106B-15VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1006B-15VC V21 28-Lead (300-Mil) Molded SOJ
CY7C106B-15VI V28 28-Lead (400-Mil) Molded SOJ Industrial
CY7C1006B-15VI V21 28-Lead (300-Mil) Molded SOJ
20 CY7C106B-20VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1006B-20VC V21 28-Lead (300-Mil) Molded SOJ
CY7C106B-20VI V28 28-Lead (400-Mil) Molded SOJ Industrial
CY7C1006B-20VI V21 28-Lead (300-Mil) Molded SOJ
25 CY7C106B-25VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1006B-25VC V21 28-Lead (300-Mil) Molded SOJ
CY7C106B-25VI V28 28-Lead (400-Mil) Molded SOJ Industrial
CY7C1006B-25VI V21 28-Lead (300-Mil) Molded SOJ
35 CY7C106B-35VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C106B-35VI V28 28-Lead (400-Mil) Molded SOJ Industrial
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Semicond uctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
28-Lead (400-Mil) Molded SOJ V28
51-85032-A
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. ** Page 10 of 10
Document Title: CY7C106B, CY7C1006B 256K x 4 Static RAM
Document Number: 38-05037
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 106831 09/17/01 SZV Change from Spec number: 38-00955 to 38-05037
