SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
High Degree of Linearity
D
High On-Off Output Voltage Ratio
D
Low Crosstalk Between Switches
D
Low On-State Impedance —
Typically, 50 Ω at VCC = 6 V
D
Individual Switch Controls
D
Extremely Low Input Current
D
Package Options Include Plastic
Small-Outline (D), Plastic Shrink
Small-Outline (DB), and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic (N) 300-mil DIPs
description
The SN74HC4066 is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital
signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction.
Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the
associated switch section.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
The SN74HC4066 is characterized for operation from –40
_
C to 85
_
C.
FUNCTION TABLE
(each switch)
INPUT
CONTROL
(C) SWITCH
L OFF
H ON
logic symbol†
X1
13
1C
1
1
1A 1B
2
1
5
2C 4
2A 2B
3
6
3C 8
3A 3B
9
12
4C 11
4A 4B
10
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2B
2A
2C
3C
GND
VCC
1C
4C
4A
4B
3B
3A
D, DB, PW, OR N PACKAGE
(TOP VIEW)
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram, each switch (positive logic)
A
VCC VCC
B
One of Four Switches
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control-input diode current, II (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port diode current, II (VI < 0 or VI/O < VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-state switch current (VI/O = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 2†5 6 V
VI/O I/O port voltage 0 VCC V
VCC = 2 V 1.5 VCC
VIH High-level input voltage, control inputs VCC = 4.5 V 3.15 VCC V
VCC = 6 V 4.2 VCC
VCC = 2 V 0 0.3
VIL Low-level input voltage, control inputs VCC = 4.5 V 0 0.9 V
VCC = 6 V 0 1.2
VCC = 2 V 1000
ttInput rise/fall time VCC = 4.5 V 500 ns
VCC = 6 V 400
TAOperating free-air temperature –40 85 °C
†With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25
_
C
MIN
MAX
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX
MIN
MAX
UNIT
I1AV0tV
2 V 150
Ron On-state switch resistance IT = –1 mA, VI = 0 to VCC,
VC=V
IH (see Figure 1)
4.5 V 50 85 106 Ω
VC
=
VIH
,
(see
Figure
1)
6 V 30
V V GND V V
2 V 320
Ron(p) Peak on resistance VI = VCC or GND, VC = VIH,
IT=
–
1mA
4.5 V 70 170 215 Ω
()
IT
=
–
1
mA
6 V 50
IIControl input current VC = 0 or VCC 6 V ±0.1 ±100 ±1000 nA
Isoff Off-state switch leakage current VI = VCC or 0, VO = VCC or 0,
VC = VIL, (see Figure 2) 6 V ±0.1 ±5µA
Ison On-state switch leakage current VI = VCC or 0, VC = VIH,
(see Figure 3) 6 V ±0.1 ±5µA
ICC Supply current VI = 0 or VCC, IO = 0 6 V 2 20 µA
Ci
In
p
ut ca
p
acitance
A or B
5V
9p
F
C
i
Inp
u
t
capacitance
C
5
V
3 10 10
pF
CfFeedthrough
capacitance A to B VI = 0 0.5 pF
CoOutput capacitance A or B 5 V 9 pF
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range
PARAMETER
FROM TO TEST
VCC
TA = 25
_
C
MIN
MAX
UNIT
PARAMETER
(INPUT) (OUTPUT) CONDITIONS
V
CC MIN TYP MAX
MIN
MAX
UNIT
t
Pti
2 V 10 60 75
tPLH,
tPHL
Propagation
delay time
A or B B or A CL = 50 pF,
4.5 V 4 12 15 ns
tPHL
delay
time
6 V 3 10 13
t
Sith
=
2 V 70 180 225
tPZH,
tPZL
Switch
turn
-
on time
CA or B
,
CL = 50 pF, 4.5 V 21 36 45 ns
tPZL
turn
-
on
time
(see Figure 5) 6 V 18 31 38
t
Sith
=
2 V 50 200 250
tPLZ,
tPHZ
Switch
turn
-
off time
CA or B
,
CL = 50 pF, 4.5 V 25 40 50 ns
tPHZ
turn
-
off
time
(see Figure 5) 6 V 22 34 43
Control
CL = 15 pF,
2 V 15
fI
Control
input
frequency
CA or B
L =
,
VC = VCC or GND,
4.5 V 30 MHz
f
requency
O =
CC
,
(see Figure 6) 6 V 30
Control
feedthrough
C
AorB
CL = 50 pF,
Rin = RL = 600 Ω,
4.5 V 15 mV
feedthrough
noise
C
A
or
B
C =
CC
,
fin = 1 MHz,
(see Figure 7) 6 V 20 (rms)
operating characteristics, VCC = 4.5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz 45 pF
Minimum through bandwidth, A to B or B to A† [20 log (VO/VI)] = –3 dB CL = 50 pF,
VC = VCC,RL = 600 Ω,
(see Figure 8) 30 MHz
Crosstalk between any switches‡CL = 10 pF,
fin = 1 MHz, RL = 50 Ω,
(see Figure 9) 45 dB
Feedthrough, switch off, A to B or B to A‡CL = 50 pF,
fin = 1 MHz, RL = 600 Ω,
(see Figure 10) 42 dB
Amplitude distortion rate, A to B or B to A CL = 50 pF,
fin = 1 kHz, RL = 10 kΩ,
(see Figure 11) 0.05%
†Adjust the input amplitude for output = 0 dBm at f = 10 kHz. Input signal must be a sine wave.
‡Adjust the input amplitude for output = 0 dBm at f = 1 MHz. Input signal must be a sine wave.
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VI = VCC
VC = VIH
1.0 mA –+
VO
RON
+
VI–O
10–3
W
VI–O
VCC
GND
(ON)
V
Figure 1. On-State Resistance Test Circuit
VCC
VC = VIL
AB
VS = VA – VB
CONDITION 1: VA = 0, VB = VCC
CONDITION 2: VA = VCC, VB = 0
VCC
GND
(OFF)
A
Figure 2. Off-State Switch Leakage Current Test Circuit
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VC = VIH
AB
Open
VCC
VA = VCC TO GND
VCC
GND
(ON)
A
Figure 3. On-State Leakage Current Test Circuit
VCC
VC = VIH
VIVO
50 pF
TEST CIRCUIT
tPLH tPHL
50% 50%
VCC
0 V
50% 50% VOH
VOL
VI
A or B
VO
B or A
VOLTAGE WAVEFORMS
50 Ω
tr
90%
10%
tf
10%
90%
VCC
GND
(ON)
Figure 4. Propagation Delay Time, Signal Input to Signal Output
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CL
50 pF
GND
VCC
VIVO
TEST CIRCUIT
tPLZ
50%
VOLTAGE WAVEFORMS
RL
1 kΩ
10%
S1
VC
50 Ω
S2
tPZH
tPHZ
50%
50%
50%
90%
tPZL
tPZH
tPLZ
tPHZ
GND
VCC
GND
VCC
TEST S1 S2
VCC
GND
VCC
GND
tPZL
50%
VCC
VO50%
0 V
VOL
VOH
VC
(tPZL, tPZH)
(tPLZ, tPHZ)
VCC
VCC
VO
0 V
VOL
VOH
VC
VCC
0 V
VOL
VOH
VCC
0 V
VOL
VOH
Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
GND
VO
RL
1 kΩCL
15 pF
VCC
VC
50 Ω
VI = VCC
VCC
VC0 V
VCC/2
Figure 6. Control Input Frequency
VCC
GND VO
RL
600 ΩCL
50 pF
VCC
VC
50 Ω
VI
VCC/2
Rin
600 Ω
VCC/2
trtf
90%
10%
(f = 1 MHz)
tr = tf = 6 ns
90%
10%
VCC
VC0 V
Figure 7. Control Feedthrough Noise
VO
VCC
50 Ω
fin
VCC/2
600 Ω
VCC/2
VC = VCC
0.1 µFVIVI
(VI = 0 dBm at f = 10 kHz)
VCC
GND
(ON)
RL
600 ΩCL
50 pF
Figure 8. Minimum Through Bandwidth
SN74HC4066
QUADRUPLE BILATERAL ANALOG SWITCH
SCLS325B – MARCH 1996 – REVISED MAY 1997
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VO1
RL
600 Ω CL
50 pF
VCC
50 Ω
fin
VCC/2
VC = VCC
0.1 µF
VI
VI
(VI = 0 dBm at f = 1 MHz)
VO2
VCC
Rin
600 Ω
VCC/2
VC = GND
Rin
600 Ω
VCC
GND
(ON)
VCC
GND
(OFF) RL
600 Ω CL
50 pF
Figure 9. Crosstalk Between Any Two Switches
VO
VCC
50 Ω
fin
VC = GND
0.1 µFVIVI
(VI = 0 dBm at f = 10 kHz)
VCC
GND
(ON)
Rin
600 Ω RL
600 Ω CL
50 pF
VCC/2 VCC/2
Figure 10. Feedthrough, Switch Off
VI
(VI = 0 dBm at f = 10 kHz)
VO
RL
10 kΩCL
50 pF
VCC
VCC/2
VC = VCC
10 µF
VI
fin VCC
GND
(ON)
Figure 11. Amplitude Distortion Rate
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Copyright 1998, Texas Instruments Incorporated