SSM6N7002BFU
2009-11-26
1
TOSHIBA Field-Effect Transistor Silicon N Channel MOS Type (U-MOSⅣ)
SSM6N7002BFU
High-Speed Switching Applications
Analog Switch Applications
• Small package
• Low ON-resistance : RDS(ON) = 3.3 Ω (max) (@VGS = 4.5 V)
: RDS(ON) = 2.6 Ω (max) (@VGS = 5 V)
: RDS(ON) = 2.1 Ω (max) (@VGS = 10 V)
Absolute Maximum Ratings (Ta = 25°C) (Q1, Q2 Common)
Characteristics Symbol Rating Unit
Drain-source voltage VDSS 60 V
Gate-source voltage VGSS ± 20 V
DC ID 200
Drain current
Pulse IDP 800
mA
Drain power dissipation (Ta = 25°C) PD (Note 1) 300 mW
Channel temperature Tch 150 °C
Storage temperature range Tstg −55 to 150 °C
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and
individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1:Total rating, mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.32mm2 × 6)
Marking Equivalent Circuit (top view)
Unit: mm
0.9±0.1
0 to 0.1
0.15±0.05
2.1±0.1
1.25±0.1
2.0±0.2
1.3±0.1
0.65
+0.1
0.2 -0.05
0.65
1
2
34
5
6
JEDEC ―
JEITA SC-88
TOSHIBA 2-2J1C
Weight: 6.8 mg (typ.)
0.4 mm
0.8 mm
US6
1.SOURCE1
2.GATE1
3.DRAIN2
4.SOURCE2
5.GATE2
6.DRAIN1
NM
6 5 4
1 2 3
Q1
Q2
654
123
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SSM6N7002BFU
2009-11-26
2
Electrical Characteristics (Ta = 25°C) (Q1, Q2 Common)
Characteristics Symbol Test Condition Min Typ Max Unit
Gate leakage current IGSS V
GS = ± 20 V, VDS = 0 V ⎯ ⎯ ±10 μA
V (BR) DSS ID =10 mA, VGS = 0 V 60 ⎯ ⎯
Drain-source breakdown voltage V (BR) DSX ID = 10 mA, VGS = -10 V 45 ⎯ ⎯ V
Drain cutoff current IDSS V
DS = 60 V, VGS = 0 V ⎯ ⎯ 1 μA
Gate threshold voltage Vth V
DS = 10 V, ID = 0.25 mA 1.5 ⎯ 3.1 V
Forward transfer admittance ⎪Yfs⎪ V
DS = 10 V, ID = 200 mA (Note 2) 225 ⎯ ⎯ mS
ID = 500 mA, VGS = 10 V (Note 2) ⎯ 1.62 2.1
ID = 100 mA, VGS = 5 V (Note 2) ⎯ 1.90 2.6
Drain-source ON-resistance RDS (ON)
ID = 100 mA, VGS = 4.5 V (Note 2) ⎯ 2.10 3.3
Ω
Input capacitance Ciss ⎯ 17.0 ⎯
Reverse transfer capacitance Crss ⎯ 1.9 ⎯
Output capacitance Coss
VDS = 25 V, VGS = 0 V, f = 1 MHz
⎯ 3.6 ⎯
pF
Turn-on delay time td(on) ⎯ 3.3 6.6
Switching time Turn-off delay time td(off)
VDD = 30 V , ID = 200 mA ,
VGS = 0 to 10 V ⎯ 14.5 40 ns
Drain-source forward voltage VDSF I
D = -200 mA, VGS = 0 V (Note 2) ⎯ -0.84 -1.2 V
Note2: Pulse test
Switching Time Test Circuit
Precaution
Let Vth be the voltage applied between gate and source that causes the drain current (ID) to be low (0.25 mA for the
SSM6N7002BFU). Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower
than Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on).
Take this into consideration when using the device
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
(c) VOUT
(b) VIN (a) Test circuit
td(on)
90 %
10 %
0 V
10 V
10 %
90 %
td(off)
tr tf
VDD
VDS
(
ON
)
VDD = 30 V
Duty ≤ 1%
VIN: tr, tf < 2 ns
(Zout = 50 Ω)
Common Source
Ta = 25 °C
10 V
0
10 μs VDD
OUT
IN
50 Ω
RL
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SSM6N7002BFU
2009-11-26
3
(Q1,Q2 Common)
Ambient temperature Ta (°C)
RDS (ON) – Ta
Drain–source ON-resistance
RDS (ON) (Ω)
0
−50 0 50 150 100
5
2
Common Source
ID = 500 mA / VGS = 10 V
100 mA / 4.5 V
100 mA / 5.0V
4
3
1
Ambient temperature Ta (°C)
Vth – Ta
Gate threshold voltage Vth (V)
3.0
0
−50 0 150
2.0
50 100
1.0
Common Source
VDS = 10 V
ID = 0.25 mA
Gate–source voltage VGS (V)
ID – VGS
Drain current ID (mA)
1000
0
10
100
0.1
1
0.01
5.0
4.0
-25 °C
2.0 3.0
1.0
Common Source
VDS = 10 V
25 °C
Ta = 100 °C
Drain–source voltage VDS (V)
ID – VDS
Drain current ID (mA)
0
400
0 0.4 0.8 1.2 2.0
200
1.6
600
800 10 V
Common Source
Ta = 25 °C
7.0 V
3.5 V
VGS = 3.3 V
4.5 V
1000
5.0 V
4.0 V
Drain–source ON-resistance
RDS (ON) (Ω)
0 10
Gate–source voltage VGS (V)
0
RDS (ON) – VGS
20
2
25 °C
5
Ta = 100 °C
-25 °C
ID = 100 mA
Common Source
Ta = 25°C
4
3
1
300
RDS (ON) – ID
Drain current ID (mA)
Drain–source ON-resistance
RDS (ON) (Ω)
10 30
0
100 1000
5
1
VGS = 10 V
5.0 V
4.5 V
4
3
2
Common Source
Ta = 25°C
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SSM6N7002BFU
2009-11-26
4
(Q1, Q2 Common)
Drain current ID (mA)
Forward transfer admittance
⎪
Yfs
⎪
(S)
|Yfs| – ID
0.001
1000
0.01
0.1
10 100
0.03
0.003
1
1
0.3
Common Source
VDS = 10 V
Ta = 25°C
Drain current ID (mA)
Switching time t (ns)
t – ID
1
1
100
1000
100 1000
td(off)
Common Source
VDD = 30 V
VGS = 0 to 10 V
Ta = 25 ° C
10
10
tf
tr
td(on)
Drain reverse current IDR (mA)
Drain–source voltage VDS (V)
IDR – VDS
1000
0
600
800
0
200
-0.2 -0.6 -0.4 -1.0 -0.8 -1.2
400
Common Source
VGS = 0 V
Ta = 25°C
G
D
S
IDR
Drain–source voltage VDS (V)
C – VDS
Capacitance C (pF)
1
0.1 1 10 100
100
30
50
10
5
3
Ciss
Crss
Coss
Common Source
Ta = 25°C
f = 1 MHz
VGS = 0 V
PD* – Ta
0
0
200
500
16040
100
300
400
80 120
Ambient temperature Ta (°C)
Drain power dissipation PD* (mW)
Mounted on FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.32 mm2 × 6)
*:Total Rating
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SSM6N7002BFU
2009-11-26
5
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product’s quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the “TOSHIBA Semiconductor Reliability Handbook” and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR
APPLICATIONS.
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