SLVS317 - MAY 2001 features applications D Fully Integrated VCC and Vpp Switching for D D D D D D D D D D D D D D D 3.3 V, 5 V, and 12 V (no 12 V on TPS2223) Meets Current PC Cardt Standards Vpp Output Selection Independent of VCC 12-V and 5-V Supplies Can Be Disabled TTL-Logic Compatible Inputs Short-Circuit and Thermal Protection 24-Pin HTSSOP, 24- or 30-Pin SSOP 140-A (Typical) Quiescent Current from 3.3-V Input Break-Before-Make Switching Power-On Reset -40C to 85C Operating Ambient Temperature Range Notebook and Desktop Computers Bar Code Scanners Digital Cameras Set-Top Boxes PDAs TPS2223, TPS2224 DB OR PWP PACKAGE (TOP VIEW) 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC GND RESET description 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 5V NC NC SHDN 12V BVPP BVCC BVCC NC OC 3.3V 3.3V The TPS2223, TPS2224 and TPS2226 CardNC - No internal connection Bus power-interface switches provide an Pin 7 and 20 are NC for TPS2223. integrated power-management solution for two PC Card sockets. These devices allow the controlled distribution of 3.3 V, 5 V, and 12 V to each card slot. The current-limiting and thermal-protection features eliminate the need for fuses. Current-limit reporting helps the user isolate a system fault. The switch rDS(on) and current-limit values have been set for the peak and average current requirements stated in the PC Card specification, and optimized for cost. Like the TPS2214 and TPS2214A and the TPS2216 and TPS2216A, this family of devices supports independent VPP/VCC switching; however, the standby and interface-mode pins are not supported. Shutdown mode is now supported independently on SHDN as well as in the serial interface. Optimized for lower power implementation, the TPS2223 does not support 12-V switching to VPP. See the available options table for pin-compatible device information. AVAILABLE OPTIONS PACKAGED DEVICES -40C to 85C PowerPAD PLASTIC SMALL OUTLINE (PWP-24) PLASTIC SMALL OUTLINE TA DB-24 DB-30 TPS2223DB, TPS2224DB TPS2226DB Pin compatibles TPS2214, TPS2214A Pin compatibles TPS2216, TPS2216A, TPS2206 TPS2223PWP, TPS2224PWP The DB and PWP packages are also available taped and reeled. Add R suffix to device type (e.g., TPS2223PWPR) for taped and reeled. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. CardBus and PC Card are trademarks of PCMCIA (Personal Computer Memory Card International Association). Copyright 2001, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLVS317 - MAY 2001 TPS2226 DB PACKAGE (TOP VIEW) 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC AVCC GND NC RESET 3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 5V NC NC NC NC SHDN 12V BVPP BVCC BVCC BVCC NC OC 3.3V 3.3V 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NC - No internal connection functional block diagram Power Inputs 5V 13 S2 14 S5 1 5V 2 5V 5 V 24 S3 3.3 V 3.3 V 12 V 9 CS 10 S1 S6 17 CS S8 7 S4 18 8 CS AVCC AVCC BVCC BVCC AVPP S9 S7 Power Inputs 12V S10 S12 12 V 20 S13 S11 S14 Control Logic 21 12 SHDN 3 4 DATA 5 15 19 CS Discharge Element Current Limit RESET Thermal Limit CLOCK LATCH 11 GND UVLO OC POR Diagram shown for 24-pin DB package. Current sense The two 12-V pins must be externally connected. No Connections for TPS2223 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 BVPP Power Outputs Power Inputs 3.3V SLVS317 - MAY 2001 Terminal Functions TERMINAL NO. NAME I/O DESCRIPTION TPS2223 TPS2224 TPS2226 3.3V 13, 14 13, 14 15, 16, 17 I 3.3-V input for card power and chip power 5V 1, 2, 24 1, 2, 24 1, 2, 30 I 5-V input for card power 12V NA 7, 20 7, 24 I 12-V input for card power (xVPP). The two 12-V pins must be externally connected. AVCC 9, 10 9, 10 9, 10, 11 O Switched output that delivers 3.3 V, 5 V, ground or high impedance to card AVPP 8 8 8 O Switched output that delivers 3.3 V, 5 V, 12 V, ground or high impedance to card (12 V not applicable to TPS2223) BVCC 17, 18 17, 18 20, 21, 22 O Switched output that delivers 3.3 V, 5 V, ground or high impedance to card BVPP 19 19 23 O Switched output that delivers 3.3 V, 5 V, 12 V, ground or high impedance to card (12 V not applicable for TPS2223) GND 11 11 12 OC 15 15 18 O Open-drain overcurrent reporting output that goes low when an overcurrent condition exists. An external pullup is required. SHDN 21 21 25 I Hi-Z (open) all switches. Identical function to serial D8. Asynchronous active-low command, internal pullup RESET 12 12 14 I Logic-level RESET input active low. Asynchronous active-low command, internal pullup CLOCK 4 4 4 I Logic-level clock for serial data word DATA 3 3 3 I Logic-level serial data word LATCH 5 5 5 I Logic-level latch for serial data word, internal pulldown 6, 7, 16, 20, 22, 23 6, 16, 22, 23 6, 13, 19, 26 -29 NC Ground No internal connection POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLVS317 - MAY 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Input voltage range for card power: VI(3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 5.5 V VI(5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 5.5 V VI(12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 14 V Logic input/output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Output voltage: VO(xVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V VO(xVPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 14 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Output current: IO(xVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited IO(xVPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 100C Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C OC sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Not applicable for TPS2223 DISSIPATION RATING TABLE PACKAGE DB PWP TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING 356 mW 24 890 mW 8.9 mW/C 489 mW 30 1095 mW 10.95 mW/C 602 mW 438 mW 24 3322 mW 33.22 mW/C 1827 mW 1329 mW These devices are mounted on an JEDEC low-k board (2-oz. traces on surface). recommended operating conditions Input voltage, VI(3.3V) is required for all circuit operations. 5V and 12V are only required for their respective functions. Output current, IO VI(3.3V) VI(5V) VI(12V) MIN MAX 3 3.6 3 5.5 7 13.5 IO(xVCC) at TJ = 100C IO(xVPP) at TJ = 100C 1 Clock frequency, f(clock) Pulse duration, tw Data 200 Latch 250 Clock 100 Reset 100 UNIT V A 100 mA 2.5 MHz ns Data-to-clock hold time (see Figure 2) 100 ns Data-to-clock setup time, tsu (see Figure 2) 100 ns Latch delay time, td(latch) (see Figure 2) 100 ns Clock delay time, td(clock) (see Figure 2) 250 Operating virtual junction temperature, TJ (maximum to be calculated at worst cast PD at 85C ambient) -40 ns 100 C Not applicable for TPS2223 It is understood that for VI(3.3V)< 3 V, voltages within the absolute maximum ratings applied to pin 5V or pin 12V will not damage the IC. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS317 - MAY 2001 electrical characteristics, TJ = 25C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for TPS2223), all outputs unloaded (unless otherwise noted) power switch TEST CONDITIONS PARAMETER rDS(on) Static drain-source on-state resistance Output discharge resistance IOS 3.3V to xVCC , with two switches on IO = 750 mA each IO = 750 mA each, 5V to xVCC , with two switches on IO = 500 mA each IO = 500 mA each, 3.3V or 5V to xVPP , with two switches on IO = 50 mA each IO = 50 mA each, 12V to xVPP , with two switches on IO = 50 mA each IO = 50 mA each, Discharge at xVCC IO(disc) = 1 mA Discharge at xVPP IO(disc) = 1 mA Thermal trip point, TJ II Ilkg Leakage current, output off state TJ = 100C MAX 85 110 110 140 95 130 120 160 0.8 1 1 1.3 2 2.5 2.5 3.4 0.5 0.7 1 0.2 0.4 0.5 TJ = 100C TJ = 100C Limit (steady-state value), output powered into a short circuit IOS(xVCC) 1 1.4 2 IOS(xVPP) 120 200 300 Limit (steady-state value), output powered into a short circuit, TJ = 100C IOS(xVCC) 1 1.4 2 IOS(xVPP) 120 200 300 Rising temperature UNIT m A mA A mA 135 C Hysteresis, TJ 10 Current-limit response time (see Note 1) Input current, quiescent TJ = 100C TYP k Short-circuit output current Thermal shutdown temperature (see Note 1) MIN Normal operation and reset mode Shutdown mode, VO(xVCC) = Hi-Z, VO(xVPP) = Hi-Z Shutdown mode VO(xVCC) with 100-m short, from short to OC signal falling edge 10 VO(xVPP) with 100-m short, from short to OC signal falling edge 3 ss II(3.3V) II(5V) 140 8 12 II(12V) II(3.3V) 100 180 0.3 2 II(5V) II(12V) 0.1 2 0.3 VO(xVCC) = 5 V, VI(5V) = VI(12V) = 0 VO(xVPP) = 12 V, VI(5V) = VI(12V) = 0 200 A A 2 10 TJ = 100C 50 10 A A TJ = 100C 50 Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. NOTE 1: Specified by design; not tested in production. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLVS317 - MAY 2001 electrical characteristics, TJ = 25C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for TPS2223), all outputs unloaded (unless otherwise noted) (continued) logic section (CLOCK, DATA, LATCH, RESET, SHDN, OC) PARAMETER TEST CONDITIONS RESET = 5.5 V II(/RESET) (see Note 2) RESET = 0 V SHDN = 5.5 V II Input current, logic II(/SHDN) (see Note 2) SHDN = 0 V MIN TYP MAX -20 -10 -1 -30 1 -1 1 -50 -3 LATCH = 5.5 V LATCH = 0 V -1 1 II(CLOCK, DATA) 0 V to 5.5 V -1 1 High-level input voltage, logic VO(sat) Ilkg Output saturation voltage at OC 2 V Low-level input voltage, logic 0.8 V 0.14 0.4 V 0 1 A MIN TYP MAX 2.4 2.7 2.9 70 100 2.3 2.5 70 100 mV 4 s IO = 2 mA VO(/OC) = 5.5 V Leakage current at OC A 50 II(LATCH) (see Note 2) VIH VIL UNIT NOTE 2: LATCH has low current pulldown. RESET and SHDN have low-current pullup. UVLO and POR (power-on reset) PARAMETER TEST CONDITIONS VI(3.3V) Input voltage at 3.3V pin, UVLO 3.3 V level below which all switches are Hi-Z Vhys(3.3V) UVLO hysteresis voltage at VA (see Note 1) VI(5V) Input voltage at 5V pin, UVLO Vhys(5V) UVLO hysteresis voltage at 5V (see Note 1) tdf Delay time for falling response, UVLO (see Note 1) Delay from voltage hit (step from 3 V to 2.3 V) to Hi-Z control (90% VG to GND) VI(POR) Input voltage, power-on reset (see Note 1) 3.3 V voltage below which POR is asserted causing a RESET internally with all line switches open and all discharge switches closed. 5 V level below which only 5V switches are Hi-Z NOTE 1: Specified by design; not tested in production. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT V mV 2.9 1.7 V V SLVS317 - MAY 2001 switching characteristics, VCC = 5 V, TA = 25C, VI(3.3V) = 3.3 V, VI(5V) = 5 V, VI(12) = 12 V (not applicable for TPS2223) all outputs unloaded (unless otherwise noted) PARAMETER tr tf Output rise times (see Note 1) Output fall times (see Note 1) CL(xVCC)= 0.1 F, CL(xVPP)= 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A CL(xVCC)= 150 F, CL(xVPP)= 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA CL(xVCC)= 0.1 F, CL(xVPP)= 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A CL(xVCC)= 150 F, CL(xVPP)= 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA CL(xVCC)= 0.1 F, CL(xVPP)= 0.1 F, IO(xVCC) = 0 A, IO(xVPP) = 0 A tpd TEST CONDITIONS LOAD CONDITION TYP VO(xVCC) = 5 V 0.9 VO(xVPP) = 12 V 0.26 VO(xVCC) = 5 V 1.1 VO(xVPP) = 12 V 0.6 VO(xVCC) = 5 V, Discharge switches ON 0.5 VO(xVPP) = 12 V, Discharge switches ON 0.2 MAX UNIT ms ms VO(xVCC) = 5 V 2.35 VO(xVPP) = 12 V 3.9 Latch to xVPP (12 V) tpdon tpdoff 0.77 Latch to xVPP (5 V) tpdon tpdoff tpdon tpdoff 0.75 Latch to xVPP (3.3 V) tpdon tpdoff 0.3 Latch to xVCC (5 V) 0.3 Latch to xVCC (3.3V) tpdon tpdoff Latch to xVPP (12 V) tpdon tpdoff 2.2 tpdon tpdoff 0.8 Latch to xVPP (5 V) 0.8 Latch to xVPP (3.3 V) tpdon tpdoff tpdon tpdoff 0.6 Latch to xVCC (5 V) tpdon tpdoff 0.5 Latch to xVCC (3.3V) Propagation delay (see Note 1) CL(xVCC)= 150 F, CL(xVPP)= 10 F, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA MIN 2 0.62 0.51 0.52 ms 2.5 2.8 0.8 0.6 0.6 ms 2.5 2.6 Refer to Parameter Measurement Information in Figure 1. No card inserted, assumes a 0.1-F output capacitor (see Figure 1). Not applicable for TPS2223 NOTE 1: Specified by design; not tested in production. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLVS317 - MAY 2001 PARAMETER MEASUREMENT INFORMATION xVPP xVCC IO(xVPP) IO(xVCC) LOAD CIRCUIT (xVPP) LATCH LOAD CIRCUIT (xVCC) VDD 50% LATCH VDD 50% GND tpd(on) GND tpd(off) VI(12V/5V/3.3V) 90% VO(xVPP) tpd(on) Propagation Delay (xVCC) tf tr VI(12V/5V/3.3V) VO(xVCC) 90% GND VI(5V/3.3V) 90% GND 10% Rise/Fall Time (xVCC) Rise/Fall Time (xVPP) VDD 50% GND 10% tf 10% LATCH 90% GND Propagation Delay (xVPP) VO(xVPP) VI(5V/3.3V) VO(xVCC) 10% tr tpd(off) VDD 50% LATCH GND GND ton VO(xVPP) toff toff ton VI(12V/5V/3.3V) 90% 10% VI(5V/3.3V) VO(xVCC) 90% GND 10% Turn On/Off Time (xVCC) Turn On/Off Time (xVPP) VOLTAGE WAVEFORMS Figure 1. Test Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 GND SLVS317 - MAY 2001 PARAMETER MEASUREMENT INFORMATION DATA D10 D9 D8 D6 D7 Data Setup Time D5 D4 D3 Data Hold Time D2 D1 D0 Latch Delay Time LATCH Clock Delay Time CLOCK NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D10, see the control logic table. Figure 2. Serial-Interface Timing for TPS2226 Table of Graphs FIGURE Short-circuit response, short applied to powered-on 5-V xVCC-switch output vs Time 3 Short-circuit response, short applied to powered-on 12-V xVPP-switch output vs Time 4 OC response with ramped overcurrent-limit load on 5-V xVCC-switch output vs Time 5 OC response with ramped overcurrent-limit load on 12-V xVPP-switch output vs Time 6 xVCC Turnon propagation delay time (CL = 150 F) vs Junction temperature 7 xVCC Turnoff propagation delay time (CL = 150 F) vs Junction temperature 8 xVPP Turnon propagation delay time (CL = 10 F) vs Junction temperature 9 xVPP Turnoff propagation delay time (CL = 10 F) vs Junction temperature 10 xVCC Turnon propagation delay time (TJ = 25C) vs Load capacitance 11 xVCC Turnoff propagation delay time (TJ = 25C) vs Load capacitance 12 xVPP Turnon propagation delay time (TJ = 25C) vs Load capacitance 13 xVPP Turnoff propagation delay time (TJ = 25C) vs Load capacitance 14 xVCC Rise time (CL = 150 F) vs Junction temperature 15 xVCC Fall time (CL = 150 F) vs Junction temperature 16 xVPP Rise time (CL = 10 F) vs Junction temperature 17 xVPP Fall time (CL = 10 F) vs Junction temperature 18 xVCC Rise time (TJ = 25C) vs Load capacitance 19 xVCC Fall time (TJ = 25C) vs Load capacitance 20 xVPP Rise time (TJ = 25C) vs Load capacitance 21 xVPP Fall time (TJ = 25C) vs Load capacitance 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLVS317 - MAY 2001 PARAMETER MEASUREMENT INFORMATION VO(/OC) 2 V/div VO(/OC) 2 V/div IO(VCC) 5 A/div IO(xVPP) 2 A/div 0 100 200 300 400 500 0 3 4 5 Figure 3. Short-Circuit Response, Short Applied to Powered-on 5-V xVCC-Switch Output Figure 4. Short-Circuit Response, Short Applied to Powered-on 12-V xVPP-Switch Output VO(/OC) 5 V/div IO(xVCC) 1 A/div IO(xVPP) 100 mA/div 10 20 30 40 50 0 2 4 6 8 t - Time - ms t - Time - ms Figure 5. OC Response With Ramped Overcurrent-Limit Load on 5-V xVCC-Switch Output 10 2 t - Time - ms VO(/OC) 5 V/div 0 1 t - Time - s POST OFFICE BOX 655303 Figure 6. OC Response With Ramped Overcurrent-Limit Load on 12-V xVPP-Switch Output * DALLAS, TEXAS 75265 10 SLVS317 - MAY 2001 PARAMETER MEASUREMENT INFORMATION TURNOFF PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE 0.8 xVCC = 5 V IO = 0.75 A CL = 150 F 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -20 10 40 70 TJ - Junction Temperature - C 100 t pd(off) - Turnoff Propagation Delay Time, xVCC - ms t pd(on)- Turnon Propagation Delay Time, xVCC - ms TURNON PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE 2.6 xVCC = 5 V IO = 0.75 A CL = 150 F 2.55 2.5 2.45 2.4 2.35 2.3 2.25 -50 Figure 7 xVPP = 12 V IO = 0.05 A CL = 10 F 2 1.5 1 0.5 -20 10 40 70 TJ - Junction Temperature - C 100 TURNOFF PROPAGATION DELAY TIME, xVPP vs JUNCTION TEMPERATURE t pd(off) - Turnoff Pro;agation Delay Time, xVPP - ms t pd(on)- Turnon Propagation Delay Time, xVPP - ms 3 0 -50 100 Figure 8 TURNON PROPAGATION DELAY TIME, xVPP vs JUNCTION TEMPERATURE 2.5 -20 10 40 70 TJ - Junction Temperature - C 0.9 0.8 0.7 0.6 0.5 0.4 0.3 xVCC = 12 V IO = 0.05 A CL = 10 F 0.2 0.1 0 -50 Figure 9 -20 10 40 70 TJ - Junction Temperature - C 100 Figure 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SLVS317 - MAY 2001 t pd(on)- Turnon Propagation Delay Time, xVCC - ms TURNON PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE 0.7 xVCC = 5 V IO = 0.75 A TJ = 25C 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 1 10 100 CL - Load Capacitance - F 1000 t pd(off) - Turnoff Propagation Delay Time, xVCC - ms PARAMETER MEASUREMENT INFORMATION TURNOFF PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE 2.55 2.5 xVCC = 5 V IO = 0.75 A TJ = 25C 2.45 2.4 2.35 2.3 2.25 0.1 1 10 100 CL - Load Capacitance - F Figure 11 Figure 12 2.25 xVPP = 12 V IO = 0.05 A TJ = 25C 2.15 2.1 2.05 2 1.95 0.1 1 CL - Load Capacitance - F 10 TURNOFF PROPAGATION DELAY TIME, xVPP vs LOAD CAPACITANCE t pd(off) - Turnoff Propagation Delay Time, xVPP - ms t pd(on) - Turnon Propagation Delay Time, xVPP - ms TURNON PROPAGATION DELAY TIME, xVPP vs LOAD CAPACITANCE 2.2 0.9 0.8 xVPP = 12 V IO = 0.05 A TJ = 25C 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 Figure 13 12 1000 1 CL - Load Capacitance - F Figure 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 10 SLVS317 - MAY 2001 PARAMETER MEASUREMENT INFORMATION FALL TIME, xVCC vs JUNCTION TEMPERATURE RISE TIME, xVCC vs JUNCTION TEMPERATURE 1.22 2.41 xVCC = 5 V IO = 0.75 A CL = 150 F 1.18 2.4 t f - Fall Time xVCC - ms t r - Rise Time, xVCC - ms 1.2 1.16 1.14 1.12 1.1 xVCC = 5 V IO = 0.75 A CL 150 F 2.39 2.38 2.37 2.36 1.08 2.35 1.06 1.04 -50 -20 10 40 70 TJ - Junction Temperature - C 2.34 -50 100 -20 10 40 70 TJ - Junction Temperature - C Figure 15 100 Figure 16 FALL TIME, xVPP vs JUNCTION TEMPERATURE RISE TIME, xVPP vs JUNCTION TEMPERATURE 4.15 0.605 xVPP = 12 V IO = 0.05 A CL 10 F t f - Fall Time, xVPP - ms t r- Rise Time xVPP - ms 0.6 4.1 0.595 0.59 0.585 4.05 4 3.95 3.9 0.58 0.575 -50 xVPP = 12 V IO = 0.05 A CL = 10 F -20 10 40 70 TJ - Junction Temperature - C 100 3.85 -50 Figure 17 -20 10 40 70 TJ - Junction Temperature - C 100 Figure 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SLVS317 - MAY 2001 PARAMETER MEASUREMENT INFORMATION FALL TIME, xVCC vs LOAD CAPACITANCE RISE TIME, xVCC vs LOAD CAPACITANCE 1.2 2.5 t f - Fall Time xVCC - ms t r - Rise Time, xVCC - ms 1 0.8 0.6 0.4 xVCC = 5 V IO = 0.75 A TJ = 25C 0.2 0 0.1 1 10 100 CL - Load Capacitance - F xVCC = 5 V IO = 0.75 A TJ = 25C 2 1.5 1 0.5 0 0.1 1000 1 10 100 CL - Load Capacitance - F Figure 19 Figure 20 FALL TIME, xVPP vs LOAD CAPACITANCE RISE TIME, xVPP vs LOAD CAPACITANCE 4.5 0.7 xVPP = 12 V IO = 0.05 A TJ = 25C 4 t f - Fall Time, xVPP - ms t r - Rise Time, xVPP - ms 0.6 0.5 0.4 0.3 0.2 xVPP = 12 V IO = 0.05 A TJ = 25C 3.5 3 2.5 2 1.5 1 0.1 0 0.1 0.5 1 CL - Load Capacitance - F 10 0 0.1 Figure 21 14 1000 1 CL - Load Capacitance - F Figure 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 10 SLVS317 - MAY 2001 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Input current, xVCC = 3.3 V 23 Input current, xVCC = 5 V II vs Junction temperature 25 Static drain-source on-state resistance, 3.3 V to xVCC switch 26 Static drain-source on-state resistance, 5 V to xVCC switch rDS(on) vs Junction temperature Static drain-source on-state resistance, 12 V to xVPP switch 29 xVCC switch voltage drop, 5-V input vs Load current 31 Short-circuit current limit, 3.3 V to xVCC 32 vs Junction temperature Short-circuit current limit, 12 V to xVCC 33 34 INPUT CURRENT, xVCC = 3.3 V vs JUNCTION TEMPERATURE INPUT CURRENT, xVCC = 5 V vs JUNCTION TEMPERATURE 14 180 I I - Input Current, xVCC = 5 V - A 160 I I - Input Current, xVCC = 3.3 V - A 30 xVPP switch voltage drop, 12-V input Short-circuit current limit, 5 V to xVCC IOS 27 28 xVCC switch voltage drop, 3.3-V input VO 24 Input current, xVPP = 12 V 140 120 100 80 60 40 12 10 8 6 4 2 20 0 -50 -20 10 40 70 TJ - Junction Temperature - C 100 0 -50 Figure 23 -20 10 40 70 TJ - Junction Temperature - C 100 Figure 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SLVS317 - MAY 2001 TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 3.3 V TO xVCC SWITCH vs JUNCTION TEMPERATURE rDS(on) - Static Drain-Source On-State Resistance, 3.3 V to VCC Switch - INPUT CURRENT, xVPP = 12 V vs JUNCTION TEMPERATURE I I - Input Current, xVPP = 12 V - A 120 100 80 60 40 20 0 -50 -20 10 40 70 TJ - Junction Temperature - C 100 0.12 0.1 0.08 0.06 0.04 0.02 0 -50 Figure 25 rDS(on) - Static Drain-Source On-State Resistance, 12 V to xVPP Switch - r - Static Drain-Source On-State Resistance, DS(on) 5 V to xVCC Switch - STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 12 V TO xVPP SWITCH vs JUNCTION TEMPERATURE 0.14 0.12 0.1 0.08 0.06 0.04 0.02 -20 10 40 70 TJ - Junction Temperature - C 100 3 2.5 2 1.5 1 0.5 0 -50 Figure 27 16 100 Figure 26 STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 5 V TO xVCC SWITCH vs JUNCTION TEMPERATURE 0 -50 -20 10 40 70 TJ - Junction Temperature - C -20 10 40 70 TJ - Junction Temperature - C Figure 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 100 SLVS317 - MAY 2001 TYPICAL CHARACTERISTICS xVCC SWITCH VOLTAGE DROP, 5-V INPUT vs LOAD CURRENT xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT vs LOAD CURRENT 0.14 0.1 VO- xVCC Switch Voltage Drop, 5-V Input - V VO- xVCC Switch Voltage Drop, 3.3-V Input - V 0.12 TJ = 100C 0.08 TJ = 0C TJ = 25C 0.06 TJ = -40C 0.04 TJ = 85C 0.02 0 0 0.2 0.4 0.6 IL - Load Current - A 0.8 0.12 TJ = 0C 0.08 TJ = 25C 0.06 TJ = -40C 0.04 TJ = 85C 0.02 0 1 TJ = 100C 0.1 0 Figure 29 0.12 TJ = 100C TJ = 0C TJ = 25C 0.06 0.04 TJ = -40C 0.02 0 TJ = 85C 0 0.01 0.8 1 0.02 0.03 0.04 IL - Load Current - A 0.05 SHORT-CIRCUIT CURRENT LIMIT, 3.3 V TO xVCC vs JUNCTION TEMPERATURE I OS - Short-Circuit Current Limit, 3.3 V to xVCC - A VO - xVPP Switch Voltage Drop, 12-V Input - V 0.14 0.08 0.4 0.6 IL - Load Current - A Figure 30 xVPP SWITCH VOLTAGE DROP, 12-V INPUT vs LOAD CURRENT 0.1 0.2 1.395 1.39 1.385 1.38 1.375 1.37 1.365 1.36 1.355 -50 Figure 31 -20 10 40 70 TJ - Junction Temperature - C 100 Figure 32 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SLVS317 - MAY 2001 TYPICAL CHARACTERISTICS 1.435 1.43 1.425 1.42 1.415 1.41 1.405 1.4 1.395 1.39 1.385 -50 SHORT-CIRCUIT CURRENT LIMIT, 12 V TO xVPP vs JUNCTION TEMPERATURE I OS - Short-Circuit Current Limit, 12 V to xVPP - A I OS - Short-Circuit Current Limit, 5 V to xVCC - A SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC vs JUNCTION TEMPERATURE -20 10 40 70 TJ - Junction Temperature - C 100 0.208 0.206 0.204 0.202 xVPP = 12 V 0.2 0.198 0.196 0.194 0.192 0.19 -50 10 Figure 34 POST OFFICE BOX 655303 40 70 TJ - Junction Temperature - C Figure 33 18 -20 * DALLAS, TEXAS 75265 100 SLVS317 - MAY 2001 APPLICATION INFORMATION overview PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in cards quickly took hold, and modems, wireless LANs, global positioning satellite System (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International Association) was established, comprising members from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug-and-play concept, so that cards and hosts from different vendors would be transparently compatible. PC Card power specification System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two Vpp terminals were originally specified as separate signals, but are normally tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the Vpp terminals. Cardbus cards of today typically do not use 12 V, which is now more of an optional requirement in the host. designing for voltage regulation The current PCMCIA specification for output voltage regulation, VO(reg), of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output-voltage regulation, VPS(reg), of 2% (100 mV). Also, a voltage drop from the power supply to the PC Card will result from resistive losses, VPCB, in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, VDS, for the TPS2223, TPS2224 and TPS2226 would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops: V DS +V O(reg) -V PS(reg) -V PCB Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for output voltage regulation of the 3.3-V output is 300 mV; therefore, using the same equation by deducting the voltage drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage drop for the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of the TPS2223, TPS2224, and TPS2226. Therefore, the maximum output current, IO max, that can be delivered to the PC Card in regulation is the allowable voltage drop across the IC, divided by the output-switch resistance. V I max + r DS O DS(on) The xVCC outputs have been designed to deliver the peak and average currents defined by the PC Card specification within regulation over the operating temperature range. The xVPP outputs of the TPS2226 have been designed to deliver 100 mA continuously. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SLVS317 - MAY 2001 APPLICATION INFORMATION overcurrent and overtemperature protection PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that could lead to power-supply or PCB trace damage. Even extremely robust systems could undergo rapid battery discharge into a damaged PC Card, resulting in the rather sudden and unacceptable loss of system power. The reliability of fused systems is poor, in comparison, as blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2223, TPS2224 and TPS2226 take a two-pronged approach to overcurrent protection, which is designed to activate if an output is shorted or when an overcurrent condition is present when switches are powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. Excessive current generates an error signal that limits the output current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from 1 A to 2.2 A, typically around 1.6 A; the xVPP outputs limit from 100 mA to 250 mA, typically around 200 mA. Second, when an overcurrent condition is detected, the TPS2223, TPS2224 and TPS2226 assert an active low OC signal that can be monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message. In the event that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis. Thermal limiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings. During power up, the devices control the rise times of the xVCC and xVPP outputs and limit the inrush current into a large load capacitance, faulty card, or connector. 12-V supply not required A few PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which requires that power be present at all times. The TPS2224 and TPS2226 offer considerable power savings by using an internal charge pump to generate the required higher gate drive voltages from the VA input (3.3 V). Therefore, the external 12-V supply can be disabled except when needed by the PC Card in the slot, thereby extending battery lifetime. A special feature in the 12-V circuitry actually helps to reduce the supply current demanded from the 3.3 V input. When 12 V is supplied and requested at the VPP output, a voltage selection circuit will draw the charge-pump drive current for the 12-V FETs from the 12-V input. This selection is automatic and effectively reduces demand fluctuations on the normal 3.3-V VCC rail. For proper operation of this feature, a minimum 3.3-V input capacitance of 4.7 F is recommended, and a minimum 12-V input ramp-up rate of 12 V/50 ms (240 V/s) is required. Additional power savings are realized by the TPS2226 during a software shutdown in which quiescent current drops to a maximum of 1 A. voltage-transitioning requirement PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2223, TPS2224 and TPS2226 meet all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance cannot be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. The devices include discharge transistors on all xVCC and xVPP outputs to meet the specification requirement. 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS317 - MAY 2001 APPLICATION INFORMATION shutdown mode In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the xVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1 A or less to conserve battery power. power-supply considerations These switches have multiple pins for each 3.3-V and 5-V power input and for the switched xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended that all input and output power pins be paralleled for optimum operation. To increase the noise immunity of the TPS2223, TPS2224 and TPS2226, the power-supply inputs should be bypassed with at least a 4.7 F electrolytic or tantalum capacitor paralleled by a 0.047-F to 0.1-F ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-F (or larger) ceramic capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the devices and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below -0.3 V. RESET input To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active low RESET input will close internal switches S1, S4, S7, and S11 with all other switches left open. The TPS2223, TPS2224 and TPS2226 remain in the low-impedance output state until the signal is deasserted and further data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET is provided for direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an internal 150-k pullup resistor. calculating junction temperature The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures 26 through 28, using an initial temperature estimate about 30C above ambient. Then calculate the power dissipation for each switch, using the formula: P D +r DS(on) I2 Next, sum the power dissipation of all switches and calculate the junction temperature: P R )T T + D qJA A J Where: RJA is the inverse of the derating factor given in the dissipation rating table. Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SLVS317 - MAY 2001 APPLICATION INFORMATION logic inputs and outputs The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the clock (see Figure 2). The 11-bit (D0-D10) serial data word is loaded during the positive edge of the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs. The serial interface of the device is compatible with serial-interface PCMCIA controllers. An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the xVCC and xVPP outputs as previously discussed. TPS2223, TPS2224 and TPS2226 control logic xVPP AVPP CONTROL SIGNALS BVPP CONTROL SIGNALS OUTPUT V_AVPP D8 (SHDN) D4 D5 D10 OUTPUT V_BVPP D8 (SHDN) D0 D1 D9 1 0 0 X 0V 1 0 0 X 0V 1 0 1 0 3.3 V 1 0 1 0 3.3 V 1 0 1 1 5V 1 0 1 1 5V 1 1 0 X 12 V 1 1 0 X 12 V 1 1 1 X Hi-Z 1 1 1 X Hi-Z 0 X X X Hi-Z 0 X X X Hi-Z The output V_xVPP is Hi-Z for TPS2223. xVCC AVCC CONTROL SIGNALS 22 BVCC CONTROL SIGNALS OUTPUT V_AVCC D8 (SHDN) D6 D7 0 0V 1 0 0 0V 1 3.3 V 1 0 1 3.3 V 1 0 5V 1 1 0 5V 1 1 0V 1 1 1 0V X X Hi-Z 0 X X Hi-Z D8 (SHDN) D3 D2 1 0 1 0 1 1 0 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 OUTPUT V_BVCC SLVS317 - MAY 2001 APPLICATION INFORMATION ESD protections (see Figure 35) All inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.1-F capacitors protects the devices from discharges up to 10 kV. TPS2226 AVCC AVCC 0.1 F VCC VCC PC Card Connector A AVPP 12 V 12 V 4.7 F 0.1 F 5V 4.7 F 0.1 F 12 V BVCC BVCC 4.7 F 0.1 F 0.1 F 5V Vpp1 Vpp2 VCC VCC PC Card Connector B 5V BVPP 0.1 F 5V 3.3 V 0.1 F Vpp1 Vpp2 3.3 V 3.3 V 3.3 V Controller DATA DATA CLOCK CLOCK LATCH LATCH RESET OC From PCI or System RST GPI/O Maximum recommended output capacitance for xVCC is 220 F including card capacitance, and for xVPP is 10 F, without OC glitch when switches are powered on. Figure 35. Detailed Interconnections and Capacitor Recommendations POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 SLVS317 - MAY 2001 APPLICATION INFORMATION 12-V flash memory supply The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 36, the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB space when implemented with surface-mount components. An enable input is provided to shut the converter down and reduce the supply current to 3 A when 12 V is not needed. The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize the 0.7- MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one small capacitor. A 1.22-V reference, pin 2 of TPS6734, is brought out for external use. For additional information, see the TPS6734 data sheet (SLVS127). TPS2226 or TPS2224 AVCC 3.3 V or 5 V Enable (see Note A) R1 10 k 1 2 C1 33 F 20 V + 3 4 C2 0.01 F AVCC TPS6734 EN VCC REF FB SS OUT COMP GND 8 L1 18 H AVCC 7 AVPP D1 6 5 33 F, 20 V + C1 12 V 0.1 F 12 V 12 V BVCC BVCC C4 0.001 F 5V 1 F 0.1 F 5V 5V BVCC BVPP 5V 3.3 V 4.7 F 0.1 F 3.3 V 3.3 V 3.3 V DATA CLOCK LATCH SHDN RESET OC Not on TPS2224 NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high. Figure 36. TPS2224 and TPS2226 with TPS6734 12-V, 120-mA Supply 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2223DB ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2223DBG4 ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2223DBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2223DBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2223PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2223PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2223PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2223PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2224DB ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2224DBG4 ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2224DBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2224DBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2224PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2224PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2224PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2224PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2226DB ACTIVE SSOP DB 30 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2226DBG4 ACTIVE SSOP DB 30 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2226DBR ACTIVE SSOP DB 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2226DBRG4 ACTIVE SSOP DB 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2007 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 16.0 Q1 TPS2223DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 TPS2223PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TPS2224DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 TPS2224PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TPS2226DBR SSOP DB 30 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2223DBR SSOP DB 24 2000 367.0 367.0 38.0 TPS2223PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS2224DBR SSOP DB 24 2000 367.0 367.0 38.0 TPS2224PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS2226DBR SSOP DB 30 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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