CY74FCT162646ATPAC - Texas Instruments

16-Bit Registered Transceivers

CY74FCT16646T

CY74FCT162646T

SCCS060 - August 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

Features

• FCT-E speed at 3.8 ns

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

• Typical output skew < 250 ps

• ESD > 2000V

• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)

packages

• Industrial temperature range of −40˚C to +85˚C

•V

CC = 5V ± 10%

CY74FCT16646T Features:

• 64 mA sink current, 32 mA source current

• Typical VOLP (ground bounce) <1.0V at VCC = 5V,

TA = 25˚C

CY74FCT162646T Features:

• Balanced 24 mA output drivers

• Reduced system switching noise

• Typical VOLP (ground bounce) <0.6V at VCC = 5V,

TA= 25˚C

Functional Description

The CY74FCT16646T and CY74FCT162646T 16-bit

transceivers are three-state, D-type registers, and control

circuitry arranged for multiplexed transmission of data directly

from the input bus or from the internal registers. Data on the A

or B bus will be clocked into the registers as the appropriate

clock pin goes to a HIGH logic level. Output Enable (OE) and

direction pins (DIR) are provided to control the transceiver

function. In the transceiver mode, data present at the high

impedance port may be stored in either the A or B register, or

in both. The select controls can multiplex stored and real-time

(transparent mode) data. The direction control determines

which bus will receive data when the Output Enable (OE) is

ActiveLOW.In theisolation mode(OutputEnable(OE) HIGH),

A data may be stored in the B register and/or B data may be

stored in the A register. The output buffers are designed with

a power-off disable feature that allows live insertion of boards.

The CY74FCT16646T is ideally suited for driving

high-capacitance loads and low-impedance backplanes.

The CY74FCT162646T has 24-mA balanced output drivers

with current limiting resistors in the outputs. This reduces the

need for external terminating resistors and provides for

minimal undershoot and reduced ground bounce. The

CY74FCT162646T is ideal for driving transmission lines.

Logic Block Diagrams

FCT16646-1

1B1

1A1

TO7 OTHER CHANNELS

1SAB

1CLKAB

1CLKBA

1DIR

1SBA

1OE

B REG

A REG

2B1

2A1

2SAB

2CLKAB

2CLKBA

2DIR

2SBA

2OE

B REG

FCT16646-2

TO 7 OTHER CHANNELS

A REG

CY74FCT16646T

CY74FCT162646T

GND

1DIR

SSOP/TSSOP

Top View

1CLKAB

1SAB

1A1

1A2

1CLKBA

1SBA

1B1

1OE

GND

VCC

1A3VCC

GND

1A4

1A5

1A6

1A7

1A8

2A1

2A2

2A3

2A4

GND

2A5

2A6

VCC

2A7

2A8

2SAB

2CLKAB

GND

2DIR

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

VCC

2B7

2B8

GND

2SBA

2CLKBA

2OE

FCT16646-3

Pin Configuration

Pin Description

Pin Names Description

A Data Register A Inputs

Data Register B Outputs

B Data Register B Inputs

Data Register A Outputs

CLKAB, CLKBA Clock Pulse Inputs

SAB, SBA Output Data Source Select Inputs

DIR Direction

OE Output Enable (Active LOW)

CY74FCT16646T

CY74FCT162646T

Function Table[1]

Inputs Data I/O[2] Function

OE DIR CLKAB CLKBA SAB SBA A B

XH or L H or L X

XInput Input Isolation

Store A and B Data

H or L X

HOutput Input Real Time B Data to A Bus

Stored B Data to A Bus

H or L X

XInput Output Real Time A Data to Bus

Stored A Data to B Bus

Notes:

1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition

2. The data output functions may be enabled or disabled by various signals at the OE or DIR inputs. Data input functions are always enabled, i.e., data at the

bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

3. Cannot transfer data to A-bus and B-bus simultaneously.

BUS BBUS A

DIR

LOE

LCLKAB

XSAB

BUS BBUS A

DIR

CLKAB

SAB

SBA

BUS BBUS A

DIR

HOE

LSAB

LSBA

BUS ABUS A

DIR

SAB

SBA

Real-Time Transfer

BusB to BusA Real-Time Transfer

BusA to BusB

Storagefrom

A and/orB TransferStoredData

to A and/orB

CLKBA

XCLKAB

XCLKBA

SBA

CLKBA

XCLKAB

HorL

CLKBA

HorL

[3]

CY74FCT16646T

CY74FCT162646T

Maximum Ratings[4]

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .....................Com’l −55°C to +125°C

Ambient Temperature with

Power Applied.................................Com’l −55°C to +125°C

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage ..............................................−0.5V to +7.0V

DC Output Current

(Maximum Sink Current/Pin)...........................−60 to +120 mA

Power Dissipation..........................................................1.0W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Operating Range

Range Ambient

Temperature VCC

Industrial −40°C to +85°C 5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

VHInput Hysteresis[6] 100 mV

VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V

IIH Input HIGH Current VCC=Max., VI=VCC ±1µA

IIL Input LOW Current VCC=Max., VI=GND ±1µA

IOZH High Impedance Output Current

(Three-State Output pins) VCC=Max., VOUT=2.7V ±1µA

IOZL High Impedance Output Current

(Three-State Output pins) VCC=Max., VOUT=0.5V ±1µA

IOS Short Circuit Current[7] VCC=Max., VOUT=GND −80 −140 −200 mA

IOOutput Drive Current[7] VCC=Max., VOUT=2.5V −50 −180 mA

IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[9] ±1µA

Output Drive Characteristics for CY74FCT16646T

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VOH Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V

VCC=Min., IOH=−15 mA 2.4 3.5 V

VCC=Min., IOH=−32 mA 2.0 3.0 V

VOL Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V

Output Drive Characteristics for CY74FCT162646T

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

IODL Output LOW Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA

IODH Output HIGH Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA

VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V

VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V

Notes:

4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

5. Typical values are at VCC= 5.0V, TA= +25˚C ambient.

6. This parameter is speciﬁed but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter

tests, IOS tests should be performed last.

8. This parameter is measured at characterization but not tested.

9. Tested at +25˚C.

CY74FCT16646T

CY74FCT162646T

Capacitance (TA = +25˚C, f = 1.0 MHz)

Symbol Description[8] Conditions Typ. Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6.0 pF

COUT Output Capacitance VOUT =0V 5.5 8.0 pF

Power Supply Characteristics

Parameter Description Test Conditions[10] Min. Typ.[5] Max. Unit

ICC Quiescent Power Supply Current VCC=Max. VIN<0.2V

VIN>VCC−0.2V — 5 500 µA

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH VCC = Max.

VIN=3.4V[11] — 0.5 1.5 mA

ICCD Dynamic Power Supply

Current[12] VCC=Max.

Outputs Open

DIR=OE=GND

One-Bit Toggling

50% Duty Cycle

VIN=VCC or

VIN=GND — 75 120 µA/MHz

ICTotal Power Supply Current[13] VCC=Max.

Outputs Open

fo=10 MHz(CLKBA)

50% Duty Cycle

DIR=OE=GND

One-Bit Toggling

f1=5 MHz

50% Duty Cycle

VIN=VCC or

VIN=GND — 0.8 1.7 mA

VIN=3.4V or

VIN=GND — 1.3 3.2

VCC=Max.

Outputs Open

fo=10 MHz (CLKBA)

50% Duty Cycle

DIR=OE=GND

Sixteen-Bits Toggling

f1=2.5 MHz

50% Duty Cycle

VIN=VCC or

VIN=GND — 3.8 6.5[14]

VIN=3.4V or

VIN=GND — 8.3 20.0[14]

Notes:

10. For conditions shown as Max. or Min., use appropriate value speciﬁed under Electrical Characteristics for the applicable device type.

11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.

12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

13. IC=I

QUIESCENT + IINPUTS + IDYNAMIC

IC=I

CC+∆ICCDHNT+ICCD(f0/2 + f1N1)

ICC = Quiescent Current with CMOS input levels

∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)

DH= Duty Cycle for TTL inputs HIGH

NT= Number of TTL inputs at DH

ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)

f0= Clock frequency for registered devices, otherwise zero

f1= Input signal frequency

N1= Number of inputs changing at f1

All currents are in milliamps and all frequencies are in megahertz.

14. Values for these conditions are examples of the ICC formula. These limits are speciﬁed but not tested.

CY74FCT16646T

CY74FCT162646T

Switching Characteristics Over the Operating Range[15]

Parameter Description

CY74FCT16646T CY74FCT16646AT

CY74FCT162646AT

UnitMin. Max. Min. Max. Fig. No.[16]

tPLH

tPHL Propagation Delay

Bus to Bus 1.5 9.0 1.5 6.3 ns 1, 2

tPZH

tPZL Output Enable Time

DIR or OE to Bus 1.5 14.0 1.5 9.8 ns 1, 7, 8

tPHZ

tPLZ Output Disable Time

DIR or OE to Bus 1.5 9.0 1.5 6.3 ns 1, 7, 8

tPLH

tPHL Propagation Delay

Clock to Bus 1.5 9.0 1.5 6.3 ns 1, 5

tPLH

tPHL Propagation Delay

SBA or SAB to Bus 1.5 11.0 1.5 7.7 ns 1,5

tSU Set-Up Time HIGH or

LOW Bus to Clock 2.0 — 2.0 — ns 4

tHHold Time HIGH or

LOW Bus to Clock 1.5 — 1.5 — ns 4

tWClock Pulse Width

HIGH or LOW 5.0 — 5.0 — ns 6

tSK(O) Output Skew[17] — 0.5 — 0.5 ns —

Parameter Description

CY74FCT16646CT

CY74FCT162646CT CY74FCT16646ET

CY74FCT162646ET

UnitMin. Max. Min. Max. Fig. No.[16]

tPLH

tPHL Propagation Delay

Bus to Bus 1.5 5.4 1.5 3.8 ns 1, 2

tPZH

tPZL Output Enable Time

DIR or OE to Bus 1.5 7.8 1.5 4.8 ns 1, 7, 8

tPHZ

tPLZ Output Disable Time

DIR or OE to Bus 1.5 6.3 1.5 4.0 ns 1, 7, 8

tPLH

tPHL Propagation Delay

Clock to Bus 1.5 5.7 1.5 3.8 ns 1, 5

tPLH

tPHL Propagation Delay

SBA or SAB to Bus 1.5 6.2 1.5 4.2 ns 1,5

tSU Set-Up Time HIGH or

LOW Bus to Clock 2.0 — 2.0 — ns 4

tHHold Time HIGH or

LOW Bus to Clock 1.5 — 0.0 — ns 4

tWClock Pulse Width

HIGH or LOW 5.0 — 3.0 — ns 6

tSK(O) Output Skew[17] — 0.5 — 0.5 ns —

Notes:

15. Minimum limits are speciﬁed but not tested on Propagation Delays.

16. See “Parameter Measurement Information” in the General Information section.

17. Skew any two outputs of the same package switching in the same direction. This parameter is ensured by design.

CY74FCT16646T

CY74FCT162646T

Ordering Information CY74FCT16646

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

3.8 CY74FCT16646ETPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial

5.4 CY74FCT16646CTPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial

6.3 CY74FCT16646ATPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial

9.0 CY74FCT16646TPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial

Ordering Information CY74FCT162646

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

3.8 74FCT162646ETPACT Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT162646ETPVC O56 56-Lead (300-Mil) SSOP

74FCT162646ETPVCT O56 56-Lead (300-Mil) SSOP

5.4 74FCT162646CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT162646CTPVC O56 56-Lead (300-Mil) SSOP

74FCT162646CTPVCT O56 56-Lead (300-Mil) SSOP

6.3 74FCT162646ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT162646ATPVC O56 56-Lead (300-Mil) SSOP

74FCT162646ATPVCT O56 56-Lead (300-Mil) SSOP

CY74FCT16646T

CY74FCT162646T

Package Diagrams

56-Lead Shrunk Small Outline Package O56

56-Lead Thin Shrunk Small Outline Package Z56

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