Microelectronics,Inc. EK7011CG 160 Output Segment/ Common LCD Driver EUREKA EK7011CG 160 Output Segment/Common LCD Driver Features in Segment mode Description The EK7011 is a 160 output segment/common LCD driver adaptable to drive a large scale dot matrix panel. It uses the Tape Carrier Package(TCP) to greatly reduce the size of the LCD module. EK7011 consumes l l l l very little power. Large LCD panels can be assembled by cascading EK7011s. In Segment Mode, the input data can be either 4-bit parallel or 8-bit parallel, selected by the Mode Select pin (MD). Features CMOS process l Logic power supply : 2.5V to 5.5V Low power consumption l Features in Common mode l l l 160 LCD display output Supply voltage for LCD driver :15 to 40V l Package : TCP, COG available l Block Diagram Automatic transfer of enable signal Automatic counting in the chip select mode. The internal clock stoped by automatically counting 160 of input data. l l Shift clock frequency : 14MHz max. at VDD=5V 4bit/8bit parallel input Y1 Shift clock frequency : 4MHz max. at VDD=5V Built-in 160-bit bidirectional shift register Single mode (160-bit shift register) or Dual Mode (two 80-bit shift registers) with these options: 1. Y1 Y160 Single mode 2. Y160 3. Y1 Y1 Y80, Y81 4. Y160 Y81, Y80 Y2 Y3 Y4 Single mode Y160 Dual mode Y1 Dual mode Y 1 60 V 1 2R V 0R V 1 2L V 0L FR D ISP O FF E IO 1 LP XCK L/R MD S /C D I0 D I7 Fig.1 1 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Input/Output Circuit VDD Input Signal I (Applicable pins) L/R, S/C, DI 0 ~ DI7 DISPOFF, LP, FR, MD VSS Fig.3 Input Circuit(1) VDD Input Signal I Control Signal VSS (Applicable pins) DI7, XCK VSS Fig.4 Input Circuit(2) 2 Rev 1.3 Feb.22.2001 EUREKA EK7011CG VDD Input Signal Control Signal VSS VSS VDD Output Signal I/O Control Signal (Applicable pins) EIO1, EIO2 Fig.5 Input/Output Circuit V0 V12 Control Signal 2 Control Signal 1 O Control Signal 3 Control Signal 4 (Applicable pins) Y1 to Y 160 V43 VGND Fig.6 LCD Driver Output Circuit 3 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Pin Functions (Segment mode) Symbol Function VDD Logic circuit power supply +2.5 to +5.5 V VSS,VGND Logic circuit and high voltage ground pin V0R, V0L V12R, V12L V43R, V43L Power supply for LCD driver voltage level l Normally, the bias voltage used is set by a resistor divider. l Ensure that voltages are set such that Vss V43<V12<V0. l ViR and ViL (i=0, 12, 43) should be externally connected to reduce the difference between the waveforms of the output pins Y1~Y160. Input for display data DI0~DI7 l In 4-bit parallel input mode, input data into the 4 pins DI0~DI3. Connect DI4~DI7 to VSS or VDD. l In 8-bit parallel input mode, input data into the 8 pins DI0~DI7. XCK LP L/R Input clock pin for displaying data l Data is read on the falling edge of the clock pulse. Latch pulse input for displaying data l Data is latched on the falling edge of the clock pulse. Direction selection for reading display data l When set to VSS , data is read sequentially from Y160 to Y1. l When set to VDD, data is read sequentially from Y1 to Y160. Control input to deselect output level l The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls LCD drive circuit. DISPOFF l When set to Vss level "L", the LCD driver output pins (Y1~Y160) are set to level VGND . l While set to "L", the contents of the line latch are cleared, but read the display data in the data latch regardless of condition of DISPOFF. When the DISPOFF function is cancelled, the driver outputs deselect level (V12 or V43),then outputs the contents of the data latch on the next falling edge of the LP. At that time, if DISPOFF removal time does not meet the conditions shown in Tab.15, it can not output the reading data correctly. AC signal for LCD driver output level l The input signal is level-shifted from logic voltage level to LCD drive voltage level, and FR controls LCD drive circuit. l Normally, inputs a frame inversion signal. l The LCD driver output voltage level of output pin can be setted using the line latch output signal and the FR signal. l Truth table is shown on Tab.6 & Tab.7. Tab.2 4 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Pin Functions (Segment mode) Symbol MD S/C Function Mode selection lWhen set to VSS level "L", 4-bit parallel input mode is selected. lWhen set to VDD level "H", 8-bit parallel input mode is selected. lThe relationship between the display data and driver output pins is shown on Tab.8 & Tab.9. Segment mode/common mode selection pin lWhen set to VDD, segment input mode is set. Input/Output for chip selection EIO1 EIO2 lWhen L/R input is at VSS level "L", EIO1 is set for output, and EIO2 is set for input. lWhen L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output. lDuring output, set to "H" while LP*XCK is "H" and after 160-bit data have been read, set to "L" for one cycle (from falling edge of XCK to next falling edge of XCK), after which it returns to "H". lDuring input, after the LP signal is input, the chip is selected while EI is set to "L". After 160-bits of data have been read, the chip is deselected. LCD driver output Y1-Y160 l Corresponding directly to each bit of the data latch, one level(V0, V12, V43, or VGND) is selected for output. l Truth table values is shown on Tab.6 & Tab.7. Tab.3 5 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Pin Functions (Common mode) Symbol Function VDD Logic circuit power supply pin connects to +2.5 to +5.5 V VSS, VGND Logic circuit and high voltage ground pin V0R, V0L V12R, V12L V43R, V43L Power supply pin for LCD driver voltage bias l Normally, the bias voltage used is set by a resistor divider. l Ensure that voltages are set such that VSS VGND<V43<V12<V0. lViR and ViL (i=0, 12, 43) should be externally connected to reduce the difference betw een the waveforms of the output pins Y1~Y160. Bidirectional shift register input/output EIO1 EIO2 LP l Output w hen L/R is set at Vss level "L", input w hen L/R is at VDD level "H". l When EIO1 is used as input pin, it w ill be pull-dow n. l When EIO1 is used as output pin, it w ill not be pull-dow n. Bidirectional shift register input/output l Input w hen L/R is set at VSS level "L", output w hen L/R is at VDD level "H". l When EIO2 is used as input, it w ill be pull-dow n.. l When EIO2 is used as output, it w ill not be pull-dow n. Bidirectional shift register clock pulse input l Data is shifted on the falling edge of the clock pulse. L/R Bidirectional shift register shift direction selection l When set to VSS ,data is shifted from Y160 to Y1. l When set to VDD, data is shifted from Y1 to Y160. DISPOFF Control input pin to deselect output level l The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls LCD drive circuit. l When set to "L", the LCD driver output pins (Y1-Y160) are set to level VGND. l While set to "L", the contents of the shift resister are cleared. When the DISPOFF function is cancelled, the driver outputs deselect level (V12 or V43). and the shift data is read on the fal l i ng edge of the LP. At that ti me, i f the DISPOFF r emoval ti me does not meet the conditions shown in Fig.15, then the shift data is not read correctly. FR AC signal input for LCD driver output level l The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls LCD drive circuit. l The LCD driver output voltage level can be set by using the shift register output signal and the FR signal. l Truth table is show n on Tab6 & Tab7. Tab.4 6 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Pin Functions (Common mode) Symbol Function MD Mode selection l When set to Vss level "L", Single Mode operation is selected, w hen set to VDD level "H", Dual Mode operation is selected. DI7 Dual Mode data input l According to the data shift direction of the data shift register, data can be input starting from the 81th bit. l When the chip is used as Dual Mode, DI7 w ill be pull-dow n. l When the chip is used as Single Mode, DI7 w ill not be pull-dow n. S/C Segment mode/common mode selection l When set to VSS level "L", Common Mode is setted. DI0~DI6 Not used l Connect DI0~DI6 to VSS or VDD. Avoiding floating. XCK Not used l XCK is pull-dow n in common mode, so connect them to Vss or open. Y1~Y160 LCD driver output l Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VGND)is selected. l Truth table is show n on Tab.6 & Tab.7. Tab.5 7 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Functional Operations Truth Table (Segment Mode) FR Latch Data DISPOFF Drive r Output Voltage Le ve l(Y1-Y160) L L H V43 L H H VGND H L H V12 H H H V0 X X L VGND Here, VSS VGND < V43 < V12 < V0, H:VDD (+2.5 to +5.5V), L:VSS(0 V) X:Dont care Tab.6 (Common Mode) FR Latch Data DISPOFF Drive r Output Voltage Le ve l(Y1-Y160) L L H V43 L H H V0 H L H V12 H H H VGND X X L VGND Here,VSS VGND < V43< V12 < V0, H:VDD (+2.5 to +5.5V), L:VSS(0 V) X:Dont care Tab.7 Note:There have two kinds of power supply (logic level voltage, LCD drive voltage) for LCD driver. Supply proper voltage according to each power pin specification. Dont care means that should be connected to H or L. Do not leave them open. 8 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Relationship between the Display Data and Driver Output pins (Segment Mode) (a)4-bit Parallel Mode Figure of Clock M D L/R EIO1 L L L H O utput Input EIO2 Input O utput D ata Input 40 clock 39 clock 38 clock ........ 3 clock 2 clock 1 clock DI0 Y1 Y5 Y9 ........ Y149 Y153 Y157 DI1 Y2 Y6 Y10 ........ Y150 Y154 Y158 DI2 Y3 Y7 Y11 ........ Y151 Y155 Y159 DI3 Y4 Y8 Y12 ........ Y152 Y156 Y160 DI0 Y160 Y156 Y152 ........ Y12 Y8 Y4 DI1 Y159 Y155 Y151 ........ Y11 Y7 Y3 DI2 Y158 Y154 Y150 ........ Y10 Y6 Y2 DI3 Y157 Y153 Y149 ........ Y9 Y5 Y1 Tab.8 9 Rev 1.3 Feb.22.2001 EUREKA EK7011CG (b)8-bit Parallel Mode Figure of Clock M D L/R EIO1 H H L H O utput Input EIO2 Input O utput D ata Input 2 clock 1 clock ............ Y137 Y145 Y153 Y18 ............ Y138 Y146 Y154 Y11 Y19 ............ Y139 Y147 Y155 Y4 Y12 Y20 ............ Y140 Y148 Y156 DI4 Y5 Y13 Y21 ............ Y141 Y149 Y157 DI5 Y6 Y14 Y22 ............ Y142 Y150 Y158 DI6 Y7 Y15 Y23 ............ Y143 Y151 Y159 DI7 Y8 Y16 Y24 ............ Y144 Y152 Y160 DI0 Y160 Y152 Y144 ........ Y24 Y16 Y8 DI1 Y159 Y151 Y143 ........ Y23 Y15 Y7 DI2 Y158 Y150 Y142 ........ Y22 Y14 Y6 DI3 Y157 Y149 Y141 ........ Y21 Y13 Y5 DI4 Y156 Y148 Y140 ........ Y20 Y12 Y4 DI5 Y155 Y147 Y139 ........ Y19 Y11 Y3 DI6 Y154 Y146 Y138 ........ Y18 Y10 Y2 DI7 Y153 Y145 Y137 ........ Y17 Y9 Y1 20 clock 19 clock 18 clock ........... DI0 Y1 Y9 Y17 DI1 Y2 Y10 DI2 Y3 DI3 3 clock Tab.9 10 Rev 1.3 Feb.22.2001 EUREKA EK7011CG (Common Mode) MD L/R L(shift to left) Data Transfe r Dire ction EIO1 EIO2 DI7 Y1 Output Input X Y1 Y160 Input Output X Y160 Y80 Y81 Y1 Output Input Input Input Output Input Y160 L (Single) H(shift to right) L(shift to left) H (Dual) H(shift to right) Y80 Y160 Y1 Y81 Tab.10 L: VSS(0 V), H: VDD (+2.5V to +5.5V), X: Dont Care Note: Dont care means that should be connected to H or L. Do not leave them open. 11 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Connection Examples of Plural Segment Drives (a) Case of L/R=L Fig.7 (b) Case of L/R=H 8 Fig.8 12 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Timing Chart of 4-Device cascade Connection of Segment Drivers FR LP XCK L a st D ATA To p D ATA D I0~ D I7 n 1 2 n 1 2 (D e v ic e A ) n 1 2 n 1 2 (d e vice B ) (d e vice C ) n 1 2 (d e vice D ) H EI (D e v ic e A ) L EO (D e v ic e A ) EO (d e vice B ) EO (d e vice C ) (*) n : 4 -b it p a ra lle l m o d e 4 0 8 -b it p a ra lle l m o d e 2 0 Fig.9 13 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Connection Examples for Plural Common Drivers Fig.10 Single Mode (Shifting toward left) Fig.11 Single Mode (Shifting toward right) 14 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Fig.12 Dual Mode (Shifting toward left) Fig.13 Dual Mode (Shifting toward right) 15 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Absolute Maximum Ratings Parame te r Supply voltage(1) Symbol VDD V0 Conditions Ta=25oC Referenced to VSS(0 V) V12 V43 Storage temperature Unit VDD -0.3 to +7.0 V V0L,V0R -0.3 to +45.0 V -0.3 to V0+0.3 V -0.3 to V0+0.3 V VGND -0.3 to V0+0.3 V DI0-7, XCK, LP, L/ R, FR, MD, S/ C, EIO1 , EIO2, DISPOFF -0.3 to VDD+0.3 V43L,V43R VGND VI Ratings V12L,V12R Supply voltage(2) Input voltage Applicable Pins Referenced to VSS V Tstg -45 to +125 o C Tab.11 Recommended Operating Conditions Parame te r Symbol Supply voltage(1) VDD Supply voltage(2) V0 Storage temperature Topr Conditions Referenced to VSS (0 V) Applicable pins Min. VDD V0L, V0R Typ. Max. Unit +2.5 +5.5 V +15.0 +40 V - 20 +85 o C Tab.12 Note:Ensure that voltages are set such that VSS VGND<V43<V12<V0 16 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Electrical Characteristics DC Characteristics (Segment Mode) (VSS=VGND=0 V, VDD=+2.5V to +5.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C ) Parame te r Input voltage Symbol Conditions Applicable pins Input leakage current Output resistance VOH IOH=-0.4mA VOL IOL=+0.4mA ILIH VI=VDD ILIL VI=VSS RON Typ. DI0~7, XCK, LP, 0.8V DD L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF VIH VIL Output voltage Min. | eVON| =0.5V EIO1,EIO2 Max. Unit V 0.2VDD VDD-0.4 V V DI0~7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF +0.4 V +10.0 A - 1 0 .0 A V0=+40.0V 0 .7 1 .0 V0=+30.0V Y1-Y160 1 .0 1.5 K V0=+20.0V 1 .5 2 .0 Stand-by current ISTB *1 Vss 5 0 .0 A Consumed current(1) (Deselection) IDD1 *2 VDD 2 .0 mA Consumed current(2) (Selection) IDD2 *3 VDD 8 .0 mA I0 *4 V0 1 .0 mA Consoumed current Tab.13 Note: *1 VDD=+5.0V, V0=+40V, VI=VSS *2 VDD=+5.0V, V0=+40V, fXCK=14MHz, No-load, EI=VDD The input data is turned over by data taking clock (4-bit parallel input mode) *3 VDD=+5.0V, V0=+40V, fXCK=14MHz, No-load, EI=VSS The input data is turned over by data taking clock (4-bit parallel input mode) *4 VDD=+5.0V, V0=+40V, fXCK=14MHz, fLP=41.6KHz, fFR=80Hz, No-load The input data is turned over by data taking clock (4-bit parallel input mode) 17 Rev 1.3 Feb.22.2001 EUREKA EK7011CG (Common Mode) (VSS=VGND=0 V, VDD=+2.5V to +5.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C ) Parame te r Input voltage Symbol Conditions VIH VIL Output voltage VOH IOH=-0.4mA VOL IOL=+0.4mA ILIH V1=VDD ILIL Output resistance Min. DI0~7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF 0.8VDD EIO1, EIO2 VDD-0.4 Typ. Max. Unit V 0.2VDD V V +0.4 V DI0~6, LP, L/R, FR, MD, S/C, DISPOFF +10.0 A V1=VSS DI0~7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF - 1 0 .0 A IPD V1=VDD XCK,EIO1,EIO2, DI7 1 0 0 .0 A RON |eVON| =0.5V Input leakage current Input pull-dow n current Applicable pins V0=+40.0V V0=+30.0V Y1~Y160 V0=+20.0V 0 .7 1 .0 1 .0 1 .5 1 .5 2 .0 K Stand-by current ISTB *1 Vss 5 0 .0 A Consumed current(1) IDD *2 VDD 8 0 .0 A Consumed current(2) IO *2 V0 1 6 0 .0 A Tab.14 *1 VDD=+5.0V, V0=+40V, VI=VSS *2 VDD=+5.0V, V0=+40V, fLP=41.6KHz, fFR=80Hz, case of 1/480 duty operation, No-load 18 Rev 1.3 Feb.22.2001 EUREKA EK7011CG AC Characteristics (Segment Mode 1) (VSS=VGND=0 V, VDD=+4.5V to +5.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C ) Parame te r Shift clock period *1 Symbol Condition tr ,tf 10 ns tWCK Min. Typ. Max. Unit 71 ns Shift clock "H" pulse width tWCKH 23 ns Shift clock "L" pulse width tWCKL 23 ns Data setup time tDS 10 ns Data Hold time tDH 20 ns tWLPH 23 ns Shift clock rise to Latch pulse rise time tLD 0 ns Shift clock fall to Latch pulse fall time tSL 25 ns Latch pulse rise to Shift clock rise time tLS 25 ns Latch pulse fall to Shift clock fall time tLH 25 ns Input signal rise time*2 tr 50 ns Input signal fall time*2 tf 50 ns Enable setup time ts 21 ns DISPOFF removal time tSD 100 ns DISPOFF " L" pulse width tWDL 1 .2 s Latch pulse"H"pulse width Output delay time(1) tD CL=15pF 40 ns Output delay time(2) tpd1,tpd2 CL=15pF 1.2 s Output delay time(3) tpd3 CL=15pF 1.2 s Tab.15 Note: *1 Take the cascade connection into consideration *2 (tCK-tWCKH-tWCKL) /2 is maximum in the case of high speed operation 19 Rev 1.3 Feb.22.2001 EUREKA EK7011CG (Segment Mode 2) (VSS=VGND=0 V, VDD=+2.5V to +4.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C ) Parame te r Shift clock period *1 Symbol Condition tr ,tf 11 ns tWCK Min. Typ. Max. Unit 125 ns Shift clock "H" pulse width tWCKH 51 ns Shift clock "L" pulse width tWCKL 51 ns Data setup time tDS 30 ns Data Hold time tDH 40 ns tWLPH 51 ns Shift clock rise to Latch pulse rise time tLD 0 ns Shift clock fall to Latch pulse fall time tSL 51 ns Latch pulse rise to Shift clock rise time tLS 51 ns Latch pulse fall to Shift clock fall time tLH 51 ns Input signal rise time*2 tr 50 ns Input signal fall time*2 tf 50 ns Enable setup time ts 36 ns DISPOFF removal time tSD 100 ns DISPOFF " L" pulse width tWDL 1 .2 s Latch pulse"H"pulse width Output delay time(1) tD CL=15pF 78 ns Output delay time(2) tpd1,tpd2 CL=15pF 1.2 s Output delay time(3) tpd3 CL=15pF 1.2 s Tab.16 Note: *1 Take the cascade connection into consideration *2 (tCK-tWCKH-tWCKL) /2 is maximum in the case of high speed operation 20 Rev 1.3 Feb.22.2001 EUREKA EK7011CG (Timing Characteristics of Segment Mode) tW LP H tS L LP tLD tLH tW CKH tLS tW C K L XCK tr tf tD S tW C K D I0~D I7 tD H TOP DATA L A S T D A TA tW D L TSD D IS P O F F LP (*) n 2 1 XCK tS tD EI EO ( * ) n : 4 - b it p a ra lle l m o d e 4 0 8 - b it p a r a lle l m o d e 2 0 FR tpd1 LP tpd 2 D IS P O F F T pd3 Y 1~Y 160 Fig.14 21 Rev 1.3 Feb.22.2001 EUREKA EK7011CG (Common Mode) (VSS=VGND=0 V, VDD=+2.5V to +5.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C ) Parame te r Shift clock period Shift clock "H" pulse width Symbol tWLP Condition tr ,tf 20 ns Min. Typ. Max. Unit 250 ns VDD=+5.0 V10% 15 ns VDD=+2.5V~ +4.5V 30 ns tWLPH Data setup time tSU 30 ns Data Hold time tH 50 ns Input signal rise time tr 50 ns Input signal fall time tf 50 ns DISPOFF removal time tSD 100 ns DISPOFF " L" pulse width tWDL 1 .2 s Output delay time(1) tDL CL=15pF 200 ns Output delay time(2) tpd1, tpd2 CL=15pF 1 .2 s Output delay time(3) tpd3 CL=15pF 1 .2 s Tab.17 22 Rev 1.3 Feb.22.2001 EUREKA EK7011CG (Timing Characteristics of Common Mode) tW LP LP tr tW LP H tS U tf tH E IO 2 (D I7) tD L E IO 1 tW DL tSD D IS P O F F FR tpd1 LP tpd 2 D IS P O F F T pd3 Y 1~Y 160 [L /R = " L " ] Fig.15 23 Rev 1.3 Feb.22.2001 V EE 24 DI0~DI7 XCK DISPOFF 8 6 (3) FR LP EIO2 XCK DI0~DI7 DISPOFF L/R S/C MD Ek7011 6 8 Com479 Com480 Com2 Com1 Ek70 Ek7011 Y 1~Y 160 (3) FR LP DISP OFF XC K (2) Ek7011 Ek70 Y 1~Y 160 LCD Panel 640 x 480 DOT MATRIX FR LP DISP OFF XC K EIO 1 MD S/C L/R DI 0 ~DI 7 EIO 2 EIO 1 MD S/C L/R DI 0 ~DI 7 EIO 2 (1) Ek7011 Y 1~Y 160 SEG2 SEG1 YD FR LP (Case of 1/n bias) V ss EIO1 Y 1 ~ Y 160 V DD DI0~DI7 DISPOFF XCK EIO2 L/R FR LP (2) MD S/C Ek7011 EIO1 DI0~DI7 DISPOFF XCK EIO2 LP FR (1) S/C L/R Ek7011 EIO1 MD Y 1 ~ Y 160 V4 V3 (N-4)R V2 V1 V0 50~100 Ek7011 Ek70 (4) Y 1~Y 160 EUREKA EK7011CG Example of system Configuration S E G 64 0 S E G 63 9 EIO 1 MD S/C L/R DI 0 ~DI 7 EIO 2 FR LP DISP OFF XC K EIO 1 MD S/C L/R DI 0 ~DI 7 EIO 2 FR LP DISP OFF XC K Y 1 ~ Y 160 C o n tro lle r Fig.16 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Example of Typical Characteristic Parame te r Typical Fundamental Rating Propagation Delay Time Condition Ta=+250C, Vss=0V, VDD=+5.0V Min. Typ. 10 Max. Unit ns Tab.18 25 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Precaution l Precaution when connecting or disconnecting the power This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if a voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The detail is as follows. l When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power. l We recommend you connecting the serial resistor(50~100 ) or fuse to the LCD drive power V0 of the system as a current limitter. And set up the suitable value of the resistor in consideration of LCD display grade. And when connecting the logic power supply, the logic condition of this LSI inside is insecurity. Therefore connect the LCD drive power supply after resetting logic condition of this LSI inside on DISPOFF function. After that. cancel the DISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level VGND on DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, show the following recommend sequence. VDD VDD VSS V0 V0 VGND VDD D IS P O F F VSS 26 Rev 1.3 Feb.22.2001 EUREKA EK7011CG Chip Size:9303.6um x 1173 um PAD152 EM7011 EUREKA PAD 1 EK7011 PAD165 PAD234 PAD 152 PAD 165 PAD 1 (0,0) PAD 234 Wafer thickness : 19mil Height of Bump : within lot 18m 3m within wafer < 4m within die < 2m All pads named Dummy are floating inside the chip and maybe used to aid routing on the glass. In COG applications, the high voltage ground pad VGND should have a separate path to the connector, and not be connected to VSS on the glass. This is to prevent any ground bounce generated by high voltage switching to disturb the logic circuits. Ensure that logic VSS and high voltage VGND are at the same potential. 27 Rev 1.3 Feb.22.2001 EUREKA PAD No. PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 PAD32 Bump size Pad Name 72.8X72.8 Y005 42.8X72.8 Y006 42.8X72.8 Y007 42.8X72.8 Y008 42.8X72.8 Y009 42.8X72.8 Y010 42.8X72.8 Y011 42.8X72.8 Y012 42.8X72.8 Y013 42.8X72.8 Y014 42.8X72.8 Y015 42.8X72.8 Y016 42.8X72.8 Y017 42.8X72.8 Y018 42.8X72.8 Y019 42.8X72.8 Y020 42.8X72.8 Y021 42.8X72.8 Y022 42.8X72.8 Y023 42.8X72.8 Y024 42.8X72.8 Y025 42.8X72.8 Y026 42.8X72.8 Y027 42.8X72.8 Y028 42.8X72.8 Y029 42.8X72.8 Y030 42.8X72.8 Y031 42.8X72.8 Y032 42.8X72.8 Y033 42.8X72.8 Y034 42.8X72.8 Y035 42.8X72.8 Y036 PAD34 42.8X72.8 Y037 42.8X72.8 Y038 PAD35 42.8X72.8 Y039 PAD33 EK7011CG XYcoordinat coordinat Pad Size ( um ) e e 4545 4470 4410 4350 4290 4230 4170 4110 4050 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 28 85.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 Rev 1.3 Feb.22.2001 EUREKA PAD No. PAD36 PAD37 PAD38 PAD39 PAD40 PAD41 PAD42 PAD43 PAD44 PAD45 PAD46 PAD47 PAD48 PAD49 PAD50 PAD51 PAD52 PAD53 PAD54 PAD55 PAD56 PAD57 PAD58 PAD59 PAD60 PAD61 PAD62 PAD63 PAD64 PAD65 PAD66 PAD67 Bump size Pad Name 42.8X72.8 Y040 42.8X72.8 Y041 42.8X72.8 Y042 42.8X72.8 Y043 42.8X72.8 Y044 42.8X72.8 Y045 42.8X72.8 Y046 42.8X72.8 Y047 42.8X72.8 Y048 42.8X72.8 Y049 42.8X72.8 Y050 42.8X72.8 Y051 42.8X72.8 Y052 42.8X72.8 Y053 42.8X72.8 Y054 42.8X72.8 Y055 42.8X72.8 Y056 42.8X72.8 Y057 42.8X72.8 Y058 42.8X72.8 Y059 42.8X72.8 Y060 42.8X72.8 Y061 42.8X72.8 Y062 42.8X72.8 Y063 42.8X72.8 Y064 42.8X72.8 Y065 42.8X72.8 Y066 42.8X72.8 Y067 42.8X72.8 Y068 42.8X72.8 Y069 42.8X72.8 Y070 42.8X72.8 Y071 PAD69 42.8X72.8 Y072 42.8X72.8 Y073 PAD70 42.8X72.8 Y074 PAD68 EK7011CG XYcoordinat coordinat Pad Size ( um ) e e 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 29 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 Rev 1.3 Feb.22.2001 EUREKA PAD No. PAD71 PAD72 PAD73 PAD74 PAD75 PAD76 PAD77 PAD78 PAD79 PAD80 PAD81 PAD82 PAD83 PAD84 PAD85 PAD86 PAD87 PAD88 PAD89 PAD90 PAD91 PAD92 PAD93 PAD94 PAD95 PAD96 PAD97 PAD98 Bump size Pad Name 42.8X72.8 Y075 42.8X72.8 Y076 42.8X72.8 Y077 42.8X72.8 Y078 42.8X72.8 Y079 42.8X72.8 Y080 42.8X72.8 Y081 42.8X72.8 Y082 42.8X72.8 Y083 42.8X72.8 Y084 42.8X72.8 Y085 42.8X72.8 Y086 42.8X72.8 Y087 42.8X72.8 Y088 42.8X72.8 Y089 42.8X72.8 Y090 42.8X72.8 Y091 42.8X72.8 Y092 42.8X72.8 Y093 42.8X72.8 Y094 42.8X72.8 Y095 42.8X72.8 Y096 42.8X72.8 Y097 42.8X72.8 Y098 42.8X72.8 Y099 42.8X72.8 Y100 42.8X72.8 Y101 42.8X72.8 Y102 42.8X72.8 Y103 PAD100 42.8X72.8 Y104 PAD99 PAD101 42.8X72.8 Y105 PAD102 42.8X72.8 Y106 PAD103 42.8X72.8 Y107 PAD104 42.8X72.8 Y108 PAD105 42.8X72.8 Y109 EK7011CG XYcoordinat coordinat Pad Size ( um ) e e 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 30 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 Rev 1.3 Feb.22.2001 EUREKA PAD No. Bump size Pad Name PAD106 42.8X72.8 Y110 PAD107 42.8X72.8 Y111 PAD108 42.8X72.8 Y112 PAD109 42.8X72.8 Y113 PAD110 42.8X72.8 Y114 PAD111 42.8X72.8 Y115 PAD112 42.8X72.8 Y116 PAD113 42.8X72.8 Y117 PAD114 42.8X72.8 Y118 PAD115 42.8X72.8 Y119 PAD116 42.8X72.8 Y120 PAD117 42.8X72.8 Y121 PAD118 42.8X72.8 Y122 PAD119 42.8X72.8 Y123 PAD120 42.8X72.8 Y124 PAD121 42.8X72.8 Y125 PAD122 42.8X72.8 Y126 PAD123 42.8X72.8 Y127 PAD124 42.8X72.8 Y128 PAD125 42.8X72.8 Y129 PAD126 42.8X72.8 Y130 PAD127 42.8X72.8 Y131 PAD128 42.8X72.8 Y132 PAD129 42.8X72.8 Y133 PAD130 42.8X72.8 Y134 PAD131 42.8X72.8 Y135 PAD132 42.8X72.8 Y136 PAD133 42.8X72.8 Y137 PAD134 42.8X72.8 Y138 PAD135 42.8X72.8 Y139 PAD136 42.8X72.8 Y140 PAD137 42.8X72.8 Y141 PAD138 42.8X72.8 Y142 PAD139 42.8X72.8 Y143 PAD140 42.8X72.8 Y144 EK7011CG XYcoordinat coordinat Pad Size ( um ) e e -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 480 31 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 Rev 1.3 Feb.22.2001 EUREKA PAD No. Bump size Pad Name PAD141 42.8X72.8 Y145 PAD142 42.8X72.8 Y146 PAD143 42.8X72.8 Y147 PAD144 42.8X72.8 Y148 PAD145 42.8X72.8 Y149 PAD146 42.8X72.8 Y150 PAD147 42.8X72.8 Y151 PAD148 42.8X72.8 Y152 PAD149 42.8X72.8 Y153 PAD150 42.8X72.8 Y154 PAD151 42.8X72.8 Y155 PAD152 72.8X72.8 Y156 PAD153 42.8X72.8 Y157 PAD154 42.8X72.8 Y158 PAD155 42.8X72.8 Y159 PAD156 42.8X72.8 Y160 PAD157 42.8X72.8 V0 PAD158 42.8X72.8 V12 PAD159 42.8X72.8 V43 PAD160 42.8X72.8 VGND PAD161 42.8X72.8 Dummy PAD162 42.8X72.8 Dummy PAD163 42.8X72.8 Dummy PAD164 42.8X72.8 Dummy PAD165 72.8X72.8 VGND PAD166 42.8X72.8 VSS PAD167 42.8X72.8 Dummy PAD168 42.8X72.8 Dummy PAD169 42.8X72.8 LR PAD170 42.8X72.8 Dummy PAD171 42.8X72.8 Dummy PAD172 42.8X72.8 Dummy PAD173 42.8X72.8 vdd:P PAD174 42.8X72.8 vdd:P PAD175 42.8X72.8 vdd:P EK7011CG XYcoordinat coordinat Pad Size ( um ) e e -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4410 -4470 -4545 -4545 -4545 -4545 -4545 -4545 -4545 -4545 -4545 -4545 -4545 -4545 -4545 -4545 -4470 -4410 -4350 -4230 -4110 -4050 -3870 -3810 -3750 -3690 480 480 480 480 480 480 480 480 480 480 480 480 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 32 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 85.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 85.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 Rev 1.3 Feb.22.2001 EUREKA PAD No. Bump size Pad Name PAD176 42.8X72.8 Dummy PAD177 42.8X72.8 Dummy PAD178 42.8X72.8 SC PAD179 42.8X72.8 Dummy PAD180 42.8X72.8 Dummy PAD181 42.8X72.8 EIO_2 PAD182 42.8X72.8 Dummy PAD183 42.8X72.8 Dummy PAD184 42.8X72.8 D0 PAD185 42.8X72.8 Dummy PAD186 42.8X72.8 Dummy PAD187 42.8X72.8 D1 PAD188 42.8X72.8 Dummy PAD189 42.8X72.8 Dummy PAD190 42.8X72.8 D2 PAD191 42.8X72.8 Dummy PAD192 42.8X72.8 Dummy PAD193 42.8X72.8 Dummy PAD194 42.8X72.8 D3 PAD195 42.8X72.8 Dummy PAD196 42.8X72.8 Dummy PAD197 42.8X72.8 D4 PAD198 42.8X72.8 Dummy PAD199 42.8X72.8 Dummy PAD200 42.8X72.8 D5 PAD201 42.8X72.8 Dummy PAD202 42.8X72.8 Dummy PAD203 42.8X72.8 D6 PAD204 42.8X72.8 Dummy PAD205 42.8X72.8 Dummy PAD206 42.8X72.8 D7 PAD207 42.8X72.8 Dummy PAD208 42.8X72.8 Dummy PAD209 42.8X72.8 CK PAD210 42.8X72.8 Dummy EK7011CG XYcoordinat coordinat Pad Size ( um ) e e -3630 -3450 -3330 -3210 -3030 -2910 -2790 -2610 -2490 -2370 -2190 -2070 -1950 -1770 -1650 -1530 -1230 -930 -810 -690 -510 -390 -270 -90 30 150 330 450 570 750 870 990 1170 1290 1410 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 33 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 Rev 1.3 Feb.22.2001 EUREKA PAD No. Bump size Pad Name PAD211 42.8X72.8 Dummy PAD212 42.8X72.8 DISPOFF PAD213 42.8X72.8 Dummy PAD214 42.8X72.8 Dummy PAD215 42.8X72.8 PLP PAD216 42.8X72.8 Dummy PAD217 42.8X72.8 Dummy PAD218 42.8X72.8 EIO_1 PAD219 42.8X72.8 Dummy PAD220 42.8X72.8 Dummy PAD221 42.8X72.8 PFR PAD222 42.8X72.8 Dummy PAD223 42.8X72.8 Dummy PAD224 42.8X72.8 PMD PAD225 42.8X72.8 Dummy PAD226 42.8X72.8 Dummy PAD227 42.8X72.8 T1 PAD228 42.8X72.8 Dummy PAD229 42.8X72.8 Dummy PAD230 42.8X72.8 T2 PAD231 42.8X72.8 Dummy PAD232 42.8X72.8 Dummy PAD233 42.8X72.8 VSS PAD234 72.8X72.8 VGND PAD235 42.8X72.8 Dummy PAD236 42.8X72.8 Dummy PAD237 42.8X72.8 Dummy PAD238 42.8X72.8 Dummy PAD239 42.8X72.8 VGND PAD240 42.8X72.8 V43 PAD241 42.8X72.8 V12 PAD242 42.8X72.8 V0 PAD243 42.8X72.8 Y001 PAD244 42.8X72.8 Y002 PAD245 42.8X72.8 Y003 PAD246 42.8X72.8 Y004 EK7011CG XYcoordinat coordinat Pad Size ( um ) e e 1590 1710 1830 2010 2130 2250 2430 2550 2670 2850 2970 3090 3270 3390 3510 3690 3810 3930 4110 4230 4350 4410 4470 4545 4545 4545 4545 4545 4545 4545 4545 4545 4545 4545 4545 4545 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -480 -330 -270 -210 -150 -90 -30 30 90 150 210 270 330 34 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 85.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 55.2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 85.2 Rev 1.3 Feb.22.2001