Microelectronics,Inc.
EK7011CG
160 Output Segment/
Common LCD Driver
EUREKA EK7011CG
1 Rev 1.3 Feb.22.2001
Description
The EK7011 is a 160 output segment/common LCD
driver adaptable to drive a large scale dot matrix panel.
It uses the Tape Carrier Package(TCP) to greatly
reduce the size of the LCD module. EK7011 consumes
very little power. Large LCD panels can be assembled
by cascading EK7011s. In Segment Mode, the input
data can be either 4-bit parallel or 8-bit parallel, selected
by the Mode Select pin (MD).
160 Output Segment/Common LCD Driver
Features
l CMOS process
l Logic power supply : 2.5V to 5.5V
l Low power consumption
l 160 LCD display output
l Supply voltage for LCD driver :15 to 40V
l Package : TCP, COG available
Features in Segment mode
l Shift clock frequency : 14MHz max. at VDD=5V
l 4bit/8bit parallel input
l Automatic transfer of enable signal
l Automatic counting in the chip select mode. The
internal clock stoped by automatically counting
160 of input data.
Features in Common mode
l Shift clock frequency : 4MHz max. at VDD=5V
l Built-in 160-bit bidirectional shift register
l Single mode (160-bit shift register) or Dual Mode
(two 80-bit shift registers) with these options:
1. Y1 Y160 Single mode
2. Y160 Y1 Single mode
3. Y1 Y80, Y81 Y160 Dual mode
4. Y160 Y81, Y80 Y1 Dual mode
Y
1
Y
2
Y
3
Y
4
Y
160
XCK
L/R
MD
S/C
V
12R
V
0R
V
12L
V
0L
DI
0
DI
7
FR
DISPOFF
EIO
1
LP
Block Diagram
Fig.1
EUREKA EK7011CG
2 Rev 1.3 Feb.22.2001
Input/Output Circuit
Fig.3 Input Circuit(1)
Fig.4 Input Circuit(2)
IInput Signal
VDD
VSS
(Applicable pins)
L/R, S/C, DI0 ~ DI7
DISPOFF, LP, FR, MD
IInput Signal
VDD
VSS
(Applicable pins)
DI7, XCK
VSS
Control Signal
EUREKA EK7011CG
3 Rev 1.3 Feb.22.2001
Fig.5 Input/Output Circuit
Fig.6 LCD Driver Output Circuit
I/O
Input Signal
VDD
VSS
(Applicable pins)
EIO1, EIO2
VSS
Control Signal
Output Signal
Control Signal
VDD
O
Control Signal 3
Control Signal 1 Control Signal 2
Control Signal 4
VGND
V43
V0V12
(Applicable pins)
Y1 to Y 160
EUREKA EK7011CG
4 Rev 1.3 Feb.22.2001
Pin Functions
(Segment mode)
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
Tab.2
l
Symbol Function
VDD Logic circuit pow er supply +2.5 to +5.5 V
VSS,VGND Logic circuit and high voltage ground pin
V0R, V0L
V12R, V12L
V43R, V43L
Power supply for LCD driver voltage level
Normally, the bias voltage used is set by a resistor divider.
Ensure that voltages are set such that Vss V43<V12<V0.
V
iR and ViL (i=0, 12, 43) should be externally connected to reduce the difference between
the waveforms of the output pins Y1~Y160.
DI0~DI7
Input for display data
In 4-bit parallel input mode, input data into the 4 pins DI0~DI3.
Connect DI
4~DI7 to VSS or VDD.
In 8-bit parallel input mode, input data into the 8 pins DI0~DI7.
XCK Input clock pin for displaying data
Data is read on the falling edge of the clock pulse.
LP Latch pulse input for displaying data
Data is latched on the falling edge of the clock pulse.
L/R
Direction selection for reading display data
When set to VSS , data is read sequentially from Y160 to Y1.
When set to VDD, data is read sequentially from Y1 to Y160.
DISPOFF
Control input to deselect output level
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls LCD drive circuit.
When set to Vss level "L", the LCD driver output pins (Y1~Y160) are set to level VGND .
While set to "L", the contents of the line latch are cleared, but read the display data in the
data latch regardless of condition of DISPOFF. When the DISPOFF function is cancelled, the
driver outputs deselect level (V12 or V43),then outputs the contents of the data latch on the
next falling edge of the LP. At that time, if DISPOFF removal time does not meet the
conditions shown in Tab.15, it can not output the reading data correctly.
FR
AC signal for LCD driver output level
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls LCD drive circuit.
Normally, inputs a frame inversion signal.
The LCD driver output voltage level of output pin can be setted using the line latch output
signal and the FR signal.
Truth table is shown on Tab.6 & Tab.7.
≤
EUREKA EK7011CG
5 Rev 1.3 Feb.22.2001
Pin Functions
(Segment mode)
l
l
l
Tab.3
l
l
l
l
l
l
l
Symbol Function
MD Mode selection
When set to VSS level "L", 4-bit parallel input mode is selected.
When set to VDD level "H", 8-bit parallel input mode is selected.
The relationship between the display data and driver output pins is shown on Tab.8 & Tab.9.
S/C Segment mode/common mode selection pin
When set to VDD, segment input mode is set.
EIO1
EIO2
Input/Output for chip selection
When L/R input is at V
SS level "L", EIO1 is set for output, and EIO2 is set for input.
When L/R input is at V
DD level "H", EIO1 is set for input, and EIO2 is set for output.
During output, set to "H" while LP*XCK is "H" and after 160-bit data have been read, set
to "L" for one cycle (from falling edge of XCK to next falling edge of XCK), after which it
returns to "H".
During input, after the LP signal is input, the chip is selected while EI is set to "L". After
160-bits of data have been read, the chip is deselected.
Y1-Y160
LCD driver output
Corresponding directly to each bit of the data latch, one level(V0, V12, V43, or VGND) is
selected for output.
Truth table values is shown on Tab.6 & Tab.7.
EUREKA EK7011CG
6 Rev 1.3 Feb.22.2001
(Common mode)
lobmySnoitcnuF
V
DD
V5.5+ot5.2+otstcennocnipylppusrewoptiucriccigoL
V
SS
V,
DNG
nipdnuorgegatlovhgihdnatiucriccigoL
V
R0
V,
L0
V
R21
V,
L21
V
R34
V,
L34
saibegatlovrevirdDCLrofnipylppusrewoP
.redividrotsiseraybtessidesuegatlovsaibeht,yllamroN
VtahthcusteserasegatlovtahterusnE
SS
V
DNG
V<
34
V<
21
V<
0
.
neewtebecnereffidehtecuderotdetcennocyllanretxeebdluohs)34,21,0=i(LiVdnaRiV
.061Y~1Ysniptuptuoehtfosmrofevaweht
OIE
1
tuptuo/tupniretsigertfihslanoitceridiB
VtasiR/Lnehwtupni,"L"levelssVtatessiR/LnehwtuptuO
DD
."H"level
OIEnehW
1
.nwod-llupeblliwti,niptupnisadesusi
OIEnehW
1
.nwod-llupebtonlliwti,niptuptuosadesusi
OIE
2
tuptuo/tupniretsigertfihslanoitceridiB
VtatessiR/LnehwtupnI
SS
VtasiR/Lnehwtuptuo,"L"level
DD
."H"level
OIEnehW
2
..nwod-llupeblliwti,tupnisadesusi
OIEnehW
2
.nwod-llupebtonlliwti,tuptuosadesusi
PL tupnieslupkcolcretsigertfihslanoitceridiB
.eslupkcolcehtfoegdegnillafehtnodetfihssiataD
R/L
noitcelesnoitceridtfihsretsigertfihslanoitceridiB
VottesnehW
SS
Ymorfdetfihssiatad,
061
Yot
1
.
VottesnehW
DD
Ymorfdetfihssiatad,
1
Yot
061
.
FFOPSID
leveltuptuotcelesedotniptupnilortnoC
dna,levelegatlovevirdDCLotlevelegatlovcigolmorfdetfihs-levelsilangistupniehT
.tiucricevirdDCLslortnoc
Y(sniptuptuorevirdDCLeht,"L"ottesnehW
1
Y-
061
Vlevelottesera)
DNG
.
noitcnufFFOPSIDehtnehW.deraelceraretsisertfihsehtfostnetnoceht,"L"otteselihW
V(leveltcelesedstuptuorevirdeht,dellecnacsi
21
o
Vr
34
ehtnodaersiatadtfihsehtdna.)
ehtteemtonseodemitlavomerFFOPSIDehtfi,emittahttA.PLehtfoegdegnillaf
.yltcerrocdaertonsiatadtfihsehtneht,51.giFninwohssnoitidnoc
RF
leveltuptuorevirdDCLroftupnilangisCA
dna,levelegatlovevirdDCLotlevelegatlovcigolmorfdetfihs-levelsilangistupniehT
.tiucricevirdDCLslortnoc
langistuptuoretsigertfihsehtgnisuybtesebnaclevelegatlovtuptuorevirdDCLehT
.langisRFehtdna
.7baT&6baTnonwohssielbathturT
Pin Functions
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
Tab.4
l
l
≤
EUREKA EK7011CG
7 Rev 1.3 Feb.22.2001
Pin Functions
(Common mode)
lobmySnoitcnuF
DM
noitcelesedoM
Vottesnehw,detcelessinoitarepoedoMelgniS,"L"levelssVottesnehW
DD
,"H"level
.detcelessinoitarepoedoMlauD
ID
7
tupniatadedoMlauD
gnitratstupniebnacatad,retsigertfihsatadehtfonoitceridtfihsatadehtotgnidroccA
.tibht18ehtmorf
ID,edoMlauDsadesusipihcehtnehW
7
.nwod-llupeblliw
ID,edoMelgniSsadesusipihcehtnehW
7
.nwod-llupebtonlliw
C/S noitcelesedomnommoc/edomtnemgeS
VottesnehW
SS
.dettessiedoMnommoC,"L"level
ID
0
ID~
6
desutoN
IDtcennoC
0
ID~
6
Vot
SS
Vro
DD
.gnitaolfgnidiovA.
KCX desutoN
.neporossVotmehttcennocos,edomnommocninwod-llupsiKCX
Y
1
Y~
061
tuptuorevirdDCL
V(leveleno,retsigertfihsehtfotibhcaeotyltceridgnidnopserroC
0
V,
21
V,
34
Vro,
DNG
si)
.detceles
.7.baT&6.baTnonwohssielbathturT
l
l
l
l
l
l
Tab.5
l
l
l
EUREKA EK7011CG
8 Rev 1.3 Feb.22.2001
Functional Operations
Truth Table
(Segment Mode)
RFataDhctaLFFOPSIDY(leveLegatloVtuptuOrevirD
1
Y-
061
)
LLH V
34
LHH V
DNG
HLH V
21
HHH V
0
XXL V
DNG
Here, VSS≤ VGND < V43 < V12 < V0, H:VDD (+2.5 to +5.5V), L:VSS(0 V)
X:Donîš’t care
Tab.6
(Common Mode)
RFataDhctaLFFOPSIDY(leveLegatloVtuptuOrevirD
1
Y-
061
)
LLH V
34
LHH V
0
HLH V
21
HHH V
DNG
XXL V
DNG
Here,VSS≤ VGND < V43< V12 < V0, H:VDD (+2.5 to +5.5V), L:VSS(0 V)
X:Donîš’t care
Note:There have two kinds of power supply (logic level voltage, LCD drive voltage) for LCD
driver.
Supply proper voltage according to each power pin specification.
îš“Donîš’t careîš” means that should be connected to îš“Hîš” or îš“Lîš”. Do not leave them open.
Tab.7
EUREKA EK7011CG
9 Rev 1.3 Feb.22.2001
Relationship between the Display Data and Driver Output pins
(Segment Mode)
(a)4-bit Parallel Mode
DMR/LOIE
1
OIE
2
ataD
tupnI
kcolCfoerugiF
04
kcolc
93
kcolc
83
kcolc ........ 3
kcolc
2
kcolc
1
kcolc
LL tuptuOtupnI
ID
0
Y
1
Y
5
Y
9
........Y
941
Y
351
Y
751
ID
1
Y
2
Y
6
Y
01
........Y
051
Y
451
Y
851
ID
2
Y
3
Y
7
Y
11
........Y
151
Y
551
Y
951
ID
3
Y
4
Y
8
Y
21
........Y
251
Y
651
Y
061
LH tupnItuptuO
ID
0
Y
061
Y
651
Y
251
........Y
21
Y
8
Y
4
ID
1
Y
951
Y
551
Y
151
........Y
11
Y
7
Y
3
ID
2
Y
851
Y
451
Y
051
........Y
01
Y
6
Y
2
ID
3
Y
751
Y
351
Y
941
........Y
9
Y
5
Y
1
Tab.8
EUREKA EK7011CG
10 Rev 1.3 Feb.22.2001
(b)8-bit Parallel Mode
DMR/LOIE
1
OIE
2
ataD
tupnI
kcolCfoerugiF
02
kcolc
91
kcolc
81
kcolc ........
...
3
kcolc
2
kcolc
1
kcolc
HL tuptuOtupnI
ID
0
Y
1
Y
9
71Y............Y
731
Y
541
Y
351
ID
1
Y
2
Y
01
Y
81
............Y
831
Y
641
Y
451
ID
2
Y
3
Y
11
Y
91
............Y
931
Y
741
Y
551
ID
3
Y
4
Y
21
02Y............Y
041
Y
841
Y
651
4IDY
5
31Y12Y............Y
141
Y
941
Y
751
5IDY
6
Y
41
22Y............Y
241
Y
051
Y
851
6IDY
7
Y
51
32Y............Y
341
Y
151
Y
951
7IDY
8
Y
61
42Y............Y
441
Y
251
Y
061
HH tupnItuptuO
ID
0
Y
061
Y
251
Y
441
........42YY
61
Y
8
ID
1
Y
951
Y
151
Y
341
........32YY
51
Y
7
ID
2
Y
851
Y
051
Y
241
........22YY
41
Y
6
ID
3
Y
751
Y
941
Y
141
........12YY
31
Y
5
4IDY
651
Y
841
Y
041
........02YY
21
Y
4
5IDY
551
Y
741
Y
931
........Y
91
Y
11
Y
3
6IDY
451
Y
641
Y
831
........Y
81
Y
01
Y
2
7IDY
351
Y
541
Y
731
........Y
71
Y
9
Y
1
Tab.9
EUREKA EK7011CG
11 Rev 1.3 Feb.22.2001
(Common Mode)
DMR/L refsnarTataD
noitceriD OIE
1
OIE
2
ID
7
L
)elgniS(
)tfelottfihs(LY
061
Y
1
tuptuOtupnIX
)thgirottfihs(HY
1
Y
061
tupnItuptuOX
H
)lauD(
)tfelottfihs(L Y
061
Y
18
Y
08
Y
1
tuptuOtupnItupnI
)thgirottfihs(H Y
1
Y
08
Y
18
Y
061
tupnItuptuOtupnI
L: VSS(0 V), H: VDD (+2.5V to +5.5V), X: Donîš’t Care
Note: îš“Donîš’t careîš” means that should be connected to îš“Hîš” or îš“Lîš”. Do not leave them open.
Tab.10
EUREKA EK7011CG
12 Rev 1.3 Feb.22.2001
Connection Examples of Plural Segment Drives
(a) Case of L/R=L
(b) Case of L/R=H
8
Fig.7
Fig.8
EUREKA EK7011CG
13 Rev 1.3 Feb.22.2001
Timing Chart of 4-Device cascade Connection of Segment Drivers
EO
(device C )
EO
(device B )
EO
(D e v ic e A)
EI H
n12n12n12n12n12
(D e v ic e A) (device B ) (device C ) (device D )
To p DATA
DI ~DI
07
XCK
LP
FR
(*) n: 4-bit parallel mode 40
8-bit parallel m ode 20
La st D ATA
(D e v ic e A) L
Fig.9
EUREKA EK7011CG
14 Rev 1.3 Feb.22.2001
Connection Examples for Plural Common Drivers
Fig.10 Single Mode (Shifting toward left)
Fig.11 Single Mode (Shifting toward right)
EUREKA EK7011CG
15 Rev 1.3 Feb.22.2001
Fig.12 Dual Mode (Shifting toward left)
Fig.13 Dual Mode (Shifting toward right)
EUREKA EK7011CG
16 Rev 1.3 Feb.22.2001
Absolute Maximum Ratings
retemaraPlobmySsnoitidnoCsniPelbacilppAsgnitaRtinU
)1(egatlovylppuSV
DD
52=aT
o
C
decnerefeR
Vot
SS
)V0(
V
DD
0.7+ot3.0-V
)2(egatlovylppuS
V
0
V
L0
V,
R0
0.54+ot3.0-V
V
21
V
L21
V,
R21
Vot3.0-
0
3.0+V
V
34
V
L34
V,
R34
Vot3.0-
0
3.0+V
V
DNG
V
DNG
Vot3.0-
0
3.0+V
egatlovtupnIV
I
decnerefeR
Vot
SS
ID
7-0
,R/L,PL,KCX,
OIE,C/S,DM,RF
1
,
OIE
2
FFOPSID,
Vot3.0-
DD
3.0+
V
erutarepmetegarotSgtsT521+ot54-
o
C
Recommended Operating Conditions
retemaraPlobmySsnoitidnoCsnipelbacilppA.niM.pyT.xaMtinU
)1(egatlovylppuSV
DD
decnerefeR
Vot
SS
)V0( V
DD
5.2+5.5+V
)2(egatlovylppuSV
0
V
L0
V,
R0
0.51+04+V
erutarepmetegarotST
rpo
02-58+
o
C
Note:Ensure that voltages are set such that VSS≤ VGND<V43<V12<V0
Tab.11
Tab.12
EUREKA EK7011CG
17 Rev 1.3 Feb.22.2001
Electrical Characteristics
DC Characteristics
(Segment Mode)
(VSS=VGND=0 V, VDD=+2.5V to +5.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C )
retemaraPlobmySsnoitidnoCsnipelbacilppA.niM.pyT.xaMtinU
egatlovtupnI
V
HI
ID
7~0
,PL,KCX,
,DM,RF,R/L
OIE,C/S
1
,
OIE
2
FFOPSID,
V8.0
DD
V
V
LI
V2.0
DD
V
egatlovtuptuO
V
HO
I
HO
Am4.0-= OIE
1
OIE,
2
V
DD
4.0-V
V
LO
I
LO
Am4.0+=4.0+V
egakaeltupnI
tnerruc
I
HIL
V
I
V=
DD
ID
7~0
,PL,KCX,
,DM,RF,R/L
OIE,C/S
1
,
OIE
2
FFOPSID,
0.01+
I
LIL
V
I
V=
SS
0.01-
ecnatsisertuptuO
R
NO
V|
NO
|
V5.0=
V
0
V0.04+=
Y
1
Y-
061
7.00.1
V
0
V0.03+=0.15.1
V
0
V0.02+=5.10.2
tnerrucyb-dnatS I
TS
B
1*V
ss
0.05
)1(tnerrucdemusnoC
)noitceleseD( I
1DD
2*V
DD
0.2Am
)2(tnerrucdemusnoC
)noitceleS( I
2DD
3*V
DD
0.8Am
tnerrucdemuosnoCI
0
4*V
0
0.1Am
êKΩ
Note:
*1 VDD=+5.0V, V0=+40V, VI=VSS
*2 VDD=+5.0V, V0=+40V, fXCK=14MHz, No-load, EI=VDD
The input data is turned over by data taking clock (4-bit parallel input mode)
*3 VDD=+5.0V, V0=+40V, fXCK=14MHz, No-load, EI=VSS
The input data is turned over by data taking clock (4-bit parallel input mode)
*4 VDD=+5.0V, V0=+40V, fXCK=14MHz, fLP=41.6KHz, fFR=80Hz, No-load
The input data is turned over by data taking clock (4-bit parallel input mode)
Tab.13
µA
µA
µA
EUREKA EK7011CG
18 Rev 1.3 Feb.22.2001
(Common Mode)
(VSS=VGND=0 V, VDD=+2.5V to +5.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C )
retemaraPlobmySsnoitidnoCsnipelbacilppA.niM.pyT.xaMtinU
egatlovtupnI
V
HI
ID
7~0
,,KCX,PL
,R/L,RF,DM
,C/SOIE
1
,OIE
2
,
FFOPSID
V8.0
DD
V
V
LI
V2.0
DD
V
egatlovtuptuO
V
HO
I
HO
Am4.0-= OIE
1
,OIE
2
V
DD
4.0-V
V
LO
I
LO
Am4.0+=4.0+V
egakaeltupnI
tnerruc
I
HIL
V
1
V=
DD
ID
6~0
,R/L,PL,
,C/S,DM,RF
FFOPSID
0.01+
I
LIL
V
1
V=
SS
ID
7~0
,,KCX,PL
,R/L,RF,DM
,C/SOIE
1
,OIE
2
,
FFOPSID
0.01-
nwod-lluptupnI
tnerruc
I
DP
V
1
V=
DD
OIE,KCX
1
OIE,
2
,
ID
7
0.001
ecnatsisertuptuOR
NO
V|
NO
|
V5.0=
V
0
V0.04+=
Y
1
Y~
061
7.00.1
V
0
V0.03+=0.15.1
V
0
V0.02+=5.10.2
tnerrucyb-dnatS I
TS
B
1*V
ss
0.05
demusnoC
)1(tnerruc I
DD
2*V
DD
08
0.
demusnoC
)2(tnerruc I
O
2*V
0
061
0.
KΩ
ê
*1 VDD=+5.0V, V0=+40V, VI=VSS
*2 VDD=+5.0V, V0=+40V, fLP=41.6KHz, fFR=80Hz, case of 1/480 duty operation, No-load
Tab.14
µA
µA
µA
µA
µA
µA
EUREKA EK7011CG
19 Rev 1.3 Feb.22.2001
AC Characteristics
(Segment Mode 1)
(VSS=VGND=0 V, VDD=+4.5V to +5.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C )
≤
Note:
*1 Take the cascade connection into consideration
*2 (tCK-tWCKH-tWCKL) /2 is maximum in the case of high speed operation
retemaraPlobmySnoitidnoC.niM.pyT.xaMtinU
1*doirepkcolctfihSt
KCW
t
r
t,
f
sn0117sn
htdiweslup"H"kcolctfihSt
HKCW
32sn
htdiweslup"L"kcolctfihSt
LKCW
32sn
emitputesataDt
SD
01sn
emitdloHataDt
HD
02sn
htdiweslup"H"esluphctaLt
HPLW
32sn
otesirkcolctfihS
emitesiresluphctaL t
DL
0sn
otllafkcolctfihS
emitllafesluphctaL t
LS
52sn
otesiresluphctaL
emitesirkcolctfihS t
SL
52sn
otllafesluphctaL
emitllafkcolctfihS t
HL
52sn
2*emitesirlangistupnIt
r
05sn
2*emitllaflangistupnIt
f
05sn
emitputeselbanEt
s
12sn
emitlavomerFFOPSIDt
DS
001sn
htdiweslup"L"FFOPSIDt
LDW
2.1
)1(emityaledtuptuOt
D
C
L
Fp51=04sn
)2(emityaledtuptuOt
1dp
t,
2dp
C
L
Fp51=2.1
)3(emityaledtuptuOt
3dp
C
L
Fp51=2.1
Tab.15
µs
µs
µs
EUREKA EK7011CG
20 Rev 1.3 Feb.22.2001
(Segment Mode 2)
(VSS=VGND=0 V, VDD=+2.5V to +4.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C )
retemaraPlobmySnoitidnoC.niM.pyT.xaMtinU
1*doirepkcolctfihSt
KCW
t
r
t,
f
sn11521sn
htdiweslup"H"kcolctfihSt
HKCW
15sn
htdiweslup"L"kcolctfihSt
LKCW
15sn
emitputesataDt
SD
03sn
emitdloHataDt
HD
04sn
htdiweslup"H"esluphctaLt
HPLW
15sn
otesirkcolctfihS
emitesiresluphctaL t
DL
0sn
otllafkcolctfihS
emitllafesluphctaL t
LS
15sn
otesiresluphctaL
emitesirkcolctfihS t
SL
15sn
otllafesluphctaL
emitllafkcolctfihS t
HL
15sn
2*emitesirlangistupnIt
r
05sn
2*emitllaflangistupnIt
f
05sn
emitputeselbanEt
s
63sn
emitlavomerFFOPSIDt
DS
001sn
htdiweslup"L"FFOPSIDt
LDW
2.1
)1(emityaledtuptuOt
D
C
L
Fp51=87sn
)2(emityaledtuptuOt
1dp
t,
2dp
C
L
Fp51=2.1
)3(emityaledtuptuOt
3dp
C
L
Fp51=2.1
≤
Note:
*1 Take the cascade connection into consideration
*2 (tCK-tWCKH-tWCKL) /2 is maximum in the case of high speed operation
Tab.16
µs
µs
µs
EUREKA EK7011CG
21 Rev 1.3 Feb.22.2001
(Timing Characteristics of Segment Mode)
t
WLPH
t
WCKL
t
LH
t
WCKH
t
LD
t
LS
t
SL
t
r
t
f
t
WCK
LA S T D ATA
TOP DATA
t
DS
t
DH
t
WDL
T
SD
LP
XCK
DI DI
0~ 7
DISPOFF
()
*
12n
t
D
LP
XCK
EI
EO
t
S
(*) n : 4-bit pa ra llel mode 40
8- bi t paral l e l mode 20
t
pd1
t
pd2
T
pd3
FR
LP
DISPOFF
YY
1~ 160
Fig.14
EUREKA EK7011CG
22 Rev 1.3 Feb.22.2001
(Common Mode)
(VSS=VGND=0 V, VDD=+2.5V to +5.5V, V0=+15.0 to +40 V, Ta=-20 to +85 0C )
retemaraPlobmySnoitidnoC.niM.pyT.xaMtinU
doirepkcolctfihSt
PLW
t
r
t,
f
sn02052sn
htdiweslup"H"kcolctfihSt
HPLW
V
DD
%01V0.5+= 51sn
V
DD
V5.4+~V5.2+=03sn
emitputesataDt
US
03sn
emitdloHataDt
H
05sn
emitesirlangistupnIt
r
05sn
emitllaflangistupnIt
f
05sn
emitlavomerFFOPSIDt
DS
001sn
htdiweslup"L"FFOPSIDt
LDW
2.1
)1(emityaledtuptuOt
LD
C
L
Fp51=002sn
)2(emityaledtuptuOt
1dp
t,
2dp
C
L
Fp51=2.1
)3(emityaledtuptuOt
3dp
C
L
Fp51=2.1
≤
±
Tab.17
µs
µs
µs
EUREKA EK7011CG
23 Rev 1.3 Feb.22.2001
(Timing Characteristics of Common Mode)
t
WLPH
t
H
LP
EIO
(DI )
2
7
t
r
t
f
t
WLP
t
SU
t
DL
t
SD
t
WDL
EIO
1
DISPOFF
t
pd1
t
pd2
T
pd3
FR
LP
DISPOFF
YY
1~ 160
[L/R="L"]
Fig.15
EUREKA EK7011CG
24 Rev 1.3 Feb.22.2001
(N-4)R
Ek70
(4)
LCD Panel
640 x 480
DOT MATRIX
Com1
Com2
Com480
Com479
SEG
640
SEG
639
SEG
2
SEG
1
EIO
1
MD
S/C
L/R
EIO
2
Ek7011
(4)
EIO
1
MD
S/C
L/R
EIO
2
FR
LP
DISPOFF
XCK
Ek7011
EIO
1
MD
S/C
L/R
FR
LP
DISPOFF
XCK
Ek70
EIO
1
MD
S/C
L/R
Ek70
EIO
1
MD
S/C
L/R
EIO
2
Ek7011
MD
S/C
L/R
EIO
2
FR
LP
DISPOFF
XCK
Ek7011
EIO
1
MD
S/C
L/R
EIO
2
FR
LP
DISPOFF
XCK
EIO
1
MD
S/C
L/R
EIO
2
(3)
(2)
(1)
EIO
2
EIO
2
DI
07
~DI
EIO
1
MD
S/C
L/R
EIO
2
FR
LP
DISPOFF
XCK
FR
LP
DISPOFF
XCK
EIO
1
MD
S/C
L/R
EIO
2
EIO
1
MD
S/C
L/R
EIO
2
FR
LP
DISPOFF
XCK
Y~Y
1160
YD
FR
LP
DISPOFF
XCK
DI
07
~DI
DI
07
~DI
DI
07
~DI
DI
07
~DI
DI
07
~DI
DI
07
~DI
Controller
DI
07
~DI
50~100
V
EE
V
0
V1
V
2
V
3
V
4
V
DD
V
ss 8
6
6
8
Ek7011
(1)
Ek7011
(2)
Ek7011
(3)
(Case of 1/n bias)
Y~Y
1160
Y~Y
1160
Y~Y
1160
Y~Y
1160
Y~Y
1160
Y~Y
1160
Example of system Configuration
Fig.16
EUREKA EK7011CG
25 Rev 1.3 Feb.22.2001
Example of Typical Characteristic
retemaraPnoitidnoC.niM.pyT.xaMtinU
gnitaRlatnemadnuFlacipyT
emiTyaleDnoitagaporP 52+=aT
0
V,V0=ssV,C
DD
V0.5+=01sn
Tab.18
EUREKA EK7011CG
26 Rev 1.3 Feb.22.2001
Precaution
l Precaution when connecting or disconnecting the power
This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current which may
flow if a voltage is supplied to the LCD driver power supply while the logic system power supply is
floating.
The detail is as follows.
l When connecting the power supply, connect the LCD drive power after connecting the logic system
power. Furthermore, when disconnecting the power, disconnect the logic system power after
disconnecting the LCD drive power.
l We recommend you connecting the serial resistor(50~100Ω ) or fuse to the LCD drive power V0 of the
system as a current limitter. And set up the suitable value of the resistor in consideration of LCD display
grade.
And when connecting the logic power supply, the logic condition of this LSI inside is insecurity. Therefore
connect the LCD drive power supply after resetting logic condition of this LSI inside on DISPOFF function.
After that. cancel the DISPOFF function after the LCD drive power supply has become stable. Furthermore,
when disconnecting the power, set the LCD drive output pins to level VGND on DISPOFF function. After that,
disconnect the logic system power after disconnecting the LCD drive power. When connecting the power
supply, show the following recommend sequence.
V
DD
V
DD
V
SS
V
SS
V
GND
V
0
V
DD
DISPOFF
V
0
EUREKA EK7011CG
27 Rev 1.3 Feb.22.2001
All pads named Dummy are floating inside the chip and maybe used to aid routing on the glass.
In COG applications, the high voltage ground pad VGND should have a separate path to the connector, and
not be connected to VSS on the glass. This is to prevent any ground bounce generated by high voltage switching
to disturb the logic circuits.
Ensure that logic VSS and high voltage VGND are at the same potential.
Wafer thickness : 19mil
Height of Bump : within lot 18m ± 3µm
within wafer < 4µm
within die < 2µm
(0,0) PAD
234
PAD
1
PAD
165
PAD
152
PAD152
PAD234
PAD 1
EK7011
Chi
p
Size:9303.6um x 1173 um
EM7011 EUREKA
PAD165
EUREKA EK7011CG
28 Rev 1.3 Feb.22.2001
PAD No. Bump
size Pad Name
X-
coordi nat
e
Y-
coordi nat
e
Pad Size ( um )
PAD1 72.8X72.8 Y005 4545 480 85.2 X 85.2
PAD2 42.8X72.8 Y006 4470 480 55.2 X 85.2
PAD3 42.8X72.8 Y007 4410 480 55.2 X 85.2
PAD4 42.8X72.8 Y008 4350 480 55.2 X 85.2
PAD5 42.8X72.8 Y009 4290 480 55.2 X 85.2
PAD6 42.8X72.8 Y010 4230 480 55.2 X 85.2
PAD7 42.8X72.8 Y011 4170 480 55.2 X 85.2
PAD8 42.8X72.8 Y012 4110 480 55.2 X 85.2
PAD9 42.8X72.8 Y013 4050 480 55.2 X 85.2
PAD10 42.8X72.8 Y014 3990 480 55.2 X 85.2
PAD11 42.8X72.8 Y015 3930 480 55.2 X 85.2
PAD12 42.8X72.8 Y016 3870 480 55.2 X 85.2
PAD13 42.8X72.8 Y017 3810 480 55.2 X 85.2
PAD14 42.8X72.8 Y018 3750 480 55.2 X 85.2
PAD15 42.8X72.8 Y019 3690 480 55.2 X 85.2
PAD16 42.8X72.8 Y020 3630 480 55.2 X 85.2
PAD17 42.8X72.8 Y021 3570 480 55.2 X 85.2
PAD18 42.8X72.8 Y022 3510 480 55.2 X 85.2
PAD19 42.8X72.8 Y023 3450 480 55.2 X 85.2
PAD20 42.8X72.8 Y024 3390 480 55.2 X 85.2
PAD21 42.8X72.8 Y025 3330 480 55.2 X 85.2
PAD22 42.8X72.8 Y026 3270 480 55.2 X 85.2
PAD23 42.8X72.8 Y027 3210 480 55.2 X 85.2
PAD24 42.8X72.8 Y028 3150 480 55.2 X 85.2
PAD25 42.8X72.8 Y029 3090 480 55.2 X 85.2
PAD26 42.8X72.8 Y030 3030 480 55.2 X 85.2
PAD27 42.8X72.8 Y031 2970 480 55.2 X 85.2
PAD28 42.8X72.8 Y032 2910 480 55.2 X 85.2
PAD29 42.8X72.8 Y033 2850 480 55.2 X 85.2
PAD30 42.8X72.8 Y034 2790 480 55.2 X 85.2
PAD31 42.8X72.8 Y035 2730 480 55.2 X 85.2
PAD32 42.8X72.8 Y036 2670 480 55.2 X 85.2
PAD33 42.8X72.8 Y037 2610 480 55.2 X 85.2
PAD34 42.8X72.8 Y038 2550 480 55.2 X 85.2
PAD35 42.8X72.8 Y039 2490 480 55.2 X 85.2
EUREKA EK7011CG
29 Rev 1.3 Feb.22.2001
PAD No. Bump
size Pad Name
X-
coordi nat
e
Y-
coordi nat
e
Pad Size ( um )
PAD36 42.8X72.8 Y040 2430 480 55.2 X 85.2
PAD37 42.8X72.8 Y041 2370 480 55.2 X 85.2
PAD38 42.8X72.8 Y042 2310 480 55.2 X 85.2
PAD39 42.8X72.8 Y043 2250 480 55.2 X 85.2
PAD40 42.8X72.8 Y044 2190 480 55.2 X 85.2
PAD41 42.8X72.8 Y045 2130 480 55.2 X 85.2
PAD42 42.8X72.8 Y046 2070 480 55.2 X 85.2
PAD43 42.8X72.8 Y047 2010 480 55.2 X 85.2
PAD44 42.8X72.8 Y048 1950 480 55.2 X 85.2
PAD45 42.8X72.8 Y049 1890 480 55.2 X 85.2
PAD46 42.8X72.8 Y050 1830 480 55.2 X 85.2
PAD47 42.8X72.8 Y051 1770 480 55.2 X 85.2
PAD48 42.8X72.8 Y052 1710 480 55.2 X 85.2
PAD49 42.8X72.8 Y053 1650 480 55.2 X 85.2
PAD50 42.8X72.8 Y054 1590 480 55.2 X 85.2
PAD51 42.8X72.8 Y055 1530 480 55.2 X 85.2
PAD52 42.8X72.8 Y056 1470 480 55.2 X 85.2
PAD53 42.8X72.8 Y057 1410 480 55.2 X 85.2
PAD54 42.8X72.8 Y058 1350 480 55.2 X 85.2
PAD55 42.8X72.8 Y059 1290 480 55.2 X 85.2
PAD56 42.8X72.8 Y060 1230 480 55.2 X 85.2
PAD57 42.8X72.8 Y061 1170 480 55.2 X 85.2
PAD58 42.8X72.8 Y062 1110 480 55.2 X 85.2
PAD59 42.8X72.8 Y063 1050 480 55.2 X 85.2
PAD60 42.8X72.8 Y064 990 480 55.2 X 85.2
PAD61 42.8X72.8 Y065 930 480 55.2 X 85.2
PAD62 42.8X72.8 Y066 870 480 55.2 X 85.2
PAD63 42.8X72.8 Y067 810 480 55.2 X 85.2
PAD64 42.8X72.8 Y068 750 480 55.2 X 85.2
PAD65 42.8X72.8 Y069 690 480 55.2 X 85.2
PAD66 42.8X72.8 Y070 630 480 55.2 X 85.2
PAD67 42.8X72.8 Y071 570 480 55.2 X 85.2
PAD68 42.8X72.8 Y072 510 480 55.2 X 85.2
PAD69 42.8X72.8 Y073 450 480 55.2 X 85.2
PAD70 42.8X72.8 Y074 390 480 55.2 X 85.2
EUREKA EK7011CG
30 Rev 1.3 Feb.22.2001
PAD No. Bump
size Pad Name
X-
coordi nat
e
Y-
coordi nat
e
Pad Size ( um )
PAD71 42.8X72.8 Y075 330 480 55.2 X 85.2
PAD72 42.8X72.8 Y076 270 480 55.2 X 85.2
PAD73 42.8X72.8 Y077 210 480 55.2 X 85.2
PAD74 42.8X72.8 Y078 150 480 55.2 X 85.2
PAD75 42.8X72.8 Y079 90 480 55.2 X 85.2
PAD76 42.8X72.8 Y080 30 480 55.2 X 85.2
PAD77 42.8X72.8 Y081 -30 480 55.2 X 85.2
PAD78 42.8X72.8 Y082 -90 480 55.2 X 85.2
PAD79 42.8X72.8 Y083 -150 480 55.2 X 85.2
PAD80 42.8X72.8 Y084 -210 480 55.2 X 85.2
PAD81 42.8X72.8 Y085 -270 480 55.2 X 85.2
PAD82 42.8X72.8 Y086 -330 480 55.2 X 85.2
PAD83 42.8X72.8 Y087 -390 480 55.2 X 85.2
PAD84 42.8X72.8 Y088 -450 480 55.2 X 85.2
PAD85 42.8X72.8 Y089 -510 480 55.2 X 85.2
PAD86 42.8X72.8 Y090 -570 480 55.2 X 85.2
PAD87 42.8X72.8 Y091 -630 480 55.2 X 85.2
PAD88 42.8X72.8 Y092 -690 480 55.2 X 85.2
PAD89 42.8X72.8 Y093 -750 480 55.2 X 85.2
PAD90 42.8X72.8 Y094 -810 480 55.2 X 85.2
PAD91 42.8X72.8 Y095 -870 480 55.2 X 85.2
PAD92 42.8X72.8 Y096 -930 480 55.2 X 85.2
PAD93 42.8X72.8 Y097 -990 480 55.2 X 85.2
PAD94 42.8X72.8 Y098 -1050 480 55.2 X 85.2
PAD95 42.8X72.8 Y099 -1110 480 55.2 X 85.2
PAD96 42.8X72.8 Y100 -1170 480 55.2 X 85.2
PAD97 42.8X72.8 Y101 -1230 480 55.2 X 85.2
PAD98 42.8X72.8 Y102 -1290 480 55.2 X 85.2
PAD99 42.8X72.8 Y103 -1350 480 55.2 X 85.2
PAD100 42.8X72.8 Y104 -1410 480 55.2 X 85.2
PAD101 42.8X72.8 Y105 -1470 480 55.2 X 85.2
PAD102 42.8X72.8 Y106 -1530 480 55.2 X 85.2
PAD103 42.8X72.8 Y107 -1590 480 55.2 X 85.2
PAD104 42.8X72.8 Y108 -1650 480 55.2 X 85.2
PAD105 42.8X72.8 Y109 -1710 480 55.2 X 85.2
EUREKA EK7011CG
31 Rev 1.3 Feb.22.2001
PAD No. Bump
size Pad Name
X-
coordi nat
e
Y-
coordi nat
e
Pad Size ( um )
PAD106 42.8X72.8 Y110 -1770 480 55.2 X 85.2
PAD107 42.8X72.8 Y111 -1830 480 55.2 X 85.2
PAD108 42.8X72.8 Y112 -1890 480 55.2 X 85.2
PAD109 42.8X72.8 Y113 -1950 480 55.2 X 85.2
PAD110 42.8X72.8 Y114 -2010 480 55.2 X 85.2
PAD111 42.8X72.8 Y115 -2070 480 55.2 X 85.2
PAD112 42.8X72.8 Y116 -2130 480 55.2 X 85.2
PAD113 42.8X72.8 Y117 -2190 480 55.2 X 85.2
PAD114 42.8X72.8 Y118 -2250 480 55.2 X 85.2
PAD115 42.8X72.8 Y119 -2310 480 55.2 X 85.2
PAD116 42.8X72.8 Y120 -2370 480 55.2 X 85.2
PAD117 42.8X72.8 Y121 -2430 480 55.2 X 85.2
PAD118 42.8X72.8 Y122 -2490 480 55.2 X 85.2
PAD119 42.8X72.8 Y123 -2550 480 55.2 X 85.2
PAD120 42.8X72.8 Y124 -2610 480 55.2 X 85.2
PAD121 42.8X72.8 Y125 -2670 480 55.2 X 85.2
PAD122 42.8X72.8 Y126 -2730 480 55.2 X 85.2
PAD123 42.8X72.8 Y127 -2790 480 55.2 X 85.2
PAD124 42.8X72.8 Y128 -2850 480 55.2 X 85.2
PAD125 42.8X72.8 Y129 -2910 480 55.2 X 85.2
PAD126 42.8X72.8 Y130 -2970 480 55.2 X 85.2
PAD127 42.8X72.8 Y131 -3030 480 55.2 X 85.2
PAD128 42.8X72.8 Y132 -3090 480 55.2 X 85.2
PAD129 42.8X72.8 Y133 -3150 480 55.2 X 85.2
PAD130 42.8X72.8 Y134 -3210 480 55.2 X 85.2
PAD131 42.8X72.8 Y135 -3270 480 55.2 X 85.2
PAD132 42.8X72.8 Y136 -3330 480 55.2 X 85.2
PAD133 42.8X72.8 Y137 -3390 480 55.2 X 85.2
PAD134 42.8X72.8 Y138 -3450 480 55.2 X 85.2
PAD135 42.8X72.8 Y139 -3510 480 55.2 X 85.2
PAD136 42.8X72.8 Y140 -3570 480 55.2 X 85.2
PAD137 42.8X72.8 Y141 -3630 480 55.2 X 85.2
PAD138 42.8X72.8 Y142 -3690 480 55.2 X 85.2
PAD139 42.8X72.8 Y143 -3750 480 55.2 X 85.2
PAD140 42.8X72.8 Y144 -3810 480 55.2 X 85.2
EUREKA EK7011CG
32 Rev 1.3 Feb.22.2001
PAD No. Bump
size Pad Name
X-
coordi nat
e
Y-
coordi nat
e
Pad Size ( um )
PAD141 42.8X72.8 Y145 -3870 480 55.2 X 85.2
PAD142 42.8X72.8 Y146 -3930 480 55.2 X 85.2
PAD143 42.8X72.8 Y147 -3990 480 55.2 X 85.2
PAD144 42.8X72.8 Y148 -4050 480 55.2 X 85.2
PAD145 42.8X72.8 Y149 -4110 480 55.2 X 85.2
PAD146 42.8X72.8 Y150 -4170 480 55.2 X 85.2
PAD147 42.8X72.8 Y151 -4230 480 55.2 X 85.2
PAD148 42.8X72.8 Y152 -4290 480 55.2 X 85.2
PAD149 42.8X72.8 Y153 -4350 480 55.2 X 85.2
PAD150 42.8X72.8 Y154 -4410 480 55.2 X 85.2
PAD151 42.8X72.8 Y155 -4470 480 55.2 X 85.2
PAD152 72.8X72.8 Y156 -4545 480 85.2 X 85.2
PAD153 42.8X72.8 Y157 -4545 330 55.2 X 85.2
PAD154 42.8X72.8 Y158 -4545 270 55.2 X 85.2
PAD155 42.8X72.8 Y159 -4545 210 55.2 X 85.2
PAD156 42.8X72.8 Y160 -4545 150 55.2 X 85.2
PAD157 42.8X72.8 V0 -4545 90 55.2 X 85.2
PAD158 42.8X72.8 V12 -4545 30 55.2 X 85.2
PAD159 42.8X72.8 V43 -4545 -30 55.2 X 85.2
PAD160 42.8X72.8 VGND -4545 -90 55.2 X 85.2
PAD161 42.8X72.8 Dumm
y
-4545 -150 55.2 X 85.2
PAD162 42.8X72.8 Dumm
y
-4545 -210 55.2 X 85.2
PAD163 42.8X72.8 Dumm
y
-4545 -270 55.2 X 85.2
PAD164 42.8X72.8 Dumm
y
-4545 -330 55.2 X 85.2
PAD165 72.8X72.8 VGND -4545 -480 85.2 X 85.2
PAD166 42.8X72.8 VSS -4470 -480 55.2 X 85.2
PAD167 42.8X72.8 Dumm
y
-4410 -480 55.2 X 85.2
PAD168 42.8X72.8 Dumm
y
-4350 -480 55.2 X 85.2
PAD169 42.8X72.8 LR -4230 -480 55.2 X 85.2
PAD170 42.8X72.8 Dumm
y
-4110 -480 55.2 X 85.2
PAD171 42.8X72.8 Dumm
y
-4050 -480 55.2 X 85.2
PAD172 42.8X72.8 Dumm
y
-3870 -480 55.2 X 85.2
PAD173 42.8X72.8 vdd:P -3810 -480 55.2 X 85.2
PAD174 42.8X72.8 vdd:P -3750 -480 55.2 X 85.2
PAD175 42.8X72.8 vdd:P -3690 -480 55.2 X 85.2
EUREKA EK7011CG
33 Rev 1.3 Feb.22.2001
PAD No. Bump
size Pad Name
X-
coordi nat
e
Y-
coordi nat
e
Pad Size ( um )
PAD176 42.8X72.8 Dumm
y
-3630 -480 55.2 X 85.2
PAD177 42.8X72.8 Dumm
y
-3450 -480 55.2 X 85.2
PAD178 42.8X72.8 SC -3330 -480 55.2 X 85.2
PAD179 42.8X72.8 Dumm
y
-3210 -480 55.2 X 85.2
PAD180 42.8X72.8 Dumm
y
-3030 -480 55.2 X 85.2
PAD181 42.8X72.8 EIO_2 -2910 -480 55.2 X 85.2
PAD182 42.8X72.8 Dumm
y
-2790 -480 55.2 X 85.2
PAD183 42.8X72.8 Dumm
y
-2610 -480 55.2 X 85.2
PAD184 42.8X72.8 D0 -2490 -480 55.2 X 85.2
PAD185 42.8X72.8 Dumm
y
-2370 -480 55.2 X 85.2
PAD186 42.8X72.8 Dumm
y
-2190 -480 55.2 X 85.2
PAD187 42.8X72.8 D1 -2070 -480 55.2 X 85.2
PAD188 42.8X72.8 Dumm
y
-1950 -480 55.2 X 85.2
PAD189 42.8X72.8 Dumm
y
-1770 -480 55.2 X 85.2
PAD190 42.8X72.8 D2 -1650 -480 55.2 X 85.2
PAD191 42.8X72.8 Dumm
y
-1530 -480 55.2 X 85.2
PAD192 42.8X72.8 Dumm
y
-1230 -480 55.2 X 85.2
PAD193 42.8X72.8 Dumm
y
-930 -480 55.2 X 85.2
PAD194 42.8X72.8 D3 -810 -480 55.2 X 85.2
PAD195 42.8X72.8 Dumm
y
-690 -480 55.2 X 85.2
PAD196 42.8X72.8 Dumm
y
-510 -480 55.2 X 85.2
PAD197 42.8X72.8 D4 -390 -480 55.2 X 85.2
PAD198 42.8X72.8 Dumm
y
-270 -480 55.2 X 85.2
PAD199 42.8X72.8 Dumm
y
-90 -480 55.2 X 85.2
PAD200 42.8X72.8 D5 30 -480 55.2 X 85.2
PAD201 42.8X72.8 Dumm
y
150 -480 55.2 X 85.2
PAD202 42.8X72.8 Dumm
y
330 -480 55.2 X 85.2
PAD203 42.8X72.8 D6 450 -480 55.2 X 85.2
PAD204 42.8X72.8 Dumm
y
570 -480 55.2 X 85.2
PAD205 42.8X72.8 Dumm
y
750 -480 55.2 X 85.2
PAD206 42.8X72.8 D7 870 -480 55.2 X 85.2
PAD207 42.8X72.8 Dumm
y
990 -480 55.2 X 85.2
PAD208 42.8X72.8 Dumm
y
1170 -480 55.2 X 85.2
PAD209 42.8X72.8 CK 1290 -480 55.2 X 85.2
PAD210 42.8X72.8 Dummy 1410 -480 55.2 X 85.2
EUREKA EK7011CG
34 Rev 1.3 Feb.22.2001
PAD No. Bump
size Pad Name
X-
coordi nat
e
Y-
coordi nat
e
Pad Size ( um )
PAD211 42.8X72.8 Dumm
y
1590 -480 55.2 X 85.2
PAD212 42.8X72.8 DISPOFF 1710 -480 55.2 X 85.2
PAD213 42.8X72.8 Dumm
y
1830 -480 55.2 X 85.2
PAD214 42.8X72.8 Dumm
y
2010 -480 55.2 X 85.2
PAD215 42.8X72.8 PLP 2130 -480 55.2 X 85.2
PAD216 42.8X72.8 Dumm
y
2250 -480 55.2 X 85.2
PAD217 42.8X72.8 Dumm
y
2430 -480 55.2 X 85.2
PAD218 42.8X72.8 EIO_1 2550 -480 55.2 X 85.2
PAD219 42.8X72.8 Dumm
y
2670 -480 55.2 X 85.2
PAD220 42.8X72.8 Dumm
y
2850 -480 55.2 X 85.2
PAD221 42.8X72.8 PFR 2970 -480 55.2 X 85.2
PAD222 42.8X72.8 Dumm
y
3090 -480 55.2 X 85.2
PAD223 42.8X72.8 Dumm
y
3270 -480 55.2 X 85.2
PAD224 42.8X72.8 PMD 3390 -480 55.2 X 85.2
PAD225 42.8X72.8 Dumm
y
3510 -480 55.2 X 85.2
PAD226 42.8X72.8 Dumm
y
3690 -480 55.2 X 85.2
PAD227 42.8X72.8 T1 3810 -480 55.2 X 85.2
PAD228 42.8X72.8 Dumm
y
3930 -480 55.2 X 85.2
PAD229 42.8X72.8 Dumm
y
4110 -480 55.2 X 85.2
PAD230 42.8X72.8 T2 4230 -480 55.2 X 85.2
PAD231 42.8X72.8 Dumm
y
4350 -480 55.2 X 85.2
PAD232 42.8X72.8 Dumm
y
4410 -480 55.2 X 85.2
PAD233 42.8X72.8 VSS 4470 -480 55.2 X 85.2
PAD234 72.8X72.8 VGND 4545 -480 85.2 X 85.2
PAD235 42.8X72.8 Dumm
y
4545 -330 55.2 X 85.2
PAD236 42.8X72.8 Dumm
y
4545 -270 55.2 X 85.2
PAD237 42.8X72.8 Dumm
y
4545 -210 55.2 X 85.2
PAD238 42.8X72.8 Dumm
y
4545 -150 55.2 X 85.2
PAD239 42.8X72.8 VGND 4545 -90 55.2 X 85.2
PAD240 42.8X72.8 V43 4545 -30 55.2 X 85.2
PAD241 42.8X72.8 V12 4545 30 55.2 X 85.2
PAD242 42.8X72.8 V0 4545 90 55.2 X 85.2
PAD243 42.8X72.8 Y001 4545 150 55.2 X 85.2
PAD244 42.8X72.8 Y002 4545 210 55.2 X 85.2
PAD245 42.8X72.8 Y003 4545 270 55.2 X 85.2
PAD246 42.8X72.8 Y004 4545 330 55.2 X 85.2
