PDU138
Doc #02004 DATA DELAY DEVICES, INC. 1
5/6/02 3 Mt. Prospect Ave. Clifton, NJ 07013
3-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU138)
FEATURES PACKAGES
• Digitally programmable in 8 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully TTL interfaced & buffered
• 10 T2L fan-out capability
• Fits standard 16-pin DIP socket
• Auto-insertable
FUNCTIONAL DESCRIPTION
The PDU138-series device is a 3-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on
the address code (A2-A0) according to the following formula:
TDA = TD0 + TINC * A
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (EN/) is held LOW during normal
operation. When this signal is brought HIGH, OUT is forced into the LOW
state. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD0): 7ns typical (OUT)
• Setup time and propagation delay:
Address to input setup (TAIS): 12ns typ.
Disable to output delay (TDISO): 12ns typ.
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VCC: 5VDC ± 5%
• Supply current: ICCH = 45ma
ICCL = 20ma
• Minimum pulse width: 20% of total delay
2002 Data Delay Devices
data
delay
devices, inc.
3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
N/C
N/C
N/C
IN
OUT
N/C
EN/
GND
VCC
N/C
N/C
N/C
N/C
A0
A1
A2
PDU138-xx DIP
PDU138-xxM Military DIP
PIN DESCRIPTIONS
IN Delay Line Input
OUT Non-inverted Output
A2 Address Bit 2
A1 Address Bit 1
A0 Address Bit 0
EN/ Output Enable
VCC +5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number Incremental Delay
Per Step (ns) Total Delay
Change (ns)
PDU138-.5 .5 ± .3 3.5 ± 1.0
PDU138-1 1 ± .4 7 ± 1.0
PDU138-2 2 ± .4 14 ± 1.0
PDU138-5 5 ± .6 35 ± 1.8
PDU138-10 10 ± 1.0 70 ± 3.5
PDU138-12 12 ± 1.2 84 ± 4.2
PDU138-15 15 ± 1.3 105 ± 5.3
PDU138-20 20 ± 1.5 140 ± 7.0
PDU138-40 40 ± 2.0 280 ± 14.0
PDU138-50 50 ± 2.5 350 ± 17.5
NOTE: Any dash number between .5 and 50 not
shown is also available.
PDU138
Doc #02004 DATA DELAY DEVICES, INC. 2
5/6/02 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
ADDRESS UPDATE
The PDU138 is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, TOAX,
is required before the address lines can change.
This time is given by the following relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT pin.
The possibility of spurious signals persists until
the required TOAX has elapsed.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and the
IN signal low for a time given by:
TDISH = Ai * TINC
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
spurious signals persists until the required TDISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay tolerance
specifications and monotonicity are guaranteed.
The suggested conditions are those for which
signals will propagate through the unit without
significant distortion. The absolute conditions
are those for which the unit will produce some
type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will remain
constant from pulse to pulse if the input pulse
width and period remain fixed. In other words,
the delay of the unit exhibits frequency and pulse
width dependence when operated beyond the
recommended conditions. Please consult the
technical staff at Data Delay Devices if your
application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
TDISO
TOAX
TAENS
TENIS PWIN
TDAPWOU
TDISH
A2-A0
EN/
IN
OUT
Figure 1: Timing Diagram
A i-1 Ai
TAIS
PDU138
Doc #02004 DATA DELAY DEVICES, INC. 3
5/6/02 3 Mt. Prospect Ave. Clifton, NJ 07013
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER SYMBOL MIN TYP UNITS
Total Programmable Delay TDT7TINC
Inherent Delay TD07.0 ns
Disable to Output Low Delay TDISO 12.0 ns
Address to Enable Setup Time TAENS 2.0 ns
Address to Input Setup Time TAIS 12.0 ns
Enable to Input Setup Time TENIS 12.0 ns
Output to Address Change TOAX See Text
Disable Hold Time TDISH See Text
Absolute PERIN 20 % of TDT
Input Period Suggested PERIN 50 % of TDT
Recommended PERIN 200 % of TDT
Absolute PWIN 10 % of TDT
Input Pulse Width Suggested PWIN 25 % of TDT
Recommended PWIN 100 % of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage VCC -0.3 7.0 V
Input Pin Voltage VIN -0.3 VDD+0.3 V
Storage Temperature TSTRG -55 150 C
Lead Temperature TLEAD 300 C10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
High Level Output Voltage VOH 2.5 3.4 V VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX
Low Level Output Voltage VOL 0.35 0.5 V VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX
High Level Output Current IOH -1.0 mA
Low Level Output Current IOL 20.0 mA
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
Input Clamp Voltage VIK -1.2 V VCC = MIN, II = IIK
Input Current at Maximum
Input Voltage IIHH 0.1 mA VCC = MAX, VI = 7.0V
High Level Input Current IIH 20 µAVCC = MAX, VI = 2.7V
Low Level Input Current IIL -0.6 mA VCC = MAX, VI = 0.5V
Short-circuit Output Current IOS -60 -150 mA VCC = MAX
Output High Fan-out 25 Unit
Output Low Fan-out 12.5 Load
PDU138
Doc #02004 DATA DELAY DEVICES, INC. 4
5/6/02 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PACKAGE DIMENSIONS
.150
±.030
.820 MAX
4 5 7
1016 11
.280
MAX
.018 TYP
.410
MAX
.300
TYP
.012 TYP
.700 TYP
.020
TYP
.100
TYP
Commercial DIP (PDU138-xx)
8
9
.150
±.030
.820 MAX
4 5 7
1016 11
.320
MAX
.018 TYP
.410
MAX
.300
TYP
.012 TYP
.700 TYP
.020
TYP
.100
TYP
Military DIP (PDU138-xxM)
8
9
PDU138
Doc #02004 DATA DELAY DEVICES, INC. 5
5/6/02 3 Mt. Prospect Ave. Clifton, NJ 07013
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oCLoad: 1 FAST-TTL Gate
Supply Voltage (Vcc): 5.0V ± 0.1V Cload:5pf ± 10%
Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise/Fall Time: 3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width: PWIN = 1.5 x Total Delay
Period: PERIN = 4.5 x Total Delay
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
OUTOUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT) TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
Timing Diagram For Testing
TDAR TDAF
PERIN
PWIN
TRISE TFALL
0.6V0.6V 1.5V1.5V
2.4V 2.4V
1.5V1.5V
VIH VIL
VOH VOL
INPUT
SIGNAL
OUTPUT
SIGNAL
