This is information on a product in full production. For further information contact your local STMicroelectronics sales
office.
September 2013 Doc ID 14095 Rev 4 1/14
1
STA8058
TESEO™
high performance GPS multichip module (MCM)
Data brief production data
Features
■GPS multichip module:
– STA2058 TESEO Baseband
– STA5620 RF Front-end
■Complete embedded memory system:
– Flash 256 KB + 16 Kbytes
– RAM 64 Kbytes.
■66-MHz ARM7TDMI 32 bit processor
■High performance GPS engine (HPGPS)
■SBAS (WAAS and EGNOS) supported
■Sensitivity (-146 dBm acquisition, -159 dBm
tracking)
■Time to first fix (1 s reacquisition, 2.5 s hot start,
34 s warm start, 39 s cold start)
■Accuracy (2 m autonomous)
■Extensive GPS receiver interfaces: 32 GPIOs,
4 UARTs, 2 SPIs, 2 I2Cs, 1 CAN 2.0,
1 USB 1.1, 1 HDLC and 4 channels ADC
■Compatible with L1 signal (C/A code)
■ST proprietary technology
– CMOS Flash embebbed technology for
STA2058
– BiCMOS Sige technology for STA5620
■LFBGA104 lead-free package
■-40 °C to 85 °C operating temperature range
■Evaluation kits:
– STA8058 module reference designs
(17x19 mm and 25x25 mm)
– Evaluation board hosting STA8058 module
Description
STA8058 TESEO MCM is a fully embedded GPS
engine integrating STA2058 TESEO baseband.
and STA5620 RF front-end. The embedded Flash
memory enables the equipment manufacturer to
load the entire GPS software (including tracking,
acquisition, navigation and data output) after
customising its interfaces to his needs.
A standard GPS library is available from ST. By
combining the ARM7TDMI microcontroller core
with on-chip Flash/RAM, 16-channel GPS
correlator DSP, RF Front-end and an extensive
range of interfaces on single package solution,
the STA8058 provides a highly-flexible and cost-
effective solution for GPS applications.
LFBGA104 (7x11x1.4 mm)
Table 1. Device summary
Order code Package Packing Automotive grade CAN
STA8058 LFBGA104 (7 x 11 x 1.4 mm) Tray No No
STA8058TR LFBGA104 (7 x 11 x 1.4 mm) Tape and reel No No
STA8058A LFBGA104 (7 x 11 x 1.4 mm) Tray Yes Yes
STA8058ATR LFBGA104 (7 x 11 x 1.4 mm) Tape and reel Yes Yes
www.st.com
Contents STA8058
2/14 Doc ID 14095 Rev 4
Contents
1 Features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 LFBGA104 ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STA8058 Features summary
Doc ID 14095 Rev 4 3/14
1 Features summary
●ARM7TDMI 16/32 bit RISC CPU based host microcontroller running at a frequency up
to 66 MHz.
●Complete Embedded Memory System:
– Flash 256 Kbytes + 16 Kbytes (100 KB erasing/programming cycles)
– RAM 64 Kbytes.
●16 channel High performance GPS correlation DSP.
●ST propietary technology:
– CMOS Flash embedded technology for baseband
– BiCMOS Sige for radio front-end
●SBAS (WAAS and EGNOS) supported.
●-40 °C to 85 °C operating temperature range.
●104-pin LFBGA104 package.
●Power supply:
– 3.0 V to 3.6 V operating supply range for input/output periphery
– 3.0 V to 3.6 V operating supply range for A/D converter reference
– 1.8 V operating supply range for core supply provided by internal voltage regulator
with external stabilization capacitor or by external supply voltage
– 2.4 V to 3 V operating supply range for RF front-end section
●Reset and clock control unit able to provide low power modes (WAIT, SLOW, STOP,
Standby) and to generate the internal clock from the external reference through
integrated PLL.
●32 programmable general purpose I/O, each pin programmable independently as
digital input or digital output; 30 are multiplexed with peripheral functions; 16 can
generate an interrupt on input level/transition.
●Real time clock module with 32 kHz low power oscillator and separate power supply to
continue running during stand-by mode.
●16-bit Watchdog timer with 8 bits prescaler for system reliability and integrity.
●One CAN module compliant with the CAN specification V2.0 part B (active) and bit rate
can be programmed up to 1 MBaud.
●Four 16-bit programmable timers with 7 bit prescaler, up to two input capture/output
compare, one pulse counter function, one PWM channel with selectable frequency
each.
●4 channels 12-bit sigma-delta analog to digital converter, single channel or multi
channel conversion modes, single-shot or continuous conversion modes, sample rate
1 kHz, conversion range 0-2.5V .
●Three serial communication interfaces (UART) allow full duplex, asynchronous,
communications with external devices, independently programmable TX and RX baud
rates up to 625K baud.
●One UART adapted to suit smart card interface needs, for asynchronous SC as defined
by ISO 7816-3. It includes SC clock generation.
●Two serial peripheral interfaces (SPI) allow full duplex, synchronous communications
with external devices, master or slave operation, max baud rate of 5.5Mb/s. One SPI
may be used as multimedia card interface.
Features summary STA8058
4/14 Doc ID 14095 Rev 4
●Two I2C interfaces provide multi-master and slave functions, support normal and fast
I2C mode (400 KHz), 7/10 bit addressing modes. One I2C Interface is multiplexed with
one SPI, so either 2 x SPI + 1 x I2C or 1 x SPI + 2 x I2C may be used at a time.
●Enhanced interrupt controller supports 32 interrupt vectors, independently maskable,
with interrupt vector table for faster response and 16 priority levels, software
programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ.
●Wake-up unit allows exiting from powerdown modes by detection of an event on two
external pins (one is active high and other is active low) or on internal Real Time Clock
alarm.
●USB unit V1.1 compliant, software configurable endpoint setting, USB suspend/resume
support
●High level data link controller (HDLC) unit supports full duplex operating mode, NRZ,
NRZI, FM0 and MANCHESTER modes, and internal 8-bit Baud Rate Generator.
●RF front-end features:
– LOW IF (4 MHz) architecture
– Compatible with GPS L1 signal
– VGA gain internally regulated
– On chip programmable PLL
– SPI interface
STA8058 Pin description
Doc ID 14095 Rev 4 5/14
2 Pin description
2.1 Logic symbol
Figure 1. STA8058 TESEO MCM symbol
AVSS
CK
SPI (DI,DO,CS, CLK)
JTDI
JTDO
JTCK
JTMS
RSTINn
JTRSTn
RF_IN
BOOTEN
V18BKP
V18 [2]
V33 [7]
V27 [8]
Xtal (IN,Out,Clk)
AVDD
Power
Clock
& Reset
JTAG
Port
TESEO
GPSCLK
GPSDAT
Pads
VSS [10]
VSSRF [11]
RF Pads
Sign
GPS_CLK
Enable (Chip,RF)
Mode
IF_TEST
AGC_CNTR
P0.[15:0]
P1.[15:0]
RTCXTI
RTCXTO
USBDP
USBDN
WAKEUP
GeneraI
Purpose I/O
RTC
USB Pads
& WKUP
Pads
nSTDBY_I
MCM
Pin description STA8058
6/14 Doc ID 14095 Rev 4
2.2 System block diagram
Figure 2. STA8058 TESEO baseband block diagram
$0
$0
!&
$0
!&
)/
!&
$0
!&
!&
!&
!&
$0
!&
!&
!&
$0
!&
!&
!&
!&
!&
$0
!&
!2-4$-)
#05
+
&LASH
+
2!-
34#
*4!'
62%'
2##5
0,,
)NTERRUPT
#ONTR
BIT
!$#
4)-%2
4)-%2
4)-%2
4)-%2
24#
/3#),,
7AKEUP
7!4#(
$/'
&ULLY0ROG
)/0/243
!0'
"2)$'%
!0'
"2)$'%
!0'
"2)$'%
(0'03CH
CORRELATOR
%MARALD$30
)#
)#
30)
30)
5!24
5!24
5!24
5!24
;53"=
;#!.=
($,#
!2-.ATIVE"53
!0""53
!0""53
/NLYFOR34!!AND34!!42
'!0'#&4
STA8058 Pin description
Doc ID 14095 Rev 4 7/14
Figure 3. STA5620 RF front-end
SPI
Interface
CP CMOS Drivers
2
bi ts
Combine
r
RF
A
Buffer
X
tal Osc
PFD
/
N
IR Mixer
Pol yphase
Filter
IF filt er
GPS_CL
K
/ 48
0˚
90˚
XTAL_CL
K
RF_EN
A
GC_CTRL
RF_IN
MAG
SIGN
/ 2
/
R
SPI_C
S
/
SPI_CLK
SPI_DI
SPI_D
MODE
si gn
mag
gp s_clk
<chi p conf ig>
gc e
xc
e
A
D
C
X
I
X
O
TEST_EN2
hc e
lo48_clk gps_clk
sample_mode (1:0)
LO96
Variable Xtal
gc e & rf e
enabl ed by rfe & sp eci fic enables
Reset
Generat or
reset
IF_TES
T
TEST_EN1
test _clk
s
ign
mag
A
GC
if_out _en
CHIP_EN
xt al _clk xt al_clk
mag
Test
Logi c
TEST_CLK
Pin description STA8058
8/14 Doc ID 14095 Rev 4
Figure 4. STA8058 TESEO MCM block diagram
2&?).
3IGN '03?$AT
#()0?%.
3!7&ILTER
!'#?#.42
2&?%.
6?2&;=
,.!
*4$)*4#+*4-3*4234N*4$/
34!4ESEO-#-
34!
2&&RONT%ND
34!
"ASEBAND
30)?$)
30)?$/
30)?#,+
3?-/3)
3?-)3/
3?3#,+
'03?#,+
#+
84!,?).
-/$%
)&?4%34
6?0,,;=
6332&;=
7AKE?5P
24#84/
24#84)
4IMERS;=!$#;=
4HETWODICEMUSTBEINTERCONNECTEDEACHOTHERATBOARDLEVE
L
30);=)#;=5!243;=
0003
.234).
002.
"//4"//4"//4%.
.34$"9?).
6;= 6;= 633;=
6)/?0,,
6?2%'?"+0
!6$$ 6"+0
633;=
!633
633?"+0
633?2%'
633)/?0,,
84!,?#,+
'03#,+
'0)/
'0)/
6332&?!;=
6332&?)/
4#8/
6
3?33.
30)?#3
53";=#!.;=

($,#;=

/NLYFOR34!!AND34!!42
("1($'5
STA8058 Pin description
Doc ID 14095 Rev 4 9/14
2.3 LFBGA104 ball out
2.4 Power supply pins
Table 2. Ball out for LFBGA104 package
1234 567 8910111213
AVSS AVSS AVDD V18BKP RTCXTO RTCXTI V33REG_BKP GPSDAT nJTRST RF_EN XTAL_OUT XTAL_IN VSSRF
B
P1.2/
T3_OCMPA/
AIN.2
VSS18 V18 VSSBKP NSTDBY_IN V33 VSSREG GPSCLK GPS_CLK CHIP_EN V27PLL V27PLL V27PLL
C
P1.1/
T3_ICAPA/
AIN.1
P1.0/
T3_OCMPB/
AIN.0
P1.4/
T1_ICAPA
P1.5/
T1_ICAPB NRSTIN PO.15/
WAKEUP CK P0.5/
S1_MOSI SPI_DI XTAL_CLK VSSRF V27PLL V27RF
DV33IO_PLL
P1.3/
T3_ICAPB/
AIN.3
P1.7/
T1_OCMPA VSS VSS JTCK JTDO P0.6/S1_SCLK SPI_CLK MODE VSSRF VSSRF VSSRF_A
EVSSIO_PLL P1.8/PPS P1.9/
PRN.11
P1.6/
T1_OCMPB VSS18
P0.13/
U2_RX/
T2.OCMPA
JTMS JTDI SPI_CS IF_TEST VSSRF VSSRF RF_IN
FP1.11/
CANRX(1) USBDP P1.10/
USBCLK
P0.3/
SO_SSN/
I1.SDA
V18
P0.14/
U2_TX/
T2.ICAPA
V33 P0.4/
S1_MISO SPI_DO AGC_CNTR VSSRF VSSRF VSSRF_A
GP1.12/
CANTX(1) USBDN
P0.1/
SO_MOSI/
U3.RX
P0.0/
SO_MISO/
U3.TX
P0.7/S1_SSN
P0.9/
UO_TX/
BOOT.0
P0.11/
U1_TX/
BOOT.1
BOOTEN SIGN V27RF V27RF V27RF VSSRF
HVSS
P1.13/
HCLK/
IO.SCL
P1.14/
HRXD/
IO.SDA
P1.15/
HTXD
P0.2/
SO_SCLK/
I1.SCL
PO.12/
SCCLK
PO.8/
UO_RX/
U0.TX
P0.10/
U1_RX/
U1.TX
V33 VSSRF:IO V33 V27RF VSSRF
1. Only for STA8058A and STA8058ATR.
Table 3. Power supply pins
Symbol I/O Function LFBGA104
V33 - Digital supply voltage for I/O circuitry (3.3 Volt) B6, F7, G10, H9, H11
VSS - Digital ground for I/O circuitry A1, D4, D5, H1
V33IO-PLL - Digital supply voltage for I/O circuitry and for PLL reference (3.3V) D1
VSSIO-PLL - Digital ground for I/O circuitry and for PLL reference E1
V33REG_BKP -Digital supply voltage for backup block I/O circuitry and for Ballast I/O
(3.3V) A7
VSSREG - Digital ground for Ballast I/O B7
V18 -
Digital supply voltage for core circuitry (1.8 Volt): When using the
internal voltage regulator, this pin shall not be driven by an external
voltage supply, but a capacitance of at least 10F (Tantalum, low
series resistance) + 33nF (ceramic) shall be connected between
these pins and VSS18 to guarantee on-chip voltage stability.
B3, F5
VSS18 - Digital ground for core circuitry B2, E5
V18BKP -
Digital supply voltage for backup block (RTC, oscillator, Wake-up
controller - 1.8 Volt): when using the internal voltage regulator, this
pin shall not be driven by an external voltage supply, but a
capacitance of at least 1F shall be connected between this pin and
VSSBKP to guarantee on-chip voltage stability.
A4
Pin description STA8058
10/14 Doc ID 14095 Rev 4
Note: V33 and V33IO-PLL are all internally connected. Same for VSS and VSSIO-PLL.
All VSS, VSS18, VSSBKP
, AVSS,VSSRF
,VSSRF_A and VSSRF_IO pins must be tied together to the
common ground plane, taking care of noise filtering, especially on AVSS ,VSSRF , VSSRF_A
and VSSRF_IO
VSSBKP - Digital ground for backup logic B4
AVDD - Analog supply voltage for the A/D converter A3
AVSS - Analog supply ground for the A/D converter A2
V27RF - Analog supply voltage for RF chain (2.7V) C13, G10, G11, G12,
H12
V27PLL - Analog supply voltage for PLL embedded into RF part (2.7V) B11, B12, B13, C12
VSSRF - Analog supply ground for RF core
A13, C11, D11, D13,
E11, E12, F11, F12,
G13, H13
VSSRF_A - Analog supply ground for RF amplifier D13, F13
VSSRF_IO - Analog supply ground for RF IO circuirty H10
Table 3. Power supply pins (continued)
Symbol I/O Function LFBGA104
STA8058 Electrical characteristics
Doc ID 14095 Rev 4 11/14
3 Electrical characteristics
See STA2058 (Teseo Baseband) and STA5620 (RF Front-end) datasheet for related data.
Package information STA8058
12/14 Doc ID 14095 Rev 4
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 5. LFBGA104 (11x7x1.4mm) mechanical data and package dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A1.400 0.0551
A1 0.210 0.0083
A2 0.990 0.0390
A3 0.200 0.0079
A4 0.800 0.0315
b0.350 0.400 0.450 0.0138 0.0157 0.0177
D10.900 11.000 11.100 0.4291 0.4331 0.4370
D1 9.600 0.3780
E6.900 7.000 7.100 0.2717 0.2756 0.2795
E1 5.600 0.2205
e0.800 0.0315
F0.700 0.0276
ddd 0.100 0.0039
eee 0.150 0.0059
fff 0.080 0.0031
LFBGA104
Low profile Fine Pitch Ball Grid Array
Body: 11 x 7 x 1.4mm
8054244 B
STA8058 Revision history
Doc ID 14095 Rev 4 13/14
5 Revision history
Table 4. Document revision history
Date Revision Changes
25-Oct-2007 1 Initial release.
19-Mar-2009 2
Updated Table 1: Device summary on page 1.
Updated ECOPACK description in Section 4: Package information on
page 12.
23-Oct-2012 3
Updated Table 1: Device summary
Updated Figure 2: STA8058 TESEO baseband block diagram and
Figure 4: STA8058 TESEO MCM block diagram
Updated Table 2: Ball out for LFBGA104 package
17-Sep-2013 4 Updated Disclaimer
STA8058
14/14 Doc ID 14095 Rev 4
Rev 4
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold purs uant to ST’s terms and conditi ons of sale.
Purchasers are so lel y res ponsibl e fo r the c hoic e, se lecti on an d use o f the S T prod ucts and s ervic es des crib ed he rein , and ST assumes n o
liability whatsoever rel ating to the choice, selection or use of the ST products and ser vices describe d herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document ref er s to an y t hird pa rty p ro duc ts or se rv ic es it sh all n ot be deem ed a li ce ns e gran t by ST fo r the use of su ch t hir d party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or se rvices or any int ellectual pr operty contai ned therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVAL ENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PAT ENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPL ANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTI VE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warrant y granted by ST for the S T product or se rvice descr ibed herein a nd shall no t create or e xtend in any manner whatsoe ver, any
liability of ST.
ST and the ST lo go are trademark s or registered trademarks of ST i n various countr ies.
Information in this docu ment supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroele ctr on ic s gr oup of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Swed en - Switzerland - Un ited Kingdom - United States of America
www.st.com