SPICE Device Model Si9948AEY Vishay Siliconix Dual P-Channel Enhancement-Mode MOSFET CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model schematic is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device(s). SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70517 18-Apr-01 www.vishay.com 1 SPICE Device Model Si9948AEY Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit Static Gate Threshold Voltage a On-State Drain Current a Drain-Source On-State Resistance a Forward Transconductance a Diode Forward Voltage Dynamic VGS(th) VDS = VGS, ID = -250 A 2 V ID(on) VDS = -5 V, VGS = -10 V 30 A VGS = -10 V, ID = -2.6 A 0.15 VGS = -4.5 V, ID = -2.1 A 0.20 gfs VDS = -15 V, ID = -2.6 A 5.3 S VSD IS = -2 A, VGS = 0 V 0.81 V rDS(on) b Total Gate Chargeb Qg b 9.5 VDS = -30 V, VGS = -10 V, ID = -2.6 A Gate-Source Charge Qgs Gate-Drain Chargeb Qgd 1.8 Turn-On Delay Timeb td(on) 1.1 b tr Turn-Off Delay Timeb td(off) Rise Time Fall Timeb tf Source-Drain Reverse Recovery Time trr VDD = -30 V, RL = 30 ID -1 A, VGEN = -10 V, RG = 6 2.5 nC 7.4 22 ns 8 IF = -2 A, di/dt = 100 A/s 50 Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70517 18-Apr-01 SPICE Device Model Si9948AEY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70517 18-Apr-01 www.vishay.com 3