SPICE Device Model Si9948AEY
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 70517 www.vishay.com
18-Apr-01 1
Dual P-Channel Enhancement-Mode MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model schematic is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-to-5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
g
d model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device(s).
SUBCIRCUIT MODEL SCHEMATIC
SPICE Device Model Si9948AEY
Vishay Siliconix
www.vishay.com Document Number: 70517
218-Apr-01
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Typical Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 µA2V
On-State Drain CurrentaID(on) VDS = −5 V, VGS = −10 V 30 A
VGS = −10 V, ID = −2.6 A 0.15
Drain-Source On-State ResistancearDS(on)
VGS = −4.5 V, ID = −2.1 A 0.20
Ω
Forward Transconductanceagfs VDS = −15 V, ID = −2.6 A 5.3 S
Diode Forward VoltageaVSD IS = −2 A, VGS = 0 V 0.81 V
Dynamicb
Total Gate ChargebQg9.5
Gate-Source ChargebQgs 2.5
Gate-Drain ChargebQgd
VDS = −30 V, VGS = −10 V, ID = −2.6 A
1.8
nC
Turn-On Delay Timebtd(on) 1.1
Rise Timebtr7.4
Turn-Off Delay Timebtd(off) 22
Fall Timebtf
VDD = −30 V, RL = 30 Ω
ID ≅ −1 A, VGEN = −10 V, RG = 6 Ω
8
Source-Drain Reverse Recovery Time trr IF = −2 A, di/dt = 100 A/µs50
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
SPICE Device Model Si9948AEY
Vishay Siliconix
Document Number: 70517 www.vishay.com
18-Apr-01 3
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
