FDD8880 N April 2008 FDD8880 tm N-Channel PowerTrench(R) MOSFET 30V, 58A, 9m General Description Features This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed. * rDS(ON) = 9m, VGS = 10V, ID = 35A * rDS(ON) = 12m, VGS = 4.5V, ID = 35A * High performance trench technology for extremely low rDS(ON) * Low gate charge Applications * High power and current handling capability * DC/DC converters * RoHS Compliant D D G G S D-PAK TO-252 (TO-252) S MOSFET Maximum Ratings TC = 25C unless otherwise noted Symbol VDSS Drain to Source Voltage Parameter Ratings 30 Units V VGS Gate to Source Voltage 20 V Continuous (TC = 25oC, VGS = 10V) (Note 1) 58 A Continuous (TC = 25oC, VGS = 4.5V) (Note 1) 51 A Continuous (Tamb = 25oC, VGS = 10V, with RJA = 52oC/W) 13 A Drain Current ID Pulsed EAS Single Pulse Avalanche Energy (Note 2) Power dissipation PD Derate above 25oC TJ, TSTG Operating and Storage Temperature Figure 4 A 53 mJ 55 W 0.37 W/oC -55 to 175 oC Thermal Characteristics RJC Thermal Resistance Junction to Case TO-252 2.73 o C/W RJA Thermal Resistance Junction to Ambient TO-252 100 o C/W RJA Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52 oC/W Package Marking and Ordering Information Device Marking FDD8880 Device FDD8880 Package TO-252AA (c)2008 Fairchild Semiconductor Corporation Reel Size 13" Tape Width 12mm Quantity 2500 units FDD8880 Rev. B3 http://store.iiic.cc/ Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 24V VGS = 0V TC = 150oC VGS = 20V 30 - - V - - 1 - - 250 A - - 100 nA V On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage VGS = VDS, ID = 250A Drain to Source On Resistance 1.2 - 2.5 ID = 35A, VGS = 10V - 0.007 0.009 ID = 35A, VGS = 4.5V - 0.009 0.012 ID = 35A, VGS = 10V, TJ = 175oC - 0.013 0.015 - 1260 - - 260 - pF - 150 - pF Dynamic Characteristics pF CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance RG Gate Resistance VGS = 0.5V, f = 1MHz - 2.3 - Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V - 23 31 nC VDS = 15V, VGS = 0V, f = 1MHz Qg(5) Total Gate Charge at 5V VGS = 0V to 5V Qg(TH) Threshold Gate Charge VGS = 0V to 1V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain "Miller" Charge Switching Characteristics VDD = 15V ID = 35A Ig = 1.0mA - 13 17 nC - 1.3 1.7 nC - 3.8 - nC - 2.5 - nC - 5.0 - nC (VGS = 10V) tON Turn-On Time - - 147 ns td(ON) Turn-On Delay Time - 8 - ns tr Rise Time td(OFF) Turn-Off Delay Time tf tOFF - 91 - ns - 38 - ns Fall Time - 32 - ns Turn-Off Time - - 108 ns ISD = 35A - - 1.25 V ISD = 15A - - 1.0 V VDD = 15V, ID = 35A VGS = 10V, RGS = 10 Drain-Source Diode Characteristics VSD Source to Drain Diode Voltage trr Reverse Recovery Time ISD = 35A, dISD/dt = 100A/s - - 27 ns QRR Reverse Recovered Charge ISD = 35A, dISD/dt = 100A/s - - 14 nC Notes: 1: Package current limitation is 35A. 2: Starting TJ = 25C, L = 0.14mH, IAS = 28A, VDD = 27V, VGS = 10V. 3 (c)2008 Fairchild Semiconductor Corporation FDD8880 Rev. B3 http://store.iiic.cc/ FDD8880 Electrical Characteristics TC = 25C unless otherwise noted FDD8880 Typical Characteristics TC = 25C unless otherwise noted 1.2 60 1.0 50 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER CURRENT LIMITED BY PACKAGE 0.8 0.6 0.4 40 VGS = 10V 30 VGS = 4.5V 20 10 0.2 0 0 0 25 50 75 100 150 125 25 175 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Case Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 500 TC = 25oC IDM, PEAK CURRENT (A) TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK VGS = 10V CURRENT AS FOLLOWS: 175 - TC I = I25 VGS = 4.5V 150 100 30 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability (c)2008 Fairchild Semiconductor Corporation FDD8880 Rev. B3 http://store.iiic.cc/ FDD8880 Typical Characteristics TC = 25C unless otherwise noted 500 IAS, AVALANCHE CURRENT (A) 1000 ID, DRAIN CURRENT (A) 10s 100 100s 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 1 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC DC 1 0.01 0.1 1 60 10 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching Capability 80 80 VGS = 5V ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 60 40 TJ = 25oC 20 TJ = 175oC 60 VGS = 4V VGS = 10V 40 VGS = 3V 20 TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TJ = -55oC 0 0 1.5 2.0 2.5 3.0 3.5 VGS , GATE TO SOURCE VOLTAGE (V) 0 4.0 0.25 0.5 0.75 1.0 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 25 1.8 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 35A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 10 0.1 1 tAV, TIME IN AVALANCHE (ms) 20 15 ID = 1A 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.6 1.4 1.2 1.0 0.8 VGS = 10V, ID = 35A 5 2 4 6 8 10 0.6 -80 VGS, GATE TO SOURCE VOLTAGE (V) Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature (c)2008 Fairchild Semiconductor Corporation FDD8880 Rev. B3 http://store.iiic.cc/ FDD8880 Typical Characteristics TC = 25C unless otherwise noted 1.10 1.2 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 1.05 1.00 0.95 0.90 -80 200 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 2000 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 15V CISS = CGS + CGD C, CAPACITANCE (pF) 1000 CRSS = CGD COSS CDS + CGD VGS = 0V, f = 1MHz 100 0.1 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 35A ID = 1A 2 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 30 Figure 13. Capacitance vs Drain to Source Voltage 0 5 10 15 Qg, GATE CHARGE (nC) 20 25 Figure 14. Gate Charge Waveforms for Constant Gate Current (c)2008 Fairchild Semiconductor Corporation FDD8880 Rev. B3 http://store.iiic.cc/ FDD8880 Test Circuits and Waveforms VDS BVDSS tP L VDS VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDD VDD - VGS DUT tP IAS 0V 0 0.01 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS = 10V VGS Qg(5) + Qgs2 VDD VGS = 5V DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 10% 0 DUT 90% RGS VGS VGS 0 Figure 19. Switching Time Test Circuit 50% 10% 50% PULSE WIDTH Figure 20. Switching Time Waveforms (c)2008 Fairchild Semiconductor Corporation FDD8880 Rev. B3 http://store.iiic.cc/ FDD8880 Thermal Resistance vs. Mounting Pad Area ( T JM - TA ) P DM = ----------------------------R JA (EQ. 1) In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 125 RJA = 33.32+ 23.84/(0.268+Area) EQ.2 RJA = 33.32+ 154/(1.73+Area) EQ.3 100 RJA (oC/W) The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 75 50 25 0.01 (0.0645) 0.1 (0.645) 1 (6.45) 10 (64.5) AREA, TOP COPPER AREA in2 (cm2) Figure 21. Thermal Resistance vs Mounting Pad Area 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. 23.84 ( 0.268 + Area ) R JA = 33.32 + ------------------------------------- (EQ. 2) Area in Inches Squared 154 ( 1.73 + Area ) R JA = 33.32 + ---------------------------------- (EQ. 3) Area in Centimeters Squared (c)2008 Fairchild Semiconductor Corporation FDD8880 Rev. B3 http://store.iiic.cc/ .SUBCKT FDD8880 2 1 3 ; rev April 2004 Ca 12 8 9.5e-10 Cb 15 14 9.5e-10 Cin 6 8 1.15e-9 LDRAIN DPLCAP DRAIN 2 5 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 33.15 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 RLDRAIN RSLC1 51 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 5.3e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.7e-9 LSOURCE CIN 8 7 SOURCE 3 RSOURCE RLSOURCE RLgate 1 9 53 RLdrain 2 5 10 RLsource 3 7 17 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD S1A 12 S2A 13 8 14 13 S1B CA 15 17 18 RVTEMP S2B 13 CB 19 6 8 VBAT 5 8 EDS - IT 14 + + EGS Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 3.2e-3 Rgate 9 20 2.2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 3.2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD RBREAK - + 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))} .MODEL DbodyMOD D (IS=2E-12 IKF=10 N=1.01 RS=3.76e-3 TRS1=8e-4 TRS2=2e-7 + CJO=4.8e-10 M=0.55 TT=1e-17 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=5.5e-10 IS=1e-30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=2.0 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.2) .MODEL MstroMOD NMOS (VTO=2.5 KP=170 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.69 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=22 RS=0.1) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=1.8e-3 TC2=8e-6) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-1e-3 TC2=-8.2e-6) .MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.3 VOFF=-0.8) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=-1.3) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2008 Fairchild Semiconductor Corporation FDD8880 Rev. B3 http://store.iiic.cc/ FDD8880 PSPICE Electrical Model FDD8880 SABER Electrical Model rev April 2004 template FDD8880 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2e-12,ikf=10,nl=1.01,rs=3.76e-3,trs1=8e-4,trs2=2e-7,cjo=4.8e-10,m=0.55,tt=1e-17,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5.5e-10,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=2.0,kp=10,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.5,kp=170,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.69,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.3,voff=-0.8) RLDRAIN RSLC1 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.8,voff=-1.3) 51 c.ca n12 n8 = 9.5e-10 RSLC2 c.cb n15 n14 = 9.5e-10 ISCL c.cin n6 n8 = 1.15e-9 spe.ebreak n11 n7 n17 n18 = 33.15 GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE DBREAK 50 - dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN DRAIN 2 8 LSOURCE 7 SOURCE 3 RSOURCE RLSOURCE i.it n8 n17 = 1 S1A 12 l.lgate n1 n9 = 5.3e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.7e-9 S2A S1B CA 15 14 13 13 8 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 VBAT 5 8 EDS - IT 14 + + res.rlgate n1 n9 = 53 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 17 RBREAK - m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u + 8 22 RVTHRES res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7 res.rdrain n50 n16 = 3.2e-3, tc1=1.8e-3,tc2=8e-6 res.rgate n9 n20 = 2.2 res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.2e-3, tc1=5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-1e-3,tc2=-8.2e-6 res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5)) } } (c)2008 Fairchild Semiconductor Corporation FDD8880 Rev. B3 http://store.iiic.cc/ th FDD8880 PSPICE Thermal Model JUNCTION REV 23 April 2004 FDD8880T CTHERM1 TH 6 8e-4 CTHERM2 6 5 1e-3 CTHERM3 5 4 2.5e-3 CTHERM4 4 3 2.6e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 1.5e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 1.44e-1 RTHERM2 6 5 1.9e-1 RTHERM3 5 4 3.0e-1 RTHERM4 4 3 4.0e-1 RTHERM5 3 2 5.7e-1 RTHERM6 2 TL 5.8e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDD8880T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =8e-4 ctherm.ctherm2 6 5 =1e-3 ctherm.ctherm3 5 4 =2.5e-3 ctherm.ctherm4 4 3 =2.6e-3 ctherm.ctherm5 3 2 =8e-3 ctherm.ctherm6 2 tl =1.5e-2 RTHERM3 CTHERM3 4 RTHERM4 rtherm.rtherm1 th 6 =1.44e-1 rtherm.rtherm2 6 5 =1.9e-1 rtherm.rtherm3 5 4 =3.0e-1 rtherm.rtherm4 4 3 =4.0e-1 rtherm.rtherm5 3 2 =5.7e-1 rtherm.rtherm6 2 tl =5.8e-1 } CTHERM4 3 RTHERM5 CTHERM5 2 CTHERM6 RTHERM6 tl (c)2008 Fairchild Semiconductor Corporation CASE FDD8880 Rev. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I34 FDD8880 Rev. B3 @2008 Fairchild Semiconductor Corporation http://store.iiic.cc/