© 2007 Microchip Technology Inc. DS21950D-page 1
MCP3550/1/3
Features
22-bit ADC in Small 8-pin MSOP Package with
Automatic Internal Offset and Gain Calibration
Low-Output Noise of 2.5 µVRMS with Effective
Resolution of 21.9 bits (MCP3550/1)
3 µV Typical Offset Error
2 ppm Typical Full-Sc ale Error
6 ppm Maximum INL Error
Total Unadjusted Error Less Than 10 ppm
No Digital Filter Settling Time, Single-Command
Conversions through 3-wire SPI Interface
Ultra-Low Conversion Current (MCP3550/1):
-100µA typical (V
DD = 2.7V)
-120µA typical (V
DD = 5.0V)
Differential Input with VSS to VDD Common Mode
Range
2.7V to 5.5V Single-Supply Operation
Extended Temperature Range:
- -40°C to +125°C
Applications
Weigh Scales
Direct Temperature Measurement
6-digit DVMs
Instrumentation
Data Acquisition
Strain Gauge Measurement
Block Diagram
Description
The Microchip Technology Inc. MCP3550/1/3 devices
are 2.7V to 5.5V low-power, 22-bit Delta-Sigma Ana-
log-to-Digital Converters (ADCs). The devices offer
output noise as low as 2.5 µVRMS, with a total
unadjusted error of 10 ppm. The family exhibits 6 ppm
Integral Non -Lin eari ty (INL) error, 3 µV of fset error an d
less than 2 ppm full-scale error. The MCP3550/1/3
devices provide high accuracy and low noise
performance for applications where sensor
measurements (such as pressure, temperature and
humidity) are performed. With the internal oscillator
and high oversampling rate, minimal external
components are required for high-accuracy
applications.
This product line has fully differential analog inputs,
making it compatible with a wide variety of sensor,
industri al control or process control appli ca tio ns .
The MCP3550/1/3 devices operate from -40°C to
+125°C and are available in the space-saving 8-pin
MSOP and SOIC packages.
Package Types:
Device Selection Table
VSS
VIN+
VIN-
SCK
VDD
SDO
CS
SINC 4
Internal
Ser i a l Interfa c e
VREF
POR
Oscillator
3rd-Order
DS ADC
Modulator
w/ Internal
Calibration
VDD
RDY
Part Number Sample
Rate Effective
Resolution 50/60 Hz
Rejection
MCP3550-50 12.5 sps 21.9 bits 50 Hz
MCP3550-60 15 sps 21.9 bits 60 Hz
MCP3551 13.75 sps 21.9 bits 50/60 Hz
(simultaneous)
MCP3553 60 sps 20.6 bits N/A
VIN
VIN+
MCP3550/1/3
VSS
CS
SDO/RDY
1
2
3
4
8
7
6
5SCK
VDD
VREF
SOIC, MSOP
Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs
MCP3550/1/3
DS21950D-page 2 © 2007 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings*
VDD...................................................................................7.0V
All inputs and outputs w.r.t VSS .............. -0.3V to VDD + 0.3V
Difference Input Voltage ...................... .................|VDD - VSS|
Output Short Circuit Current ....... .... .... .. ......... .... ...Continuous
Current at Input Pins .................... .. .... .. ......... .. .... .. .... ...±2 mA
Current at Output and Supply Pins ............................±10 mA
Storage Temperature................... .. .... .. .. .. ......-65°C to +150°C
Ambient temp. with power applied. ...............-55°C to +125°C
ESD protection on all pins (HBM, MM) ............ 6kV, 400V
Maximum Junction Temperature (TJ)..........................+150°C
Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of th e device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C TA +85°C, VDD = 2. 7V or 5.0V.
VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full-scale range. Unless otherwise noted, specification
applies to entire MCP3550/1/3 family.
Parameters Sym Min Typ Max Units Conditions
Noise Performance (MCP3550/1)
No Missing Codes NMC 22 bits At DC (Note 5)
Output Noise eN—2.5 µV
RMS
Effective Resolution ER 21.9 bits RMS VREF = 5V
Noise Performance (MCP3553)
No Missing Codes NMC 20 bits At DC (Note 5)
Output Noise eN—6µV
RMS
Effective Resolution ER 20.6 bits RMS VREF = 5V
Conversion Times
MCP3550-50 tCONV -1.0% 80 +1.0% ms
MCP3550-60 tCONV -1.0% 66.67 +1.0% ms
MCP3551 tCONV -1.0% 72.73 +1.0% ms
MCP3553 tCONV -1.0% 16.67 +1.0% ms
Accuracy
Integral Non-Linearity INL ±2 6 ppm TA = +25°C only (Note 2)
Offset Error VOS -12 ±3 +12 µV TA = +25°C
—±4 µVT
A = +85°C
—±6 µVT
A = +125°C
Positive Full-Scale Error VFS,P -10 ±2 +10 ppm TA = +25°C only
Negative Full-Scale Error VFS,N -10 ±2 +10 ppm TA = +25°C only
Offset Drift 0.040 ppm/°C
Positive/Negative Full-Scale Error
Drift 0.028 ppm/°C
Note 1: This parameter is established by characterization and not 100% tested.
2: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
3: This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-.
4: Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF =5V.
5: Characterized by design, but not tested.
6: Rejection performance depends on internal oscillator accuracy; see Section 4.0 “Device Overview” for more informa-
tion on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz.
© 2007 Microchip Technology Inc. DS21950D-page 3
MCP3550/1/3
Rejection Performanc e(1,6)
Common Mode DC Rejection -135 dB VCM range from 0 to VDD
Power Supply DC Rejection -115 dB
Common Mode 50/60 Hz Rejection CMRR -135 dB VCM varies from 0V to VDD
Power Supply 50/60 Hz Rejection PSRR -85 dB MCP3551 only, VDD varies from
4.5V to 5.5V
Power Supply 50/60 Hz Rejection PSRR -120 dB MCP3550-50 or MCP3550-60 only
at 50 or 60 Hz respectively, VDD
varies from 4.5V to 5.5V
Normal Mode 50 and 60 Hz
Rejection NMRR -85 dB MCP3551 only,
0 < VCM < VDD,
-VREF < VIN = (VIN + - VIN-) < +VREF
Normal Mode 50 or 60 Hz
Rejection NMRR -120 dB MCP3550-50 or MCP3550-60 only
at 50 or 60 Hz respectively,
0 < VCM < VDD,
-VREF < VIN = (VIN + - VIN-) < +VREF
Analog In puts
Differential Input Range VIN+ VIN- -VREF —+V
REF V
Absolute/Common Mode Voltages VSS - 0.3 VDD + 0.3 V
Analog Input Sampling Capacitor 10 pF Note 5
Differential Input Impedance 2.4 MΩ
Shutdown Mode Leakage Current 1 nA VIN+ = VIN- = VDD; CS = VDD
(Note 3)
Reference Input
Voltage Range 0.1 VDD V
Reference Input Sampling
Capacitor —15 pFNote 5
Reference Input Impedance 2.4 MΩNote 4
Shutdown Mode Reference
Leakage Current —1 nAV
IN+ = VIN- = V SS; CS = VDD
Power Requirements
Power Supply Volt age Range VDD 2.7 5.5 V
MCP3550-50, MCP3551 Supply
Current IDD 120 170 µA VDD = 5V
100 µA VDD = 2.7V
MCP3550-60, MCP3553 Supply
Current IDD 140 185 µA VDD = 5V
120 µA VDD = 2.7V
Supply Current, Sleep Mode IDDSL —10 µA
Supply Current, Shut down Mode IDDS —— 1 µACS = SCK = VDD
Serial Interface
Voltage Input High (CS, SCK) VIH 0.7 VDD —— V
Voltage Input Low (CS, SC K) VIL ——0.4 V
Voltage Output High (SDO/RDY)V
OH VDD - 0. 5 V VOH = 1 mA, VDD = 5.0V
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C TA +85°C, VDD = 2. 7V or 5.0V.
VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full-scale range. Unless otherwise noted, specification
applies to entire MCP3550/1/3 family.
Parameters Sym Min Typ Max Units Conditions
Note 1: This parameter is established by characterization and not 100% tested.
2: INL is the difference between the endpoints line and the measured code at the cent er of the quantization band.
3: This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-.
4: Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF =5V.
5: Characterized by design, but not tested.
6: Rejection performance depends on internal oscillator accuracy; see Section 4.0 “Device Overview” for more informa-
tion on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz.
MCP3550/1/3
DS21950D-page 4 © 2007 Microchip Technology Inc.
Voltage Output Low (SDO/RDY)V
OL ——0.4 VV
OH = -1 mA, VDD = 5.0V
Input leakage Current
(CS, SCK ) ILI -1 1 µA
Internal Pin Capacitanc e
(CS, SCK , SDO/RDY)CINT —5 pFNote 1
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C TA +85°C, VDD = 2. 7V or 5.0V.
VREF = 2.5V. VIN+ = VIN- = VCM = VREF/2. All ppm units use 2*VREF as full-scale range. Unless otherwise noted, specification
applies to entire MCP3550/1/3 family.
Parameters Sym Min Typ Max Units Conditions
Note 1: This parameter is established by characterization and not 100% tested.
2: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
3: This current is due to the leakage current and the current due to the offset voltage between VIN+ and VIN-.
4: Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. VREF =5V.
5: Characterized by design, but not tested.
6: Rejection performance depends on internal oscillator accuracy; see Section 4.0 “Device Overview” for more informa-
tion on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 +85 °C
Operati ng Tempe rature Range TA-40 +125 °C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP θJA —206°C/W
Thermal Resistance, 8L-SOIC θJA —163°C/W
SERIAL TIMINGS
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C TA +85°C,
VDD = 3.3V or 5.0V, SDO load = 50 pF.
Parameters Sym Min Typ Max Units Conditions
CLK Frequency fSCK —— 5MHz
CLK High tHI 90 ns
CLK Low tLO 90 ns
CLK fall to output data va lid tDO 0 90 ns
CS low to indicate RDY state tRDY 0 50 ns
CS minimum low ti me tCSL 50 ns
RDY flag setup time tSU 20 ns
CS rise to output disable tDIS 20 ns
CS disable time tCSD 90 ns
Power-up to CS LOW t PUCSL —10—µs
CS High to Shutdown Mode tCSHSD —10µs
© 2007 Microchip Technology Inc. DS21950D-page 5
MCP3550/1/3
FIGURE 1-1: Serial Timing.
FIGURE 1-2: Power-up Timing.
tRDY
tCSL
tDO
tSU
fSCK
tHI tLO
tDIS
CS
SDO
SCK
tCSD tCSHSD
/RDY
VDD
CS
tPUCSL
MCP3550/1/3
DS21950D-page 6 © 2007 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units use 2* VREF as full-scale range. Unless otherw i se not ed, grap hs apply to entire MCP3550/1/3 family.
FIGURE 2-1: INL Error vs. Input Voltage
(VDD = 2.7V).
FIGURE 2-2: INL Error vs. Input Voltage
(VDD = 5.0V).
FIGURE 2-3: INL Error vs. Input Voltage
(VDD = 5.0V, VREF = 5V).
FIGURE 2-4: Maximum INL Error vs .
VREF.
FIGURE 2-5: Maximum INL Error vs .
Temperature.
FIGURE 2-6: Output Noise vs. Input
Voltage (VDD = 2.7V).
Note: The g r ap hs and t ables provid ed fol low i ng thi s n ote are a statistical s umm ar y based on a l im ite d n um ber of
samples and are prov ided for informational purposes only. The performance charac teristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-5
-4
-3
-2
-1
0
1
2
3
4
5
-2.5 -1.5 -0.5 0.5 1.5 2.5
VIN(V)
INL (ppm)
+125 C
+85 C
-40 C
+25 C
-5
-4
-3
-2
-1
0
1
2
3
4
5
-2.5 -1.5 -0.5 0.5 1.5 2.5
VIN (V)
INL (ppm)
+125 C
+85 C
+25 C
- 40 C
-10
-8
-6
-4
-2
0
2
4
6
8
10
-5 -4 -3 -2 -1 0 1 2 3 4 5
VIN (V)
INL (ppm)
+125 C
+85 C
+25 C
-40 C
0
2
4
6
8
10
00.511.522.533.544.55
VREF (V)
INL Error (ppm)
0
1
2
3
4
5
6
7
8
9
10
-50 -25 0 25 50 75 100 125
Temperature (°C)
Max INL (ppm)
0
1
2
3
4
5
6
7
8
9
10
-2.5 -1.5 -0.5 0.5 1.5 2.5
VIN (Volts)
Output Noise (µV RMS)
MCP3553
MCP3550/1
© 2007 Microchip Technology Inc. DS21950D-page 7
MCP3550/1/3
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units use 2* VREF as full-scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.
FIGURE 2-7: Output Noise vs. Input
Voltage (VDD = 5.0V).
u
FIGURE 2-8: Output Noise vs. VREF.
FIGURE 2-9: Output Noise vs.VDD.
FIGURE 2-10: Output Noise vs.
Temperature.
FIGURE 2-11: Offset Error vs VDD
(VCM =0V).
FIGURE 2-12: Offset Error vs.
Temperature (VREF = 5.0V).
0
5
10
15
-2.5 -1.5 -0.5 0.5 1.5 2.5
VIN (V)
Output Noise (µV RMS)
MCP3553
MCP3550/1
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
0.0 1.0 2.0 3.0 4.0 5.0
VREF (V)
Output Nois e (µVRMS)
MCP3550/1
MCP3553
0
1
2
3
4
5
6
7
8
9
10
2.533.544.555.5
VDD (V)
Output Noise (µV RMS)
MCP3550/1
MCP3553
0
1
2
3
4
5
6
7
8
9
10
-50-250 255075100125
Temperature (°C)
Output Noise (µV RMS)
MCP3550/1
MCP3553
0
1
2
3
4
5
2.533.544.555.5
VDD (V)
Offset (µV)
0
1
2
3
4
5
6
7
-50 -25 0 25 50 75 100 125
Temper atu re (°C)
Offset (µV)
MCP3550/1/3
DS21950D-page 8 © 2007 Microchip Technology Inc.
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units are ratioed against 2*VREF . Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.
FIGURE 2-13: Full-Sca le Error vs. VDD.
FIGURE 2-14: Full-Sca le Error vs.
Temperature.
FIGURE 2-15: Full-Sca le Error vs.
Temperature (VREF = 5.0V).
FIGURE 2-16: MCP3550/1 Output Noise
Histogram.
FIGURE 2-17: MCP3553 Output Noise
Histogram.
FIGURE 2-18: Total Unadjusted Error
(TUE) vs. Input Voltage (VDD = 2.7V).
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.533.544.555.5
VDD (V)
Full-Scale Error (ppm)
Positive Full- Scale
Negative Full-Scale
-10
-8
-6
-4
-2
0
2
4
6
8
10
-50 -25 0 25 50 75 100 125
Temperature (°C)
Full-Scale Error (ppm)
Positive Full-Scale
Negative Full - S c a le
-10
-8
-6
-4
-2
0
2
4
6
8
10
-50 -25 0 25 50 75 100 125
Temperature (°C)
Full-Scale Error (ppm)
Positive Full-Scale
Negative Full-Scale
0
500
1000
1500
2000
2500
3000
3500
4000
-15 -10 -5 0 5 10 15
Output Code (LS B)
Number of Occurrences
VDD = 5V
VREF = 2.5V
VCM = 1.25V
VIN = 0V
TA = 25C
16384
consecutive
readings
0
200
400
600
800
1000
1200
1400
1600
1800
-15 -10 -5 0 5 10 15
Output Code (LSB)
Number of Occurrences
VDD = 5V
VREF = 2.5V
VCM = 1.25V
VIN = 0V
TA = 25°C
16384 consecutive
readings
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
VIN (V)
TUE (ppm)
© 2007 Microchip Technology Inc. DS21950D-page 9
MCP3550/1/3
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All pp m units us e 2*V REF as full-scale range. Unless otherwise noted, grap hs appl y to enti re M C P355 0/1 /3 fam il y.
FIGURE 2-19: Total Unadjusted Error
(TUE) vs. Input Voltage.
FIGURE 2-20: Total Unadjusted Error
(TUE) vs. Input Voltage (VREF = 5.0V).
FIGURE 2-21: Maximum TUE vs. VREF.
FIGURE 2-22: Maximum TUE vs.
Temperature.
FIGURE 2-23: Maximum TUE vs. VDD.
FIGURE 2-24: IDDS vs. Temperature.
-5
-4
-3
-2
-1
0
1
2
3
4
5
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5
VIN (V)
TUE (ppm)
-10
-8
-6
-4
-2
0
2
4
6
8
10
-5-4-3-2-1012345
VIN (V)
TUE (ppm)
0
1
2
3
4
5
6
7
8
9
10
012345
VREF (V)
Maximum TUE (ppm)
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperat ur e (° C)
Maximum TUE (ppm)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
2.5 2.7 3 3.3 4 5 5.5
VDD (V)
TUE (ppm)
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
-50-250 255075100125
Temperatu r e ( °C)
IDDS (µA)
MCP3550/1
MCP3553
MCP3550/1/3
DS21950D-page 10 © 2007 Microchip Technology Inc.
Note: Unless otherwise specified, TA = +25°C, VDD = 5V, VREF = 2.5V, VSS = 0V, VCM = VREF/2, VIN+ = VIN-.
All ppm units use 2* VREF as full-scale range. Unless otherw i se not ed, grap hs apply to entire MCP3550/1/3 family.
FIGURE 2-25: IDD vs. VDD.FIGURE 2-26: IDD vs. Temp erature.
0
20
40
60
80
100
120
140
160
180
200
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
IDD (µA)
MCP3550-60, MCP3553
MCP3550-50, MCP3550/1
0
20
40
60
80
100
120
140
160
-50 -25 0 25 50 75 100 125
Temperatur e (°C)
IDD (µA)
MCP3550-60, MCP3553
MCP3550-50, MCP3550/1
© 2007 Microchip Technology Inc. DS21950D-page 11
MCP3550/1/3
3.0 PIN DESCRIPTIONS
TABLE 3-1: PIN FUNCTION TABLE
3.1 Voltage Reference (VREF)
The MCP3550/1/3 devices accept single-ended refer-
ence voltages from 0.1V to VDD. Since the converter
output noise is dominated by thermal noise, which is
independent of the reference voltage, the output noise
is not significantly improved by diminishing the refer-
enc e voltag e at th e VREF input pin. A reduced voltage
reference will significantly improve the INL perfor-
mance (see Figure 2-4); the INL max error is
proportional to VREF2.
3.2 Analog Inputs (VIN+, VIN-)
The MCP3550/1/3 devices accept a fully differential
analog input voltage to be connected on the VIN+ and
VIN- input pins. The differential voltage that is con-
verted is defined by VIN = VIN+ – VIN-. Th e di fferen ti al
voltage range specified for ensured accuracy is from
-VREF to +VREF. However, the converter will still output
valid and usable codes with the inputs overranged by
up to 12% (see Section 5.0 “Serial Interface”) at
room temperature. This overrange is clearly specified
by two overload bits in the output code.
The absolute voltage range on these input pins extends
from VSS – 0.3V to VDD + 0.3V. Any voltage above or
below this range will create leakage currents through
the El ectrostatic Discharge (ESD) diodes. T his current
will increase exponentially, degrading the accuracy and
noise performance of the device. The common mode of
the analog inputs sho uld be chosen su ch that bo th th e
differential analog input range and the absolute voltage
range on each pin are within the specified operating
range d efined in Section 1.0 “Electrical Characteris-
tics”.
3.3 Supply Voltage (VDD, VSS)
VDD is the power supply pin for the analog and digital
circuitry within the MCP3550/1/3. This pin requires an
appropriate bypass capacitor of 0.1 µF. The voltage on
this pin shoul d be ma int ain ed in th e 2.7V to 5.5V range
for specified operation. VSS is the ground pin and the
current return path for both analog and di gital circuitry
of the MCP3550/1/3. If an analog ground plane is
available, it is recommended that this device be tied to
the analog ground plane of the Printed Circuit Board
(PCB).
3.4 Serial Clock (SCK)
SCK synchronizes data communication with the
device . T he devic e operates in both SPI mode 1,1 and
SPI m ode 0,0. Data is sh ifted o ut of the device on the
falling edge of SCK. Data is latched in on the rising
edge of SCK. During CS high times, the SCK pin can
idle either high or low.
3.5 Data Output (SDO/RDY)
SDO/RDY is the output data pin for the device. Once a
conversion is complete, this pin will go active-low,
acting as a ready flag. Subsequent falling clock edges
will then place the 24-bit data word (two overflow bits
and 22 bits of data, see Section 5.0 “Serial Inter-
face”) on the SPI bus through the SDO pin. Data is
clocked out on the falling edge of SCK.
3.6 Chip Select (C S)
CS gates all communication to the device and can be
used to select multiple devices that share the same
SCK and SDO/RDY pins. This pin is also used to
control the internal conversions, which begin on the
falling edge of CS. Raising CS before the first internal
conversion is complete places the device in Single
Conversion mode. Leaving CS low will place the
device in Co ntinuo us Conv ersion mode (i .e., add itiona l
inte rnal conv ersi ons will au toma tical ly occur ). CS may
be tied permanently low for two-wire Continuous
Conv ersion mode op erati on. SDO/ RDY enters a high-
impedance state with CS high.
Pin No. Symbol I/O/P Function
1V
REF I Reference Voltage Analog Input Pin
2V
IN+ I Non-inverting Analog Input Pin
3V
IN- I Inverting Analog Input Pin
4V
SS P Grou nd Pin
5 SCK I Ser ial Clock Digital Input Pin
6 SDO/RDY O Data/Ready Digi tal Output Pin
7CS
I Chip Select Digital Input Pin
8V
DD P Pos itive Supply Voltage Pin
Type Identification: I = Input; O = Output; P = Power
MCP3550/1/3
DS21950D-page 12 © 2007 Microchip Technology Inc.
4.0 DEVICE OVERVIEW
The MCP3550/1/3 devices are 22-bit delta-sigma
ADCs that include fully differential analog inputs, a
third-order delta-sigma modulator, a fourth-order
modif ied SI NC deci mation f ilter, an on-c hip, lo w-noise
internal oscillator, a power supp ly monitoring circuit and
an SPI 3-wire digital interface. These devices can be
easily used to measure low-frequency, low-level
signals such as those found in pressure transducers,
tempera ture, strai n ga uge, i ndust rial c ontrol or p roces s
control applications. The power supply range for this
produ ct family is 2.7V to 5.5V ; t he temper ature range is
-40°C to +125°C. The functional block diagram for the
MCP3550/1/3 devices is shown in Figure 4-1.
A Power-On Reset (POR) monit oring circuit is in cluded
to ensure proper power supply voltages during the
conversion process. The clock source for the part is
internally generated to ±0.5% over the full-power
supply vol tage range and indus trial tempe ratur e rang e.
This stable clock source allows for superior conversion
repeatability and minimal drift across conversions.
The MCP3550/1/3 devices employ a delta-sigma
conversion technique to realize up to 22 bits of no
missin g co de per f or ma nc e wit h 21 . 9 Effec tiv e Num be r
of Bits (ENOB). These devices provide single-cycle
conversions with no digital filter settling time. Every
conversion includes an internal offset and gain auto-
calibration to reduce device error. These calibrations
are transparent to the user and are done in real-time
during the conve rsi on. There fore, thes e devi ces do not
require any additional time or conversion to proceed,
allowing easy usage of the devices for multiplexed
applications. The MCP3550/1/3 devices incorporate a
fourth-order digital decimation filter in order to allow
superior averaging performance, as well as excellent
line frequency rejection capabilities. The oversampling
frequency also reduces any external anti-aliasing filter
requirements.
The MCP3 550 /1/3 dev ices communic ate wit h a simple
3-wire SPI interface. The interface controls the
conversion start event, with an added feature of an
auto-conversion at system power-up by tying the CS
pin to logic - lo w. The device ca n com municate with bus
speeds of up to 5 MHz, with 50 pF capacitive loading.
The interface offers two conversion modes: Single
Conversion mode for multiplexed applications and a
Continuous Conversion mode for multiple conversions
in series. Every conversion is independent of each
other. That is , all inte rnal re giste rs are flus hed b etwee n
conversions. When the device is not converting, it auto-
matically goes into Shutdown mode and, while in this
mode, consumes less than 1 µA.
FIGURE 4-1: MCP3550/1/3 Functional Block Diagram.
Internal
Oscillator
Third-Order
ΔΣ
Modulator
Digital
Decimation
Filter (SINC4)
SPI 3-wire
Interface
Gain and
Offset
Calibration
Differential
Analog Input Bit Conversion
Code Output
Code
Clock
Charge
Transfer
Reference
Input
Stream
© 2007 Microchip Technology Inc. DS21950D-page 13
MCP3550/1/3
4.1 MCP3550/1/3 Delta-Sigma
Modulator with Inter nal Offset and
Gain C a libratio n
The converter core of the MCP3550/1/3 devices is a
third-order delta-sigma modulator with automatic gain
and of fset error calibrations. The modulator uses a 1-bit
DAC structure. The delta-sigma modulator processes
the sampled charges through switched capacitor
structures controlled by a very low drift oscillator for
reduced clock jitter.
During the conversion process, the modulator outputs
a bit stream with the bit frequency equivalent to the
fOSC/4 (see Table 4-1). The high oversampling
implemented in the modulator ensures very high
resolution and high averaging factor to achieve low-
noise specifications. The bit stream output of the mod-
ulator is then processed by the digital decimation filter
in order to pro vide a 22-bi t output code at a da ta rat e of
12.5 Hz for the MCP3550-50, 15 Hz for the MCP3550-
60, 13.75 Hz for the MCP3551 and 60 Hz for the
MCP3553. Since the oversampling ratio is lower with
the MCP3 553 device, a much hi gher output dat a rate is
achiev ed whi le still achieving 20 bit s No Missing Codes
(NMC) and 20.6 ENOB.
A self-calibration of offset and gain occurs at the onset
of every conversion. The conversion data available at
the output of the device is always calibrated for offset
and gain through this process. This offset and gain
auto-calibration is performed internally and has no
impact on the speed of the converter since the offset
and gain errors are calibrated in real-time during the
conversion. The real-time offset and gain calibration
schemes do not affect the conversion process.
4.2 Digital Filt er
The MCP3550/1/3 devices include a digital decimation
filter, which is a fourth-order modified SINC filter. This
filter averages the incoming bit stream from the modu-
lator and outputs a 22-bit conversion word in binary
two's complement. When all bits have been processed
by the filter, the output code is ready for SPI communi-
cation, th e RDY flag is set on th e SDO/RDY pin and al l
the internal registers are reset in order to process the
next conversion.
Like the comm only used SIN C filte r, the modifie d SINC
filter in the MCP3550/1/3 family has the main notch
frequency located at fS/(OSR*L), where fS is the bit
stream sample frequency. OSR is the Oversampling
Ratio and L is the order of the filter.
The MCP3550-50 device has the main filter notch
located at 50 Hz. For the MCP3550-60 device, the
notch is loc ated at 60 Hz. The MCP35 51 dev ice h as it s
notch located at 55 Hz, and for the MCP3553 device,
the main notch is located at 240 Hz, with an OSR of
128. (see Table 4-1 for rejection performance).
The digital decimation SINC filter has been modified in
order to offer staggered zeros in its transfer function.
This mo dification i s intended to widen the ma in notch in
order to be less sensitive to oscillator deviation or line-
frequency drift. The MCP3551 filter has staggered
zeros spread in order to reject both 50 Hz and 60 Hz
line frequencies simultaneously (see Figure 4-2).
TABLE 4-1: DATA RATE, OUTPUT NOISE AND DIGITAL FILTE R SPECIFICATIONS BY DEVICE
Device Output Data
Rate (tCONV)
(Note)
Output
Noise
VRMS)
Primary
Notch
(Hz)
Sample
Frequency
(fS)
Internal
Clock
fOSC
50/60 Hz Rejection
MCP3550-50 80.00 ms 2.5 50 25600 Hz 102.4 kHz -120 dB min. at
50 Hz
MCP3550-60 66.67 ms 2.5 60 30720 Hz 122.88 kHz -120 dB min. at
60 Hz
MCP3551 72.73 ms 2.5 55 28160 Hz 112.64 kHz -82 d B min. from
48 Hz to 63 Hz. -
82 dB at 50 Hz and
-88 dB at 60 Hz
MCP3553 16.67 ms 6 240 30720 Hz 122.88 kHz Not Applicable
Note: For the first conversion after exiting Shutdown, tCONV must include an additional 144 fOSC periods before
the conv ersion is complete and the RDY (Ready) flag appears on SDO/RDY.
MCP3550/1/3
DS21950D-page 14 © 2007 Microchip Technology Inc.
:
FIGURE 4-2: SINC Filter Response,
MCP3550- 50 Devic e.
:
FIGURE 4-3: SINC Filter Response,
MCP3550- 60 Devic e.
:
FIGURE 4-4: SINC Filter Response,
MCP3551 Device, Simultaneous 50/60 Hz
Rejection.
FIGURE 4-5: SINC Filter Response at
Integer Multiples of the Sampling Frequency (fs).
4.3 Internal Oscil lator
The MCP3550/1/3 devices include a highly stable and
accurate internal oscillator that provides clock signals
to th e delta-s igma A DC with minimu m jitt er. Th e oscil -
lator is a specialized structure with a low temperature
coefficient across the full range of specified operation.
See Table 4-1 for oscillator frequencies.
The conversion time is an integer multiple of the inter-
nal cloc k period and, therefore, ha s the same ac curacy
as the internal clock frequency. The internal oscillator
frequency is 102.4 kHz ±1% for the MCP3550-50,
112.64 kHz ±1% for the MCP3551, and 122.88 kHz
±1% for the MCP3550-60 and MCP3553 devices,
across the full power supply voltage and specified
temperature ranges.
The notch of the digital filter is proportional to the
internal oscillator frequency, with the exact notch
frequency equivalent to the oscillator accuracy (< 1%
deviation). This high accuracy, combined with wide
notches , will ensure tha t the MCP3551 w ill hav e simu l-
taneous 50 Hz and 60 Hz line frequency rejection and
the MCP3550-50 or MCP3550-60 devices will have
greater than 120 dB rejection (a t either 50 or 60 Hz) by
the digital filtering, even when jitter is present.
The internal oscillator is held in the reset condition
when the part is in Shutdown mode to en sure very low
power consumption (< 1 µA in Shutdown mode). The
internal oscillator is independent of all serial digital
interface edges (i.e., state machine processing the
digit al SPI interfa ce is async hronous with respect to the
internal clock edges).
-120
-100
-80
-60
-40
-20
0
0 50 100 150 200
Frequency (Hz)
Attenuation (dB)
-120
-100
-80
-60
-40
-20
0
0 60 120 180 240
Frequency (Hz)
Attenuat i on (dB)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 102030405060708090100110
Frequency (Hz)
Attenuation (dB)
-140
-120
-100
-80
-60
-40
-20
0
0 28160 56320 84480 112640 140800 168960 197120 225280 253440
Frequency (Hz)
Normal Mode Rejection (dB)
© 2007 Microchip Technology Inc. DS21950D-page 15
MCP3550/1/3
4.4 Different ial Analog Inputs
The MCP3550/1/3 devices accept a fully differential
analog input voltage to be connected to the VIN+ and
VIN- input pins. The differential voltage that is converted
is define d by VIN = VIN+ – V IN-. The di f fe r en tia l vol t age
range specified for ensured accuracy is from -VREF to
+VREF.
The conv erter will output v alid an d usabl e code s from -
112% to 112% of output range (see Section 5.0
“Serial Interface”) at room temperature. The ±12%
overrange is clearly specified by two overload bits in
the outp ut code: OVH and OVL. This fe ature a llo w s for
system calibration of a positive gain error.
The absolute voltage range on these input pins extends
from VSS - 0.3V to VDD + 0.3V. If the input vo lt a ges are
above or below this range, the leakage currents of the
ESD diodes will increase exponentially, degrading the
accuracy and noise performance of the converter. The
common mode of the analog inputs should be chosen
such that both the differential analog input range and
absolute voltage range on each pin are within the
specified operating range defined in Section 1.0
“Electrical Cha racteristics”.
Both the analog differential inputs and the reference
input have switched-capacitor input structures. The
input capacitors are charged and discharged alterna-
tively with the input and the reference in order to
proc ess a conversi on. The charge and discharge of th e
input capacitors create dynamic input currents at the
VIN+ and VIN- input pins inversely proportional to the
sampling capacitor. This current is a function of the
differential input voltages and their respective common
modes. The typical value of the dif ferential input imped-
ance is 2.4 MΩ, with VCM = 2.5V, VDD = V REF = 5V. The
DC leakage current caused by the ESD input diodes,
even th ough o n the order o f 1 nA, can caus e add itiona l
offset errors proportiona l to the source resistance at the
VIN+ and VIN- input pins.
From a transient response standpoint and as a first-
order approximation, these input structures form a
simple RC fil tering c ircui t with the source imped ance i n
series with the RON (switc hed resi stance when closed)
of the input switch a nd the sampling c apacitor. In order
to ensure the accuracy of the sampled charge, proper
settling time of the input circuit has to be considered.
Slow settling of the input circuit will create additional
gain error. As a rule of thumb, in order to obtain 1 ppm
absolute measurement accuracy, the sampling period
must b e 14 ti mes greater t han the in put circuit RC tim e
constant.
4.5 Voltage Reference Input Pin
The MCP3550/1/3 devices accept a single-ended
external reference voltage, to be connected on the
VREF input pin. Internally, the reference voltage for the
ADC is a differential voltage with the non-inverting input
connected to the VREF pin and the inverting input
connected to the VSS pin. The value of the reference
voltage is VREF - VSS and the common mode of the
reference is always (VREF - VSS)/2.
The MCP3550/1/3 devices accept a single-ended
reference voltage from 0.1V to VDD. The converter
output noise is dominated by thermal noise that is
independent of the reference voltage. Therefore, the
output noise is not significantly improved by lowering
the referenc e volta ge at the VREF input pin. However, a
reduced referen ce v olt age w ill signi ficant ly impro ve th e
INL performance since the INL max error is
proportional to VREF2 (see Figure 2-4).
The charg e and di scha rge of the input c apa citor c reate
dynamic input currents at the VREF input pin inversely
proportional to the sampl ing capacitor, which is a func-
tion of the input reference voltage. The typical value of
the single-ended input impedance is 2.4 MΩ, with
VDD =V
REF = 5V. The DC leakage current caused by
the ESD input diodes, though on the order of 1 nA
typica lly , can cause additi onal gain error pr oportional to
the source resistance at the VREF pin.
4.6 Power-On Reset (POR)
The MCP3550/1/3 devices contain an internal Power-
On Reset (POR) circuit that monitors power supply
voltage VDD during operation. This circuit ensures
correct de vice st art-u p at syste m power-up and power-
down events. The POR has built-in hysteresis and a
timer to give a high degree of immunity to potential
ripple and noise on the power supplies, as well as to
allow proper settl ing of t he pow er supply durin g pow er-
up. A 0 .1 µF de coupl ing capaci tor shou ld be mount ed
as close as possible t o the VDD pin, providing additional
transient immunity.
The threshold vol t ag e is s et at 2.2V, with a tol erance of
approximately ±5%. If the supply voltage falls below
this thre shold , the MC P3550 /1/3 devic es wil l be he ld in
a reset condition or in Shutdown mode. When the part
is in Shutdown mode, the power consumption is less
than 1 µA. The typical hysteresis value is around
200 mV in order to prevent reset during brown-out or
other glitches on the power supply.
MCP3550/1/3
DS21950D-page 16 © 2007 Microchip Technology Inc.
Once a power-up event has occurred, the device must
require additional time before a conversion can take
place. Du ring this tim e, all interna l analog circui try must
settle before the first conversion can occur. An internal
timer counts 32 internal clock periods before the
internal oscillator can provide clock to the conversion
process. This allows all internal analog circuitry to
settle to their proper operating point. This timing is
typically less than 300 µs, which is negligible compared
to one conversion time (e.g. 72.7 ms for the
MCP3551). Figure 4-6 illustrates the conditions for a
power-u p and powe r-down ev ent unde r typica l st art-up
conditions.
FIGURE 4-6: Power-On Reset Operation.
4.7 Shutdown Mode
When not internally converting, the two modes of
operation for the MCP3550/1/3 devices are the
Shutdown and Sleep modes. During Shutdown mode,
all interna l analog circuitry , including the POR, is turned
off and the device consumes less than 1 µA. When
exiti ng S hutdo wn m ode, t he device must requ ir e ad di-
tional time before a conversion can take place. During
this time, all internal analog circuitry must settle before
the first conversion can occur. An internal timer counts
32 internal clock periods before the internal oscillator
can provide clock to the conversion process. This
allows all internal analog circuitry to settle to their
prope r operating poi nt. This timi ng is typically less than
300 µs, which is negligible comp ared to one conversion
time (72.7 ms for MCP3551).
4.8 Sleep Mode
During Sle ep mo de, the devic e i s not co nv erti ng and i s
awaiting data retrieval; the internal analog circuitry is
still running and the device typically consumes 10 µA.
In order to restart a conversion while in Sleep mode,
toggling CS to a logic-high (placing the part in Shut-
down mode) and t hen back t o a logic-l ow will res tart the
conversion. Sleep can only be entered in Single
Conversion mode. Once a conversion is complete in
Single Conversion mode, the device automatically
enters Sleep mode.
VDD
2.2V
2.0V
0V
Reset Normal
Operation ResetStart-up
Time
300 µs
© 2007 Microchip Technology Inc. DS21950D-page 17
MCP3550/1/3
5.0 SERIAL INTERFACE
5.1 Overview
Serial communication between the microcontroller and
the MCP3550/1/3 devices is achieved using CS, SCK
and SDO/RDY. There are two modes of operation:
Single Conversion and Continuous Conversion. CS
controls the conversion start. There are 24 bits in the
data word : 22 bi t s of conv ers io n dat a and tw o overfl ow
bits. The conversion process takes place via the inter-
nal oscillator and the status of this conversion must be
detected. The typical method of communication is
shown in Figure 5-1. The status of the internal conver-
sion is the SDO/RDY pin and is available with CS low.
A High state on SDO/RDY means the device is busy
converting, while a Low state means the conversion is
finished and data is ready for transfer using SCK.
SDO/RDY remains in a high-impedance state when
CS is hel d hi gh. CS must be low wh en clocking o ut th e
data using SCK and SDO/RDY.
Bit 22 is Overflow High (OVH) when VIN > VRE F – 1 LSB,
OVH toggles to logic1’, detecting an overflow high in
the analog input voltage.
Bit 23 is Overflow Low (OVL) when VIN < -V REF, OVL
toggles to logic 1’, detecting an overflow low in the
analog input voltage. The state OVH = OVL = ‘1’ is not
defined and should be considered as an interrupt for
the SPI interfa ce me ani ng erron eo us co mm uni ca tion.
Bit 21 to bit 0 represents the output code in 22-bit
binary two's complement. Bit 21 is the sign bit and is
logic ‘0’ when the differential analog input is positive
and logic ‘1’ when the differential analog input is
negative. From Bit 20 to bit 0, the output code is given
MSb first (MSb is bit 20 and LSB is Bit 0). When the
analog input value is comprised between -VREF and
VREF 1 LSB, the two overflow bits are set to logic ‘0’.
The relationship between input voltage and output
code is shown in Figure 5-1.
The delta-sigma modulator saturation point for the
differential analog input is located at around ±112% of
VREF (at ro om te mp erature), meanin g t hat the modul a-
tor will still give accurate output codes with an over-
range of 12% below or above the reference voltage.
Unlike the usual 22-bit device, the 22-bit output code
will not lock at 0x1FFFFF for positive sign inputs or
0x200000 for negative sign inputs in order to take
advantage of the overrange capabilities of the device.
This can be practical for closed-loop operations, for
instance. In case of an overflow, the output code
becomes a 23-bit two's complement output code,
where the sign bit will be the OVL bit. If an overflow high
or low is detected, OVL (bit 23) becomes the sign bit
(instead of bit 21), the MSb is then bit 21 and the con-
vert er ca n be us ed as a 23 - bit t wo' s co mp l em ent co de
converter, with output code from bits B21 to B0, and
OVL as the sign bit. Figure 5-1 summarizes the output
coding data format with or without overflow high and
low.
FIGURE 5-1: Typical Serial Device Communication and Example Digital Output Codes for Specific
Analog Input Voltages.
CS
SCK
DOO21 20 19 18 17 16 15 14 13 12 11 10 9 87654321 0
READY HLR HI-Z
SDO/RDY
MCP3550/1/3
DS21950D-page 18 © 2007 Microchip Technology Inc.
5.2 Controlling Internal Conversions
and the Internal Oscillator
During Shutdown mode, on the falling edge of CS, the
conversion process begins. During this process, the
inter nal oscillator cl ocks the delt a-sigma mod ulator and
the SINC filter until a conversion is complete. This
conversion time is tCONV and the timing is shown in
Figure 5-2. At the end of tCONV, the digital filter has
settled complete ly and the re is n o latency in volved w ith
the digital SINC filter of the MCP3550/1/3.
The two modes of conversion for the MCP3550/1/3
devices are Single Conversion and Continuous
Conve rsion. In Single Conve rsion mo de, a consecu tive
convers ion wi ll not autom atica lly b egin. Instea d, after a
single conversion is complete and all four filters have
settled , the device put s the data into the output reg ister
and enters shutd own.
In Continuous Conversion mode, a consecutive
conversion will be automatic. In this mode, the device
is continuously converting, independent of the serial
interface. The most recent conversion data will always
be availab le in the Ou tput register.
When the device exits Shutdown, there is an internal
power-up delay that must be observed.
FIGURE 5-2: Single Conversion Mode.
FIGURE 5-3: Continuous Conversion Mode.
CS
Int. Osc
tCONV Sleep Shutdown
SCK (opt)
SDO/RDY Hi-Z Hi-Z
x24
CS
Int. Osc
tCONV
Shutdown
SCK (opt)
tCONV tCONV
SDO/RDY Hi-Z
x24
© 2007 Microchip Technology Inc. DS21950D-page 19
MCP3550/1/3
5.3 Single Conversion Mode
If a ris ing ed ge of Chip Select (CS) occurs during tCONV,
a subsequent conversion will not take place and the
device will enter low-power Shutdown mode after
tCONV completes. This is referred to as Single
Conversion mode. This operation is demonstrated in
Figure 5-3. Note that a falling edge of CS during the
same conversion that detected a rising edge, as in
Figure 5-2, will not initiate a new conversion. Once a
rising edge is seen, the device will enter Sleep, then
Shutdown mode. Once the device has been put into
Single C onve rsion m ode, the dat a mus t be clo cked out
in order for a new conversion to take place. A
subseq uent fal ling edg e on CS during Shutdown mode
will not initiate a new conversion, unless the prior
conversion data has been clocked out of the device.
After the fin al data bit has be en clocked o ut on the 25 th
clock, the SDO/RDY pin will go active-high.
5.3.1 READY FUNCTION OF SDO/RDY
PIN, SINGLE CONVERSION MODE
At every falling edge of CS during the internal conver-
sion, the state of the internal conversion is latched on
the SDO/RDY pin to give ready or busy information. A
High st ate me ans the dev ice is cu rrently performin g an
internal conversion and data cannot be clocked out. A
Low s tat e means the devi ce has finish ed its conver sion
and t he d at a is read y f or retrieval on the fal lin g ed ge of
SCK. This operation is demonstrated in Figure 5-4.
Note that the device has been put into Single
Conversion mode with the first rising edge of CS.
FIGURE 5-4: RDY Functionality in Single
Conversion Mode.
5.4 Continuous Conversion Mode
If no rising edg e of CS occ urs durin g any giv en co nver-
sion per Figure 5-2, a subsequent conversion will take
place and the contents of the previous conversion will
be overwritten. This operation is demonstrated in
Figur e 5-5. O nce conv ersio n outpu t dat a has s ta rted to
be clocked out, the output buffer is not refreshed until
all 24 bits have been clocked. A complete read must
occur in order to read th e next conve rsion in thi s mode.
The su bsequent co nversion d ata to b e read wil l then be
the most recent conversion. The conversion time is
fixed an d cannot be shortened by the risin g edge of CS.
This rising edge will place the part in Shutdown mode
and all conversion data will be lost.
The transfer of data from the SINC filter to the output
buffer is demonstrated in Figure 5-5. If the previous
conversion data is not clocked out of the device, it will
be lost and replaced by the new conversion. When the
device is in Continuous Conversion mode, the most
recent conversion data is always present at the output
register for data retrieval.
FIGURE 5-5: Mo st Cur rent C ontinuo us
Conversion Mode Data.
If a conversion is in process, it cannot be terminated
with the rising edge of CS. SDO/RDY must first
transition to a Low state, whic h will indicate the end of
conversion.
5.4.1 READY FUNCTION OF SDO/RDY
PIN IN CONTINUOUS CONVERSION
MODE
The device enters Continuous Conversion mode if no
rising edge of CS is seen during tCONV and consecu-
tive conversions ensue. SDO/RDY will be high,
indicating that a conversion is in process. When a
conversion is complete, SDO/RDY will change to a
Low state. With the Low state of SDO/RDY after this
first conversion, the conversion data can be accessed
with the com binati on of SCK and SDO/RD Y. If the data
ready event happens during the clocking out of the
data, the data ready bit will be displayed after the
complete 24-bit word communication (i.e., the data
ready event will not interrupt a data transfer).
Note: The R ea dy st at e is latc he d on eac h fal lin g
edge of CS and will not dynamically
update if CS is held low. CS must be
toggled high through low.
tCONV
CS
Int. Osc
SDO/RDY Hi-Z
tCONV
tCONV tCONV
CS
Int. Osc
SCK & SDO/RDY
ABC
Conversion B data is clocked
out of the device here.
MCP3550/1/3
DS21950D-page 20 © 2007 Microchip Technology Inc.
If 24 bits o f data a re required from this conversi on, they
must be ac c ess ed duri ng this communication. You can
terminate data transition by bringing CS high, but the
remaini ng data wil l be lost and the con verter will go into
Shutdown mode. Once the data has been transmitted
by the converter, the SDO/RDY pin will remain in the
LSB state until the 25th falling edge of SCK. At this
point, SDO/RDY is released from the Data Acquisition
mode and changed to the RDY state.
5.4.2 2-WIRE CONTINUOUS
CONVERSION OPERATION,
(CS TIED PERMANEN TLY LOW)
It is p ossible to use o nly two w ires to c ommunicat e with
the MCP3550/1/3 devices. In this state, the device is
always in Continuous Conversion mode, with internal
conversions continuously occurring. This mo de can be
enter ed by h aving CS lo w during power-up or c hanging
it to a l ow position after p ower-up. If CS is low at power-
up, the first conversion of the converter is initiated
approximately 300 µs after the power supply has
stabilized.
Note: The RDY state is not latched to CS in this
mode; the RDY flag dynamically updates
on the SDO/RDY pin and remains in this
state until data is clocked out using the
SCK pin.
© 2007 Microchip Technology Inc. DS21950D-page 21
MCP3550/1/3
5.5 Using The MCP3550/1/3 with
Microcontroll er (MCU) SPI Ports
It is req uired that the m icrocontroller SPI port be confi g-
ured to clock out data on the falling edge of clock and
latch data in on the rising edge. Figure 5-6 depicts the
operation shown in SPI mode 1,1, which requires that
the SCK from the MCU idles in the High state, while
Figure 5-7 shows the similar case of SPI Mode 0,0,
where the clock idles in the Low state. The waveforms
in the figures are examples of an MCU operating the
SPI port in 8-bit mode, and the MCP3550/1/3 devices
do not require data in 8-bit groups.
In SPI mode 1,1, data is read using only 24 clocks or
three byte transfers. The data ready bit must be read
by testing the SDO/RDY line prior to a falling edge of
the cl ock.
In SPI mode 0,0, data is read using 25 clocks or four
byte transfers. Please note that the data ready bit is
included in the transfer as the first bit in this mode.
FIGURE 5-6: SPI Communication – Mode 1,1.
FIGURE 5-7: SPI Communication – Mode 0,0.
CS
SCK
SDO/RDY
MCU
Data stored into MCU receive
register after transmission of
first byte
Receive
Buffer
Data stored into MCU receive
register after transmission of
second byte
Data stored into MCU receive
register after transmission of
third byte
DOO
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7654321 0
OL OH 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RHL
CS
SCK
SDO/RDY
MCU
Data stored into MCU receive
register after transmission of
first byte
Receive
Buffer
Data stored into MCU receive
register after transmission of
second byte
Data stored into MCU receive
register after transmission of
third byte
Data stored into MCU receive
register after transmission of
fourth byte
DR OO21 20 19 18 17 16 14 1312 11 10 9 65432 0
OH OL 21 20 19 18 17 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0
DR
8
16
15 7
8
1
HL
MCP3550/1/3
DS21950D-page 22 © 2007 Microchip Technology Inc.
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free J EDEC designa tor ( )
can be found on the outer packaging for this package.
Note: In the ev ent the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
8-Lead SOIC (150 mil) Examples:
XXXXXXXX
XXXXYYWW
NNN
MCP3551E
SN^^ 0715
256
8-Lead MSOP Example:
XXXXXX
YWWNNN 3553E
715256
3
e
3
e
© 2007 Microchip Technology Inc. DS21950D-page 23
MCP3550/1/3
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]
N
otes:
1
. Pin 1 visual index feature may vary, but must be located within the hatched area.
2
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not ex ceed 0.15 mm per side.
3
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A 1.10
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 0.15
Overall Width E 4.90 BSC
Molded Package Width E1 3.00 BSC
Overall Length D 3.00 BS C
Foot Length L 0.40 0 .60 0.80
Footprint L1 0.95 REF
Foot Angle φ
Lead Thickness c 0.08 0.23
Lead Width b 0.22 0. 40
D
N
E
E1
NOTE 1
12
e
b
A
A1
A2
c
L1 L
φ
Microchip Technology Drawing C04-111
B
MCP3550/1/3
DS21950D-page 24 © 2007 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
N
otes:
1
. Pin 1 visual index feature may vary, but must be located within the hatched area.
2
. § Significant Characteristic.
3
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not ex ceed 0.15 mm per side.
4
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 1.75
Molded Package Thickness A2 1.25
Standoff §A1 0.10 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BS C
Chamfer (optional) h 0.25 0.50
Foot Length L 0.40 1. 27
Footprint L1 1.04 REF
Foot Angle φ
Lead Thickness c 0.17 0.25
Lead Width b 0.31 0. 51
Mold Draft Angle Top α 15°
Mold Draft Angle Bottom β 15°
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
Microchip Technology Drawing C04-057
B
© 2007 Microchip Technology Inc. DS21950D-page 25
MCP3550/1/3
APPENDIX A: REVISION HISTORY
Revision A (September 2005)
Original Release of this Document.
Revision B (October 2005)
Changed LSb refefences to LSB.
Revision C (December 2005)
Added MCP3550-50, MCP3550-60 references
throughout this document.
Revision D (January 2007)
This update includes revisions to the packaging
diagrams.
MCP3550/1/3
DS21950D-page 26 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS21950D-page 27
MCP3550/1/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP3550-50: Single Channel 22-Bit Delta-Sigma ADC
MCP3550T-50: Single Channel 22-Bit Delta-Sigma ADC
(Tape and Reel)
MCP3550-60: Single Channel 22-Bit Delta-Sigma ADC
MCP3550T-60: Single Channel 22-Bit Delta-Sigma ADC
(Tape and Reel)
MCP3551: Single Channel 22-Bit Delta-Sigma ADC
MCP3551T: Single Channel 22-Bit Delta-Sigma ADC
(Tape and Reel)
MCP3553: Single Channel 22-Bit Delta-Sigma ADC
MCP3553T: Single Channel 22-Bit Delta-Sigma ADC
(Tape and Reel)
Temperature Range: E = -40°C to +125°C
Package: MS = Plastic MSOP, 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
PART NO. –X /XX
PackageTemperature
Range
Device
Examples:
a) MCP3550-50-E/MS: Extended Temp.,
8LD MSOP.
b) MCP3550/1T-50E/MS:Tape and Reel,
Extend ed Temp.,
8LD MSOP.
c) MCP3550-60-E/SN: Ext ended Temp.,
8LD SOIC.
d) MCP3550/1T-60E/SN:Tape and Reel ,
Extend ed Temp.,
8LD SOIC.
a) MCP3551-E/MS: Extended Temp.,
8LD MSOP.
b) MCP3551T-E/MS: Tape and Reel,
Extend ed Temp.,
8LD MSOP.
c) MCP3553-E/SN: Extended Temp.,
8LD SOIC.
d) MCP3553T-E/SN: Tape and Reel,
Extend ed Temp.,
8LD SOIC.
MCP3550/1/3
DS21950D-page 28 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS21950D-page 29
Information contained in this publication regarding device
applications and the like is provided on ly for your c onvenience
and may be supersed ed by upda t es . It is y our respo ns i bil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC , Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInf o, PowerMate, Pow erTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Inco rporated, Pr inted in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their par ticular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure famili es of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal m ethods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellec tual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving the c ode prot ection f eatures of our
products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
T empe, Arizona, Gresham, Oregon and Mountain View , California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS21950D-page 30 © 2007 Microchip Technology Inc.
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