DUAL IN-LINE PACKAGES CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz Q-TECH CORPORATION Description Q-Tech's Dual In-line (DIP) crystal oscillators consist of a source clock square wave generator, logic output buffers and/or logic divider stages, and a round AT high-precision quartz crystal built in a metal through-hole package in DIP-8 or DIP-14 configurations. Features * Made in the USA * ECCN: EAR99 * DFARS 252-225-7014 Compliant: Electronic Component Exemption * USML Registration # M17677 * Wide frequency range from 0.01Hz to 200MHz * Available as QPL MIL-PRF-55310/8, /11, /14, /15, /16, /17, /18, /25, and /26 * Wide operating temperature range * Choice of output logic options * Supply voltages from 1.8Vdc to 15Vdc * Lower or higher supply voltages available * All metal hermetically sealed package * Tight or custom symmetry available * Fast rise and fall times * Fast start-up time * Capacitive load drive capability (Z output) * Multiple outputs available * Fundamental and third overtone designs * High operating temperature up to +225C * Custom design available tailors to meet customer's needs * Q-Tech does not use pure lead or pure tin in its products * RoHS compliant Ordering Information Sample part number QT6HCD9M-20.000MHz QT 6 HC D 9 M - 20.000MHz T = Standard S = Solder Dip (*) Output frequency Model # (See page 3) C AC HC T L N R E EH EF PE LP Z = = = = = = = = = = = = = CMOS +5V to +15V (**) ACMOS +5V HCMOS +5V TTL +5V LVHCMOS +3.3V LVHCMOS +2.5V LVHCMOS +1.8V 10K ECL -5.2V 10KH ECL -5.2V 100K/300K ECL -4.5V PECL +5V PECL +3.3V Z output Tristate Option D (Left blank if no Tristate) Screened to MIL-PRF-55310,level B (Left blank if no screening) 1 3(***) 4 5 6 9 10 11 12 = = = = = = = = = 100ppm 5ppm 50ppm 25ppm 50ppm 50ppm 100ppm 50ppm 100ppm at at at at at at at at at 0C 0C 0C -20C -55C -55C -55C -40C -40C to +70C to +50C to +70C to +70C to +105C to +125C to +125C to +85C to +85C (*) Hot Solder Dip Sn60 per MIL-PRF 55310 is optional for an additional cost (**) Please specify supply voltage when ordering CMOS (***) Requires an external capacitor Frequency stability vs. temperature codes may not be available in all frequencies. Q-Tech will assign a custom part number for custom specifications and all high temperature applications with typical frequency stability at 250ppm up to +200C. For Non-Standard requirements, contact Q-Tech Corporation at Sales@Q-Tech.com Applications * Designed to meet today's requirements for all voltage applications * Wide military clock applications * Smart munitions * Navigation * Industrial controls * Microcontroller driver * Down-hole applications up to +225C Packaging Options * Standard packaging in black foam * Optional anti-static plastic tube Other Options Available For An Additional Charge * Lead forming available on all packages. Please contact for details. * P. I. N. D. test (MIL-STD 883, Method 2020) * Lead trimming All DIP packages are available in surface mount form. Specifications subject to change without prior notice. Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Dual In-line Packages (Revision E, August 2010) (ECO# 9933) 1 DUAL IN-LINE PACKAGES CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz Q-TECH CORPORATION Electrical Characteristics Parameters Output freq. range (Fo) C AC HC T L (*) ECL / PECL (**) DIP 14 0.01Hz -- 15MHz 0.01Hz -- 160MHz 0.01Hz -- 160MHz 0.01Hz -- 160MHz 0.01Hz -- 160MHz 1MHz -- 200MHz DIP 8 245Hz -- 15MHz 0.01Hz -- 85MHz 0.01Hz -- 85MHz 10Hz -- 85MHz 0.01Hz -- 100MHz Supply voltage (Vdd) Maximum Applied Voltage (Vdd max.) 5V ~ 15Vdc 10% 5.0Vdc 10% 3.3Vdc 10% -0.5 to +18Vdc -0.5 to +7.0Vdc -0.5 to +5.0Vdc Freq. stability (F/T) See Option codes Operating temp. (Topr) See Option codes Storage temp. (Tsto) Operating supply current (Idd) (No Load) 1MHz -- 110MHz -5.2Vdc 5% (10K / 10KHECL) 5Vdc 5% (PECL) 3.3Vdc 5% (LVPECL) 0 to -8.0Vdc (10K / 10KHECL) 0 to +8.0Vdc (PECL) 0 to +5.0Vdc (LVPECL) -62C to + 125C F and Vdd dependent 3 mA max. at 5V up to 5MHz 25 mA max. at 15V up to 15MHz Symmetry (50% of ouput waveform or 1.4Vdc for TTL) 20 mA max. - 0.01Hz ~ 25 mA max. - 16MHz ~ 35 mA max. - 40MHz ~ 45 mA max. - 60MHz ~ 55 mA max. - 85MHz ~ 65 mA max. - 110MHz ~ 75 mA max. - 125MHz ~ < 16MHz < 40MHz < 60MHz < 85MHz < 110MHz < 125MHz 160MHz 3 mA max. - 0.01Hz ~ < 500kHz 6 mA max. - 500kHz ~ < 16MHz 10 mA max. - 16MHz ~ < 32MHz 20 mA max. - 32MHz ~ < 60MHz 30 mA max. - 60MHz ~ < 100MHz 40 mA max. - 100MHz ~ < 130MHz 50 mA max. - 130MHz ~ 160MHz 45/55% max. Fo < 4MHz 40/60% max. Fo 4MHz 45/55% max. Fo < 12MHz 40/60% max. Fo 12MHz 30ns max. 15ns max. Fo < 15kHz 6ns max. Fo 15kHz ~ 39.999MHz 3ns max. Fo 40MHz ~ 160MHz (Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL) Rise and Fall times (Tr/Tf) (with typical load) (Measured from 10% to 90%) 15pF // 10k Output Load 45/55% max. Fo < 12MHz 40/60% max. Fo 12MHz 3.5ns max. Fo < 125MHz 3ns max. Fo 125MHz ~ 200MHz (Measured from 20% to 80%) 15pF // 10k 10TTL Fo < 20MHz 6TTL Fo 20MHz Start-up time (Tstup) 45 mA max. - 1MHz ~ < 125MHz 75 mA max. - 125MHz ~ 200MHz 50 to -2V (10K / 10KH) 50 to Vcc -2V (P & LP) 10ms max. 0.9 x Vdd min.; 0.1 x Vdd max. -1.15V min; -1.54V max. (E) 4V min.; 3.37V max. (PE) 2.27V min.; 1.68V max. (LP) 2.4V min.; 0.4V max. 0.9 x Vdd min.; 0.1 x Vdd max. -1.6mA / TTL +40A / TTL 4mA . -50mA VIH 0.7 x Vdd Oscillation; VIL 0.3 x Vdd High Impedance Call for details 15ps typ. - < 40MHz 8ps typ. - 40MHz Integrated phase jitter 12kHz - 20MHz 1ps typ. Output voltage (Voh/Vol) Output Current (Ioh/Iol) 1mA typ. at 5V 6.8mA typ. at 15V Enable/Disable Tristate function Pin 1 Call for details 24mA 8 mA VIH 2.2V Oscillation; VIL 0.8V High Impedance 8ps typ. - < 40MHz 5ps typ. - 40MHz Jitter RMS 1 (at 25C) 5ppm max. first year / 2ppm typ. per year thereafter Aging (at 70C) DIP 14: QT6, QT18, QT41, QT42, QT47 DIP 8: QT50, QT51, QT55 Q-TECH Corporation (*) Available in 2.5Vdc (N) or 1.8Vdc (R) (**) Please contact Q-Tech for details on 100KECL logic (EF) Z Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf) - 10150 W. Jefferson Boulevard, Culver City 90232 Dual In-line Packages (Revision E, August 2010) (ECO# 9933) - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech .co m 2 DUAL IN-LINE PACKAGES CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz Q-TECH CORPORATION Package Configuration Versus Pin Connections DIP 14 A QT6 B QT18 C QT41 Q-TECH P/N FREQ. D/C S/N Q-TECH P/N FREQ. D/C S/N D QT42 Q-TECH P/N FREQ. D/C S/N Q-TECH P/N FREQ. D/C S/N Q-TECH P/N FREQ. D/C S/N .200 MAX. (5.08) .200 MAX. (5.08) .200 MAX. (5.08) .200 MAX. (5.08) .200 MIN. (5.08) .200 MIN. (5.08) .200 MIN. (5.08) .200 MIN. (5.08) .018 (.457) .600 .600 (15.24) (15.24) .018 (.457) .800 .880 MAX. (22.35) (20.32) .505 MAX. .300 (12.83) 7 1 7 14 14 8 .505 MAX. .300 (12.83) (7.62) .020 .080 .010 .600 (.508) (2.032.254) (15.24) .800 MAX. (20.32) MAX. 1 7 14 8 8 .300 (7.62) .800 (20.32) MAX. 4 .505 MAX. (12.83) .505 MAX. (12.83) .300 (7.62) 8 1 4 8 5 .505 MAX. .300 (12.83) (7.62) 5 .100 (2.54) .100 (2.54) .020 (.508) (.457) (20.32) (7.62) .011 (.279) .600 (15.24) .800 MAX. .200 MAX. .290 MAX. (5.08) (7.36) .018 (.457) .018 1 1 E QT47 .024 o .080 (o 2.03) (.609) .600 MAX (15.24) DIP 8 F QT50 G QT51 Q-TECH P/N FREQ. D/C S/N QT # Conf Vcc GND Case H QT55 QT4 A 4 7 7 Output (*) E/D or N/C Ext. Cap 5 1 10 & 11 1 /16 = QT6T /17 = QT6T** 10 & 11 /18 = QT6C /26A = QT6HC Q-TECH P/N FREQ. D/C S/N Q-TECH P/N FREQ. D/C S/N Equivalent MIL-PRF-55310 Configuration /14 = QT4T QT6 A 14 7 7 8 QT10 A 14 8 2 1 QT12 A 14 7 7 4 1 10 & 11 N/A QT18 B 14 7 7 8 1 10 & 11 N/A QT41 C 14 7 7 8 1 N/A QT42 D 14 7 7 8 1 N/A N/A QT47 E 14 7 7 8 1 N/A N/A Package Information QT50 F 8 4 4 5 1 N/A N/A * Package material (header and leads): Kovar * Lead finish: Gold Plated - 50 ~ 80 inches Nickel Underplate - 100 ~ 250 inches * Package to lid attachment: Resistance weld * Cover (DIP-14): Pure Nickel Grade A (DIP-8): Stainless Steel * Weight (DIP-14): 3.4g typ.,14.2g max. (DIP-8): 2.0g typ., 14.2g max. QT51 G 8 4 4 5 1 N/A N/A QT55 H 8 4 4 5 1 N/A N/A .200 MAX. (5.08) .250 MIN. (6.35) 1 .018 .020 (.457) (.508) 8 .011 (.279) .018 .080 .010 1 (.457) 1 4 N/A 10 & 11 5 .300 (7.62) SQ. 8 /08 = QT10T /11 = QT10C /15 = QT10C 4 .505 SQ. MAX. .300 SQ. (12.83) (7.62) .505 SQ. MAX. (12.83) 8 5 .250 MIN. (6.35) .020 (.508) (2.032.254) 4 .300 (7.62) SQ. .200 MAX. (5.08) .200 MAX. .290 MAX. (5.080) (7.366) .505 SQ. MAX. (12.83) 5 .024 o .060 (o 1.52) (.609) .300 /26B = QT41HC (7.62) Dimensions are in inches (mm) (*) ECL / PECL complimentary output available on pin 9 (For QT6 and QT18 only) with a Q-Tech custom part number (**) Gated Output, gate control pin 9 Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Dual In-line Packages (Revision E, August 2010) (ECO# 9933) 3 DUAL IN-LINE PACKAGES CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz Q-TECH CORPORATION Output Waveform (Typical) Startup Time TH SYMMETRY = x 100% T TYPICAL SET-UP FOR START-UP TIME Tr Tf Variable Ramp Oscilloscope 54616B Agilent Vdd VOH 0.9xVdd DUT 0.5xVdd Ts 0.1xVdd VOL Start-up box GND TH T Test Circuit TYPICAL TEST CIRCUIT FOR QT6T3 (6TTL) +5VDC 0.01uF Typical test circuit for ECL logic. OUTPUT 430 mA GND OUT D1 14 OUT + 8 Vcc POWER SUPPLY + Vdc - - QT6T3 D2 50 0.1F or 0.01F 10k 10 11 12pF(*) 7 D3 D4 -2Vdc -4.5V or -5.2V GND Cext D1-D4: 1N4148 or equivalent (*) CL includes scope probe capacitance Typical test circuit for CMOS logic Vdd Typical test circuit for TTL logic. RL + mA + Power supply - Vdd Out + Vdc - + Output 0.1F or E/D GND 0.01F 15pF (*) mA + + POWER SUPPLY - 10k Vdd OUT OUT E/D GND Vdc - 0.1F or 0.01F CL Rs Ground Tristate Function (*) CL includes probe and jig capacitance The Tristate function on pin 1 has a built-in pull-up resistor typical 50k, so it can be left floating or tied to Vdd without deteriorating the electrical performance. LOAD 6 TTL CL(*) 12pF RL 430 RS 10k 10 TTL 20pF 270 6k (*) CL inclides the loading effect of the oscilloscope probe. Frequency vs. Temperature Curve Frequency Stability (PPM) 40 FREQUENCY VERSUS TEMPERATURE QT6L9M-64.5MHz 30 20 10 0 -10 -20 -30 -40 -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 Temperature (C) 1_5 2_5 3_5 Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Dual In-line Packages (Revision E, August 2010) (ECO# 9933) 4 DUAL IN-LINE PACKAGES CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz Q-TECH CORPORATION Thermal Characteristics The heat transfer model in a hybrid package is described in figure 1 (Based on single ASIC design) . D/A epoxy Die D/A epoxy 45 Heat spreading occurs when heat flows into a material layer of increased cross-sectional area. It is adequate to assume that spreading occurs at a 45 angle. The total thermal resistance is calculated by summing the thermal resistances of each material in the thermal path between the device and hybrid case. 45 Heat Hybrid Case R1 R2 Die D/A epoxy R3 Substrate R4 D/A epoxy R5 Hybrid Case (Figure 1) RT = R1 + R2 + R3 + R4 + R5 The total thermal resistance RT (see figure 2) between the heat source (die) to the hybrid case is the Theta Junction to Case (Theta JC) inC/W. T A CA * Theta junction to case (Theta JC) for this product is 24C/W. * Theta case to ambient (Theta CA) for this part is 105C/W. * Theta Junction to ambient (Theta JA) is 130C/W. T C T J Die JC Maximum power dissipation PD for this package at 25C is: * PD(max) = (TJ (max) - TA)/Theta JA * With TJ = 175C (Maximum junction temperature of die) * PD(max) = (175 - 25)/130 = 1.15W Substrate JA JC CA (Figure 2) Environmental Specifications Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our DIP packages. Q-Tech can also customize screening and test procedures to meet your specific requirements. The DIP packages are designed and processed to exceed the following test conditions: Environmental Test Temperature cycling Constant acceleration Seal: Fine and Gross Leak Burn-in Aging Vibration sinusoidal Shock, non operating Thermal shock, non operating Ambient pressure, non operating Resistance to solder heat Moisture resistance Terminal strength Resistance to solvents Solderability ESD Classification Moisture Sensitivity Level Test Conditions MIL-STD-883, Method 1010, Cond. B MIL-STD-883, Method 2001, Cond. A, Y1 MIL-STD-883, Method 1014, Cond. A and C 160 hours, 125C with load 30 days, 70C, 0.7ppm max MIL-STD-202, Method 204, Cond. D MIL-STD-202, Method 213, Cond. I MIL-STD-202, Method 107, Cond. B MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum MIL-STD-202, Method 210, Cond. C MIL-STD-202, Method 106 MIL-STD-202, Method 211, Cond. C MIL-STD-202, Method 215 MIL-STD-202, Method 208 MIL-STD-883, Method 3015, Class 1HBM 0 to 1,999V J-STD-020, MSL=1 Please contact Q-Tech for higher shock requirements Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Dual In-line Packages (Revision E, August 2010) (ECO# 9933) 5 DUAL IN-LINE PACKAGES CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz Q-TECH CORPORATION Period Jitter As data rates increase, effects of jitter become critical with its budgets tighter. Jitter is the deviation of a timing event of a signal from its ideal position. Jitter is complex and is composed of both random and deterministic jitter components. Random jitter (RJ) is theoretically unbounded and Gaussian in distribution. Deterministic jitter (DJ) is bounded and does not follow any predictable distribution. DJ is also referred to as systematic jitter. A technique to measure period jitter (RMS) one standard deviation (1) and peak-to-peak jitter in time domain is to use a high sampling rate (>8G samples/s) digitizing oscilloscope. Figure shows an example of peak-to-peak jitter and RMS jitter (1) of a QT6AC8-24MHz, at 5.0Vdc. Phase Noise and Phase Jitter Integration RMS jitter (1): 5.86ps Peak-to-peak jitter: 52.4ps Phase noise is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1Hz bandwidth at an offset frequency from the carrier, e.g. 10Hz, 100Hz, 1kHz, 10kHz, 100kHz, etc. Phase noise measurement is made with an Agilent E5052A Signal Source Analyzer (SSA) with built-in outstanding low-noise DC power supply source. The DC source is floated from the ground and isolated from external noise to ensure accuracy and repeatability. In order to determine the total noise power over a certain frequency range (bandwidth), the time domain must be analyzed in the frequency domain, and then reconstructed in the time domain into an rms value with the unwanted frequencies excluded. This may be done by converting L(f) back to S(f) over the bandwidth of interest, integrating and performing some calculations. Symbol Definition L(f) Integrated single side band phase noise (dBc) S (f)=(180/)x2 L(f)df Spectral density of phase modulation, also known as RMS phase error (in degrees) RMS jitter = S (f)/(fosc.360) Jitter(in seconds) due to phase noise. Note S (f) in degrees. The value of RMS jitter over the bandwidth of interest, e.g. 10kHz to 20MHz, 10Hz to 20MHz, represents 1 standard deviation of phase jitter contributed by the noise in that defined bandwidth. Figure below shows a typical Phase Noise/Phase jitter of a QT6AC8, 5.0Vdc, 24MHz and a QT50T, 5.0Vdc, 60 MHz clock at offset frequencies 10Hz to 5MHz, and phase jitter integrated over the bandwidth of 12kHz to 1MHz. QT6AC8, 5.0Vdc, 24MHz QT50T, 5.0Vdc, 60 MHz Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Dual In-line Packages (Revision E, August 2010) (ECO# 9933) 6