Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF51MM256 Rev. 5, 07/2012 An Energy-Efficient Solution from Freescale MCF51MM256/128 The MCF51MM256 series devices are members of the low-cost, low-power, high-performance ColdFire V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices. 80-LQFP 12mm x 12mm 81-BGA 10mm x 10mm 100-LQFP 14mm x 14mm 104-BGA 10mm x 10mm Not all features are available in all devices or packages; see Table 1 for a comparison of features by device. 32-Bit ColdFire V1 Central Processor Unit (CPU) * Up to 50.33 MHz ColdFire CPU above 2.4 V and 40 MHz CPU above 2.1V and 20 MHz CPU above 1.8 V across temperature range of -40C to 105C. * ColdFire Instruction Set Revision C (ISA_C). * 32-bit multiply and accumulate (MAC) supports signed or unsigned integer or signed fractional inputs. On-Chip Memory * 256 K Flash comprised of two independent 128 K flash arrays; read/program/erase over full operating voltage and temperature; allows interrupt processing while programming. * 32 KB System Random-access memory (RAM). * Security circuitry to prevent unauthorized access to RAM and Flash contents. Power-Saving Modes * Two ultra-low power stop modes. Peripheral clock enable register can disable clocks to unused modules to reduce currents. * Time of Day (TOD) -- Ultra low-power 1/4 sec counter with up to 64 sec timeout. * Ultra-low power external oscillator that can be used in stop modes to provide accurate clock source to the TOD. 6 s typical wake up time from stop3 mode. Clock Source Options * Oscillator (XOSC1) -- Loop-control Pierce oscillator; 32.768 kHz crystal or ceramic resonator dedicated for TOD operation. * Oscillator (XOSC2) for high frequency crystal input for MCG reference to be used for system clock and USB operations. * Multipurpose Clock Generator (MCG) -- PLL and FLL; precision trimming of internal reference allows 0.2% resolution and typical +0.5% to -1% deviation over temperature and voltage; supports CPU frequencies from 4 kHz to 50 MHz. 2.0. Allows control, bulk, interrupt and isochronous transfers. * SCIx -- Two serial communications interfaces with optional 13-bit break; option to connect Rx input to PRACMP output on SCI1 and SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge. * SPI1 -- Serial peripheral interface with 32-bit FIFO buffer; 16-bit or 8-bit data transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting. * SPI2 -- Serial peripheral interface with full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting. * IIC -- Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing. * CMT -- Carrier Modulator timer for remote control communications. Carrier generator, modulator and driver for dedicated infrared out (IRO). Can be used as an output compare timer. * TPMx -- Two 4-channel Timer/PWM Module; Selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; external clock input/pulse accumulator. * Mini-FlexBus -- Multi-function external bus interface with user programmable chip selects and the option to multiplex address and data lines. * PRACMP -- Analog comparator with selectable interrupt; compare option to programmable internal reference voltage; operation in stop3. Measurement Engine * Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock. * Low-voltage detection with reset or interrupt; selectable trip points; separate low voltage warning with optional interrupt; selectable trip points. * Illegal opcode and illegal address detection with reset. * Flash block protection for each array to prevent accidental write / erasure. * Hardware CRC to support fast cyclic redundancy checks. * ADC16 -- 16-bit successive approximation ADC with up to 4 dedicated differential channels and 8 single-ended channels; range compare function; 1.7 mV/xC temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V, Configurable hardware trigger for 8 Channel select and result registers. * PDB -- Programmable delay block with 16-bit counter and modulus and prescale to set reference clock to bus divided by 1 to bus divided by 2048; 8 trigger outputs for ADC module provides periodic coordination of ADC sampling sequence with sequence completion interrupt; Back-to-Back mode and Timed mode. * DAC -- 12-bit resolution DAC; configurable settling time. * OPAMPx -- 2 flexible operational amplifiers configurable for general operations; Low offset and temperature drift. * TRIAMPx -- 2 trans-impedance amplifiers dedicated for converting current inputs into voltages. Development Support Input/Output System Protection * Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM connection supports same electrical interface used by the S08 family debug modules. * Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1 data). * On-chip trace buffer provides programmable start/stop recording conditions. Peripherals * USB -- Dual-role USB On-The-Go (OTG) device, supports USB in either device, host or OTG configuration. On-chip transceiver and 3.3V regulator help save system cost, fully compliant with USB Specification (c) Freescale Semiconductor, Inc., 2009-2012. All rights reserved. * * * * * Up to 68 GPIOs and 1 output-only pin. Voltage Reference output (VREFO). Dedicated infrared output pin (IRO)with high current sink capability. Up to 16 KBI pins with selectable polarity. Up to 16 pins of rapid general purpose I/O (RGPIO). Table of Contents 1 2 3 4 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pinouts and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .17 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17 3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18 3.4 ESD Protection Characteristics. . . . . . . . . . . . . . . . . . .20 3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .23 3.7 PRACMP Electrical Parameters . . . . . . . . . . . . . . . . . .26 3.8 12-Bit DAC Electrical Parameters . . . . . . . . . . . . . . . . .26 3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.10 MCG and External Oscillator (XOSC) Characteristics .35 3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .38 3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.15 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .47 3.17 TRIAMP Electrical Parameters . . . . . . . . . . . . . . . . . . .49 3.18 OPAMP Electrical Parameters . . . . . . . . . . . . . . . . . . .50 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 4.1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .52 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 List of Figures Figure 1. MCF51MM256/128 Block Diagram . . . . . . . . . . . . . . . . 6 Figure 2. 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Stop IDD versus Temperature. . . . . . . . . . . . . . . . . . . 25 Figure 7. Offset at Half Scale vs Temperature . . . . . . . . . . . . . . 28 Figure 8. ADC Input Impedance Equivalency Diagram . . . . . . . 30 Figure 9. Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . 39 Figure 10.Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 39 Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . 42 Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . Figure 19.Typical VREF Output vs. Temperature . . . . . . . . . . . . Figure 20.Typical VREF Output vs. VDD. . . . . . . . . . . . . . . . . . . 44 44 45 45 48 48 List of Tables Table 1. MCF51MM256/128 Features by MCU and Package . . 3 Table 2. MCF51MM256/128 Functional Units . . . . . . . . . . . . . . . 6 Table 3. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 18 Table 6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 20 Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 20 Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10.Supply Current Characteristics . . . . . . . . . . . . . . . . . . 23 Table 11.Typical Stop Mode Adders. . . . . . . . . . . . . . . . . . . . . . 24 Table 12.PRACMP Electrical Specifications . . . . . . . . . . . . . . . 26 Table 13.DAC 12LV Operating Requirements . . . . . . . . . . . . . . 26 Table 14.DAC 12-Bit Operating Behaviors . . . . . . . . . . . . . . . . . 27 Table 15.16-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 28 Table 16.16-bit SAR ADC Characteristics full operating range (VREFH = VDDA > 1.8, VREFL = VSSA 8 Hz, -40 oC to 85 oC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17.16-bit SAR ADC Characteristics full operating range (VREFH = VDDA 2.7 V, VREFL = VSSA, fADACK 4 MHz, ADHSC=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 18.MCG (Temperature Range = -40 oC to 105 oC Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 19.XOSC Specifications (Temperature Range = -40 oC to 105 oC Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 20.Mini-FlexBus AC Timing Specifications . . . . . . . . . . . . 38 Table 21.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 22.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 23.SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 24.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 25.Internal USB 3.3 V Voltage Regulator Characteristics 46 Table 26.VREF Electrical Specifications . . . . . . . . . . . . . . . . . . 47 Table 27.VREF Limited Range Operating Behaviors . . . . . . . . . 47 Table 28.TRIAMP Electrical Characteristics 1.8-3.6 V, -40C~105C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 29.OPAMP Characteristics 1.8-3.6 V . . . . . . . . . . . . . . . . 50 Table 30.Orderable Part Number Summary. . . . . . . . . . . . . . . . 51 Table 31.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 32.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MCF51MM256/128, Rev. 5 2 Freescale Semiconductor Features 1 Features The following table provides a cross-comparison of the features of the MCF51MM256/128 according to package. Table 1. MCF51MM256/128 Features by MCU and Package Feature FLASH Size (bytes) MCF51MM256 MCF51MM128 262144 131072 32K 32K RAM Size (bytes) Pin Quantity 104 100 81 80 81 80 Programmable Analog Comparator (PRACMP) yes yes yes yes yes yes Debug Module (DBG) yes yes yes yes yes yes Multipurpose Clock Generator (MCG) yes yes yes yes yes yes Inter-Integrated Communication (IIC) yes yes yes yes yes yes Interrupt Request Pin (IRQ) yes yes yes yes yes yes Keyboard Interrupt (KBI) 16 16 16 16 16 16 1 69 65 48 47 48 47 Dedicated Analog Input Pins 14 14 14 14 14 14 Power and Ground Pins 8 8 8 8 8 8 Time Of Day (TOD) yes yes yes yes yes yes Serial Communications (SCI1) yes yes yes yes yes yes Digital General Purpose I/O Serial Communications (SCI2) yes yes yes yes yes yes Serial Peripheral Interface (SPI1(FIFO)) yes yes yes yes yes yes Serial Peripheral Interface(SPI2) yes yes yes yes yes yes Carrier Modulator Timer Pin (IRO) yes yes yes yes yes yes TPM Input Clock Pin (TPMCLK) yes yes yes yes yes yes TPM1 Channels 4 4 4 4 4 4 TPM2 Channels 4 4 4 4 4 4 yes yes yes yes yes yes XOSC1 XOSC2 yes yes yes yes yes yes USB On-the-Go yes yes yes yes yes yes Mini-FlexBus yes yes DATA2 DATA2 DATA2 DATA2 Rapid GPIO 16 16 9 9 9 9 MEASUREMENT ENGINE Programmable Delay Block (PDB) yes yes yes yes yes yes 16-Bit SAR ADC Differential Channels 4 4 4 4 4 4 16-Bit SAR ADC Single-Ended Channels 8 8 8 8 8 8 3 DAC Ouput Pin (DACO) yes yes yes yes yes yes Voltage Reference Output Pin (VREFO) yes yes yes yes yes yes General Purpose Operational Amplifier (OPAMP) yes yes yes yes yes yes Trans-Impedance Amplifier (TRIAMP) yes yes yes yes yes yes 1 2 3 Port I/O count does not include BLMS, BKGD and IRQ. BLMS and BKGD are Output only, IRQ is input only. The 80/81 pin packages contain the Mini-FlexBus data pins to support an 8-bit data bus interface to external peripherals. Each differential channel is comprised of 2 pin inputs. MCF51MM256/128, Rev. 5 Freescale Semiconductor 3 COCOx VREFH/VREFL VREFO ADC16 DADP/M [3:0] HWTS[H:A] AD[11:4] DADP/M[3:0] VDDA/VSSA VREFH/VREFL VREFO DACO PDB HWTS[H:A] Dtrig Port A VDDA/VSSA ACMPO Dtrig DACO OPAMP2 INP1INP1+ OUT1 VREFH/VREFL VINP0 VINN0 TRIOUT0 TRIAMP1 VINN0/VINP0 VINP1 VINN1 TRIAMP2 SCI2 RX2 TX2 IIC SDA SCL TRIOUT1 KBI1 & KBI2 VREF VREFO RX1 TX1 TRIOUT0 TRIOUT1 VINN1/VINP1 SCI1 IRO KBI1P[7:0] KBI2P[7:0] TPM1CH [3:0] TPMCLK IRO CMT TPM1 (4-Ch) Hardware CRC DBG BDM Port D OUT1 INP1- ACMPO TPM2CH [3:0] TPMCLK Port E OUT0 INP0- Port C OPAMP1 INP0INP0+ OUT0 Port B PRACMP VDDA/VSSA TPM2 (4-Ch) RGPIO[15:8] SPI1 SPI2 PTD1/CMPP2/ RESET SIM IRCLK Clock Check & Select MOSI1 SS1 MISO1 SPSCK1 Port G V1 ColdFire Core with MAC REF CLK MOSI2 SS2 MISO2 SPSCK2 PTE4/CMPP3/ TPMCLK/IRQ XOSC2 LVD IRQ FB_AD12 FLASH1 128/64 KB FLASH2 128/64 KB RAM Robust Update Manager FB_D[7:0] FB_AD[19:0] USB_DM USB_DP USB_ALTCLK USB_PULLUP(D+) USB_DM_DOWN USB_DP_DOWN USB_VBUSVLD USB_ID USB_SESSVLD USB_SESSEND 32KB VDD1,2,3 VSS1,2,3 EXTAL1 XTAL1 USBOTG VREG USB_DM USB_DP CLKO VUSB33 XOSC1 VBUS CLKO control COP MINIFLEX BUS Port F MCG Port A: RGPIO[7:0] Port H RGPIO TOD Port J INTC control BKGD/MS PTD0/BKGD/MS PTA7/INP1+ PTA6 PTA5 PTA4/INP0+ PTA3/KBI1P2/FB_D6/ADP5 PTA2/KBI1P1/RX1/ADP4 PTA1/KBI1P0/TX1/FB_D1 PTA0/FB_D2/SS1 PTB7/KBI1P4/RGPIOP1/FB_AD0 PTB6/KBI1P3/RGPIOP0/FB_AD17 PTB5/XTAL2 PTB4/EXTAL2 PTB3/XTAL1 PTB2/EXTAL1 PTB1/BLMS PTB0 PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2/FB_D0/FB_AD1 PTC0/MOSI2/FB_OE_b/FB_CS0 PTD7/USB_PULLUP(D+)/RX1 PTD6/USB_ALTCLK/TX1 PTD5/SCL/RGPIOP11/TPM1CH3 PTD4/SDA/RGPIOP10/TPM1CH2 PTD3/USB_PULLUP(D+)/RGPIOP9/ TPM1CH1 PTD2/USB_ALTCLK/RGPIOP8/ TPM1CH0 PTE7/USB_VBUSVLD/TPM2CH3 PTE6/FB_RW_b/USB_SESSEND/RX2 PTE5/FB_D7/USB_SESSVLD/TX2 PTE3/KBI2P6/FB_AD8 PTE2/KBI2P5/RGPIOP14/FB_AD7 PTE1/KBI2P4/RGPIOP13/FB_AD6 PTE0/KBI2P3/FB_ALE/FB_CS1 PTF7/MISO1 PTF6/MOSI1 PTF5/KBI2P7/FB_D3/FB_AD9 PTF4/SDA/FB_D4/FB_AD10 PTF3/SCL/FB_D5/FB_AD11 PTF2/TX2/USB_DM_DOWN/TPM2CH0 PTF1/RX2/USB_DP_DOWN/TPM2CH1 PTF0/USB_ID/TPM2CH2 PTG7/FB_AD18 PTG6/FB_AD19 PTG5/FB_RW_b PTG4/USB_SESSVLD PTG3/USB_DP_DOWN PTG2/USB_DM_DOWN PTG1/USB_SESSEND PTG0/SPSCK1 PTH7/RGPIOP7/FB_D2 PTH6/RGPIOP6/FB_D3 PTH5/RGPIOP5/FB_D4 PTH4/RGPIOP4/FB_D5 PTH3/RGPIOP3/FB_D6 PTH2/RGPIOP2/FB_D7 PTH1/FB_D0 PTH0/FB_OE_b PTJ7/FB_AD13 PTJ6/FB_AD14 PTJ5/FB_AD15 PTJ4/RGPIOP15/FB_AD16 PTJ3/RGPIOP12/FB_AD5 PTJ2/FB_AD4 PTJ1/FB_AD3 PTJ0/FB_AD2 Green -- pins not available on the 100, 81 or 80-pin package Blue -- pins not available on the 81 or 80-pin package Red -- pin not available on the 80-pin package Figure 1. MCF51MM256 Series Block Diagram MCF51MM256/128, Rev. 5 4 Freescale Semiconductor Features The following table describes the functional units of the MCF51MM256/128. Table 2. MCF51MM256/128 Functional Units Unit Function DAC (digital to analog converter) -- Used to output voltage levels. 16-BIT SAR ADC (analog-to-digital converter) -- Measures analog voltages at up to 16 bits of resolution. The ADC has up to four differential and 8 single-ended inputs. Measurement Engine OPAMP -- General purpose op amp used for signal filtering or amplification. TRIAMP --- Transimpedance amplifier optimized for converting small currents into voltages. Measurement Engine PDB -- The measurement engine PDB is used to precisely trigger the DAC and the ADC modules to complete sensor biasing and measuring. Mini-FlexBus Provides expansion capability for off-chip memory and peripherals. USB On-the-Go Supports the USB On-the-Go dual-role controller. CMT (Carrier Modulator Timer) Infrared output used for the Remote Controller operation. MCG (Multipurpose Clock Generator) Provides clocking options for the device, including a phase-locked loop (PLL) and frequency-locked loop (FLL) for multiplying slower reference clock sources. BDM (Background Debug Module) Provides single pin debugging interface (part of the V1 ColdFire core). CF1 CORE (V1 ColdFire Core) Executes programs and interrupt handlers. PRACMP Analog comparators for comparing external analog signals against each other, or a variety of reference levels. COP (Computer Operating Properly) Software Watchdog. IRQ (Interrupt Request) Single-pin high-priority interrupt (part of the V1 ColdFire core). CRC (Cyclic Redundancy Check) High-speed CRC calculation. DBG (Debug) Provides debugging and emulation capabilities (part of the V1 Co ldFire. core) FLASH (Flash Memory) Provides storage for program code, constants, and variables. IIC (Inter-integrated Circuits) Supports standard IIC communications protocol and SMBus. INTC (Interrupt Controller) Controls and prioritizes all device interrupts. KBI1 & KBI2 Keyboard Interfaces 1 and 2. LVD (Low-voltage Detect) Provides an interrupt to theColdFire V1 CORE in the event that the supply voltage drops below a critical value. The LVD can also be programmed to reset the device upon a low voltage event. VREF (Voltage Reference) The Voltage Reference output is available for both on- and off-chip use. RAM (Random-Access Memory) Provides stack and variable storage. RGPIO (Rapid General-purpose Input/output) Allows for I/O port access at CPU clock speeds. RGPIO is used to implement GPIO functionality. MCF51MM256/128, Rev. 5 Freescale Semiconductor 5 Features Table 2. MCF51MM256/128 Functional Units (continued) Unit SCI1, SCI2 (Serial Communications Interfaces) Function Serial communications UARTs capable of supporting RS-232 and LIN protocols. SIM (system integration unit) SPI1 (FIFO), SPI2 (Serial Peripheral Interfaces) SPI1 and SPI2 provide standard master/slave capability. SPI contains a FIFO buffer in order to increase the throughput for this peripheral. TPM1, TPM2 (Timer/PWM Module) Timer/PWM module can be used for a variety of generic timer operations as well as pulse-width modulation. VREG (Voltage Regulator) Controls power management across the device. These devices incorporate redundant crystal oscillators. One is XOSC1 and XOSC2 (Crystal Oscillators) intended primarily for use by the TOD, and the other by the CPU and other peripherals. MCF51MM256/128, Rev. 5 6 Freescale Semiconductor Pinouts and Pin Assignments 2 Pinouts and Pin Assignments 2.1 104-Pin MAPBGA The following figure shows the 104-pin MAPBGA pinout configuration. 1 2 3 4 5 6 7 8 9 10 11 A PTF6 PTF7 USB_DP USB_DM VUSB33 PTF4 PTF3 FB_AD12 PTJ7 PTJ5 PTJ4 A B PTG0 PTA0 PTG3 VBUS PTF5 PTJ6 PTH0 PTE5 PTF0 PTF1 PTF2 B C IRO PTG4 PTA6 PTG2 PTG6 PTG5 PTG7 PTH1 PTE4 PTE6 PTE7 C D PTA5 PTA4 PTB1 VDD1 VDD3 PTA1 PTE3 PTE2 D E VSSA PTA7 PTB0 PTA2 PTJ3 PTE1 E F VREFL INP1- INP2- PTJ2 PTJ0 PTJ1 F TRIOUT1 OUT1 OUT2 PTD5 PTD7 PTE0 G VINP1 VINN1 PTA3 VSS1 VSS3 PTD4 PTD3 PTD2 H J DADP0 DADM0 PTH7 PTH6 PTH4 PTH3 PTH2 PTD6 PTC2 PTC0 PTC1 J K VINP2 VINN2 DADP1 PTH5 PTB6 PTB7 PTC3 PTD1 PTC4 PTC5 PTC6 K L TRIOUT2 DACO DADM1 VREFO VREFH VDDA PTB3 PTB2 PTD0 PTB5 PTB4 L 1 2 3 4 5 6 7 8 9 10 11 G H VDD2 PTG1 PTC7 VSS2 Figure 2. 104-Pin MAPBGA MCF51MM256/128, Rev. 5 Freescale Semiconductor 7 Pinouts and Pin Assignments 2.2 100-Pin LQFP PTA0/FB_D2/SS1 IRO PTG5/FB_RW PTG6/FB_AD19 PTG7/FB_AD18 PTH0/FB_OE PTH1/FB_D0 PTA1/KBI1P0/TX1/FB_D1 PTA2/KBI1P1/RX1/ADP4 PTA3/KBI1P2/FB_D6/ADP5 PTA4/INP1+ PTA5 PTA6 PTA7/INP2+ PTB0 PTB1/BLMS VSSA VREFL INP1OUT1 TRIOUT1/DADP2VINP1 VINN1/DADM2 INP2- PTE7/USB_VBUSVLD/TPM2CH3 PTE6/FB_RW/USB_SESSEND/RX2 PTE5/FB_D7/USB_SESSVLD/TX2 VDD3 VSS3 PTF0/USB_ID/TPM2CH2 PTJ4/RGPIOP15/FB_AD16 PTF2/TX2/USB_DM_DOWN/TPM2CH0 PTF1/RX2/USB_DP_DOWN/TPM2CH1 PTF5/KBI2P7/FB_D3/FB_AD9 PTF4/SDA/FB_D4/FB_AD10 PTF3/SCL/FB_D5/FB_AD11 FB_AD12 PTJ7/FB_AD13 PTJ6/FB_AD14 PTJ5/FB_AD15 VSS1 VBUS USB_DP USB_DM VUSB33 VDD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 LQFP PTE4/CMPP3/TPMCLK/IRQ PTE3/KBI2P6/FB_AD8 PTE2/KBI2P5/RGPIOP14/FB_AD7 PTE1/KBI2P4/RGPIOP13/FB_AD6 PTJ3/RGPIOP12/FB_AD5 PTJ2/FB_AD4 PTJ1/FB_AD3 PTJ0/FB_AD2 PTE0/KBI2P3/FB_ALE/FB_CS1 PTD7/USB_PULLUP(D+)/RX1 PTD6/USB_ALTCLK/TX1 PTD5/SCL/RGPIOP11/TPM1CH3 PTD4/SDA/RGPIOP10/TPM1CH2 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1 PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2/FB_D0/FB_AD1 PTC0/MOSI2/FB_OE/FB_CS0 PTH7/RGPIOP7/FB_D2 PTH6/RGPIOP6/FB_D3 PTH5/RGPIOP5/FB_D4 PTB5/XTAL2 PTB6/KBI1P3/RGPIOP0/FB_AD17 PTB7/KBI1P4/RGPIOP1/FB_AD0 PTH2/RGPIOP2/FB_D7 PTH3/RGPIOP3/FB_D6 PTH4/RGPIOP4/FB_D5 VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 DADP0 DADM0 VREFO DADP1 DADM1 VREFH DACO TRIOUT2/DADP3 VINP2 VINN2/DADM3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 OUT2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 The following figure shows the 100-pin LQFP pinout configuration. Figure 3. 100-Pin LQFP MCF51MM256/128, Rev. 5 8 Freescale Semiconductor Pinouts and Pin Assignments 2.3 81-Pin MAPBGA The following figure shows the 81-pin MAPBGA pinout configuration. 1 2 3 4 5 6 7 8 9 A IRO PTG0 PTF6 USB_DP VBUS VUSB33 PTF4 PTF3 PTE4 A B PTF7 PTA0 PTG1 USB_DM PTF5 PTE7 PTF1 PTF0 PTE3 B C PTA4 PTA5 PTA6 PTA1 PTF2 PTE6 PTE5 PTE2 PTE1 C D INP1- PTA7 PTB0 PTB1 PTA2 PTA3 PTD5 PTD7 PTE0 D E OUT1 VINN1 OUT2 VDD2 VDD3 VDD1 PTD2 PTD3 PTD6 E F VINP1 TRIOUT1 INP2- VSS2 VSS3 VSS1 PTB7 PTC7 PTD4 F G DADP0 DACO TRIOUT2 VINN2 VREFO PTB6 PTC0 PTC1 PTC2 G H DADM0 DADM1 DADP1 VINP2 PTC3 PTC4 PTD0 PTC5 PTC6 H J VSSA VREFL VREFH VDDA PTB2 PTB3 PTD1 PTB4 PTB5 J 1 2 3 4 5 6 7 8 9 Figure 4. 81-Pin MAPBGA MCF51MM256/128, Rev. 5 Freescale Semiconductor 9 Pinouts and Pin Assignments 2.4 80-Pin LQFP PTA5 PTA6 PTA7/INP2+ PTB0 PTB1/BLMS VSSA VREFL INP1OUT1 80-Pin LQFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTE4/CMPP3/TPMCLK/IRQ PTE3/KBI2P6/FB_AD8 PTE2/KBI2P5/RGPIOP14/FB_AD7 PTE1/KBI2P4/RGPIOP13/FB_AD6 PTE0/KBI2P3/FB_ALE/FB_CS1 PTD7/USB_PULLUP(D+)/RX1 PTD6/USB_ALTCLK/TX1 PTD5/SCL/RGPIOP11/TPM1CH3 PTD4/SDA/RGPIOP10/TPM1CH2 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1 PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2/FB_D0/FB_AD1 DACO TRIOUT2/DADP3 VINP2 VINN2/DADM3 DADP0 DADM0 VREFO DADP1 DADM1 VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 PTB6/KBI1P3/RGPIOP0/FB_AD17 PTB7/KBI1P4/RGPIOP1/FB_AD0 PTC0/MOSI2/FB_OE/FB_CS0 TRIOUT1/DADP2VINP1 VINN1DADM2 INP2OUT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PTA0/FB_D2/SS1 IRO PTA1/KBI1P0/TX1/FB_D1 PTA2/KBI1P1/RX1/ADP4 PTA3/KBI1P2/FB_D6/ADP5 PTA4/INP1+ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 VDD1 VSS1 VBUS USB_DP USB_DM VUSB33 PTF5/KBI2P7/FB_D3/FB_AD9 PTF4/SDA/FB_D4/FB_AD10 PTF3/SCL/FB_D5/FB_AD11 PTF2/TX2/USB_DM_DOWN/TPM2CH0 PTF1/RX2/USB_DP_DOWN/TPM2CH1 PTF0/USB_ID/TPM2CH2 PTE7/USB_VBUSVLD/TPM2CH3 PTE6/FB_RW/USB_SESSEND/RX2 PTE5/FB_D7/USB_SESSVLD/TX2 VDD3 VSS3 The following figure shows the 80-pin LQFP pinout configuration. Figure 5. 80-Pin LQFP MCF51MM256/128, Rev. 5 10 Freescale Semiconductor Pinouts and Pin Assignments 2.5 Pin Assignments Table 3. Package Pin Assignments 104 MAPBGA 100 LQFP 81 MAPBGA 80 LQFP Package B2 1 B2 1 PTA0 FB_D2 SS1 -- PTA0/FB_D2/SS1 C1 2 A1 2 IRO -- -- -- IRO C6 3 -- -- PTG5 FB_RW -- -- PTG5/FB_RW C5 4 -- -- PTG6 FB_AD19 -- -- PTG6/FB_AD19 C7 5 -- -- PTG7 FB_AD18 -- -- PTG7/FB_AD18 B7 6 -- -- PTH0 FB_OE -- -- PTH0/FB_OE C8 7 -- -- PTH1 FB_D0 -- -- PTH1/FB_D0 D9 8 C4 3 PTA1 KBI1P0 TX1 FB_D1 PTA1/KBI1P0/TX1/FB_D1 E9 9 D5 4 PTA2 KBI1P1 RX1 ADP4 PTA2/KBI1P1/RX1/ADP4 H3 10 D6 5 PTA3 KBI1P2 FB_D6 ADP5 PTA3/KBI1P2/FB_D6/ADP5 D2 11 C1 6 PTA4 INP1+ -- -- PTA4/INP1+ D1 12 C2 7 PTA5 -- -- -- PTA5 C3 13 C3 8 PTA6 -- -- -- PTA6 E2 14 D2 9 PTA7 INP2+ -- -- PTA7/INP2+ E3 15 D3 10 PTB0 -- -- -- PTB0 D3 16 D4 11 PTB1 BLMS -- -- PTB1/BLMS E1 17 J1 12 VSSA -- -- -- VSSA F1 18 J2 13 VREFL -- -- -- VREFL F2 19 D1 14 INP1- -- -- -- INP1- G2 20 E1 15 OUT1 -- -- -- OUT1 G1 21 F2 16 DADP2 TRIOUT1 -- -- DADP2/TRIOUT1 H1 22 F1 17 VINP1 -- -- -- VINP1 H2 23 E2 18 DADM2 VINN1 -- -- DADM2/VINN1 F3 24 F3 19 INP2- -- -- -- INP2- G3 25 E3 20 OUT2 -- -- -- OUT2 L2 26 G2 21 DACO -- -- -- DACO L1 27 G3 22 DADP3 TRIOUT2 -- -- DADP3/TRIOUT2 K1 28 H4 23 VINP2 -- -- -- VINP2 K2 29 G4 24 DADM3 VINN2 -- -- DADM3/VINN2 Default Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name MCF51MM256/128, Rev. 5 Freescale Semiconductor 11 Pinouts and Pin Assignments Table 3. Package Pin Assignments (continued) 104 MAPBGA 100 LQFP 81 MAPBGA 80 LQFP Package J1 30 G1 25 DADP0 -- -- -- DADP0 J2 31 H1 26 DADM0 -- -- -- DADM0 L4 32 G5 27 VREFO -- -- -- VREFO K3 33 H3 28 DADP1 -- -- -- DADP1 L3 34 H2 29 DADM1 -- -- -- DADM1 L5 35 J3 30 VREFH -- -- -- VREFH L6 36 J4 31 VDDA -- -- -- VDDA H6 37 F4 32 VSS2 -- -- -- VSS2 L8 38 J5 33 PTB2 EXTAL1 -- -- PTB2/EXTAL1 L7 39 J6 34 PTB3 XTAL1 -- -- PTB3/XTAL1 D6 40 E4 35 VDD2 -- -- -- VDD2 L11 41 J8 36 PTB4 EXTAL2 -- -- PTB4/EXTAL2 L10 42 J9 37 PTB5 XTAL2 -- -- PTB5/XTAL2 K5 43 G6 38 PTB6 KBI1P3 RGPIOP0 FB_AD17 PTB6/KBI1P3/RGPIOP0/FB_AD17 K6 44 F7 39 PTB7 KBI1P4 RGPIOP1 FB_AD0 PTB7/KBI1P4/RGPIOP1/FB_AD0 J7 45 -- -- PTH2 RGPIOP2 FB_D7 -- PTH2/RGPIOP2/FB_D7 J6 46 -- -- PTH3 RGPIOP3 FB_D6 -- PTH3/RGPIOP3/FB_D6 J5 47 -- -- PTH4 RGPIOP4 FB_D5 -- PTH4/RGPIOP4/FB_D5 K4 48 -- -- PTH5 RGPIOP5 FB_D4 -- PTH5/RGPIOP5/FB_D4 J4 49 -- -- PTH6 RGPIOP6 FB_D3 -- PTH6/RGPIOP6/FB_D3 J3 50 -- -- PTH7 RGPIOP7 FB_D2 -- PTH7/RGPIOP7/FB_D2 J10 51 G7 40 PTC0 MOSI2 FB_OE FB_CS0 PTC0/MOSI2/FB_OE/FB_CS0 J11 52 G8 41 PTC1 MISO2 FB_D0 FB_AD1 PTC1/MISO2/FB_D0/FB_AD1 J9 53 G9 42 PTC2 KBI1P5 SPSCK2 ADP6 PTC2/KBI1P5/SPSCK2/ADP6 K7 54 H5 43 PTC3 KBI1P6 SS2 ADP7 PTC3/KBI1P6/SS2/ADP7 K9 55 H6 44 PTC4 KBI1P7 CMPP0 ADP8 PTC4/KBI1P7/CMPP0/ADP8 K10 56 H8 45 PTC5 KBI2P0 CMPP1 ADP9 PTC5/KBI2P0/CMPP1/ADP9 K11 57 H9 46 PTC6 KBI2P1 PRACMPO ADP10 PTC6/KBI2P1/PRACMPO/ADP10 F8 58 F8 47 PTC7 KBI2P2 CLKOUT ADP11 PTC7/KBI2P2/CLKOUT/ADP11 L9 59 H7 48 PTD0 BKGD MS -- PTD0/BKGD/MS K8 60 J7 49 PTD1 CMPP2 RESET -- PTD1/CMPP2/RESET Default Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name MCF51MM256/128, Rev. 5 12 Freescale Semiconductor Pinouts and Pin Assignments Table 3. Package Pin Assignments (continued) 104 MAPBGA 100 LQFP 81 MAPBGA 80 LQFP Package H11 61 E7 50 PTD2 USB_ALTCLK RGPIOP8 TPM1CH0 H10 62 E8 51 PTD3 USB_PULLUP (D+) RGPIOP9 TPM1CH1 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1 H9 63 F9 52 PTD4 SDA RGPIOP10 TPM1CH2 PTD4/SDA/RGPIOP10/TPM1CH2 G9 64 D7 53 PTD5 SCL RGPIOP11 TPM1CH3 PTD5/SCL/RGPIOP11/TPM1CH3 J8 65 E9 54 PTD6 USB_ALTCLK TX1 -- PTD6/USB_ALTCLK/TX1 G10 66 D8 55 PTD7 USB_PULLUP (D+) RX1 -- PTD7/USB_PULLUP(D+) /RX1 G11 67 D9 56 PTE0 KBI2P3 FB_ALE FB_CS1 PTE0/KBI2P3/FB_ALE/FB_CS1 F10 68 -- -- PTJ0 FB_AD2 -- -- PTJ0/FB_AD2 F11 69 -- -- PTJ1 FB_AD3 -- -- PTJ1/FB_AD3 F9 70 -- -- PTJ2 FB_AD4 -- -- PTJ2/FB_AD4 E10 71 -- -- PTJ3 RGPIOP12 FB_AD5 -- PTJ3/RGPIOP12/FB_AD5 E11 72 C9 57 PTE1 KBI2P4 RGPIOP13 FB_AD6 PTE1/KBI2P4/RGPIOP13/FB_AD6 D11 73 C8 58 PTE2 KBI2P5 RGPIOP14 FB_AD7 PTE2/KBI2P5/RGPIOP14/FB_AD7 D10 74 B9 59 PTE3 KBI2P6 FB_AD8 -- PTE3/KBI2P6/FB_AD8 C9 75 A9 60 PTE4 CMPP3 TPMCLK IRQ PTE4/CMPP3/TPMCLK/IRQ H8 76 F5 61 VSS3 -- -- -- VSS3 D8 77 E5 62 VDD3 -- -- -- VDD3 B8 78 C7 63 PTE5 FB_D7 USB_ SESSVLD TX2 PTE5/FB_D7/USB_SESSVLD/TX2 C10 79 C6 64 PTE6 FB_RW USB_ SESSEND RX2 PTE6/FB_RW/USB_SESSEND/RX2 C11 80 B6 65 PTE7 USB_ VBUSVLD TPM2CH3 -- PTE7/USB_VBUSVLD/TPM2CH3 B9 81 B8 66 PTF0 USB_ID TPM2CH2 -- PTF0/USB_ID/TPM2CH2 B10 82 B7 67 PTF1 RX2 USB_DP_D TPM2CH1 OWN PTF1/RX2/USB_DP_DOWN/TPM2CH1 B11 83 C5 68 PTF2 TX2 USB_DM_ TPM2CH0 DOWN PTF2/TX2/USB_DM_DOWN/TPM2CH0 A11 84 -- -- PTJ4 RGPIOP15 FB_AD16 -- PTJ4/RGPIOP15/FB_AD16 A10 85 -- -- PTJ5 FB_AD15 -- -- PTJ5/FB_AD15 B6 86 -- -- PTJ6 FB_AD14 -- -- PTJ6/FB_AD14 A9 87 -- -- PTJ7 FB_AD13 -- -- PTJ7/FB_AD13 Default Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0 MCF51MM256/128, Rev. 5 Freescale Semiconductor 13 Pinouts and Pin Assignments Table 3. Package Pin Assignments (continued) 104 MAPBGA 100 LQFP 81 MAPBGA 80 LQFP Package A8 88 -- -- FB_AD12 -- -- -- FB_AD12 A7 89 A8 69 PTF3 SCL FB_D5 FB_AD11 PTF3/SCL/FB_D5/FB_AD11 A6 90 A7 70 PTF4 SDA FB_D4 FB_AD10 PTF4/SDA/FB_D4/FB_AD10 B5 91 B5 71 PTF5 KBI2P7 FB_D3 FB_AD9 PTF5/KBI2P7/FB_D3/FB_AD9 A5 92 A6 72 VUSB33 -- -- -- VUSB33 A4 93 B4 73 USB_DM -- -- -- USB_DM A3 94 A4 74 USB_DP -- -- -- USB_DP B4 95 A5 75 VBUS -- -- -- VBUS H4 96 F6 76 VSS1 -- -- -- VSS1 D4 97 E6 77 VDD1 -- -- -- VDD1 A1 98 A3 78 PTF6 MOSI1 -- -- PTF6/MOSI1 A2 99 B1 79 PTF7 MISO1 -- -- PTF7/MISO1 B1 100 A2 80 PTG0 SPSCK1 -- -- PTG0/SPSCK1 F4 -- A1 -- PTG1 USB_ SESSEND -- -- PTG1/USB_SESSEND C4 -- -- -- PTG2 USB_DM_ DOWN -- -- PTG2/USB_DM_DOWN B3 -- -- -- PTG3 USB_DP_ DOWN -- -- PTG3/USB_DP_DOWN C2 -- -- -- PTG4 USB_SESSVLD -- -- PTG4/USB_SESSVLD Default Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name MCF51MM256/128, Rev. 5 14 Freescale Semiconductor Electrical Characteristics 3 Electrical Characteristics This section contains electrical specification tables and reference timing diagrams for the MCF51MM256/128 microcontroller, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this data sheet supersede any values found in the module specifications. 3.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 4. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. MCF51MM256/128, Rev. 5 Freescale Semiconductor 15 Electrical Characteristics 3.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. Table 5. Absolute Maximum Ratings # 1 2 3 Rating Symbol Value Unit 1 Supply voltage VDD -0.3 to +3.8 V 2 Maximum current into VDD IDD 120 mA 3 Digital input voltage VIn -0.3 to VDD + 0.3 V 4 Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID 25 mA 5 Storage temperature range Tstg -55 to 150 C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. All functional non-supply pins are internally clamped to VSS and VDD. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). MCF51MM256/128, Rev. 5 16 Freescale Semiconductor Electrical Characteristics 3.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 6. Thermal Characteristics # Symbol 1 TA 2 TJMAX 3 JA 4 1 2 3 4 JA Rating Value C Operating temperature range (packaged): MCF51MM256 -40 to 105 MCF51MM128 -40 to 105 Maximum junction temperature Unit 135 Thermal resistance1,2,3,4 Single-layer board -- 1s C C/W 104-pin MBGA 67 100-pin LQFP 53 81-pin MBGA 67 80-pin LQFP 53 Thermal resistance1, 2, 3, 4 Four-layer board -- 2s2p C/W 104-pin MBGA 39 100-pin LQFP 41 81-pin MBGA 39 80-pin LQFP 39 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Junction to Ambient Natural Convection 1s -- Single layer board, one signal layer 2s2p -- Four layer board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD JA) Eqn. 1 where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint PI/O Pint = IDD VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined MCF51MM256/128, Rev. 5 Freescale Semiconductor 17 Electrical Characteristics For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K (TJ + 273C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD (TA + 273C) + JA (PD)2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 3.4 ESD Protection Characteristics Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E. A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 7. ESD and Latch-up Test Conditions Model Human Body Machine Latch-up Description Symbol Value Unit Series Resistance R1 1500 Storage Capacitance C 100 pF Number of Pulse per pin -- 3 -- Series Resistance R1 0 Storage Capacitance C 200 pF Number of Pulse per pin -- 3 -- Minimum input voltage limit -- -2.5 V Maximum input voltage limit -- 7.5 V Table 8. ESD and Latch-Up Protection Characteristics # Rating Symbol Min Max Unit C 1 Human Body Model (HBM) VHBM 2000 -- V T 2 Machine Model (MM) VMM 200 -- V T MCF51MM256/128, Rev. 5 18 Freescale Semiconductor Electrical Characteristics Table 8. ESD and Latch-Up Protection Characteristics (continued) 3 Charge Device Model (CDM) 4 Latch-up Current at TA = 125C VCDM 500 -- V T ILAT 00 -- mA T MCF51MM256/128, Rev. 5 Freescale Semiconductor 19 Electrical Characteristics 3.5 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. Table 9. DC Characteristics Num Symbol 1 -- 2 VOH Characteristic Operating Voltage Output high voltage Condition Min Typ1 Max Unit C -- 1.82 -- 3.6 V -- VDD - 0.5 -- -- V C VDD 2.7 V, ILoad = -10 mA VDD - 0.5 -- -- V P VDD 2.3 V, ILoad = -6 mA VDD - 0.5 -- -- V T VDD 1.8V, ILoad = -3 mA VDD - 0.5 -- -- V C -- -- 100 mA D -- -- 0.5 V C VDD 2.7 V, ILoad = 10 mA -- -- 0.5 V P VDD 2.3 V, ILoad = 6 mA -- -- 0.5 V T VDD 1.8 V, ILoad = 3 mA -- -- 0.5 V C -- -- -- 100 mA D VDD 2.7 V 0.70 x VDD -- -- V P VDD 1.8 V 0.85 x VDD -- -- V C All I/O pins, low-drive strength VDD 1.8 V, ILoad = -600 A All I/O pins, high-drive strength 3 IOHT Output high current Max total IOH for all ports -- 4 VOL Output low voltage All I/O pins, low-drive strength VDD 1.8 V, ILoad = 600 A All I/O pins, high-drive strength 5 IOLT Output low current Max total IOL for all ports 6 VIH Input high voltage all digital inputs MCF51MM256/128, Rev. 5 20 Freescale Semiconductor Electrical Characteristics Table 9. DC Characteristics (continued) Num Symbol 7 VIL Condition Min Typ1 Max Unit C VDD 2.7 V -- -- 0.35 x VDD V P VDD 1.8 V -- -- 0.30 x VDD V C -- 0.06 x VDD -- -- mV C all input only pins VIn = VDD or VSS (Per pin) -- -- 0.5 A P all digital input/output VIn = VDD or VSS (per pin) -- 0.003 0.5 A P -- 17.5 -- 52.5 k P -- 17.5 -- 52.5 k P VSS > VIN > VDD -0.2 -- 0.2 mA D Characteristic Input low voltage all digital inputs 8 Vhys Input hysteresis 9 |IIn| Input leakage current 10 |IOZ| Hi-Z (off-state) leakage current3 11 RPU Pull-up resistors 12 RPD Internal pull-down resistors4 13 IIC DC injection current 5, 6, 7 all digital inputs all digital inputs, when enabled Single pin limit Total MCU limit, includes sum of all stressed pins 14 CIn 15 VRAM VSS > VIN > VDD -5 -- 5 mA D Input Capacitance, all pins -- -- -- 8 pF C RAM retention voltage -- -- 0.6 1.0 V C 8 16 VPOR POR re-arm voltage -- 0.9 1.4 1.79 V C 17 tPOR POR re-arm time -- 10 -- -- s D -- 2.11 2.16 2.22 V P -- 2.16 2.21 2.27 V P -- 1.80 1.82 1.91 V P -- 1.86 1.90 1.99 V P 18 Low-voltage detection VLVDH9 threshold -- high range VDD falling VDD rising 19 VLVDL Low-voltage detection threshold -- low range9 VDD falling VDD rising MCF51MM256/128, Rev. 5 Freescale Semiconductor 21 Electrical Characteristics Table 9. DC Characteristics (continued) Num Symbol 20 Characteristic Low-voltage warning VLVWH threshold -- high range9 Condition Min Typ1 Max Unit C -- 2.36 2.46 2.56 V P -- 2.36 2.46 2.56 V P -- 2.11 2.16 2.22 V P -- 2.16 2.21 2.27 V P VDD falling VDD rising 21 Low-voltage warning VLVWL threshold -- low range9 VDD falling VDD rising 1 2 3 4 5 6 7 8 9 10 11 22 Vhys Low-voltage inhibit reset/recoverhysteresis10 -- -- 50 -- mV C 23 VBG Bandgap Voltage Reference11 -- 1.110 1.17 1.230 V P Typical values are measured at 25C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. Does not include analog module pins. Dedicated analog pins should not be pulled to VDD or VSS and should be left floating when not used to reduce current leakage. Measured with VIn = VDD. All functional non-supply pins are internally clamped to VSS and VDD except PTD1. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Run at 1 MHz bus frequency Low voltage detection and warning limits measured at 1 MHz bus frequency. Factory trimmed at VDD = 3.0 V, Temp = 25C MCF51MM256/128, Rev. 5 22 Freescale Semiconductor Electrical Characteristics 3.6 Supply Current Characteristics Table 10. Supply Current Characteristics # Symbol 1 RIDD 2 3 4 RIDD RIDD RIDD Parameter Run supply current Run supply current Run supply current Run supply current Bus Freq VDD (V) Typ1 Max Unit Temp (C) C FEI mode; all modules ON2 25.165 MHz 3 44 48 mA -40 to 25 P 25.165 MHz 3 44 48 mA 105 P 20 MHz 3 32.3 -- mA -40 to 105 T 8 MHz 3 16.4 -- mA -40 to 105 T 1 MHz 3 2.9 -- mA -40 to 105 T FEI mode; all modules OFF3 25.165 MHz 3 29 29.6 mA -40 to 105 C 20 MHz 3 25.4 -- mA -40 to 105 T 8 MHz 3 12.7 -- mA -40 to 105 T 1 MHz 3 2.4 -- mA -40 to 105 T 16 kHz FBI 3 232 280 A -40 to 105 T 16 kHz FBE 3 231 296 A -40 to 105 T 16 kHz BLPE 3 74 75 A 0 to 70 T 16 kHz BLPE 3 74 120 A -40 to 105 T LPR=0; all modules OFF3 LPR=1, all modules OFF3 MCF51MM256/128, Rev. 5 Freescale Semiconductor 23 Electrical Characteristics Table 10. Supply Current Characteristics (continued) # Symbol 5 WIDD 6 7 LPWIDD S2IDD Parameter Wait mode supply current Bus Freq VDD (V) Typ1 Max Unit Temp (C) C FEI mode, all modules OFF3 25.165 MHz 3 16.5 -- mA -40 to 105 C 20 MHz 3 10.3 -- mA -40 to 105 T 8 MHz 3 6.6 -- mA -40 to 105 T 1 MHz 3 1.7 -- mA -40 to 105 T 16 KHz 3 28 62 A -40 to 105 T N/A 3 0.410 1.00 A -40 to 25 P N/A 3 3.7 10 A 70 C N/A 3 10 20 A 85 C N/A 3 21 31.5 A 105 P N/A 2 0.410 0.640 A -40 to 25 C N/A 2 3.4 9 A 70 C N/A 2 9.5 18 A 85 C N/A 2 20 30 A 105 C Low-Power Wait mode supply current Stop2 mode supply current4 MCF51MM256/128, Rev. 5 24 Freescale Semiconductor Electrical Characteristics Table 10. Supply Current Characteristics (continued) # Symbol Bus Freq Parameter VDD (V) Temp (C) C 1.3 -40 to 25 P 8.5 18 70 C 20 28 85 C 53 63 105 P 0.400 0.900 -40 to 25 C 8.2 16 70 C 18 26 85 C 47 59 105 C Typ1 Max 0.750 Unit 3 8 Stop3 mode supply current4 No clocks active S3IDD A n/a 2 1 2 3 4 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. ON = System Clock Gating Control registers turn on system clock to the corresponding modules. OFF = System Clock Gating Control registers turn off system Clock to the corresponding modules. All digital pins must be configured to a known state to prevent floating pins from adding current. Smaller packages may have some pins that are not bonded out; however, software must still be configured to the largest pin package available so that all pins are in a known state. Otherwise, floating pins that are not bonded in the smaller packages may result in a higher current draw. NOTE: I/O pins are configured to output low; input-only pins are configured to pullup-enabled. IRO pin connects to ground. FB_AD12 pin is pullup-enabled. TRIAMPx, OPAMPx, DACO, and VREFO pins are at reset state and unconnected. Table 11. Typical Stop Mode Adders Temperature (C) # 1 LPO 2 EREFSTEN 3 1 IREFSTEN 4 TOD 5 LVD1 Condition Units C 250 nA D 850 1000 nA D 80 93 125 A T 75 100 150 250 nA D 116 117 126 132 172 A T -40 25 70 85 105 50 75 100 150 600 650 750 -- 73 Does not include clock source current 50 LVDSE = 1 -- RANGE = HGO = 0 -- 6 PRACMP Not using the bandgap (BGBE = 0) 17 18 24 35 74 A T 7 ADC1 ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) 190 195 210 220 260 A T 8 DAC1 High-Power mode; no load on DACO 339 345 346 346 360 A T Low-Power mode 41 43 43 44 50 A T 9 OPAMP1 High-Power mode 276 350 370 376 390 A T Low-Power mode 42 49 57 58 68 A T High-Power mode 420 432 433 438 478 A T Low-Power mode 52 52 52 55 60 A T 10 1 Parameter 1 TRIAMP1 Not available in stop2 mode. MCF51MM256/128, Rev. 5 Freescale Semiconductor 25 Electrical Characteristics Figure 7. Stop IDD versus Temperature MCF51MM256/128, Rev. 5 26 Freescale Semiconductor Electrical Characteristics 3.7 PRACMP Electricals Table 12. PRACMP Electrical Specifications # Characteristic Symbol Min Typical Max Unit C VPWR 1.8 -- 3.6 V P 1 Supply voltage 2 Supply current (active) (PRG enabled) IDDACT1 -- -- 80 A D 3 Supply current (active) (PRG disabled) IDDACT2 -- -- 40 A D 4 Supply current (ACMP and PRG all disabled) IDDDIS -- -- 2 nA D 5 Analog input voltage VAIN VSS - 0.3 -- VDD V D 6 Analog input offset voltage VAIO -- 5 40 mV D 7 Analog comparator hysteresis VH 3.0 -- 20.0 mV D 8 Analog input leakage current IALKG -- -- 1 nA D 9 Analog comparator initialization delay tAINIT -- -- 1.0 s D 10 Programmable reference generator inputs VIn2 (VDD25) 1.8 -- 2.75 V D 11 Programmable reference generator setup delay tPRGST -- 1 -- s D 12 Programmable reference generator step size Vstep 0.75 1 1.25 LSB D 13 Programmable reference generator voltage range Vprgout VIn/32 -- Vin V P 3.8 12-Bit DAC Electricals Table 13. DAC 12LV Operating Requirements # Characteristic Symbol Min Max Unit C 1 Supply voltage VDDA 1.8 3.6 V P 2 Reference voltage VDACR 1.15 3.6 V C 3 Temperature TA -40 105 C C 4 Output load capacitance CL -- 100 pF C 5 Output load current IL -- 1 mA C Notes A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. Table 14. DAC 12-Bit Operating Behaviors # 1 Characteristic Resolution Symbol Min Typ Max Unit C N 12 -- 12 bit T Notes MCF51MM256/128, Rev. 5 Freescale Semiconductor 27 Electrical Characteristics Table 14. DAC 12-Bit Operating Behaviors (continued) # Characteristic Symbol Min Typ Max 2 Supply current low-power mode IDDA_DACLP -- 50 100 3 Supply current high-power mode IDDA_DACHP -- 345 500 4 Full-scale Settling time (1 LSB) (0x080 to 0xF7F or 0xF7F to 0x080) low-power mode 5 Full-scale Settling time (1 LSB) (0x080 to 0xF7F or 0xF7F to 0x080) high-power mode 6 Code-to-code Settling time (1 LSB) (0xBF8 to 0xC08 or 0xC08 to 0xBF8) low-power mode 7 Code-to-code Settling time (1 LSB) (0xBF8 to 0xC08 or 0xC08 to 0xBF8) high-power mode (3 V at Room Temperature) 8 DAC output voltage range low (high-power mode, no load, DAC set to 0) (3 V at Room Temperature) 9 DAC output voltage range high (high-power mode, no load, DAC set to 0x0FFF) 10 11 12 13 TsFSLP TsFSHP TsC-CLP -- -- -- -- -- -- 200 30 5 Unit A A s s s C T T T T T TsC-CHP -- 1 -- s T Vdacoutl -- -- 100 mV T Vdacouth VDACR -100 -- -- mV T Integral non-linearity error INL -- -- 8 LSB T Differential non-linearity error VDACR is > 2.4 V DNL -- -- 1 LSB T Offset error Gain error, VREFH = Vext = VDD EO EG -- -- 0.4 0.1 3 0.5 %FSR %FSR Notes T T * VDDA = 3 V or 2.2 V * VREFSEL = 1 * Temperature = 25C * VDDA = 3 V or 2.2 V * VREFSEL = 1 * Temperature = 25C * VDDA = 3 V or 2.2 V * VREFSEL = 1 * Temperature = 25C * VDDA = 3 V or 2.2 V * VREFSEL = 1 * Temperature = 25C Calculated by a best fit curve from VSS + 100mV to VREFH -100mV Calculated by a best fit curve from VSS + 100mV to VREFH -100mV MCF51MM256/128, Rev. 5 28 Freescale Semiconductor Electrical Characteristics Table 14. DAC 12-Bit Operating Behaviors (continued) # Characteristic Symbol Min Typ Max Unit C PSRR 60 -- -- dB T 14 Power supply rejection ratio VDD 2.4 V 15 Temperature drift of offset voltage (DAC set to 0x0800) Tco -- -- 2 mV T 16 Offset aging coefficient Ac -- -- 8 V/yr T Notes See Typical Drift figure that follows. Figure 7. Offset at Half Scale vs Temperature 3.9 ADC Characteristics Table 15. 16-Bit ADC Operating Conditions # Symb Characteristic 1 VDDA 2 VDDA 3 VSSA Ground voltage 4 VREFH Ref Voltage High Supply voltage Conditions Absolute Delta to VDD (VDD-VDDA)2 Delta to VSS (VSS-VSSA)2 Min Typ1 Max Unit C 1.8 -- 3.6 V D -100 0 +100 mV D -100 0 +100 mV D 1.15 VDDA VDDA V D Comment MCF51MM256/128, Rev. 5 Freescale Semiconductor 29 Electrical Characteristics Table 15. 16-Bit ADC Operating Conditions (continued) # Symb 5 VREFL Ref Voltage Low 6 VADIN Input Voltage 7 CADIN Input Capacitance 8 RADIN Input Resistance 9 RAS Characteristic Conditions 16-bit modes 8/10/12-bit modes Max Unit C VSSA VSSA VSSA V D VREFL -- VREFH V D -- 8 4 10 5 pF T -- 2 5 k T Comment External to MCU Assumes ADLSMP=0 -- -- 0.5 k T 4 MHz < fADCK < 8 MHz -- -- 1 k T fADCK < 4 MHz -- -- 2 k T -- -- 1 k T 4 MHz < fADCK < 8 MHz -- -- 2 k T fADCK < 4 MHz -- -- 5 k T -- -- 2 k T 4 MHz < fADCK < 8 MHz -- -- 5 k T fADCK < 4 MHz -- -- 10 k T -- -- 5 k T -- -- 10 k T 1.0 -- 8.0 MHz D 1.0 -- 5.0 MHz D 1.0 -- 2.5 MHz D fADCK > 8 MHz 13/12-bit mode fADCK > 8 MHz 11/10-bit mode fADCK > 8 MHz 9/8-bit mode fADCK > 8 MHz fADCK < 8 MHz fADCK Typ1 Analog Source Resistance 16-bit mode 10 Min ADC Conversion Clock Frequency ADLPC=0, ADHSC=1 ADLPC=0, ADHSC=0 ADLPC=1, ADHSC=0 1 2 Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. DC potential difference. MCF51MM256/128, Rev. 5 30 Freescale Semiconductor Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + - CAS - RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 8. ADC Input Impedance Equivalency Diagram MCF51MM256/128, Rev. 5 Freescale Semiconductor 31 Electrical Characteristics Table 16. 16-Bit SAR ADC Characteristics full operating range (VREFH = VDDA, > 1.8, VREFL = VSSA 8 MHz, -40 to 85 C) # 1 Characteristic Supply Current Conditions1 Min Typ2 Max ADLPC=1, ADHSC=0 -- 215 -- ADLPC=0, ADHSC=0 -- 470 -- -- 610 -- -- 0.01 -- -- 2.4 -- -- 5.2 -- Symb IDDAD ADLPC=0, ADHSC=1 2 Supply Current 3 ADC Asynchronous Clock Source Stop, Reset, Module Off IDDAD ADLPC=1, ADHSC=0 ADLPC=0, ADHSC=0 fADACK ADLPC=0, ADHSC=1 -- 4 Sample Time See Reference Manual for sample times 5 Conversion Time See Reference Manual for conversion times 6 7 Total Unadjusted Error Differential Non-Linearity 6.2 -- Unit C A T A T MHz C -- -- 16 20 48/ -40 56/ -28 13-bit differential mode 12-bit single-ended mode -- -- 1.5 1.75 3.0 3.5 T 11-bit differential mode 10-bit single-ended mode -- -- 0.7 0.8 1.5 1.5 T 9-bit differential mode 8-bit single-ended mode -- -- 0.5 0.5 1.0 1.0 T -- -- 2.5 2.5 5/-3 +5/-3 13-bit differential mode 12-bit single-ended mode -- -- 0.7 0.7 1 1 T 11-bit differential mode 10-bit single-ended mode -- -- 0.5 0.5 0.75 0.75 T 9-bit differential mode 8-bit single-ended mode -- -- 0.2 0.2 0.5 0.5 T 16-bit differential mode 16-bit single-ended mode 16-bit differential mode 16-bit single-ended mode TUE DNL LSB3 LSB2 T Comment ADLSMP =0 ADCO=1 tADACK = 1/fADACK 32x Hardware Averaging (AVGE = %1 AVGS = %11) T MCF51MM256/128, Rev. 5 32 Freescale Semiconductor Electrical Characteristics Table 16. 16-Bit SAR ADC Characteristics full operating range (VREFH = VDDA, > 1.8, VREFL = VSSA 8 MHz, -40 to 85 C) (continued) # Characteristic 8 Integral Non-Linearity 9 10 11 Zero-Scale Error Full-Scale Error Quantization Error Conditions1 Symb Min Typ2 Max Unit C 16-bit differential mode 16-bit single-ended mode INL -- -- 6.0 10.0 16.0 20.0 LSB2 T 13-bit differential mode 12-bit single-ended mode -- -- 1.0 1.0 2.5 2.5 T 11-bit differential mode 10-bit single-ended mode -- -- 0.5 0.5 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode -- -- 0.3 0.3 0.5 0.5 T -- -- 4.0 4.0 +32/ -24 +24/ -16 13-bit differential mode 12-bit single-ended mode -- -- 0.7 0.7 2.5 2.0 T 11-bit differential mode 10-bit single-ended mode -- -- 0.4 0.4 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode -- -- 0.2 0.2 0.5 0.5 T -- -- +10/0 +14/0 +42/-2 +46/-2 13-bit differential mode 12-bit single-ended mode -- -- 1.0 1.0 3.5 3.5 T 11-bit differential mode 10-bit single-ended mode -- -- 0.4 0.4 1.5 1.5 T 9-bit differential mode 8-bit single-ended mode -- -- 0.2 0.2 0.5 0.5 T -- -1 to 0 -- -- -- 0.5 12.8 12.7 12.6 12.5 11.9 14.2 13.8 13.6 13.3 12.5 -- -- -- -- -- 16-bit differential mode 16-bit single-ended mode 16-bit differential mode 16-bit single-ended mode 16-bit modes EZS EFS EQ <13-bit modes 12 Effective Number of Bits 16-bit differential mode Avg=32 Avg=16 Avg=8 Avg=4 Avg=1 13 Signal to Noise plus Distortion See ENOB ENOB SINAD SINAD = 6.02 ENOB + 1.76 LSB2 LSB2 LSB2 Bits T T Comment VADIN = VSSA VADIN = VDDA D C Fin = Fsample/10 0 dB MCF51MM256/128, Rev. 5 Freescale Semiconductor 33 Electrical Characteristics Table 16. 16-Bit SAR ADC Characteristics full operating range (VREFH = VDDA, > 1.8, VREFL = VSSA 8 MHz, -40 to 85 C) (continued) # 14 15 16 17 18 Conditions1 Characteristic Total Harmonic Distortion Spurious Free Dynamic Range Input Leakage Error Temp Sensor Slope Temp Sensor Voltage Symb 16-bit differential mode Avg=32 16-bit single-ended mode Avg=32 16-bit differential mode Avg=32 16-bit single-ended mode Avg=32 all modes -40C - 25C THD SFDR Typ2 Max -- -91.5 -74.3 -- -85.5 -- 75.0 92.2 -- -- 86.2 -- IIn * RAS -- 1.646 -- m VTEMP2 5 Unit dB EIL 25C - 125C 25C Min -- 1.769 -- -- 718.2 -- C Comment C Fin = Fsample/10 0 D C dB D mV D mV/x C C mV C Fin = Fsample/10 0 IIn = leakage current (refer to DC characteri stics) 1 All accuracy numbers assume the ADC is calibrated with VREFH=VDDA Typical values assume VDDA = 3.0V, Temp = 25C, f ADCK=2.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3 1 LSB = (V N REFH - VREFL)/2 2 MCF51MM256/128, Rev. 5 34 Freescale Semiconductor Electrical Characteristics Table 17. 16-bit SAR ADC Characteristics full operating range (VREFH = VDDA, 2.7 V, VREFL = VSSA, fADACK 4 MHz, ADHSC = 1) # 1 2 3 4 Characteristic Total Unadjusted Error Differential Non-Linearity Integral Non-Linearity Zero-Scale Error Conditions1 Symb Min Typ2 Max Unit C Comment T 32x Hardware Averaging (AVGE = %1 AVGS = %11) -- -- 16 20 24/ -24 32/-20 13-bit differential mode 12-bit single-ended mode -- -- 1.5 1.75 2.0 2.5 T 11-bit differential mode 10-bit single-ended mode -- -- 0.7 0.8 1.0 1.25 T 9-bit differential mode 8-bit single-ended mode -- -- 0.5 0.5 1.0 1.0 T -- -- 2.5 2.5 3 3 13-bit differential mode 12-bit single-ended mode -- -- 0.7 0.7 1 1 T 11-bit differential mode 10-bit single-ended mode -- -- 0.5 0.5 0.75 0.75 T 9-bit differential mode 8-bit single-ended mode -- -- 0.2 0.2 0.5 0.5 T -- -- 6.0 10.0 12.0 16.0 13-bit differential mode 12-bit single-ended mode -- -- 1.0 1.0 2.0 2.0 T 11-bit differential mode 10-bit single-ended mode -- -- 0.5 0.5 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode -- -- 0.3 0.3 0.5 0.5 T -- -- 4.0 4.0 +16/0 +16/-8 13-bit differential mode 12-bit single-ended mode -- -- 0.7 0.7 2.0 2.0 T 11-bit differential mode 10-bit single-ended mode -- -- 0.4 0.4 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode -- -- 0.2 0.2 0.5 0.5 T 16-bit differential mode 16-bit single-ended mode 16-bit differential mode 16-bit single-ended mode 16-bit differential mode 16-bit single-ended mode 16-bit differential mode 16-bit single-ended mode TUE DNL INL EZS LSB3 LSB2 LSB2 LSB2 T T T VADIN = VSSA MCF51MM256/128, Rev. 5 Freescale Semiconductor 35 Electrical Characteristics Table 17. 16-bit SAR ADC Characteristics full operating range (VREFH = VDDA, 2.7 V, VREFL = VSSA, fADACK 4 MHz, ADHSC = 1) (continued) # Characteristic Conditions1 Symb Min Typ2 Max Unit C Comment 5 Full-Scale Error 16-bit differential mode 16-bit single-ended mode EFS -- -- +8/0 +12/0 +24/0 +24/0 LSB2 T VADIN = VDDA 13-bit differential mode 12-bit single-ended mode -- -- 0.7 0.7 2.0 2.5 T 11-bit differential mode 10-bit single-ended mode -- -- 0.4 0.4 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode -- -- 0.2 0.2 0.5 0.5 T -- -1 to 0 -- -- -- 0.5 14.3 13.8 13.4 13.1 12.4 14.5 14.0 13.7 13.4 12.6 -- -- -- -- -- 6 Quantization Error 16-bit modes EQ <13-bit modes 7 Effective Number of Bits 16-bit differential mode Avg=32 Avg=16 Avg=8 Avg=4 Avg=1 8 Signal to Noise plus Distortion See ENOB 9 Total Harmonic Distortion 10 Spurious Free Dynamic Range 11 Input Leakage Error ENO B SINA D 16-bit differential mode Avg=32 16-bit single-ended mode Avg=32 16-bit differential mode Avg=32 16-bit single-ended mode Avg=32 all modes THD SFDR EIL SINAD = 6.02 ENOB + 1.76 -- -95.8 LSB2 Bits C dB -- -- 91.0 96.5 -- -- -- -- IIn * RAS C Fin = Fsample/10 0 dB -90.4 -- D D C dB D mV D Fin = Fsample/10 0 Fin = Fsample/10 0 IIn = leakage current (refer to DC characteri stics) 1 All accuracy numbers assume the ADC is calibrated with VREFH=VDDA Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3 1 LSB = (V N REFH - VREFL)/2 2 MCF51MM256/128, Rev. 5 36 Freescale Semiconductor Electrical Characteristics 3.10 MCG and External Oscillator (XOSC) Characteristics Table 18. MCG (Temperature Range = -40 to 105C Ambient) # Rating 1 Internal reference startup time Average internal reference 2 frequency factory trimmed at VDD=3.0 V and temp=25C Symbol Min Typical Max Unit C tirefst -- 55 100 s D -- 31.25 -- 31.25 -- 39.0625 C 16 -- 20 C 32 -- 40 C 40 -- 60 C -- 0.1 0.2 -- 0.2 0.4 -- 1.0 2 fint_ft user trimmed DCO output frequency range -- 3 trimmed Low range (DRS=00) Mid range (DRS=01) fdco_t High range1 (DRS=10) Resolution of trimmed DCO 4 output frequency at fixed voltage and temperature with FTRIM without FTRIM over voltage and temperature Total deviation of trimmed DCO 5 output frequency over voltage and over fixed voltage temperature and temp range of 0 - 70 C 6 7 Acquisition time fdco_res_t fdco_t %fdco C C P %fdco -- 0.5 1 C tfll_acquire -- -- 1 tpll_acquire -- -- 1 CJitter -- 0.02 0.2 %fdco C fvco 7.0 -- 55.0 MHz D fpll_ref 1.0 -- 2.0 MHz D fpll_jitter_625 -- 0.5664 -- %fpll D 2.98 9 PLL reference frequency range 11 Lock frequency tolerance MHz PLL3 Long term Jitter of DCO output clock (averaged over 2mS interval) 4 Jitter of PLL output clock measured over 625ns 5 C FLL2 8 VCO operating frequency 10 kHz Long term ns Entry6 Dlock 1.49 -- Exit7 Dunl 4.47 -- 5.97 tfll_acquire+ 1075(1/fint_t) FLL tfll_lock -- -- PLL tpll_lock -- -- 12 Lock time tpll_acquire+ 1075(1/fpll_re ms % C D D D D s D f) 1 Loss of external clock minimum frequency - RANGE = 13 0 floc_low (3/5) x fint_t -- -- kHz D Loss of external clock minimum frequency - RANGE = 14 1 floc_high (16/5) x fint_t -- -- kHz D This should not exceed the maximum CPU frequency for this device which is 50.33 MHz. MCF51MM256/128, Rev. 5 Freescale Semiconductor 37 Electrical Characteristics 2 3 4 5 6 7 This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 625 ns represents 5 time quanta for CAN applications, under worst-case conditions of 8 MHz CAN bus clock, 1 Mbps CAN Bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already in lock, then the MCG may stay in lock. Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock. Table 19. XOSC (Temperature Range = -40 to 105C Ambient) # Symbol Min Typ1 Max Unit flo 32 -- 38.4 kHz * High range (RANGE = 1), * FEE or FBE mode 2 fhi-fll 1 -- 5 MHz D * High range (RANGE = 1), * PEE or PBE mode 3 fhi-pll 1 -- 16 MHz D * High range (RANGE = 1), * High gain (HGO = 1), * BLPE mode fhi-hgo 1 -- 16 MHz D * High range (RANGE = 1), * Low power (HGO = 0), * BLPE mode fhi-lp 1 -- 8 MHz D Characteristic * Low range (RANGE = 0) 1 2 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Feedback resistor 3 4 C1 C2 Load capacitors * Low range (32 kHz to 38.4 kHz) * High range (1 MHz to 16 MHz) Series resistor -- Low range * Low Gain (HGO = 0) * High Gain (HGO = 1) RF See crystal or resonator manufacturer's recommendation. -- 10 -- 8 MHz D D -- RS -- 1 -- -- 0 -- -- 100 -- -- 0 -- D D k D D * High Gain (HGO = 1) Series resistor -- High range D M * Low Gain (HGO = 0) 5 C D RS -- 0 0 4 MHz -- 0 10 D 1 MHz -- 0 20 D k D MCF51MM256/128, Rev. 5 38 Freescale Semiconductor Electrical Characteristics Table 19. XOSC (Temperature Range = -40 to 105C Ambient) (continued) # Characteristic * Low range, low gain (RANGE = 0, HGO = 0) * Low range, high gain (RANGE = 0, HGO = 1) Crystal start-up time 4 6 * High range, low gain (RANGE = 1, HGO = 0)5 * High range, high gain (RANGE = 1, HGO = 1)5 1 2 3 4 5 Symbol Min t CSTL-LP -- t CSTL-HG O tCSTH-LP tCSTH-HG O Typ1 200 Max Unit C -- D D -- 400 -- -- 5 -- -- 15 -- ms D D Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2 MHz. This parameter is characterized and not tested on each device. Proper PC board layout porcedures must be followed to achieve specifications. 4 MHz crystal. MCU EXTAL C1 XTAL RF RS Crystal or Resonator C2 o 3.11 Mini-FlexBus Timing Specifications A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values. MCF51MM256/128, Rev. 5 Freescale Semiconductor 39 Electrical Characteristics Table 20. Mini-FlexBus AC Timing Specifications 1 2 Num C Characteristic Min Max Unit Notes -- -- Frequency of Operation -- 25.1666 MHz -- MB1 D Clock Period 39.73 -- ns -- MB2 D Output Valid -- 20 ns 1 MB3 D Output Hold 1.0 -- ns 1 MB4 D Input Setup 22 -- ns 2 MB5 D Input Hold 10 -- ns 2 Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE. Specification is valid for all MB_D[7:0]. S0 S1 S2 S3 S0 FB_CLK MB1 FB_A[19:16] MB3 ADDR[19:0] MB2 8-bit Non-Mux'd Bus FB_D[7:0] ADDR[31:24] MB5 DATA[7:0] MB4 16-bit Mux'd Bus FB_AD[19:16] FB_AD[15:0] ADDR[19:16] ADDR[15:0] DATA[15:0] FB_R/W FB_ALE FB_CSn, FB_OE Figure 9. Mini-FlexBus Read Timing MCF51MM256/128, Rev. 5 40 Freescale Semiconductor Electrical Characteristics S0 S1 S2 S3 S0 FB_CLK MB1 FB_AD[19:8] MB3 ADDR[19:8] 8-bit Non-Mux'd Bus MB2 FB_AD[7:0] ADDR[7:0] FB_AD[19:16] DATA[7:0] ADDR[19:16] 16-bit Mux'd Bus FB_AD[15:0] ADDR[15:0] DATA[15:0] FB_R/W FB_ALE FB_CSn FB_OE Figure 10. Mini-FlexBus Write Timing MCF51MM256/128, Rev. 5 Freescale Semiconductor 41 Electrical Characteristics 3.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. 3.12.1 Control Timing Table 21. Control Timing # Symbol 1 fBus Parameter Min Typical1 Max C Bus frequency (tcyc = 1/fBus) Unit MHz VDD 1.8 V dc -- 10 VDD > 2.1 V dc -- 20 VDD > 2.4 V dc -- D D 25.165 D 2 tLPO Internal low-power oscillator period 700 1000 1300 P s 3 textrst External reset pulse width2 (tcyc = 1/fSelf_reset) 100 -- -- D ns 4 trstdrv Reset low drive 66 x tcyc -- -- D ns 5 tMSSU Active background debug mode latch setup time 500 -- -- D ns 6 tMSH Active background debug mode latch hold time 100 -- -- D ns tILIH, tIHIL IRQ pulse width * Asynchronous path2 * Synchronous path3 100 1.5 x tcyc -- -- tILIH, tIHIL KBIPx pulse width * Asynchronous path2 * Synchronous path3 100 1.5 x tcyc -- -- 7 8 D D ns ns MCF51MM256/128, Rev. 5 42 Freescale Semiconductor Electrical Characteristics Table 21. Control Timing (continued) # Symbol 9 tRise, tFall Parameter Min Typical1 Max C Port rise and fall time (load = 50 pF)4, Low Drive Unit ns Slew rate control disabled (PTxSE = 0) -- 11 -- D Slew rate control enabled (PTxSE = 1) -- 35 -- D Slew rate control disabled (PTxSE = 0) -- 40 -- D Slew rate control enabled (PTxSE = 1) -- 75 -- D 1 Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40 C to 105 C. 2 textrst RESET PIN Figure 11. Reset Timing tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 12. IRQ/KBIPx Timing MCF51MM256/128, Rev. 5 Freescale Semiconductor 43 Electrical Characteristics 3.12.2 TPM Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 22. TPM Input Timing # C Function Symbol Min Max Unit 1 -- External clock frequency fTPMext dc fBus/4 MHz 2 -- External clock period tTPMext 4 -- tcyc 3 D External clock high time tclkh 1.5 -- tcyc 4 D External clock low time tclkl 1.5 -- tcyc 5 D Input capture pulse width tICPW 1.5 -- tcyc tTPMext tclkh TPMxCLK tclkl Figure 13. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure 14. Timer Input Capture Pulse MCF51MM256/128, Rev. 5 44 Freescale Semiconductor Electrical Characteristics 3.13 SPI Characteristics Table 23 and Figure 15 through Figure 18 describe the timing requirements for the SPI system. Table 23. SPI Timing No.1 Characteristic2 Symbol Min Max Unit C Master Slave fop fBus/2048 0 fBus/2 fBus/4 Hz Hz D Master Slave tSPSCK 2 4 2048 -- tcyc tcyc D Master Slave tLead 12 1 -- -- tSPSCK tcyc D Master Slave tLag 12 1 -- -- tSPSCK tcyc D Master Slave tWSPSCK tcyc -30 tcyc - 30 1024 tcyc -- ns ns D Operating frequency 1 SPSCK period 2 Enable lead time 3 Enable lag time 4 Clock (SPSCK) high or low time 5 Data setup time (inputs) 6 Master Slave tSU tSU 15 15 -- -- ns ns D Master Slave tHI tHI 0 25 -- -- ns ns D ta -- 1 tcyc D tdis -- 1 tcyc D Master Slave tv -- -- 25 25 ns ns D Master Slave tHO 0 0 -- -- ns ns D Input Output tRI tRO -- -- tcyc - 25 25 ns ns D Input Output tFI tFO -- -- tcyc - 25 25 ns ns D Data hold time (inputs) 7 8 9 Slave access time3 Slave MISO disable time 4 Data valid (after SPSCK edge) 10 Data hold time (outputs) 11 Rise time 12 Fall time 13 1 2 3 4 Numbers in this column identify elements in Figure 15 through Figure 18. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. Time to data active from high-impedance state. Hold time to high-impedance state. MCF51MM256/128, Rev. 5 Freescale Semiconductor 45 Electrical Characteristics SS1 (OUTPUT) 2 2 SCK (CPOL = 0) (OUTPUT) 3 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 11 MOSI (OUTPUT) LSB IN 11 MSB OUT2 12 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 15. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 2 2 SCK (CPOL = 0) (OUTPUT) 3 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN(2) 11 MOSI (OUTPUT) BIT 6 . . . 1 LSB IN 12 MSB OUT(2) BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 16. SPI Master Timing (CPHA = 1) MCF51MM256/128, Rev. 5 46 Freescale Semiconductor Electrical Characteristics SS (INPUT) 3 2 SCK (CPOL = 0) (INPUT) 5 4 2 SCK (CPOL = 1) (INPUT) 5 4 8 MISO (OUTPUT) 12 11 BIT 6 . . . 1 MSB OUT SLAVE SLAVE LSB OUT SEE NOTE 7 6 MOSI (INPUT) 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined, but normally MSB of character just received Figure 17. SPI Slave Timing (CPHA = 0) SS (INPUT) 2 3 2 SCK (CPOL = 0) (INPUT) 5 4 SCK (CPOL = 1) (INPUT) 5 4 11 MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) SLAVE 12 MSB OUT 6 BIT 6 . . . 1 9 SLAVE LSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined, but normally LSB of character just received Figure 18. SPI Slave Timing (CPHA = 1) MCF51MM256/128, Rev. 5 Freescale Semiconductor 47 Electrical Characteristics 3.14 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory chapter in the Reference Manual for this device (MCF51MM256RM). Table 24. Flash Characteristics # 3 4 Min Typical Max Unit C Supply voltage for program/erase -40C to 105C Vprog/erase 1.8 -- 3.6 V 2 Supply voltage for read operation VRead 1.8 -- 3.6 V D fFCLK 150 -- 200 kHz D 5 -- 6.67 s D frequency1 D 3 Internal FCLK 4 Internal FCLK period (1/FCLK) tFcyc 5 Byte program time (random location)2 tprog 9 tFcyc P 7 2 Symbol 1 6 1 Characteristic Byte program time (burst mode)2 tBurst 4 tFcyc P 2 tPage 4000 tFcyc P 2 tMass 20,000 tFcyc P Page erase time 8 Mass erase time 9 Program/erase endurance3 TL to TH = -40C to + 105C T = 25C 10 Data retention4 tD_ret 10,000 -- -- 100,000 -- -- cycles 15 100 -- years C C The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. MCF51MM256/128, Rev. 5 48 Freescale Semiconductor Electrical Characteristics 3.15 USB Electricals The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the standard or require additional information, this space would be used to communicate that information. Table 25. Internal USB 3.3 V Voltage Regulator Characteristics # Characteristic Symbol Min Typ Max Unit C 1 Regulator operating voltage Vregin 3.9 -- 5.5 V C 2 VREG output Vregout 3 3.3 3.75 V P 3 VUSB33 input with internal VREG disabled Vusb33in 3 3.3 3.6 V C 4 VREG Quiescent Current IVRQ -- 0.5 -- mA C MCF51MM256/128, Rev. 5 Freescale Semiconductor 49 Electrical Characteristics 3.16 VREF Electrical Specifications Table 26. VREF Electrical Specifications # 1 2 Characteristic Symbol Min Max Unit C VDDA 1.80 3.6 V C 1 Supply voltage 2 Operating temperature range TA -40 105 C C 3 Output Load Capacitance CL -- 100 nF D 4 Maximum Load -- -- 10 mA -- 5 Voltage Reference Output with Factory Trim. VDD = 3 V at 25 C Vout 1.145 1.153 V P 6 Temperature Drift (Vmin--Vmax across the full temperature range) Tdrift -- 25 mV1 T 7 Aging Coefficient2 AC -- 60 V/year C 8 Powered down Current (Off Mode, VREFEN=0, VRSTEN=0) I -- 0.10 A C 9 Bandgap only (Mode_LV[1:0] = 00) I -- 75 A T 10 Low-Power buffer (MODE_LV[1:0] = 01) I -- 125 A T 11 Tight-Regulation buffer (MODE_LV[1:0] = 10) I -- 1.1 mA T 12 Load Regulation MODE_LV = 10 -- -- 100 V/mA C 13 Line Regulation MODE = 1:0, Tight Regulation VDD < 2.3 V, Delta VDDA =100 mV, VREFH = 1.2 V driven externally with VREFO disabled. (Power Supply Rejection) DC 70 -- dB C See typical chart that follows (Figure 20). Linear reliability model (1008 hours stress at 125C = 10 years operating life) used to calculate Aging V/year. VREF0 data recorded per month. Table 27. VREF Limited Range Operating Behaviors # 1 Characteristic Symbol Min Max Unit C 1 Voltage Reference Output with Factory Trim (Temperature range from 0C to 50 C) Vout 1.149 1.152 mV T 2 Temperature Drive (Vmin --Vmax Temperature range from 0 C to 50 C) Tdrift -- 3 mV1 T See typical chart that follows (Figure 20). MCF51MM256/128, Rev. 5 Freescale Semiconductor 47 Electrical Characteristics Figure 19. Typical VREF Output vs. Temperature Figure 20. Typical VREF Output vs. VDD MCF51MM256/128, Rev. 5 Freescale Semiconductor 51 Electrical Characteristics 3.17 TRIAMP Electrical Parameters Table 28. TRIAMP Characteristics 1.8-3.6 V, -40C~105C Characteristic1 # Symbol Min Typ2 Max Unit C VDD 1.8 -- 3.6 V C 1 Operating Voltage 2 Supply Current (IOUT=0mA, CL=0) Low-power mode ISUPPLY -- 52 60 A T 3 Supply Current (IOUT=0mA, CL=0) High-speed mode ISUPPLY -- 432 480 A T 4 Input Offset Voltage VOS -- 1 5 mV T 5 Input Offset Voltage Temperature Drift VOS -- 600 -- V T 6 Input Offset Current IOS -- 120 500 pA T 7 Input Bias Current (0 ~ 50C) IBIAS -- < 350 < 500 pA T 8 Input Bias Current (-40 ~ 105C) IBIAS -- 3 6.55 nA T 9 Input Common Mode Voltage Low VCML 0 -- -- V T 10 Input Common Mode Voltage High VCMH -- -- VDD-1.4 V T 11 Input Resistance RIN 500 -- -- M T 12 Input Capacitances CIN -- -- 5 pF D 13 AC Input Impedance (fIN=100kHz) |XIN| -- 1 -- M D 14 Input Common Mode Rejection Ratio CMRR 60 70 -- dB T 15 Power Supply Rejection Ration PSRR 60 70 -- dB T 16 Slew Rate (VIN=100mV) Low-power mode SR -- 0.1 -- V/s T 17 Slew Rate (VIN=100mV) High-speed mode SR -- 1 -- V/s T 18 Unity Gain Bandwidth (Low-power mode) 50pF GBW 0.15 0.25 -- MHz T 19 Unity Gain Bandwidth (High-speed mode) 50pF GBW -- 1.6 -- MHz T 20 DC Open Loop Voltage Gain AV -- 80 -- dB T 21 Load Capacitance Driving Capability CL(max) -- -- 100 pF T 22 Output Impedance AC Open Loop (@100 kHz Low-power mode) ROUT -- 1.4 -- k D 23 Output Impedance AC Open Loop (@100 kHz High-speed mode) ROUT -- 184 -- D 24 Output Voltage Range triout 0.15 -- VDD - 0.15 V T 25 Output Drive Capability IOUT -- 1.0 -- mA T 26 Gain Margin GM 20 -- -- dB D 27 Phase Margin PM 45 55 -- deg T MCF51MM256/128, Rev. 5 52 Freescale Semiconductor Electrical Characteristics Table 28. TRIAMP Characteristics 1.8-3.6 V, -40C~105C (continued) Characteristic1 # 28 1 2 Input Voltage Noise Density Symbol Min Typ2 Max Unit C f= 1 kHz -- 160 -- nV/Hz T All parameters are measured at 3.0 V, CL= 47 pF across temperature -40 to + 105 C unless specified. Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. 3.18 OPAMP Electrical Parameters Table 29. OPAMP Characteristics 1.8-3.6 V # Characteristics1 Symbol Min Typ2 Max Unit C VDD 1.8 -- 3.6 V C 1 Operating Voltage 2 Supply Current (IOUT=0mA, CL=0 Low-Power mode) ISUPPLY -- 48 80 A T 3 Supply Current (IOUT=0mA, CL=0 High-Speed mode) ISUPPLY -- 350 500 A T 4 Input Offset Voltage VOS -- 2 6 mV T 5 Input Offset Voltage Temperature Coefficient VOS -- 10 -- V/C T 6 Input Offset Current (-40C to 105C) IOS -- 2.5 250 nA T 7 Input Offset Current (-40C to 50C) IOS -- -- 45 nA T 8 Positive Input Bias Current (-40C to 105C) IBIAS -- 0.8 3.5 nA T 9 Positive Input Bias Current (-40C to 50C) IBIAS -- -- 2 nA T 10 Negative Input Bias Current (-40C to 105C) IBIAS -- 2.5 250 nA T 11 Negative Input Bias Current (-40C to 50C) IBIAS -- -- 45 nA T 12 Input Common Mode Voltage Low VCML 0.1 -- -- V T 13 Input Common Mode Voltage High VCMH -- -- VDD V T 14 Input Resistance RIN -- 500 -- M T 15 Input Capacitances CIN -- -- 10 pF D 16 AC Input Impedance (fIN=100kHz Negative Channel) |XIN| -- 52 -- k D 17 AC Input Impedance (fIN=100kHz Positive Channel) |XIN| -- 132 -- k D 18 Input Common Mode Rejection Ratio CMRR 55 65 -- dB T 19 Power Supply Rejection Ratio PSRR 60 65 -- dB T 20 Slew Rate (VIN=100mV Low-Power mode) SR 0.1 -- -- V/s T 21 Slew Rate (VIN=100mV High-Speed mode) SR 1 -- -- V/s T 22 Unity Gain Bandwidth (Low-Power mode) GBW 0.2 -- -- MHz T 23 Unity Gain Bandwidth (High-Speed mode) GBW 1 -- -- MHz T 24 DC Open Loop Voltage Gain AV 80 90 -- dB T 25 Load Capacitance Driving Capability CL(max) -- -- 100 pF T 26 Output Impedance AC Open Loop (@100 kHz Low-Power mode) ROUT -- 4k -- D MCF51MM256/128, Rev. 5 Freescale Semiconductor 53 Electrical Characteristics Table 29. OPAMP Characteristics 1.8-3.6 V (continued) 1 2 # Characteristics1 Symbol Min Typ2 Max Unit C 27 Output Impedance AC Open Loop (@100 kHz High-Speed mode) ROUT -- 220 -- D 28 Output Voltage Range VOUT 0.15 -- VDD-0.1 5 V T 29 Output Drive Capability IOUT 0.5 1.0 -- mA T 30 Gain Margin GM 20 -- -- dB D 31 Phase Margin PM 45 55 -- deg T 32 GPAMP startup time (Low-Power mode) (Tolerance < 1%, Vin = 0.5 Vp-p, CL = 25 pF, RL = 100k) Tstartup -- 4 -- uS T 33 GPAMP startup time (Low-Power mode) (Tolerance < 1%, Vin = 0.5 Vp-p, CL = 25 pF, RL = 100k) Tstartup -- 1 -- uS T 34 Input Voltage Noise Density f=1 kHz -- 250 -- nV/Hz T All parameters are measured at 3.3 V, CL =4 7 pF across temperature -40 to + 105C unless specified. Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. MCF51MM256/128, Rev. 5 54 Freescale Semiconductor Ordering Information 4 Ordering Information This section contains ordering information for the device numbering system. See Table 1 for feature summary by package information. 4.1 Part Numbers Table 30. Orderable Part Number Summary Freescale Part Number Description Flash / SRAM (Kbytes) Package Temperature MCF51MM256VML MCF51MM256 ColdFire Microcontroller 256K/32K 104 MAPBGA -40 to 105 C MCF51MM256VLL MCF51MM256 ColdFire Microcontroller 256K/32K 100 LQFP -40 to 105 C MCF51MM256VMB MCF51MM256 ColdFire Microcontroller 256K/32K 81 MAPBGA -40 to 105 C MCF51MM256VLK MCF51MM256 ColdFire Microcontroller 256K/32K 80 LQFP -40 to 105 C MCF51MM128VMB MCF51MM128 ColdFire Microcontroller 128K/32K 81 MAPBGA -40 to 105 C MCF51MM128VLK MCF51MM128 ColdFire Microcontroller 128K/32K 80 LQFP -40 to 105 C 4.2 Package Information Table 31. Package Descriptions Pin Count 4.3 Package Type Abbreviation Designator Case No. Document No. 100 Low Quad Flat Package LQFP LL 983-03 98ASS23308W 80 Low Quad Flat Package LQFP LK 1418 98ASS23174W 104 MAP BGA Package MAPBGA ML 1285-02 98ARH98267A 81 MAP BGA Package MAPBGA MB 1662-01 98ASA10670D Mechanical Drawings Table 31 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MCF51MM256/128 Product Summary pages at http://www.freescale.com. To view the latest drawing, either: * Click on the appropriate link in Table 31, or * Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate document number (from Table 31) in the "Enter Keyword" search box at the top of the page. . MCF51MM256/128, Rev. 5 Freescale Semiconductor 53 Revision History 5 Revision History This section lists major changes between versions of the MCF51MM256 Data Sheet. Table 32. Revision History Revision 0 Date Description March/April 2009 Initial Draft 1 July 2009 * * * * 2 July 2009 * Changed MCG (XOSC) Electricals Table - Row 2, Average Internal Reference Frequency typical value from 32.768 to 31.25. 3 April 2010 * Updated Thermal Characteristics table. Reinserted the 81 and 104 MapBGA devices. * Revised the ESD and Latch-Up Protection Characteristic description to read: Latch-up Current at TA = 125C. * Changed Table 9. DC Characteristics rows 2 and 4, to 1.8 V, ILoad = -600 mA conditions to 1.8 V, ILoad = 600A respectively. * Corrected the 16-bit SAR ADC Operating Condition table Ref Voltage High Min value to be 1.13 instead of 1.15. * Updated the ADC electricals. * Inserted the Mini-FlexBus Timing Specifications. * Added a Temp Drift parameter to the VREF Electrical Specifications. * Removed the S08 Naming Convention diagram. * Updated the Orderable Part Number Summary to include the Freescale Part Number suffixes. * Completed the Package Description table values. * Changed the 80LQFP package drawing from 98ARL10530D to 98ASS23174W. * Updated electrical characteristic data. 4 October 2010 * Updated with the latest characteristic data. Added several figures. Added the ADC Typical Operation table. July 2012 In "Supply current characteristics" table, * For S3IDD, the maximum value for the first row at 1A is changed to 1.3 A and the typical value 0.65 A is changed to 0.75A. * For parameter 3, changed "LPS" to "LPR", "FBILP" to "FBI" and "FBELP" to "FBE". * For parameter 4, changed "LPS" to "LPR", and "FBELP" to "BLPE" in both instances. 5 Revised to follow standard template. Removed extraneous headings from the TOC. Corrected units for Monotonocity to be blank in for the DAC specification. Updated ADC characteristic tables to include 16-Bit SAR in headings. MCF51MM256/128, Rev. 5 Freescale Semiconductor 53 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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