Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51MM256
Rev. 5, 07/2012
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
32-Bit ColdFire V1 Central Processor Unit (CPU)
• Up to 50.33 MHz ColdFire CPU above 2.4 V and 40 MHz CPU
above 2.1V and 20 MHz CPU above 1.8 V across temperature
range of -40°C to 105°C.
• ColdFire Instruction Set Revision C (ISA_C).
• 32-bit multiply and accumulate (MAC) supports signed or
unsigned integer or signed fractional inputs.
On-Chip Memory
• 256 K Flash comprised of two independent 128 K flash arrays;
read/program/erase over full operating voltage and temperature;
allows interrupt processing while programming.
• 32 KB System Random-access memory (RAM).
• Security circuitry to prevent unauthorized access to RAM and
Flash contents.
Power-Saving Modes
• Two ultra-low power stop modes. Peripheral clock enable register
can disable clocks to unused modules to reduce currents.
• Time of Day (TOD) — Ultra low-power 1/4 sec counter with up to
64 sec timeout.
• Ultra-low power external oscillator that can be used in stop modes to
provide accurate clock source to the TOD. 6 µs typical wake up
time from stop3 mode.
Clock Source Options
• Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz
crystal
or ceramic resonator dedicated for TOD operation.
• Oscillator (XOSC2) for high frequency crystal input for MCG
reference to be used for system clock and USB operations.
• Multipurpose Clock Generator (MCG) — PLL and FLL; precision
trimming of internal reference allows 0.2% resolution and typical
+0.5%
to -1% deviation over temperature and voltage; supports CPU
frequencies from 4 kHz to 50 MHz.
System Protection
• Watchdog computer operating properly (COP) reset with option to
run from dedicated 1 kHz internal clock source or bus clock.
• Low-voltage detection with reset or interrupt; selectable trip points;
separate low voltage warning with optional interrupt; selectable
trip points.
• Illegal opcode and illegal address detection with reset.
• Flash block protection for each array to prevent accidental write /
erasure.
• Hardware CRC to support fast cyclic redundancy checks.
Development Support
• Integrated ColdFire DEBUG_Rev_B+ interface with single wire
BDM connection supports same electrical interface used by the
S08 family debug modules.
• Real-time debug with 6 hardware breakpoints (4 PC, 1 address
and 1 data).
• On-chip trace buffer provides programmable start/stop
recording conditions.
Peripherals
•
USB
— Dual-role USB On-The-Go (OTG) device, supports USB in
either device, host or OTG configuration. On-chip transceiver and 3.3V
regulator help save system cost, fully compliant with USB Specification
2.0. Allows control, bulk, interrupt and isochronous transfers.
•
SCIx
— Two serial communications interfaces with optional 13-bit
break; option to connect Rx input to PRACMP output on SCI1 and
SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from
stop3 on Rx edge.
•
SPI1
— Serial peripheral interface with 32-bit FIFO buffer; 16-bit or
8-bit data transfers; full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave mode;
MSB-first or LSB-first shifting.
•
SPI2
— Serial peripheral interface with full-duplex or single-wire
bidirectional; Double-buffered transmit and receive; Master or Slave
mode; MSB-first or LSB-first shifting.
•
IIC
— Up to 100 kbps with maximum bus loading; Multi-master
operation; Programmable slave address; Interrupt driven
byte-by-byte data transfer; supports broadcast mode and 11-bit
addressing.
•
CMT
— Carrier Modulator timer for remote control communications.
Carrier generator, modulator and driver for dedicated infrared out
(IRO). Can be used as an output compare timer.
•
TPM
x — Two 4-channel Timer/PWM Module; Selectable input
capture, output compare, or buffered edge- or center-aligned PWM
on each channel; external clock input/pulse accumulator.
•
Mini-FlexBus
— Multi-function external bus interface with user
programmable chip selects and the option to multiplex address and
data lines.
•
PRACMP
— Analog comparator with selectable interrupt; compare
option to programmable internal reference voltage; operation in
stop3.
Measurement Engine
•
ADC16
— 16-bit successive approximation ADC with up to 4
dedicated differential channels and 8 single-ended channels; range
compare function; 1.7 mV/×C temperature sensor; internal bandgap
reference channel; operation in stop3; fully functional from 3.6 V to
1.8 V, Configurable hardware trigger for 8 Channel select and result
registers.
•
PDB
— Programmable delay block with 16-bit counter and modulus
and prescale to set reference clock to bus divided by 1 to bus divided
by 2048; 8 trigger outputs for ADC module provides periodic
coordination of ADC sampling sequence with sequence completion
interrupt; Back-to-Back mode and Timed mode.
•
DAC
— 12-bit resolution DAC; configurable settling time.
•
OPAMPx
— 2 flexible operational amplifiers configurable for general
operations; Low offset and temperature drift.
•
TRIAMPx
— 2 trans-impedance amplifiers dedicated for converting
current inputs into voltages.
Input/Output
• Up to 68 GPIOs and 1 output-only pin.
• Voltage Reference output (VREFO).
• Dedicated infrared output pin (IRO)with high current sink capability.
• Up to 16 KBI pins with selectable polarity.
• Up to 16 pins of rapid general purpose I/O
(RGPIO).
MCF51MM256/128
The MCF51MM256 series devices are members of the
low-cost, low-power, high-performance ColdFire V1 family of
32-bit microcontrollers (MCUs) designed for handheld metering
devices.
Not all features are available in all devices or packages; see
Table 1 for a comparison of features by device.
80-LQFP
12mm x 12mm 81-BGA
10mm x 10mm
100-LQFP
14mm x 14mm 104-BGA
10mm x 10mm
Document Number: MCF51MM256
Rev. 5, 07/2012
An Energy-Efficient Solution from Freescale
Freescale Semiconductor2
Table of Contents
1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Pinouts and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .17
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
3.4 ESD Protection Characteristics. . . . . . . . . . . . . . . . . . .20
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .23
3.7 PRACMP Electrical Parameters . . . . . . . . . . . . . . . . . .26
3.8 12-Bit DAC Electrical Parameters . . . . . . . . . . . . . . . . .26
3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.10 MCG and External Oscillator (XOSC) Characteristics .35
3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .38
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.15 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .47
3.17 TRIAMP Electrical Parameters . . . . . . . . . . . . . . . . . . .49
3.18 OPAMP Electrical Parameters . . . . . . . . . . . . . . . . . . .50
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .52
5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
List of Figures
Figure 1.MCF51MM256/128 Block Diagram . . . . . . . . . . . . . . . . 6
Figure 2.104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3.100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4.81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5.80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6.Stop IDD versus Temperature. . . . . . . . . . . . . . . . . . . 25
Figure 7.Offset at Half Scale vs Temperature . . . . . . . . . . . . . . 28
Figure 8.ADC Input Impedance Equivalency Diagram . . . . . . . 30
Figure 9.Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . 39
Figure 10.Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 39
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13.Timer External Clock. . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . 42
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 44
Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 44
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 45
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 45
Figure 19.Typical VREF Output vs. Temperature . . . . . . . . . . . . 48
Figure 20.Typical VREF Output vs. VDD. . . . . . . . . . . . . . . . . . . 48
List of Tables
Table 1. MCF51MM256/128 Features by MCU and Package . . 3
Table 2. MCF51MM256/128 Functional Units . . . . . . . . . . . . . . . 6
Table 3. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 18
Table 6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 20
Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 20
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10.Supply Current Characteristics . . . . . . . . . . . . . . . . . . 23
Table 11.Typical Stop Mode Adders. . . . . . . . . . . . . . . . . . . . . . 24
Table 12.PRACMP Electrical Specifications . . . . . . . . . . . . . . . 26
Table 13.DAC 12LV Operating Requirements . . . . . . . . . . . . . . 26
Table 14.DAC 12-Bit Operating Behaviors . . . . . . . . . . . . . . . . . 27
Table 15.16-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 28
Table 16.16-bit SAR ADC Characteristics full operating range
(VREFH = VDDA > 1.8, VREFL = VSSA 8 Hz, -40 oC to
85 oC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17.16-bit SAR ADC Characteristics full operating range
(VREFH = VDDA 2.7 V, VREFL = VSSA, fADACK 4 MHz,
ADHSC=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 18.MCG (Temperature Range = –40 oC to 105 oC Ambient)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19.XOSC Specifications (Temperature Range = –40 oC to
105 oC Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20.Mini-FlexBus AC Timing Specifications . . . . . . . . . . . . 38
Table 21.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23.SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25.Internal USB 3.3 V Voltage Regulator Characteristics 46
Table 26.VREF Electrical Specifications . . . . . . . . . . . . . . . . . . 47
Table 27.VREF Limited Range Operating Behaviors . . . . . . . . . 47
Table 28.TRIAMP Electrical Characteristics 1.8-3.6 V, -40°C~105°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 29.OPAMP Characteristics 1.8-3.6 V . . . . . . . . . . . . . . . . 50
Table 30.Orderable Part Number Summary. . . . . . . . . . . . . . . . 51
Table 31.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 32.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MCF51MM256/128, Rev. 5
Features
Freescale Semiconductor 3
1Features
The following table provides a cross-comparison of the features of the MCF51MM256/128 according to
package. Table 1. MCF51MM256/128 Features by MCU and Package
Feature MCF51MM256 MCF51MM128
FLASH Size (bytes) 262144 131072
RAM Size (bytes) 32K 32K
Pin Quantity 104 100 81 80 81 80
Programmable Analog Comparator (PRACMP) yes yes yes yes yes yes
Debug Module (DBG) yes yes yes yes yes yes
Multipurpose Clock Generator (MCG) yes yes yes yes yes yes
Inter-Integrated Communication (IIC) yes yes yes yes yes yes
Interrupt Request Pin (IRQ) yes yes yes yes yes yes
Keyboard Interrupt (KBI) 16 16 16 16 16 16
Digital General Purpose I/O1
1Port I/O count does not include BLMS, BKGD and IRQ. BLMS and BKGD are Output only, IRQ is input only.
69 65 48 47 48 47
Dedicated Analog Input Pins 14 14 14 14 14 14
Power and Ground Pins 8 8 8 8 8 8
Time Of Day (TOD) yes yes yes yes yes yes
Serial Communications (SCI1) yes yes yes yes yes yes
Serial Communications (SCI2) yes yes yes yes yes yes
Serial Peripheral Interface (SPI1(FIFO)) yes yes yes yes yes yes
Serial Peripheral Interface(SPI2) yes yes yes yes yes yes
Carrier Modulator Timer Pin (IRO) yes yes yes yes yes yes
TPM Input Clock Pin (TPMCLK) yes yes yes yes yes yes
TPM1 Channels 4 4 4 4 4 4
TPM2 Channels 4 4 4 4 4 4
XOSC1 yes yes yes yes yes yes
XOSC2 yes yes yes yes yes yes
USB On-the-Go yes yes yes yes yes yes
Mini-FlexBus yes yes DATA2
2The 80/81 pin packages contain the Mini-FlexBus data pins to support an 8-bit data bus interface to external peripherals.
DATA2DATA2DATA2
Rapid GPIO 16 16 9 9 9 9
MEASUREMENT ENGINE
Programmable Delay Block (PDB) yes yes yes yes yes yes
16-Bit SAR ADC Differential Channels3
3Each differential channel is comprised of 2 pin inputs.
444444
16-Bit SAR ADC Single-Ended Channels 8 8 8 8 8 8
DAC Ouput Pin (DACO) yes yes yes yes yes yes
Voltage Reference Output Pin (VREFO) yes yes yes yes yes yes
General Purpose Operational Amplifier (OPAMP) yes yes yes yes yes yes
Trans-Impedance Amplifier (TRIAMP) yes yes yes yes yes yes
MCF51MM256/128, Rev. 5
Freescale Semiconductor4
Figure 1. MCF51MM256 Series Block Diagram
OUT1
INP1–
Port B
Port D Port C
Port E Port A
SPI1
VREG
SIM
V1 ColdFire Core
USB_DM
USB_DP
SS1
SPSCK1
MOSI1
MISO1
SCI2 RX2
TX2
RAM
MCG
VREFH/VREFL
VDDA/VSSA
VDD1,2,3 VSS1,2,3
COP
32KB
XOSC2
LVD
TPM2 (4-Ch)
DBG
INTC
TPM1 (4-Ch)
VREF
CMT IRO
RGPIO RGPIO[15:8]
Port A:
RGPIO[7:0]
CLKO
SCI1 RX1
TX1
PDB
KBI1 &
PTD0/BKGD/MS
IIC
SDA
SCL
PRACMP
VREFO
ACMPO
ACMPO
FLASH1
128/64 KB
Robust
Update
Manager
Hardware CRC
KBI1P[7:0]
with MAC
VDDA/VSSA
VREFH/VREFL
ADC16 DADP/M[3:0]
AD[11:4]
HWTS[H:A]
HWTS[H:A]
EXTAL1
XTAL1
XOSC1 CLKO
TOD
control
REF CLK IRCLK
Clock Check
& Select
SPI2
SS2
SPSCK2
MOSI2
MISO2
Port F
IRQ
PTE4/CMPP3/
TPMCLK/IRQ
TPMCLK
TPM1CH [3:0]
TPMCLK
TPM2CH [3:0]
control
KBI2P[7:0]
VDDA/VSSA
VREFH/VREFL
DACO
USBOTG
FLASH2
128/64 KB
USB_DM USB_DP VBUS
OPAMP1
TRIAMP2
Port G
Port H
Port J
Dtrig
Dtrig
COCOx
USB_ALTCLK
USB_PULLUP(D+)
USB_DM_DOWN
USB_DP_DOWN
USB_VBUSVLD
USB_ID
USB_SESSVLD
USB_SESSEND
MINIFLEX
FB_AD[19:0]
BUS
FB_D[7:0]
DACO
DADP/M [3:0]
INP0+
INP0-
VINP1
VINN1
TRIOUT1
TRIOUT1
VINN1/VINP1
IRO
FB_AD12
Green —pins not available on the 100, 81 or 80-pin package
Blue — pins not available on the 81 or 80-pin package
Red —pin not available on the 80-pin package
VUSB33
PTB3/XTAL1
PTB4/EXTAL2
PTB5/XTAL2
PTB2/EXTAL1
PTB1/BLMS
PTB0
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTD3/USB_PULLUP(D+)/RGPIOP9/
PTD4/SDA/RGPIOP10/TPM1CH2
PTD5/SCL/RGPIOP11/TPM1CH3
PTD2/USB_ALTCLK/RGPIOP8/
PTD1/CMPP2/
PTD6/USB_ALTCLK/TX1
PTD7/USB_PULLUP(D+)/RX1
PTC3/KBI1P6/SS2/ADP7
PTC4/KBI1P7/CMPP0/ADP8
PTC5/KBI2P0/CMPP1/ADP9
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE_b/FB_CS0
PTC6/KBI2P1/PRACMPO/ADP10
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP0+
PTA5
PTA2/KBI1P1/RX1/ADP4
PTA1/KBI1P0/TX1/FB_D1
PTA0/FB_D2/SS1
PTA6
PTA7/INP1+
PTF3/SCL/FB_D5/FB_AD11
PTF4/SDA/FB_D4/FB_AD10
PTF5/KBI2P7/FB_D3/FB_AD9
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTF6/MOSI1
PTF7/MISO1
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE3/KBI2P6/FB_AD8
PTE5/FB_D7/USB_SESSVLD/TX2
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTE6/FB_RW_b/USB_SESSEND/RX2
PTE7/USB_VBUSVLD/TPM2CH3
PTG3/USB_DP_DOWN
PTG4/USB_SESSVLD
PTG5/FB_RW_b
PTG2/USB_DM_DOWN
PTG1/USB_SESSEND
PTG0/SPSCK1
PTG6/FB_AD19
PTG7/FB_AD18
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
PTH5/RGPIOP5/FB_D4
PTH2/RGPIOP2/FB_D7
PTH1/FB_D0
PTH0/FB_OE_b
PTH6/RGPIOP6/FB_D3
PTH7/RGPIOP7/FB_D2
PTJ3/RGPIOP12/FB_AD5
PTJ4/RGPIOP15/FB_AD16
PTJ5/FB_AD15
PTJ2/FB_AD4
PTJ1/FB_AD3
PTJ0/FB_AD2
PTJ6/FB_AD14
PTJ7/FB_AD13
PTC7/KBI2P2/CLKOUT/ADP11
TRIAMP1
VINP0
VINN0
TRIOUT0
TRIOUT0
VINN0/VINP0
OUT0
OPAMP2 INP1+
INP1-
OUT1
RESET
KBI2
BKGD/MS
BDM
OUT0
INP0–
VREFO
VREFO
TPM1CH1
TPM1CH0
MCF51MM256/128, Rev. 5
Features
Freescale Semiconductor 5
The following table describes the functional units of the MCF51MM256/128.
Table 2. MCF51MM256/128 Functional Units
Unit Function
Measurement Engine
DAC (digital to analog converter) — Used to output voltage levels.
16-BIT SAR ADC (analog-to-digital converter) — Measures analog
voltages at up to 16 bits of resolution. The ADC has up to four differential
and 8 single-ended inputs.
OPAMP — General purpose op amp used for signal filtering or
amplification.
TRIAMP —- Transimpedance amplifier optimized for converting small
currents into voltages.
Measurement Engine PDB — The measurement engine PDB is used to
precisely trigger the DAC and the ADC modules to complete sensor
biasing and measuring.
Mini-FlexBus Provides expansion capability for off-chip memory and peripherals.
USB On-the-Go Supports the USB On-the-Go dual-role controller.
CMT (Carrier Modulator Timer) Infrared output used for the Remote Controller operation.
MCG (Multipurpose Clock Generator) Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources.
BDM (Background Debug Module) Provides single pin debugging interface (part of the V1 ColdFire core).
CF1 CORE (V1 ColdFire Core) Executes programs and interrupt handlers.
PRACMP Analog comparators for comparing external analog signals against
each other, or a variety of reference levels.
COP (Computer Operating Properly) Software Watchdog.
IRQ (Interrupt Request) Single-pin high-priority interrupt (part of the V1 ColdFire core).
CRC (Cyclic Redundancy Check) High-speed CRC calculation.
DBG (Debug) Provides debugging and emulation capabilities (part of the V1 Co ldFire.
core)
FLASH (Flash Memory) Provides storage for program code, constants, and variables.
IIC (Inter-integrated Circuits) Supports standard IIC communications protocol and SMBus.
INTC (Interrupt Controller) Controls and prioritizes all device interrupts.
KBI1 & KBI2 Keyboard Interfaces 1 and 2.
LVD (Low-voltage Detect)
Provides an interrupt to theColdFire V1 CORE in the event that the
supply voltage drops below a critical value. The LVD can also be
programmed to reset the device upon a low voltage event.
VREF (Voltage Reference) The Voltage Reference output is available for both on- and off-chip use.
RAM (Random-Access Memory) Provides stack and variable storage.
RGPIO (Rapid General-purpose
Input/output)
Allows for I/O port access at CPU clock speeds. RGPIO is used to
implement GPIO functionality.
MCF51MM256/128, Rev. 5
Features
Freescale Semiconductor6
SCI1, SCI2 (Serial Communications
Interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols.
SIM (system integration unit)
SPI1 (FIFO), SPI2 (Serial Peripheral
Interfaces)
SPI1 and SPI2 provide standard master/slave capability. SPI contains a
FIFO buffer in order to increase the throughput for this peripheral.
TPM1, TPM2 (Timer/PWM Module) Timer/PWM module can be used for a variety of generic timer
operations as well as pulse-width modulation.
VREG (Voltage Regulator) Controls power management across the device.
XOSC1 and XOSC2 (Crystal Oscillators)
These devices incorporate redundant crystal oscillators. One is
intended primarily for use by the TOD, and the other by the CPU and
other peripherals.
Table 2. MCF51MM256/128 Functional Units (continued)
Unit Function
MCF51MM256/128, Rev. 5
Pinouts and Pin Assignments
Freescale Semiconductor 7
2 Pinouts and Pin Assignments
2.1 104-Pin MAPBGA
The following figure shows the 104-pin MAPBGA pinout confi guration.
1234567891011
APTF6 PTF7 USB_DP USB_DM VUSB33 PTF4 PTF3 FB_AD12 PTJ7 PTJ5 PTJ4 A
BPTG0 PTA0 PTG3 VBUS PTF5 PTJ6 PTH0 PTE5 PTF0 PTF1 PTF2 B
CIRO PTG4 PTA6 PTG2 PTG6 PTG5 PTG7 PTH1 PTE4 PTE6 PTE7 C
DPTA5 PTA4 PTB1 VDD1 VDD2 VDD3 PTA1 PTE3 PTE2 D
EVSSA PTA7 PTB0 PTA2 PTJ3 PTE1 E
FVREFL INP1- INP2- PTG1 PTC7 PTJ2 PTJ0 PTJ1 F
GTRIOUT1 OUT1 OUT2 PTD5 PTD7 PTE0 G
HVINP1 VINN1 PTA3 VSS1 VSS2 VSS3 PTD4 PTD3 PTD2 H
JDADP0 DADM0 PTH7 PTH6 PTH4 PTH3 PTH2 PTD6 PTC2 PTC0 PTC1J
KVINP2 VINN2 DADP1 PTH5 PTB6 PTB7 PTC3 PTD1 PTC4 PTC5 PTC6 K
LTRIOUT2 DACO DADM1 VREFO VREFH VDDA PTB3 PTB2 PTD0 PTB5 PTB4 L
1234567891011
Figure 2. 104-Pin MAPBGA
MCF51MM256/128, Rev. 5
Pinouts and Pin Assignments
Freescale Semiconductor8
2.2 100-Pin LQFP
The following figure shows the 100-pin LQFP pinout configuration.
Figure 3. 100-Pin LQFP
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
FB_AD12
PTJ7/FB_AD13
PTJ6/FB_AD14
PTJ4/RGPIOP15/FB_AD16
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
VDD3
VSS3
PTJ5/FB_AD15
PTC2/KBI1P5/SPSCK2/ADP6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTA0/FB_D2/SS1
IRO
PTG5/FB_RW
PTG6/FB_AD19
PTG7/FB_AD18
PTH0/FB_OE
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA5
PTA6
PTB0
PTB1/BLMS
VSSA
VREFL
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
PTJ1/FB_AD3
PTJ0/FB_AD2
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE/FB_CS0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DACO
DADP0
DADM0
VREFO
DADP1
DADM1
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTH2/RGPIOP2/FB_D7
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
PTH5/RGPIOP5/FB_D4
PTH6/RGPIOP6/FB_D3
PTH7/RGPIOP7/FB_D2
PTH1/FB_D0
PTC3/KBI1P6/SS2/ADP7
PTE4/CMPP3/TPMCLK/IRQ
PTA4/INP1+
PTA7/INP2+
INP1-
OUT1
TRIOUT1/DADP2-
VINP1
VINN1/DADM2
INP2-
OUT2
TRIOUT2/DADP3
VINP2
VINN2/DADM3
MCF51MM256/128, Rev. 5
Pinouts and Pin Assignments
Freescale Semiconductor 9
2.3 81-Pin MAPBGA
The following figure shows the 81-pin MAPBGA pinout configuration.
123456789
AIRO PTG0 PTF6 USB_DP VBUS VUSB33 PTF4 PTF3 PTE4 A
BPTF7 PTA0 PTG1 USB_DM PTF5 PTE7 PTF1 PTF0 PTE3 B
CPTA4 PTA5 PTA6 PTA1 PTF2 PTE6 PTE5 PTE2 PTE1 C
DI N P 1 - P TA 7 P T B 0 P T B 1 P TA 2 P TA 3 P T D 5 P T D 7 P T E 0 D
EOUT1 VINN1 OUT2 VDD2 VDD3 VDD1 PTD2 PTD3 PTD6 E
FVINP1 TRIOUT1 INP2- VSS2 VSS3 VSS1 PTB7 PTC7 PTD4 F
GDADP0 DACO TRIOUT2 VINN2 VREFO PTB6 PTC0 PTC1 PTC2 G
HDADM0 DADM1 DADP1 VINP2 PTC3 PTC4 PTD0 PTC5 PTC6 H
JVSSA VREFL VREFH VDDA PTB2 PTB3 PTD1 PTB4 PTB5 J
123456789
Figure 4. 81-Pin MAPBGA
MCF51MM256/128, Rev. 5
Pinouts and Pin Assignments
Freescale Semiconductor10
2.4 80-Pin LQFP
The following figure shows the 80-pin LQFP pinout configuration.
Figure 5. 80-Pin LQFP
PTA0/FB_D2/SS1
IRO
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA5
PTA6
PTB0
PTB1/BLMS
VSSA
VREFL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
DACO
DADP0
DADM0
VREFO
DADP1
DADM1
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTC0/MOSI2/FB_OE/FB_CS0
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
VDD3
VSS3
80-Pin LQFP
PTE4/CMPP3/TPMCLK/IRQ
PTA4/INP1+
PTA7/INP2+
INP1-
OUT1
TRIOUT1/DADP2-
VINP1
VINN1DADM2
INP2-
OUT2
TRIOUT2/DADP3
VINP2
VINN2/DADM3
MCF51MM256/128, Rev. 5
Pinouts and Pin Assignments
Freescale Semiconductor 11
2.5 Pin Assignments
Table 3. Package Pin Assignments
Package
Default
Function
Alternate
1
Alternate
2
Alternate
3Composite Pin Name
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
B2 1 B2 1 PTA0 FB_D2 SS1 — PTA0/FB_D2/SS1
C1 2 A1 2 IRO — — — IRO
C6 3 — — PTG5 FB_RW — — PTG5/FB_RW
C5 4 — — PTG6 FB_AD19 — — PTG6/FB_AD19
C7 5 — — PTG7 FB_AD18 — — PTG7/FB_AD18
B7 6 — — PTH0 FB_OE— — PTH0/FB_OE
C8 7 — — PTH1 FB_D0 — — PTH1/FB_D0
D9 8 C4 3 PTA1 KBI1P0 TX1 FB_D1 PTA1/KBI1P0/TX1/FB_D1
E9 9 D5 4 PTA2 KBI1P1 RX1 ADP4 PTA2/KBI1P1/RX1/ADP4
H3 10 D6 5 PTA3 KBI1P2 FB_D6 ADP5 PTA3/KBI1P2/FB_D6/ADP5
D2 11 C1 6 PTA4 INP1+ — — PTA4/INP1+
D1 12 C2 7 PTA5 — — — PTA5
C3 13 C3 8 PTA6 — — — PTA6
E2 14 D2 9 PTA7 INP2+ — — PTA7/INP2+
E3 15 D3 10 PTB0 — — — PTB0
D3 16 D4 11 PTB1 BLMS — — PTB1/BLMS
E1 17 J1 12 VSSA — — — VSSA
F1 18 J2 13 VREFL — — — VREFL
F2 19 D1 14 INP1- — — — INP1-
G2 20 E1 15 OUT1 — — — OUT1
G1 21 F2 16 DADP2 TRIOUT1 — — DADP2/TRIOUT1
H1 22 F1 17 VINP1 — — — VINP1
H2 23 E2 18 DADM2 VINN1 — — DADM2/VINN1
F3 24 F3 19 INP2- — — — INP2-
G3 25 E3 20 OUT2 — — — OUT2
L2 26 G2 21 DACO — — — DACO
L1 27 G3 22 DADP3 TRIOUT2 — — DADP3/TRIOUT2
K1 28 H4 23 VINP2 — — — VINP2
K2 29 G4 24 DADM3 VINN2 — — DADM3/VINN2
MCF51MM256/128, Rev. 5
Pinouts and Pin Assignments
Freescale Semiconductor12
J1 30 G1 25 DADP0 — — — DADP0
J2 31 H1 26 DADM0 — — — DADM0
L4 32 G5 27 VREFO — — — VREFO
K3 33 H3 28 DADP1 — — — DADP1
L3 34 H2 29 DADM1 — — — DADM1
L5 35 J3 30 VREFH — — — VREFH
L6 36 J4 31 VDDA — — — VDDA
H6 37 F4 32 VSS2 — — — VSS2
L8 38 J5 33 PTB2 EXTAL1 — — PTB2/EXTAL1
L7 39 J6 34 PTB3 XTAL1 — — PTB3/XTAL1
D6 40 E4 35 VDD2 — — — VDD2
L11 41 J8 36 PTB4 EXTAL2 — — PTB4/EXTAL2
L10 42 J9 37 PTB5 XTAL2 — — PTB5/XTAL2
K5 43 G6 38 PTB6 KBI1P3 RGPIOP0 FB_AD17 PTB6/KBI1P3/RGPIOP0/FB_AD17
K6 44 F7 39 PTB7 KBI1P4 RGPIOP1 FB_AD0 PTB7/KBI1P4/RGPIOP1/FB_AD0
J7 45 — — PTH2 RGPIOP2 FB_D7 — PTH2/RGPIOP2/FB_D7
J6 46 — — PTH3 RGPIOP3 FB_D6 — PTH3/RGPIOP3/FB_D6
J5 47 — — PTH4 RGPIOP4 FB_D5 — PTH4/RGPIOP4/FB_D5
K4 48 — — PTH5 RGPIOP5 FB_D4 — PTH5/RGPIOP5/FB_D4
J4 49 — — PTH6 RGPIOP6 FB_D3 — PTH6/RGPIOP6/FB_D3
J3 50 — — PTH7 RGPIOP7 FB_D2 — PTH7/RGPIOP7/FB_D2
J10 51 G7 40 PTC0 MOSI2 FB_OE FB_CS0 PTC0/MOSI2/FB_OE/FB_CS0
J11 52 G8 41 PTC1 MISO2 FB_D0 FB_AD1 PTC1/MISO2/FB_D0/FB_AD1
J9 53 G9 42 PTC2 KBI1P5 SPSCK2 ADP6 PTC2/KBI1P5/SPSCK2/ADP6
K7 54 H5 43 PTC3 KBI1P6 SS2 ADP7 PTC3/KBI1P6/SS2/ADP7
K9 55 H6 44 PTC4 KBI1P7 CMPP0 ADP8 PTC4/KBI1P7/CMPP0/ADP8
K10 56 H8 45 PTC5 KBI2P0 CMPP1 ADP9 PTC5/KBI2P0/CMPP1/ADP9
K11 57 H9 46 PTC6 KBI2P1 PRACMPO ADP10 PTC6/KBI2P1/PRACMPO/ADP10
F8 58 F8 47 PTC7 KBI2P2 CLKOUT ADP11 PTC7/KBI2P2/CLKOUT/ADP11
L9 59 H7 48 PTD0 BKGD MS — PTD0/BKGD/MS
K8 60 J7 49 PTD1 CMPP2 RESET — PTD1/CMPP2/RESET
Table 3. Package Pin Assignments (continued)
Package
Default
Function
Alternate
1
Alternate
2
Alternate
3Composite Pin Name
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
MCF51MM256/128, Rev. 5
Pinouts and Pin Assignments
Freescale Semiconductor 13
H11 61 E7 50 PTD2 USB_ALTCLK RGPIOP8 TPM1CH0 PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
H10 62 E8 51 PTD3 USB_PULLUP
(D+) RGPIOP9 TPM1CH1 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
H9 63 F9 52 PTD4 SDA RGPIOP10 TPM1CH2 PTD4/SDA/RGPIOP10/TPM1CH2
G9 64 D7 53 PTD5 SCL RGPIOP11 TPM1CH3 PTD5/SCL/RGPIOP11/TPM1CH3
J8 65 E9 54 PTD6 USB_ALTCLK TX1 — PTD6/USB_ALTCLK/TX1
G10 66 D8 55 PTD7 USB_PULLUP
(D+) RX1 — PTD7/USB_PULLUP(D+) /RX1
G11 67 D9 56 PTE0 KBI2P3 FB_ALE FB_CS1 PTE0/KBI2P3/FB_ALE/FB_CS1
F10 68 — — PTJ0 FB_AD2 — — PTJ0/FB_AD2
F11 69 — — PTJ1 FB_AD3 — — PTJ1/FB_AD3
F9 70 — — PTJ2 FB_AD4 — — PTJ2/FB_AD4
E10 71 — — PTJ3 RGPIOP12 FB_AD5 — PTJ3/RGPIOP12/FB_AD5
E11 72 C9 57 PTE1 KBI2P4 RGPIOP13 FB_AD6 PTE1/KBI2P4/RGPIOP13/FB_AD6
D11 73 C8 58 PTE2 KBI2P5 RGPIOP14 FB_AD7 PTE2/KBI2P5/RGPIOP14/FB_AD7
D10 74 B9 59 PTE3 KBI2P6 FB_AD8 — PTE3/KBI2P6/FB_AD8
C9 75 A9 60 PTE4 CMPP3 TPMCLK IRQ PTE4/CMPP3/TPMCLK/IRQ
H8 76 F5 61 VSS3 — — — VSS3
D8 77 E5 62 VDD3 — — — VDD3
B8 78 C7 63 PTE5 FB_D7 USB_
SESSVLD TX2 PTE5/FB_D7/USB_SESSVLD/TX2
C10 79 C6 64 PTE6 FB_RW USB_
SESSEND RX2 PTE6/FB_RW/USB_SESSEND/RX2
C11 80 B6 65 PTE7 USB_
VBUSVLD TPM2CH3 — PTE7/USB_VBUSVLD/TPM2CH3
B9 81 B8 66 PTF0 USB_ID TPM2CH2 — PTF0/USB_ID/TPM2CH2
B10 82 B7 67 PTF1 RX2 USB_DP_D
OWN TPM2CH1 PTF1/RX2/USB_DP_DOWN/TPM2CH1
B11 83 C5 68 PTF2 TX2 USB_DM_
DOWN TPM2CH0 PTF2/TX2/USB_DM_DOWN/TPM2CH0
A11 84 — — PTJ4 RGPIOP15 FB_AD16 — PTJ4/RGPIOP15/FB_AD16
A10 85 — — PTJ5 FB_AD15 — — PTJ5/FB_AD15
B6 86 — — PTJ6 FB_AD14 — — PTJ6/FB_AD14
A9 87 — — PTJ7 FB_AD13 — — PTJ7/FB_AD13
Table 3. Package Pin Assignments (continued)
Package
Default
Function
Alternate
1
Alternate
2
Alternate
3Composite Pin Name
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
MCF51MM256/128, Rev. 5
Pinouts and Pin Assignments
Freescale Semiconductor14
A8 88 — — FB_AD12 — — — FB_AD12
A7 89 A8 69 PTF3 SCL FB_D5 FB_AD11 PTF3/SCL/FB_D5/FB_AD11
A6 90 A7 70 PTF4 SDA FB_D4 FB_AD10 PTF4/SDA/FB_D4/FB_AD10
B5 91 B5 71 PTF5 KBI2P7 FB_D3 FB_AD9 PTF5/KBI2P7/FB_D3/FB_AD9
A5 92 A6 72 VUSB33 — — — VUSB33
A4 93 B4 73 USB_DM — — — USB_DM
A3 94 A4 74 USB_DP — — — USB_DP
B4 95 A5 75 VBUS — — — VBUS
H4 96 F6 76 VSS1 — — — VSS1
D4 97 E6 77 VDD1 — — — VDD1
A1 98 A3 78 PTF6 MOSI1 — — PTF6/MOSI1
A2 99 B1 79 PTF7 MISO1 — — PTF7/MISO1
B1 100 A2 80 PTG0 SPSCK1 — — PTG0/SPSCK1
F4 — A1 — PTG1 USB_
SESSEND — — PTG1/USB_SESSEND
C4 — — — PTG2 USB_DM_
DOWN — — PTG2/USB_DM_DOWN
B3 — — — PTG3 USB_DP_
DOWN — — PTG3/USB_DP_DOWN
C2 — — — PTG4 USB_SESSVLD — — PTG4/USB_SESSVLD
Table 3. Package Pin Assignments (continued)
Package
Default
Function
Alternate
1
Alternate
2
Alternate
3Composite Pin Name
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 15
3 Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the
MCF51MM256/128 microcontroller, including detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These
specifications will, however , be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
3.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
Table 4. Parameter Classifications
PThose parameters are guaranteed during production testing on each individual device.
CThose parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
DThose parameters are derived mainly from simulations.
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor16
3.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. S tress beyond the limits specified in the following table may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the re maining tables in this
section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
Table5. Absolute Maximum Ratings
# Rating Symbol Value Unit
1 Supply voltage VDD –0.3 to +3.8 V
2 Maximum current into VDD IDD 120 mA
3 Digital input voltage VIn –0.3 to VDD +0.3 V
4Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor ,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
2All functional non-supply pins are internally clamped to VSS and VDD.
3Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of
VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current
greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power.
Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
ID 25 mA
5 Storage temperature range Tstg –55 to 150 C
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 17
3.3 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or
VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
loads), the difference between pin voltage and VSS or VDD will be very small.
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)Eqn. 1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip inte rnal power
PI/O = Power dissipation on input and output pins — user determined
Table 6. Thermal Characteristics
# Symbol Rating Value Unit
1T
AOperating temperature range (packaged): C
MCF51MM256 –40 to 105
MCF51MM128 –40 to 105
2T
JMAX Maximum junction temperature 135 C
3JA Thermal resistance1,2,3,4 Single-layer board — 1s
1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2Junction to Ambient Natural Convection
31s — Single layer board, one signal layer
42s2p — Four layer board, 2 signal and 2 power layers
C/W
104-pin MBGA 67
100-pin LQFP 53
81-pin MBGA 67
80-pin LQFP 53
4JA Thermal resistance1, 2, 3, 4 Four-layer board — 2s2p C/W
104-pin MBGA 39
100-pin LQFP 41
81-pin MBGA 39
80-pin LQFP 39
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor18
For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K (TJ + 273C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)2Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
3.4 ESD Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 7. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human Body
Series Resistance R1 1500
Storage Capacitance C 100 pF
Number of Pulse per pin — 3 —
Machine
Series Resistance R1 0
Storage Capacitance C 200 pF
Number of Pulse per pin — 3 —
Latch-up Minimum input voltage limit — –2.5 V
Maximum input voltage limit — 7.5 V
Table 8. ESD and Latch-Up Protection Characteristics
# Rating Symbol Min Max Unit C
1 Human Body Model (HBM) VHBM 2000 — V T
2 Machine Model (MM) VMM 200 — V T
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 19
3 Charge Device Model (CDM) VCDM 500 — V T
4 Latch-up Current at TA = 125CI
LAT 00 — mA T
Table 8. ESD and Latch-Up Protection Characteristics (continued)
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor20
3.5 DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table 9. DC Characteristics
Num Symbol Characteristic Condition Min Typ1Max Unit C
1—
Operating
Voltage —1.8
2—3.6V—
2V
OH
Output high
voltage All I/O pins, low-drive strength
VDD 1.8 V,
ILoad = –600 AVDD – 0.5 — — V C
All I/O pins, high-drive strength
VDD 2.7 V,
ILoad = –10 mA VDD – 0.5 — — V P
VDD 2.3 V,
ILoad = –6 mA VDD – 0.5 — — V T
VDD 1.8V,
ILoad = –3 mA VDD – 0.5 — — V C
3I
OHT
Output high
current Max total IOH for all ports
———100mAD
4V
OL
Output low
voltage All I/O pins, low-drive strength
VDD 1.8 V,
ILoad = 600 A——0.5VC
All I/O pins, high-drive strength
VDD 2.7 V,
ILoad = 10 mA ——0.5VP
VDD 2.3 V,
ILoad = 6 mA ——0.5VT
VDD 1.8 V,
ILoad = 3 mA ——0.5VC
5I
OLT
Output low
current
Max total IOL
for all ports ———100mAD
6V
IH Input high voltage all digital inputs
VDD 2.7 V 0.70 x VDD ——VP
VDD 1.8 V 0.85 x VDD ——VC
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 21
7V
IL Input low voltage all digital inputs
VDD 2.7 V — — 0.35 x
VDD
VP
VDD 1.8 V — — 0.30 x
VDD
VC
8V
hys Input hysteresis all digital inputs — 0.06 x VDD ——mVC
9|I
In|
Input leakage
current
all input only
pins
(Per pin)
VIn = V
DD or V
SS ——0.5AP
10 |IOZ|
Hi-Z (off-state)
leakage current3
all digital
input/output
(per pin)
VIn = VDD or VSS —0.0030.5AP
11 RPU Pull-up resistors all digital inputs,
when enabled — 17.5 — 52.5 kP
12 RPD
Internal
pull-down
resistors4
— 17.5 — 52.5 kP
13 IIC
DC injection
current 5, 6, 7 Single pin limit
VSS > VIN > VDD –0.2 — 0.2 mA D
Total MCU limit, includes sum of all stressed pins
VSS > VIN > VDD –5 — 5 mA D
14 CIn Input Capacitance, all pins — — — 8 pF C
15 VRAM RAM retention voltage — — 0.6 1.0 V C
16 VPOR POR re-arm voltage8 — 0.9 1.4 1.79 V C
17 tPOR POR re-arm time — 10 — — sD
18 VLVDH 9
Low-voltage
detection
threshold —
high range
VDD falling
— 2.11 2.16 2.22 V P
VDD rising
— 2.16 2.21 2.27 V P
19 VLVDL
Low-voltage
detection
threshold —
low range9
VDD falling
— 1.80 1.82 1.91 V P
VDD rising
— 1.86 1.90 1.99 V P
Table 9. DC Characteristics (continued)
Num Symbol Characteristic Condition Min Typ1Max Unit C
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor22
20 VLVWH
Low-voltage
warning
threshold —
high range9
VDD falling
— 2.36 2.46 2.56 V P
VDD rising
— 2.36 2.46 2.56 V P
21 VLVWL
Low-voltage
warning
threshold —
low range9
VDD falling
— 2.11 2.16 2.22 V P
VDD rising
— 2.16 2.21 2.27 V P
22 Vhys
Low-voltage inhibit
reset/recoverhysteresis10 ——50—mVC
23 VBG Bandgap Voltage Reference11 — 1.110 1.17 1.230 V P
1Typical values are measured at 25C. Characterized, not tested
2As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
3Does not include analog module pins. Dedicated analog pins should not be pulled to VDD or VSS and should be left floating when not
used to reduce current leakage.
4Measured with VIn = VDD.
5All functional non-supply pins are internally clamped to VSS and VDD except PTD1.
6Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
7Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions.
If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power
supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which
would reduce overall power consumption).
8Maximum is highest voltage that POR is guaranteed.
9Run at 1 MHz bus frequency
10 Low voltage detection and warning limits measured at 1 MHz bus frequency.
11 Factory trimmed at VDD = 3.0 V, Temp = 25C
Table 9. DC Characteristics (continued)
Num Symbol Characteristic Condition Min Typ1Max Unit C
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 23
3.6 Supply Current Characteristics
Table 10. Supply Current Characteristics
# Symbol Parameter Bus
Freq VDD (V) Typ1Max Unit Temp
(C) C
1RI
DD
Run supply
current FEI mode; all modules ON2
25.165
MHz 34448mA –40 to
25 P
25.165
MHz 34448mA 105 P
20 MHz 3 32.3 — mA –40 to
105 T
8 MHz 3 16.4 — mA –40 to
105 T
1 MHz 3 2.9 — mA –40 to
105 T
2RI
DD
Run supply
current FEI mode; all modules OFF3
25.165
MHz 3 29 29.6 mA –40 to
105 C
20 MHz 3 25.4 — mA –40 to
105 T
8 MHz 3 12.7 — mA –40 to
105 T
1 MHz 3 2.4 — mA –40 to
105 T
3RI
DD
Run supply
current LPR=0; all modules OFF3
16 kHz
FBI 3 232 280 A–40 to
105 T
16 kHz
FBE 3 231 296 A–40 to
105 T
4RIDD Run supply
current LPR=1, all modules OFF3
16 kHz
BLPE 37475A0 to 70 T
16 kHz
BLPE 3 74 120 A–40 to
105 T
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor24
5WIDD Wait mode
supply
current
FEI mode, all modules OFF3
25.165
MHz 316.5—mA –40 to
105 C
20 MHz 3 10.3 — mA –40 to
105 T
8 MHz 3 6.6 — mA –40 to
105 T
1 MHz 3 1.7 — mA –40 to
105 T
6LPWIDD
Low-Power
Wait mode
supply
current
16 KHz 3 28 62 µA –40 to
105 T
7S2IDD
Stop2 mode
supply
current4
N/A 3 0.410 1.00 µA –40 to
25 P
N/A 3 3.7 10 µA 70 C
N/A 3 10 20 µA 85 C
N/A 3 21 31.5 µA 105 P
N/A 2 0.410 0.640 µA –40 to
25 C
N/A 2 3.4 9 µA 70 C
N/A 2 9.5 18 µA 85 C
N/A 2 20 30 µA 105 C
Table 10. Supply Current Characteristics (continued)
# Symbol Parameter Bus
Freq VDD (V) Typ1Max Unit Temp
(C) C
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 25
8S3IDD Stop3 mode supply current4
No clocks active n/a
3
0.750 1.3
A
–40 to 25 P
8.5 18 70 C
20 28 85 C
53 63 105 P
2
0.400 0.900 –40 to 25 C
8.2 16 70 C
18 26 85 C
47 59 105 C
1Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2ON = System Clock Gating Control registers turn on system clock to the corresponding modules.
3OFF = System Clock Gating Control registers turn off system Clock to the corresponding modules.
4All digital pins must be configured to a known st ate to prevent floating pins from adding current. Smaller packages may have some pins that
are not bonded out; however, software must still be configured to the largest pin package available so that all pins are in a known state.
Otherwise, floating pins that are not bonded in the smaller packages may result in a higher current draw. NOTE: I/O pins are configured to
output low; input-only pins are configured to pullup-enabled. IRO pin connects to ground. FB_AD12 pin is pullup-enabled. TRIAMPx,
OPAMPx, DACO, and VREFO pins are at reset state and unconnected.
Table 11. Typical Stop Mode Adders
# Parameter Condition Temperature (°C) Units C
-40257085105
1LPO —50 75 100 150 250 nA D
2EREFSTEN RANGE = HGO = 0 600 650 750 850 1000 nA D
3IREFSTEN1
1Not available in stop2 mode.
——738093125AT
4TOD Does not include clock source current 50 75 100 150 250 nA D
5LVD1LVDSE = 1 116 117 126 132 172 AT
6PRACMP1Not using the bandgap (BGBE = 0) 17 18 24 35 74 AT
7ADC1ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0) 190 195 210 220 260 AT
8DAC1High-Power mode; no load on DACO 339 345 346 346 360 AT
Low-Power mode 41 43 43 44 50 AT
9OPAMP1High-Power mode 276 350 370 376 390 AT
Low-Power mode 42 49 57 58 68 AT
10 TRIAMP1High-Power mode 420 432 433 438 478 AT
Low-Power mode 52 52 52 55 60 AT
Table 10. Supply Current Characteristics (continued)
# Symbol Parameter Bus
Freq VDD
(V) Typ1Max Unit Temp
(C) C
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor26
Figure 7. Stop IDD versus Temperature
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 27
3.7 PRACMP Electricals
3.8 12-Bit DAC Electricals
Table 12. PRACMP Electrical Specifications
# Characteristic Symbol Min Typical Max Unit C
1 Supply voltage VPWR 1.8 — 3.6 V P
2 Supply current (active) (PRG enabled) IDDACT1 ——80AD
3 Supply current (active) (PRG disabled) IDDACT2 ——40AD
4Supply current (ACMP and PRG all
disabled) IDDDIS —— 2 nAD
5 Analog input voltage VAIN VSS – 0.3 — VDD VD
6 Analog input offset voltage VAIO — 5 40 mV D
7 Analog comparator hysteresis VH3.0 — 20.0 mV D
8 Analog input leakage current IALKG —— 1 nAD
9 Analog comparator initialization delay tAINIT — — 1.0 sD
10 Programmable reference generator inputs VIn2 (VDD25)1.8 — 2.75 V D
11 Programmable reference generator setup
delay tPRGST —1—µsD
12 Programmable reference generator step
sizeVstep 0.75 1 1.25 LSB D
13 Programmable reference generator voltage
range Vprgout VIn/32 — Vin VP
Table 13. DAC 12LV Operating Requirements
# Characteristic Symbol Min Max Unit C Notes
1 Supply voltage VDDA 1.8 3.6 V P
2 Reference voltage VDACR 1.15 3.6 V C
3 Temperature TA–40 105 °C C
4 Output load capacitance CL— 100 pFC
A small load capaci-
tance (47 pF) can
improve the band-
width performance of
the DAC.
5 Output load current IL—1mAC
Table 14. DAC 12-Bit Operating Behaviors
# Characteristic Symbol Min Typ Max Unit C Notes
1Resolution N 12 —12 bit T
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor28
2 Supply current low-power mode IDDA_DACLP —50
100 µA T
3 Supply current high-power mode IDDA_DACHP — 345 500 µA T
4
Full-scale Settling time
(±1 LSB)
(0x080 to 0xF7F or 0xF7F to
0x080)
low-power mode
TsFSLP — — 200 µs T
•V
DDA = 3 V
or 2.2 V
•V
REFSEL = 1
• Temperature
= 25°C
5
Full-scale Settling time
(±1 LSB)
(0x080 to 0xF7F or 0xF7F to
0x080)
high-power mode
TsFSHP — — 30 µs T
•V
DDA = 3 V
or 2.2 V
•V
REFSEL = 1
• Temperature
= 25°C
6
Code-to-code Settling time
(±1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
low-power mode
TsC-CLP
—— 5 µs T
•V
DDA = 3 V
or 2.2 V
•V
REFSEL = 1
• Temperature
= 25°C
7
Code-to-code Settling time
(±1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
high-power mode (3 V at Room
Temperature)
TsC-CHP —1— µs T
•V
DDA = 3 V
or 2.2 V
•V
REFSEL = 1
• Temperature
= 25°C
8
DAC output voltage range low
(high-power mode, no load, DAC
set to 0) (3 V at Room
Temperature)
Vdacoutl ——100 mV T
9
DAC output voltage range high
(high-power mode, no load, DAC
set to 0x0FFF)
Vdacouth VDACR
-100 ——mV
T
10 Integral non-linearity error INL ——± 8 LSB T
11 Differential non-linearity error
VDACR is > 2.4 V DNL ——± 1 LSB T
12 Offset error EO—±0.4 ± 3 %FSR T
Calculated
by a best fit
curve from
VSS +
100mV to
VREFH
–100mV
13 Gain error, VREFH = Vext = VDD EG—±0.1 ± 0.5 %FSR T
Calculated
by a best fit
curve from
VSS +
100mV to
VREFH
–100mV
Table 14. DAC 12-Bit Operating Behaviors (continued)
# Characteristic Symbol Min Typ Max Unit C Notes
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 29
Figure 7. Offset at Half Scale vs Temperature
3.9 ADC Characteristics
14 Power supply rejection ratio
VDD 2.4 V PSRR 60 —— dB T
15 Temperature drift of offset voltage
(DAC set to 0x0800) Tco —— 2mV
T
See Typical
Drift figure
that follows.
16 Offset aging coefficient Ac—— 8µV/yr T
Table 15. 16-Bit ADC Operating Conditions
# Symb Characteristic Conditions Min Typ1Max Unit C Comment
1V
DDA Supply voltage Absolute 1.8 — 3.6 V D
2VDDA
Delta to VDD
(VDD–VDDA)2–100 0 +100 mV D
3VSSA Ground voltage Delta to VSS
(VSS–VSSA)2–100 0 +100 mV D
4V
REFH Ref Voltage High 1.15 VDDA VDDA VD
Table 14. DAC 12-Bit Operating Behaviors (continued)
# Characteristic Symbol Min Typ Max Unit C Notes
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor30
5V
REFL Ref Voltage Low VSSA VSSA VSSA VD
6V
ADIN Input Voltage VREFL —V
REFH VD
7C
ADIN
Input
Capacitance
16-bit modes
8/10/12-bit modes —8
4
10
5pF T
8R
ADIN Input Resistance — 2 5 kT
9R
AS
Analog Source
Resistance
External to
MCU
Assumes
ADLSMP=0
16-bit mode
fADCK > 8 MHz ——0.5kT
4 MHz < fADCK < 8
MHz ——1kT
fADCK < 4 MHz — — 2 kT
13/12-bit mode
fADCK > 8 MHz ——1kT
4 MHz < fADCK < 8
MHz ——2kT
fADCK < 4 MHz — — 5 kT
11/10-bit mode
fADCK > 8 MHz ——2kT
4 MHz < fADCK < 8
MHz ——5kT
fADCK < 4 MHz — — 10 kT
9/8-bit mode
fADCK > 8 MHz ——5kT
fADCK < 8 MHz — — 10 kT
10 fADCK
ADC Conversion Clock
Frequency
ADLPC=0, ADHSC=1 1.0 — 8.0 MHz D
ADLPC=0, ADHSC=0
1.0 — 5.0 MHz D
ADLPC=1, ADHSC=0
1.0 — 2.5 MHz D
1Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only
and are not tested in production.
2DC potential difference.
Table 15. 16-Bit ADC Operating Conditions (continued)
# Symb Characteristic Conditions Min Typ1Max Unit C Comment
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 31
Figure 8. ADC Input Impedance Equivalency Diagram
+
–
+
–
VAS
RAS
CAS
VADIN
ZAS Pad
leakage
due to
input
protection
ZADIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
RADIN ADC SAR
ENGINE
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
INPUT PIN
RADIN
CADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor32
Table 16. 16-Bit SAR ADC Characteristics full operating range
(VREFH = VDDA, > 1.8, VREFL = VSSA 8 MHz, –40 to 85 °C)
# Characteristic Conditions1Symb Min Typ2Max Unit C Comment
Supply Current
ADLPC=1, ADHSC=0
IDDAD
—215 —
AT
ADLSMP
=0
ADCO=1
1 ADLPC=0, ADHSC=0 — 470 —
ADLPC=0, ADHSC=1 — 610 —
2 Supply Current Stop, Reset, Module Off IDDAD —0.01 — AT
ADC
Asynchronous
Clock Source
ADLPC=1, ADHSC=0
fADACK
—2.4 —
MHz Ct
ADACK =
1/fADACK
3 ADLPC=0, ADHSC=0 — 5.2 —
ADLPC=0, ADHSC=1 — 6.2 —
4 Sample Time See Reference Manual for sample times
5Conversion
Time See Reference Manual for conversion times
6
Tot a l
Unadjusted
Error
16-bit differential mode
16-bit single-ended mode TUE —
—
16
20
48/ –40
56/ –28 LSB3T
32x
Hardware
Averaging
(AVGE =
%1
AVGS =
%11)
13-bit differential mode
12-bit single-ended mode
—
—
1.5
1.75
3.0
3.5 T
11-bit differential mode
10-bit single-ended mode
—
—
0.7
0.8
1.5
1.5 T
9-bit differential mode
8-bit single-ended mode
—
—
0.5
0.5
1.0
1.0 T
7Differential
Non-Linearity
16-bit differential mode
16-bit single-ended mode DNL —
—
2.5
2.5
5/–3
+5/–3 LSB2T
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
1
1T
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
0.75
0.75 T
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5 T
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 33
8Integral
Non-Linearity
16-bit differential mode
16-bit single-ended mode INL —
—
6.0
10.0
16.0
20.0 LSB2T
13-bit differential mode
12-bit single-ended mode
—
—
1.0
1.0
2.5
2.5 T
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
1.0
1.0 T
9-bit differential mode
8-bit single-ended mode
—
—
0.3
0.3
0.5
0.5 T
9Zero-Scale
Error
16-bit differential mode
16-bit single-ended mode EZS
—
—
4.0
4.0
+32/ –24
+24/ –16 LSB2TVADIN =
VSSA
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
2.5
2.0 T
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.0
1.0 T
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5 T
10 Full-Scale Error 16-bit differential mode
16-bit single-ended mode EFS
—
—
+10/0
+14/0
+42/–2
+46/–2 LSB2TVADIN =
VDDA
13-bit differential mode
12-bit single-ended mode
—
—
1.0
1.0
3.5
3.5 T
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.5
1.5 T
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5 T
11 Quantization
Error 16-bit modes EQ— –1 to 0 — LSB2
D
<13-bit modes — — 0.5
12 Effective
Number of Bits
16-bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
ENOB
12.8
12.7
12.6
12.5
11.9
14.2
13.8
13.6
13.3
12.5
—
—
—
—
—
Bits C
Fin =
Fsample/10
0
13 Signal to Noise
plus Distortion See ENOB SINAD dB
Table 16. 16-Bit SAR ADC Characteristics full operating range
(VREFH = VDDA, > 1.8, VREFL = VSSA 8 MHz, –40 to 85 °C) (continued)
# Characteristic Conditions1Symb Min Typ2Max Unit C Comment
SINAD 6.02 ENOB1.76+=
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor34
14
Total Harmonic
Distortion
16-bit differential mode
Avg=32
THD
— –91.5 –74.3
dB
CFin =
Fsample/10
0
16-bit single-ended mode
Avg=32 — –85.5 — D
15 Spurious Free
Dynamic
Range
16-bit differential mode
Avg=32
SFDR
75.0 92.2 —
dB
CFin =
Fsample/10
0
16-bit single-ended mode
Avg=32 — 86.2 — D
16 Input Leakage
Error all modes EIL IIn * RAS mV D
IIn =
leakage
current
(refer to
DC
characteri
stics)
17 Temp Sensor
Slope
–40C – 25Cm
—1.64
6 — mV/×
CC
25C – 125C — 1.769 —
18 Temp Sensor
Voltage 25CVTEMP2
5
—718.2 — mVC
1All accuracy numbers assume the ADC is calibrated with VREFH=VDDA
2Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
31 LSB = (VREFH – VREFL)/2N
Table 16. 16-Bit SAR ADC Characteristics full operating range
(VREFH = VDDA, > 1.8, VREFL = VSSA 8 MHz, –40 to 85 °C) (continued)
# Characteristic Conditions1Symb Min Typ2Max Unit C Comment
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 35
Table 17. 16-bit SAR ADC Characteristics full operating range
(VREFH = VDDA, 2.7 V, VREFL = VSSA, fADACK 4 MHz, ADHSC = 1)
# Characteristic Conditions1Symb Min Typ2Max Unit C Comment
1
Tot a l
Unadjusted
Error
16-bit differential mode
16-bit single-ended mode TUE —
—
16
20
24/ –24
32/–20 LSB3T
32x
Hardware
Averaging
(AVGE =
%1
AVGS =
%11)
13-bit differential mode
12-bit single-ended mode
—
—
1.5
1.75
2.0
2.5 T
11-bit differential mode
10-bit single-ended mode
—
—
0.7
0.8
1.0
1.25 T
9-bit differential mode
8-bit single-ended mode
—
—
0.5
0.5
1.0
1.0 T
2Differential
Non-Linearity
16-bit differential mode
16-bit single-ended mode DNL —
—
2.5
2.5
3
3LSB2T
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
1
1T
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
0.75
0.75 T
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5 T
3Integral
Non-Linearity
16-bit differential mode
16-bit single-ended mode INL —
—
6.0
10.0
12.0
16.0 LSB2T
13-bit differential mode
12-bit single-ended mode
—
—
1.0
1.0
2.0
2.0 T
11-bit differential mode
10-bit single-ended mode
—
—
0.5
0.5
1.0
1.0 T
9-bit differential mode
8-bit single-ended mode
—
—
0.3
0.3
0.5
0.5 T
4Zero-Scale
Error
16-bit differential mode
16-bit single-ended mode EZS
—
—
4.0
4.0
+16/0
+16/-8 LSB2TVADIN =
VSSA
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7 2.0 2.0 T
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.0
1.0 T
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5 T
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor36
5 Full-Scale Error 16-bit differential mode
16-bit single-ended mode EFS
—
—
+8/0
+12/0
+24/0
+24/0 LSB2TVADIN =
VDDA
13-bit differential mode
12-bit single-ended mode
—
—
0.7
0.7
2.0
2.5 T
11-bit differential mode
10-bit single-ended mode
—
—
0.4
0.4
1.0
1.0 T
9-bit differential mode
8-bit single-ended mode
—
—
0.2
0.2
0.5
0.5 T
6Quantization
Error 16-bit modes EQ— –1 to 0 — LSB2
D
<13-bit modes — — 0.5
7Effective
Number of Bits
16-bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
ENO
B
14.3
13.8
13.4
13.1
12.4
14.5
14.0
13.7
13.4
12.6
—
—
—
—
—
Bits C
Fin =
Fsample/10
0
8Signal to Noise
plus Distortion See ENOB SINA
DdB
9
Total Harmonic
Distortion
16-bit differential mode
Avg=32
THD
— –95.8 –90.4
dB
CFin =
Fsample/10
0
16-bit single-ended mode
Avg=32 — — — D
10 Spurious Free
Dynamic
Range
16-bit differential mode
Avg=32
SFDR
91.0 96.5 —
dB
CFin =
Fsample/10
0
16-bit single-ended mode
Avg=32 — — — D
11 Input Leakage
Error all modes EIL IIn * RAS mV D
IIn =
leakage
current
(refer to
DC
characteri
stics)
1All accuracy numbers assume the ADC is calibrated with VREFH=VDDA
2Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
31 LSB = (VREFH – VREFL)/2N
Table 17. 16-bit SAR ADC Characteristics full operating range
(VREFH = VDDA, 2.7 V, VREFL = VSSA, fADACK 4 MHz, ADHSC = 1) (continued)
# Characteristic Conditions1Symb Min Typ2Max Unit C Comment
SINAD 6.02 ENOB1.76+=
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 37
3.10 MCG and External Oscillator (XOSC) Characteristics
Table 18. MCG (Temperature Range = –40 to 105°C Ambient)
# Rating Symbol Min Typical Max Unit C
1 Internal reference startup time tirefst —55 100sD
2Average internal reference
frequency
factory trimmed at
VDD=3.0 V and
temp=25Cfint_ft
— 31.25 — kHz C
user trimmed 31.25 — 39.0625 C
3DCO output frequency range —
trimmed
Low range
(DRS=00) fdco_t
16 — 20
MHz
C
Mid range
(DRS=01) 32 — 40 C
High range1
(DRS=10)
1This should not exceed the maximum CPU frequency for this device which is 50.33 MHz.
40 — 60 C
4
Resolution of trimmed DCO
output frequency at fixed voltage
and temperature
with FTRIM
fdco_res_t
—0.1 0.2
%fdco
C
without FTRIM — 0.2 0.4 C
5
Total deviation of trimmed DCO
output frequency over voltage and
temperature
over voltage and
temperature
fdco_t
—1.0 2
%fdco
P
over fixed voltage
and temp range
of 0 – 70 C
—0.5 1C
6Acquisition time
FLL2tfll_acquire —— 1ms C
PLL3 tpll_acquire —— 1 D
7Long term Jitter of DCO output clock (averaged over
2mS interval) 4CJitter —0.02 0.2
%fdco C
8 VCO operating frequency fvco 7.0 — 55.0 MHz D
9 PLL reference frequency range fpll_ref 1.0 — 2.0 MHz D
10 Jitter of PLL output clock
measured over 625ns 5Long term fpll_jitter_625
ns —0.5664—%fpll D
11 Lock frequency tolerance Entry6Dlock 1.49 — 2.98 %D
Exit7Dunl 4.47 — 5.97 D
12 Lock time
FLL tfll_lock ——
tfll_acquire+
1075(1/fint_t)
s
D
PLL tpll_lock ——
tpll_acquire+
1075(1/fpll_re
f)
D
13
Loss of external clock minimum frequency - RANGE =
0floc_low
(3/5) x
fint_t ——kHzD
14
Loss of external clock minimum frequency - RANGE =
1floc_high
(16/5) x
fint_t ——kHzD
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor38
2This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is
changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a
crystal/resonator is being used as the reference, this specification assumes it is already running.
3This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
4Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the C
Jitter percentage for a given interval.
5625 ns represents 5 time quanta for CAN applications, under worst-case conditions of 8 MHz CAN bus clock, 1 Mbps CAN Bus
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the
sample point of a bit using 8 time quanta per bit.
6Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is
already in lock, then the MCG may stay in lock.
7Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
Table 19. XOSC (Temperature Range = –40 to 105°C Ambient)
# Characteristic Symbol Min Typ1Max Unit C
1Oscillator crystal or resonator
(EREFS = 1, ERCLKEN = 1)
• Low range (RANGE = 0)
flo 32 — 38.4 kHz D
• High range (RANGE = 1),
• FEE or FBE mode 2fhi-fll 1— 5MHzD
• High range (RANGE = 1),
• PEE or PBE mode 3fhi-pll 1— 16MHzD
• High range (RANGE = 1),
• High gain (HGO = 1),
• BLPE mode
fhi-hgo 1— 16MHzD
• High range (RANGE = 1),
• Low power (HGO = 0),
• BLPE mode
fhi-lp 1— 8MHzD
2 Load capacitors C1
C2
See crystal or resonator manufacturer’s
recommendation. D
3
Feedback resistor • Low range
(32 kHz to 38.4 kHz) RF—10 —
M
D
• High range
(1 MHz to 16 MHz) —— 1 — D
4
Series resistor — Low range • Low Gain (HGO = 0)
RS
—0 —
kD
• High Gain (HGO = 1) — 100 — D
5 Series resistor — High range
• Low Gain (HGO = 0)
RS
—0 —
k
D
• High Gain (HGO = 1) D
8 MHz — 0 0 D
4 MHz — 0 10 D
1 MHz — 0 20 D
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 39
o
3.11 Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to
interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected
to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or
other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple
chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect
to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus
frequency.
The following timing numbers indicate when data is latched or driven onto the exter nal bus, relative to the
Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values.
6 Crystal start-up time 4
• Low range, low gain (RANGE =
0, HGO = 0) tCSTL-LP
—200 —
ms
D
• Low range, high gain
(RANGE = 0, HGO = 1)
tCSTL-HG
O
—400 — D
• High range, low gain
(RANGE = 1, HGO = 0)5tCSTH-LP —5 — D
• High range, high gain
(RANGE = 1, HGO = 1)5
tCSTH-HG
O—15 — D
1Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
2When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
3When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2 MHz.
4This parameter is characterized and not tested on each device. Proper PC board layout porcedures must be followed to achieve specifications.
54 MHz crystal.
Table 19. XOSC (Temperature Range = –40 to 105°C Ambient) (continued)
# Characteristic Symbol Min Typ1Max Unit C
MCU
EXTAL XTAL
RS
C2
Crystal or Resonator
RF
C1
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor40
Figure 9. Mini-FlexBus Read Timing
Table 20. Mini-FlexBus AC Timing Specifications
Num C Characteristic Min Max Unit Notes
— — Frequency of Operation — 25.1666 MHz —
MB1 D Clock Period 39.73 — ns —
MB2 D Output Valid — 20 ns 1
1Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
MB3 D Output Hold 1.0 — ns 1
MB4 D Input Setup 22 — ns 2
2Specification is valid for all MB_D[7:0].
MB5 D Input Hold 10 — ns 2
FB_A[19:16]
FB_CLK
S0 S1 S2 S3
FB_R/W
FB_ALE
DATA[7:0]
8-bit Non-Mux’d Bus
16-bit Mux’d Bus
ADDR[19:0]
ADDR[31:24]
FB_D[7:0]
FB_CSn, FB_OE
S0
FB_AD[15:0]
FB_AD[19:16]
DATA[15:0]
ADDR[19:16]
ADDR[15:0]
MB1
MB2 MB5
MB3
MB4
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 41
Figure 10. Mini-FlexBus Write Timing
FB_CLK
S0 S1 S2 S3
FB_R/W
FB_ALE
FB_OE
DATA[7:0]
8-bit Non-Mux’d Bus
16-bit Mux’d Bus
ADDR[19:8]
ADDR[7:0]
FB_AD[19:8]
FB_AD[7:0]
FB_CSn
S0
FB_AD[15:0] DATA[15:0]
FB_AD[19:16] ADDR[19:16]
ADDR[15:0]
MB1
MB2
MB3
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor42
3.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.12.1 Control Timing
Table 21. Control Timing
# Symbol Parameter Min Typical1Max C Unit
1fBus Bus frequency (tcyc = 1/fBus)MHz
VDD 1.8 V dc — 10 D
VDD > 2.1 V dc — 20 D
VDD > 2.4 V dc — 25.165 D
2t
LPO
Internal low-power oscillator
period 700 1000 1300 P s
3t
extrst
External reset pulse width2
(tcyc = 1/fSelf_reset)100 — — D ns
4t
rstdrv Reset low drive 66 x tcyc ——Dns
5t
MSSU
Active background debug
mode latch setup time 500 — — D ns
6t
MSH
Active background debug
mode latch hold time 100 — — D ns
7tILIH, tIHIL
IRQ pulse width
• Asynchronous path2
• Synchronous path3
100
1.5 x tcyc
——
Dns
8tILIH, tIHIL
KBIPx pulse width
• Asynchronous path2
• Synchronous path3
100
1.5 x tcyc
——
Dns
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 43
Figure 11. Reset Timing
Figure 12. IRQ/KBIPx Timing
9t
Rise, tFall Port rise and fall time (load = 50 pF)4, Low Drive ns
Slew rate
control
disabled
(PTxSE = 0)
—11—D
Slew rate
control
enabled
(PTxSE = 1)
—35—D
Slew rate
control
disabled
(PTxSE = 0)
—40—D
Slew rate
control
enabled
(PTxSE = 1)
—75—D
1Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
2This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed
to override reset requests from internal sources.
3This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 105 C.
Table 21. Control Timing (continued)
# Symbol Parameter Min Typical1Max C Unit
textrst
RESET PIN
tIHIL
IRQ/KBIPx
tILIH
IRQ/KBIPx
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor44
3.12.2 TPM Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Figure 13. Timer External Clock
Figure 14. Timer Input Capture Pulse
Table 22. TPM Input Timing
# C Function Symbol Min Max Unit
1 — External clock frequency fTPMext dc fBus/4 MHz
2 — External clock period tTPMext 4—t
cyc
3 D External clock high time tclkh 1.5 — tcyc
4 D External clock low time tclkl 1.5 — tcyc
5 D Input capture pulse width tICPW 1.5 — tcyc
tTPMext
tclkh
tclkl
TPMxCLK
tICPW
TPMxCHn
tICPW
TPMxCHn
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 45
3.13 SPI Characteristics
Table 23 and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 23. SPI Timing
No.1
1Numbers in this column identify elements in Figure 15 through Figure 18.
Characteristic2
2All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew
rate control disabled and high drive strength enabled for SPI output pins.
Symbol Min Max Unit C
1
Operating frequency
Master
Slave
fop fBus/2048
0
fBus/2
fBus/4
Hz
Hz
D
2
SPSCK period
Master
Slave
tSPSCK 2
4
2048
—
tcyc
tcyc
D
3
Enable lead time
Master
Slave
tLead 12
1
—
—
tSPSCK
tcyc
D
4
Enable lag time
Master
Slave
tLag 12
1
—
—
tSPSCK
tcyc
D
5
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK tcyc –30
tcyc – 30
1024 tcyc
—
ns
ns
D
6
Data setup time (inputs)
Master
Slave
tSU
tSU
15
15
—
—
ns
ns
D
7
Data hold time (inputs)
Master
Slave
tHI
tHI
0
25
—
—
ns
ns
D
8 Slave access time3
3Time to data active from high-impedance state.
ta—1t
cyc D
9 Slave MISO disable time4
4Hold time to high-impedance state.
tdis —1t
cyc D
10
Data valid (after SPSCK edge)
Master
Slave
tv—
—
25
25
ns
ns
D
11
Data hold time (outputs)
Master
Slave
tHO 0
0
—
—
ns
ns
D
12
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
D
13
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
D
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor46
Figure 15. SPI Master Timing (CPHA = 0)
Figure 16. SPI Master Timing (CPHA = 1)
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS1
(OUTPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
MSB OUT2LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTES:
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. SS output mode (MODFEN = 1, SSOE = 1).
2
2 3
5
67
11 12
5
11
4
4
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MSB IN(2)
BIT 6 . . . 1
LSB IN
MSB OUT(2) LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
SS(1)
(OUTPUT)
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
NOTES:
2
2
3
45
67
11 12
54
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 47
Figure 17. SPI Slave Timing (CPHA = 0)
Figure 18. SPI Slave Timing (CPHA = 1)
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LS B OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTE:
SLAVE SEE
NOTE
1. Not defined, but normally MSB of character just received
2
2
3
4
67
8
9
11 12
5
54
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
SEE
(CPOL = 0)
(CPOL = 1)
SS
(INPUT)
NOTE:
SLAVE
NOTE
1. Not defined, but normally LSB of character just receiv ed
2
2
3
4
67
8
9
11 12
4
5
5
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor48
3.14 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information abou t program/erase operations, s ee the Memory chapter in the Reference
Manual for this device (MCF51MM256RM).
Table 24. Flash Characteristics
# Characteristic Symbol Min Typical Max Unit C
1Supply voltage for program/erase
–40C to 105CV
prog/erase 1.8 —3.6 V D
2 Supply voltage for read operation VRead 1.8 —3.6 V D
3 Internal FCLK frequency1
1The frequency of this clock is controlled by a software setting.
fFCLK 150 —200 kHz D
4 Internal FCLK period (1/FCLK) tFcyc 5—6.67 sD
5 Byte program time (random location)2tprog 9t
Fcyc P
6 Byte program time (burst mode)2tBurst 4t
Fcyc P
7 Page erase time2
2These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating
approximate time to program and erase.
tPage 4000 tFcyc P
8 Mass erase time2tMass 20,000 tFcyc P
9
Program/erase endurance3
TL to TH = –40C to + 105C
T = 25C
3Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
10,000
—
—
100,000
—
—cycles C
10 Data retention4
4Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the
Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical
Data Retention for Nonvolatile Memory.
tD_ret 15 100 — years C
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 49
3.15 USB Electricals
The USB electricals for the USB On-the-Go module conform to the standards documented by the
Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the
standard or require additional information, this space would be used to communicate that information.
Table 25. Internal USB 3.3 V Voltage Regulator Characteristics
# Characteristic Symbol Min Typ Max Unit C
1 Regulator operating voltage Vregin 3.9 — 5.5 V C
2 VREG output Vregout 3 3.3 3.75 V P
3VUSB33 input with internal VREG
disabled Vusb33in 33.33.6VC
4 VREG Quiescent Current IVRQ —0.5—mAC
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 47
3.16 VREF Electrical Specifications
Table 26. VREF Electrical Specifications
# Characteristic Symbol Min Max Unit C
1 Supply voltage VDDA 1.80 3.6 V C
2 Operating temperature range TA–40 105 °C C
3 Output Load Capacitance CL— 100 nF D
4 Maximum Load — — 10 mA —
5 Voltage Reference Output with Factory
Tr i m . V DD = 3 V at 25 °C
Vout 1.145 1.153 V P
6 Temperature Drift (Vmin—Vmax across
the full temperature range)
Tdrift — 25 mV1
1See typical chart that follows (Figure 20).
T
7 Aging Coefficient2
2Linear reliability model (1008 hours stress at 125°C = 10 years operating life) used to calculate Aging V/year. VREF0 data recorded per
month.
AC—60V/year C
8 Powered down Current (Off Mode,
VREFEN=0, VRSTEN=0)
I — 0.10 AC
9 Bandgap only (Mode_LV[1:0] = 00) I — 75 AT
10 Low-Power buffer (MODE_LV[1:0] = 01) I — 125 AT
11 Tight-Regulation buffer (MODE_LV[1:0]
= 10) I — 1.1 mA
T
12 Load Regulation MODE_LV = 10 — — 100 V/mA C
13 Line Regulation MODE = 1:0, Tight
Regulation VDD < 2.3 V, Delta
VDDA =100 mV, VREFH = 1.2 V driven
externally with VREFO disabled. (Power
Supply Rejection)
DC 70 — dB C
Table 27. VREF Limited Range Operating Behaviors
# Characteristic Symbol Min Max Unit C
1
Voltage Reference Output with
Factory Trim (Temperature range
from 0°C to 50 °C)
Vout 1.149 1.152 mV T
2
Temperature Drive (Vmin —Vmax
Temperature range from 0 °C to
50 °C)
Tdrift —3mV
1
1See typical chart that follows (Figure 20).
T
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 51
Figure 19. Typical VREF Output vs. Temperature
Figure 20. Typical VREF Output vs. VDD
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor52
3.17 TRIAMP Electrical Parameters
Table 28. TRIAMP Characteristics 1.8–3.6 V, –40°C~105°C
#Characteristic
1Symbol Min Typ2Max Unit C
1 Operating Voltage VDD 1.8 — 3.6 V C
2Supply Current (IOUT=0mA, CL=0)
Low-power mode ISUPPLY —52 60AT
3Supply Current (IOUT=0mA, CL=0)
High-speed mode ISUPPLY —432480AT
4 Input Offset Voltage VOS —± 1± 5mVT
5 Input Offset Voltage Temperature Drift VOS —600 — VT
6 Input Offset Current IOS — ±120 500 pA T
7 Input Bias Current (0 ~ 50°C) IBIAS — < 350 < ±500 pA T
8 Input Bias Current (–40 ~ 105°C) IBIAS — 3 6.55 nA T
9 Input Common Mode Voltage Low VCML 0—— VT
10 Input Common Mode Voltage High VCMH ——
VDD–1.4 VT
11 Input Resistance RIN 500 — — MT
12 Input Capacitances CIN —— 5 pFD
13 AC Input Impedance (fIN=100kHz) |XIN|—1 —MD
14 Input Common Mode Rejection Ratio CMRR 60 70 — dB T
15 Power Supply Rejection Ration PSRR 60 70 — dB T
16 Slew Rate (VIN=100mV) Low-power
mode SR — 0.1 — V/sT
17 Slew Rate (VIN=100mV) High-speed
mode SR — 1 — V/sT
18 Unity Gain Bandwidth (Low-power mode)
50pF GBW 0.15 0.25 — MHz T
19 Unity Gain Bandwidth (High-speed mode)
50pF GBW — 1.6 — MHz T
20 DC Open Loop Voltage Gain AV—80 — dBT
21 Load Capacitance Driving Capability CL(max) — — 100 pF T
22 Output Impedance AC Open Loop
(@100 kHz Low-power mode) ROUT —1.4 — kD
23 Output Impedance AC Open Loop
(@100 kHz High-speed mode) ROUT —184 — D
24 Output Voltage Range triout 0.15 — VDD –
0.15 VT
25 Output Drive Capability IOUT —± 1.0 — mA T
26 Gain Margin GM 20 — — dB D
27 Phase Margin PM 45 55 — deg T
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor 53
3.18 OPAMP Electrical Parameters
28 Input Voltage Noise Density f= 1 kHz — 160 — nV/Hz T
1All parameters are measured at 3.0 V, CL= 47 pF across temperature –40 to + 105 °C unless specified.
2Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Table 29. OPAMP Characteristics 1.8–3.6 V
# Characteristics1Symbol Min Typ2Max Unit C
1 Operating Voltage VDD 1.8 — 3.6 V C
2Supply Current (IOUT=0mA, CL=0 Low-Power
mode) ISUPPLY —4880AT
3Supply Current (I
OUT=0mA, CL=0 High-Speed
mode) ISUPPLY — 350 500 AT
4 Input Offset Voltage VOS —26mVT
5 Input Offset Voltage Temperature Coefficient VOS —10—V/C T
6 Input Offset Current (–40°C to 105°C) IOS —2.5 250 nA T
7 Input Offset Current (–40°C to 50°C) IOS ——45nAT
8 Positive Input Bias Current (–40°C to 105°C) IBIAS —0.83.5nAT
9 Positive Input Bias Current (–40°C to 50°C) IBIAS ——2nAT
10 Negative Input Bias Current (–40°C to 105°C) IBIAS — 2.5 250 nA T
11 Negative Input Bias Current (–40°C to 50°C) IBIAS ——45nAT
12 Input Common Mode Voltage Low VCML 0.1 — — V T
13 Input Common Mode Voltage High VCMH ——V
DD VT
14 Input Resistance RIN — 500 — MT
15 Input Capacitances CIN ——10pFD
16 AC Input Impedance (fIN=100kHz Negative
Channel) |XIN|—52—kD
17 AC Input Impedance (fIN=100kHz Positive
Channel) |XIN|— 132 — kD
18 Input Common Mode Rejection Ratio CMRR 55 65 — dB T
19 Power Supply Rejection Ratio PSRR 60 65 — dB T
20 Slew Rate (VIN=100mV Low-Power mode) SR 0.1 — — V/sT
21 Slew Rate (VIN=100mV High-Speed mode) SR 1 — — V/sT
22 Unity Gain Bandwidth (Low-Power mode) GBW 0.2 — — MHz T
23 Unity Gain Bandwidth (High-Speed mode) GBW 1 — — MHz T
24 DC Open Loop Voltage Gain AV80 90 — dB T
25 Load Capacitance Driving Capability CL(max) — — 100 pF T
26 Output Impedance AC Open Loop (@100 kHz
Low-Power mode) ROUT —4k—D
Table 28. TRIAMP Characteristics 1.8–3.6 V, –40°C~105°C (continued)
#Characteristic
1Symbol Min Typ2Max Unit C
MCF51MM256/128, Rev. 5
Electrical Characteristics
Freescale Semiconductor54
27 Output Impedance AC Open Loop (@100 kHz
High-Speed mode) ROUT — 220 — D
28 Output Voltage Range VOUT 0.15 — VDD–0.1
5VT
29 Output Drive Capability IOUT 0.5 1.0 — mA T
30 Gain Margin GM 20 — — dB D
31 Phase Margin PM 45 55 — deg T
32
GPAMP startup time (Low-Power mode)
(Tolerance < 1%, Vin = 0.5 Vp–p, CL = 25 pF,
RL = 100k)
Tstartup —4—uST
33
GPAMP startup time (Low-Power mode)
(Tolerance < 1%, Vin = 0.5 Vp–p, CL = 25 pF,
RL = 100k)
Tstartup —1—uST
34 Input Voltage Noise Density f=1 kHz — 250 — nV/Hz T
1All parameters are measured at 3.3 V, CL =4 7 pF across temperature –40 to + 105°C unless specified.
2Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Table 29. OPAMP Characteristics 1.8–3.6 V (continued)
# Characteristics1Symbol Min Typ2Max Unit C
MCF51MM256/128, Rev. 5
Ordering Information
Freescale Semiconductor 53
4 Ordering Information
This section contains ordering information for the device numbering system. See Table 1 for feature
summary by package information.
4.1 Part Numbers
4.2 Package Information
4.3 Mechanical Drawings
Table 31 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MCF51MM256/128 Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 31, or
• Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate
document number (from Table 31) in the “Enter Keyword” search box at the top of the page.
.
Table 30. Orderable Part Number Summary
Freescale Part
Number Description Flash / SRAM
(Kbytes) Package Temperature
MCF51MM256VML MCF51MM256 ColdFire Microcontroller 256K/32K 104 MAPBGA –40 to 105 °C
MCF51MM256VLL MCF51MM256 ColdFire Microcontroller 256K/32K 100 LQFP –40 to 105 °C
MCF51MM256VMB MCF51MM256 ColdFire Microcontroller 256K/32K 81 MAPBGA –40 to 105 °C
MCF51MM256VLK MCF51MM256 ColdFire Microcontroller 256K/32K 80 LQFP –40 to 105 °C
MCF51MM128VMB MCF51MM128 ColdFire Microcontroller 128K/32K 81 MAPBGA –40 to 105 °C
MCF51MM128VLK MCF51MM128 ColdFire Microcontroller 128K/32K 80 LQFP –40 to 105 °C
Table 31. Package Descriptions
Pin Count Package Type Abbreviation Designator Case No. Document No.
100 Low Quad Flat Package LQFP LL 983-03 98ASS23308W
80 Low Quad Flat Package LQFP LK 1418 98ASS23174W
104 MAP BGA Package MAPBGA ML 1285-02 98ARH98267A
81 MAP BGA Package MAPBGA MB 1662-01 98ASA10670D
MCF51MM256/128, Rev. 5
Revision History
Freescale Semiconductor 53
5 Revision History
This section lists major changes between versions of the MCF51MM256 Data Sheet.
Table 32. Revision History
Revision Date Description
0 March/April 2009 Initial Draft
1 July 2009
• Revised to follow standard template.
• Removed extraneous headings from the TOC.
• Corrected units for Monotonocity to be blank in for the DAC specification.
• Updated ADC characteristic tables to include 16-Bit SAR in headings.
2 July 2009 • Changed MCG (XOSC) Electricals Table - Row 2, Average Internal Reference
Frequency typical value from 32.768 to 31.25.
3 April 2010
• Updated Thermal Characteristics table. Reinserted the 81 and 104 MapBGA devices.
• Revised the ESD and Latch-Up Protection Characteristic description to read:
Latch-up Current at TA = 125°C.
• Changed Ta b l e 9 . DC Characteristics rows 2 and 4, to 1.8 V, ILoad = -600 mA
conditions to 1.8 V, ILoad = 600A respectively.
• Corrected the 16-bit SAR ADC Operating Condition table Ref Voltage High Min value
to be 1.13 instead of 1.15.
• Updated the ADC electricals.
• Inserted the Mini-FlexBus Timing Specifications.
• Added a Temp Drift parameter to the VREF Electrical Specifications.
• Removed the S08 Naming Convention diagram.
• Updated the Orderable Part Number Summary to include the Freescale Part Number
suffixes.
• Completed the Package Description table values.
• Changed the 80LQFP package drawing from 98ARL10530D to 98ASS23174W.
• Updated electrical characteristic data.
4 October 2010 • Updated with the latest characteristic data. Added several figures. Added the ADC
Typical Operatio n table.
5 July 2012
In “Supply current characteristics” table,
•For S3I
DD, the maximum value for the first row at 1A is changed to 1.3 A and the
typical value 0.65 A is changed to 0.75A.
• For parameter 3, changed “LPS” to “LPR”, “FBILP” to "FBI" and “FBELP” to “FBE”.
• For parameter 4, changed “LPS” to “LPR”, and “FBELP” to “BLPE” in both instances.
MCF51MM256/128, Rev. 5
Document Number: MCF51MM256
Rev. 5
07/2012
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