MF616-03 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C62N51 Technical Manual S1C62N51 Technical Hardware/S1C62N51 Technical Software NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. PREFACE This part explains the function of the S1C62N51, the circuit configurations, and details the controlling method. II. S1C62N51 Technical Software This part explains the programming method of the S1C62N51. Software I. S1C62N51 Technical Hardware Hardware This manual is individualy described about the hardware and the software of the S1C62N51. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 Family processors Previous No. E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08 New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08 S1C62 Family processors Previous No. E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46 New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460 Previous No. E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3 New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 Family Previous No. ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247 New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D Previous No. DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E Previous No. EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007 New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K Hardware I. S1C62N51 Technical Hardware CONTENTS CONTENTS CHAPTER 2 INTRODUCTION ............................................................... I-1 1.1 Configuration ................................................................... I-1 1.2 Features .......................................................................... I-2 1.3 Block Diagram ................................................................. I-3 1.4 Pin Layout Diagram ......................................................... I-4 1.5 Pin Description ................................................................ I-5 POWER SUPPLY AND INITIAL RESET ................................ I-6 2.1 Power Supply .................................................................. I-6 2.2 Initial Reset ...................................................................... I-7 Oscillation detection circuit ...................................... Reset pin (RESET) .................................................... Simultaneous high input to input ports (K00-K03) ... Internal register following initialization ..................... 2.3 CHAPTER 3 Hardware CHAPTER 1 I-8 I-8 I-8 I-9 Test Pin (TEST) ............................................................... I-9 CPU, ROM, RAM ............................................................ I-10 3.1 CPU ................................................................................ I-10 3.2 ROM ............................................................................... I-11 3.3 RAM ............................................................................... I-11 S1C62N51 TECHNICAL HARDWARE EPSON I-i CONTENTS CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-12 4.1 Memory Map .................................................................. I-12 4.2 Oscillation Circuit ............................................................ I-15 Crystal oscillation circuit ......................................... I-15 CR oscillation circuit ............................................... I-16 4.3 Input Ports (K00-K03) .................................................... I-17 Configuration of input ports .................................... Input comparison registers and interrupt function .. Mask option ............................................................ Control of input ports .............................................. 4.4 I-17 I-18 I-19 I-19 Output Ports (R00-R03) ................................................. I-21 Configuration of output ports .................................. I-21 Mask option ............................................................ I-22 Control of output ports ............................................ I-24 4.5 I/O Ports (P00-P03) ....................................................... I-27 Configuration of I/O ports ....................................... I/O control register and I/O mode ........................... Mask option ............................................................ Control of I/O ports ................................................ 4.6 LCD Driver (COM0-COM3, SEG0-SEG25) .................. I-30 Configuration of LCD driver ..................................... Switching between dynamic and static drive ............ Mask option (segment allocation) ............................. Control of LCD driver .............................................. 4.7 I-27 I-27 I-28 I-28 I-30 I-33 I-34 I-36 Clock Timer .................................................................... I-37 Configuration of clock timer .................................... I-37 Interrupt function ................................................... I-38 Control of clock timer .............................................. I-39 I-ii EPSON S1C62N51 TECHNICAL HARDWARE CONTENTS A/D Converter ................................................................. I-41 Configuration of A/D converter ............................... Operation of A/D converter ..................................... Interrupt function ................................................... Usage example of the A/D converter ........................ Control of A/D converter ......................................... 4.9 I-41 I-42 I-47 I-47 I-49 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function ............................. I-53 Configuration of SVD circuit and heavy load protection function .......................... Operation of SVD detection timing .......................... Operation of heavy load protection function ............ Control of SVD circuit and heavy load protection function .......................... I-53 I-55 I-56 I-57 4.10 Interrupt and HALT ......................................................... I-59 Interrupt factors ...................................................... Specific masks and factor flags for interrupt ............ Interrupt vectors ..................................................... Control of interrupt ................................................. I-60 I-61 I-61 I-62 CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM ............................ I-63 CHAPTER 6 ELECTRICAL CHARACTERISTICS .................................... I-65 6.1 Absolute Maximum Rating ............................................. I-65 6.2 Recommended Operating Conditions ............................ I-66 6.3 DC Characteristics ......................................................... I-67 6.4 Analog Circuit Characteristics and Power Current Consumption ................................... I-69 6.5 Oscillation Characteristics .............................................. I-73 S1C62N51 TECHNICAL HARDWARE EPSON I-iii Hardware 4.8 CONTENTS CHAPTER 7 CHAPTER 8 I-iv PACKAGE ...................................................................... I-75 7.1 Plastic Package .............................................................. I-75 7.2 Ceramic Package for Test Samples ............................... I-76 PAD LAYOUT .................................................................. I-77 8.1 Diagram of Pad Layout ................................................... I-77 8.2 Pad Coordinates ............................................................. I-78 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION Each member of the S1C62N51 Series of single chip microcomputers feature a 4-bit S1C6200A core CPU, 1,024 words of ROM (12 bits per word), 80 words of RAM (4 bits per word), an LCD driver, 4 bits for input ports (K00-K03), 4 bits for output ports (R00-R03), one 4-bit I/O port (P00- P03), clock timer and A/D converter. Because of their low voltage operation and low power consumption, the S1C62N51 Series are ideal for a wide range of applications. 1.1 Configuration The S1C62N51 Series are configured as follows, depending on the supply voltage. Table 1.1.1 Configuration of the S1C62N51 Series S1C62N51 TECHNICAL HARDWARE Model Supply voltage Oscillation circuits S1C62N51 3.0 V Crystal or CR S1C62L51 1.5 V Crystal or CR EPSON I-1 CHAPTER 1: INTRODUCTION 1.2 Features Supply voltage 1.5 V / 3 V Built-in oscillation circuit Crystal or CR oscillation circuit, 32,768 Hz (typ.) Instruction set 100 instructions ROM capacity 1,024 words x 12 bits RAM capacity (data RAM) 80 words x 4 bits Input port 4 bits (Supplementary pull-down resistors may be used) Output port 4 bits (Piezo buzzer and programmable frequency output can be driven directry by mask option) Input/output port 4 bits LCD driver 26 segments x 4 common duty (or 3 and 2 common duty) Timer Clock timer A/D converter CR oscillation type A/D converter built-in Supply voltage detection circuit (SVD) 1.2 V / 2.4 V Interrupts: External interrupt Input port interrupt Internal interrupt Timer interrupt A/D converter interrupt 1 system 1 system 1 system Supply voltage 1.5 V (0.9-2.0 V) S1C62L51 1.5 V (1.2-2.0 V) S1C62L51 (During A/D conversion) 3.0 V (1.8-3.5 V) S1C62N51 Current consumption (typ.) 1.0 A (Crystal oscillation CLK = 32,768 Hz, when halted) 2.5 A (Crystal oscillation CLK = 32,768 Hz, when executing) Supply form 64-pin QFP (plastic) or chip I-2 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 1: INTRODUCTION ROM 1,024 words x 12 bits RESET OSC1 OSC2 1.3 Block Diagram OSC System Reset Control Core CPU S1C6200A RAM 80 words x 4 bits COM0-3 SEG0-25 Interrupt Generator LCD Driver VDD VL1-3 CA-CC VS1 VSS Power Controller SVD Input Port Test Port K00-03 I/O Port P00-03 Output Port R00-03 Timer FOUT / BUZZER BUZZER TEST Fout & Buzzer A/D Converter ADOUT RS TH CS Fig. 1.3.1 Block diagram S1C62N51 TECHNICAL HARDWARE EPSON I-3 CHAPTER 1: INTRODUCTION 1.4 Pin Layout Diagram QFP6-60 pin (ceramic) 45 31 30 46 16 60 1 15 QFP6-64 pin (plastic) 48 33 49 32 Index 64 17 1 16 Pin No Pin name Pin No Pin name Pin No Pin name Pin No Pin name 1 COM3 16 SEG13 31 P00 46 TH 2 SEG0 17 SEG14 32 P01 47 ADOUT 3 SEG1 18 SEG15 33 P02 48 VDD 4 SEG2 19 SEG16 34 P03 49 OSC1 5 SEG3 20 SEG17 35 RESET 50 OSC2 6 SEG4 21 SEG18 36 K00 51 V SS 7 SEG5 22 SEG19 37 K01 52 CA 8 SEG6 23 SEG20 38 K02 53 CB 9 SEG7 24 SEG21 39 K03 54 CC 10 SEG8 25 SEG22 40 R00 55 V L1 11 SEG9 26 SEG23 41 R01 56 V L2 12 SEG10 27 SEG24 42 R02 57 V L3 13 SEG11 28 SEG25 43 R03 58 COM0 14 SEG12 29 VDD 44 CS 59 COM1 15 TEST 30 V S1 45 RS 60 COM2 Pin No Pin name Pin No Pin name Pin No Pin name Pin No Pin name 1 COM2 17 TEST 33 P00 49 CS 2 COM3 18 SEG13 34 P01 50 RS 3 N.C. 19 SEG14 35 P02 51 TH 4 SEG0 20 SEG15 36 P03 52 ADOUT 5 SEG1 21 SEG16 37 RESET 53 VDD 6 SEG2 22 SEG17 38 K00 54 OSC1 7 SEG3 23 SEG18 39 K01 55 OSC2 8 SEG4 24 SEG19 40 K02 56 V SS 9 SEG5 25 SEG20 41 K03 57 CA 10 SEG6 26 SEG21 42 R00 58 CB 11 SEG7 27 SEG22 43 R01 59 CC 12 SEG8 28 SEG23 44 R02 60 V L1 13 SEG9 29 SEG24 45 R03 61 V L2 14 SEG10 30 SEG25 46 N.C. 62 V L3 15 SEG11 31 VDD 47 N.C. 63 COM0 16 SEG12 32 V S1 48 N.C. 64 COM1 Fig. 1.4.1 N.C. = No connection Pin assignment I-4 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 1: INTRODUCTION 1.5 Pin Description Table 1.5.1 Pin description Pin No. Terminal name QFP6-60 pin QFP6-64 pin Input/Output Function (ceramic) (plastic) VDD 29, 48 31, 53 (I) Power source (+) terminal VSS 51 56 (I) Power source (-) terminal VS1 30 32 O Oscillation and internal logic system regulated voltage output terminal VL1 55 60 O VL2 56 61 O LCD system booster output terminal (V L1 x 2) VL3 57 62 O LCD system booster output terminal (V L1 x 3) 52-54 57-59 - Booster capacitor connecting terminal OSC1 49 54 I Crystal or CR oscillation input terminal OSC2 50 55 O Crystal or CR oscillation output terminal K00-K03 36-39 38-41 I Input terminal P00-P03 31-34 33-36 I/O I/O terminal R00-R03 40-43 42-45 O Output terminal SEG0-25 2-14 4-16 O LCD segment output terminal 16-28 18-30 58-60, 1 63, 64, 1, 2 CS 44 RS 45 TH LCD system regulated voltage output terminal (approx. -1.05V) CA-CC COM0-3 (convertible to DC output terminal by mask option) O LCD common output terminal 49 I A/D converter CR oscillation input terminal 50 O A/D converter CR oscillation output terminal 46 51 O A/D converter CR oscillation output terminal ADOUT 47 52 O A/D converter oscillation frequency output terminal RESET 35 37 I Initial setting input terminal TEST 15 17 I Test input terminal S1C62N51 TECHNICAL HARDWARE EPSON I-5 CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (*1) supplied to VDD through VSS, the S1C62N51 Series generate the necessary internal voltages with the regulated voltage circuit (<VS1> for oscillators and internal circuit, <VL1> for LCDs) and the voltage booster (<VL2, VL3> for LCDs). Figure 2.1.1 shows the power supply configuration. *1 Supply voltage: 62N51...3 V, 62L51...1.5 V Note - - External loads cannot be driven by the output voltage of the regulated voltage circuit and voltage booster circuit. See Chapter 6, "ELECTRICAL CHARACTERISTICS", for voltage values. V DD VS1 V L1 External power supply V L2 V L3 CA CB CC Internal system regulated voltage circuit V S1 Internal circuit Oscillation circuit LCD regulated voltage circuit OSC1, 2 V L1 V L1 LCD voltage booster V L2 V L3 LCD driver COM0-3 SEG0-25 Vss Fig. 2.1.1 Configuration of power supply I-6 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C62N51 Series circuits, an initial reset must be executed. There are three ways of doing this. (1) Initial reset by the oscillation detection circuit (Note) (2) External initial reset via the RESET pin (3) External initial reset by simultaneous high input to pins K00-K03 (depending on mask option) Figure 2.2.1 shows the configuration of the initial reset circuit. OSC1 OSC1 OSC2 Oscillation circuit Oscillation detection circuit K00 Vss Noise rejection circuit K01 Initial reset Noise rejection circuit K02 K03 RESET Fig. 2.2.1 Configuration of Vss initial reset circuit Note Since the circuit may sometimes not operate normally with the initial resetting by the oscillation detection circuit indicated in number (1), depending on the method of making the power, you should utilize one of the initial resetting methods mentioned in numbers (2) and (3). S1C62N51 TECHNICAL HARDWARE EPSON I-7 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Oscillation detection When the oscillation circuit has been stopped until the oscillation circuit begins to oscillate when the power is circuit turned on or for any other reason, the oscillation detection circuit will output an initial reset signal, but since the circuit may sometimes not operate normally with the initial resetting due to the oscillation detection circuit, depending on the method of making the power, you should utilize one of the initial resetting methods indicated hereafter. Reset pin (RESET) An initial reset can be invoked externally by making the reset pin high. This high level must be maintained for at least 5 ms (when oscillating frequency, fosc = 32 kHz), because the initial reset circuit contains a noise rejection circuit. When the reset pin goes low the CPU begins to operate. Simultaneous high input to input ports (K00-K03) Another way of invoking an initial reset externally is to input a high signal simultaneously to the input ports (K00-K03) selected with the mask option. The specified input port pins must be kept high for at least 4 sec (when oscillating frequency fosc = 32 kHz), because of the noise rejection circuit. Table 2.2.1 shows the combinations of input ports (K00- K03) that can be selected with the mask option. Table 2.2.1 Input port combinations A B C D Not used K00*K01 K00*K01*K02 K00*K01*K02*K03 When, for instance, mask option D (K00*K01*K02*K03) is selected, an initial reset is executed when the signals input to the four ports K00-K03 are all high at the same time. If you use this function, make sure that the specified ports do not go high at the same time during normal operation. I-8 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET Internal register following initialization An initial reset initializes the CPU as shown in the table below. Table 2.2.2 Initial values CPU Core Name Signal Number of bits Setting value Program counter step Program counter page New page pointer Stack pointer Index register X Index register Y Register pointer General register A General register B Interrupt flag Decimal flag Zero flag Carry flag PCS PCP NPP SP X Y RP A B I D Z C 8 4 4 8 8 8 4 4 4 1 1 1 1 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral circuits Name Number of bits Setting value 80 x 4 26 x 4 - Undefined Undefined *1 RAM Display memory Other peripheral circuit *1: See Section 4.1, "Memory Map" 2.3 Test Pin (TEST) This pin is used when IC is inspected for shipment. During normal operation connect it to VSS. S1C62N51 TECHNICAL HARDWARE EPSON I-9 CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C62N51 Series employs the S1C6200A core CPU, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the S1C6200A. Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200A. Note the following points with regard to the S1C62N51 Series: (1) The SLEEP operation is not provided, so the SLP instruction cannot be used. (2) Because the ROM capacity is 1,024 words, 12 bits per word, bank bits are unnecessary, and PCB and NBP are not used. (3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is invalid. PUSH POP LD LD I-10 XP XP XP,r r,XP EPSON PUSH POP LD LD YP YP YP,r r,YP S1C62N51 TECHNICAL HARDWARE CHAPTER 3: CPU, ROM, RAM 3.2 ROM The built-in ROM, a mask ROM for the program, has a capacity of 1,024 x 12-bit steps. The program area is 4 pages (0-3), each consisting of 256 steps (00H-FFH). After an initial reset, the program start address is page 1, step 00H. The interrupt vector is allocated to page l, steps 01H- 07H. Bank 0 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 07H step 08H step Program area FFH step Fig. 3.2.1 12 bits ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 80 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H-00FH is the memory area pointed by the register pointer (RP). S1C62N51 TECHNICAL HARDWARE EPSON I-11 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C62N51 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C62N51 Series has an address space of 154 words, of which 32 words are allocated to display memory and 26 words, to I/O memory. Figure 4.1.1 show the overall memory map for the S1C62N51 Series, and Tables 4.1.1(a) and (b), the memory maps for the peripheral circuits (I/O space). Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 RAM area (000H-04FH) 80 words x 4 bits (R/W) 3 4 5 6 0 7 8 Display memory area (090H-0AFH) 32 words x 4 bits (Write only) 9 A B C D E F I/O memory area Table 4.1.1(a), (b) Fig. 4.1.1 Unused area Memory map Note Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. I-12 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(a) I/O memory map Address D3 Register D2 D1 D0 K03 K02 K01 K00 TM1 TM0 TC1 TC0 TC5 TC4 TC9 TC8 TC13 TC12 EIK01 EIK00 0E0H R TM3 TM2 0E3H R TC3 TC2 0E4H R/W TC7 TC6 0E5H R/W TC11 TC10 0E6H R/W TC15 TC14 0E7H R/W EIK03 EIK02 0E8H R/W 0 EIT2 EIT8 EIT32 0EBH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 IK0 0EDH R 0 IT2 IT8 0EFH R *1 *2 *3 *4 *5 *6 IT32 Name K03 K02 K01 K00 TM3 TM2 TM1 TM0 TC3 TC2 TC1 TC0 TC7 TC6 TC5 TC4 TC11 TC10 TC9 TC8 TC15 TC14 TC13 TC12 EIK03 EIK02 EIK01 EIK00 0 EIT2 EIT8 EIT32 0 0 0 EIAD 0 0 0 IK0 0 IT2 IT8 IT32 Init *1 - *2 - *2 - *2 - *2 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 0 0 0 0 Comment 1 High High High High High High High High 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 Low Low Low Low Low Low Low Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mask Mask Mask Mask Input port data K03 Input port data K02 Input port data K01 Input port data K00 Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz Up/down counter data TC3 Up/down counter data TC2 Up/down counter data TC1 Up/down counter data TC0 (LSB) Up/down counter data TC7 Up/down counter data TC6 Up/down counter data TC5 Up/down counter data TC4 Up/down counter data TC11 Up/down counter data TC10 Up/down counter data TC9 Up/down counter data TC8 Up/down counter data TC15 (MSB) Up/down counter data TC14 Up/down counter data TC13 Up/down counter data TC12 Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz *5 0 0 0 *5 *5 *5 0 Enable Mask Interrupt mask register (A/D) *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) 0 0 0 Yes Yes Yes No No No Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *5 *4 *4 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual S1C62N51 TECHNICAL HARDWARE EPSON I-13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(b) I/O memory map Address D3 0 Register D2 D1 0 D0 0 IAD 0F0H R 0 0 0 ADRUN 0F1H R R03 R/W R01 R00 BUZZER FOUT R02 0F3H R/W P03 P02 P00 P01 0F4H R/W C3 C2 C0 C1 0F5H R/W C7 C6 C4 C5 0F6H R/W C11 C10 C8 C9 0F7H R/W C15 C14 C12 C13 0F8H R/W 0 0 0 TMRST 0F9H R HLMOD W 0 SVDDT SVDON 0FAH R/W CSDC R/W R 0 0 0 0FBH R/W 0 R 0 0 IOC 0FCH R XBZR 0 R/W XFOUT1 XFOUT0 0FDH R/W R 0 0 R/W 0 ADCLK 0FEH R I-14 R/W Name 0 0 0 IAD 0 0 0 ADRUN R03 R02 R01 BUZZER R00 FOUT P03 P02 P01 P00 C3 C2 C1 C0 C7 C6 C5 C4 C11 C10 C9 C8 C15 C14 C13 C12 0 0 0 TMRST HLMOD 0 SVDDT SVDON CSDC 0 0 0 0 0 0 IOC XBZR 0 XFOUT1 XFOUT0 0 0 0 ADCLK Init *1 1 0 Comment *5 *5 *5 Yes 0 No Interrupt factor flag (A/D) *4 *5 *5 *5 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - - - - - *2 *2 *2 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 Start High High High On High On High High High High 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Stop Low Low Low Off Low Off Low Low Low Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A/D conversion Start/Stop Output port data R03 Output port data R02 Output port data R01 Buzzer On/Off control register Output port data R00 Frequency output control register I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 Up-counter data C3 Up-counter data C2 Up-counter data C1 Up-counter data C0 (LSB) Up-counter data C7 Up-counter data C6 Up-counter data C5 Up-counter data C4 Up-counter data C11 Up-counter data C10 Up-counter data C9 Up-counter data C8 Up-counter data C15 (MSB) Up-counter data C14 Up-counter data C13 Up-counter data C12 *5 *5 *5 Reset 0 Reset Heavy - Normal Clock timer reset Heavy load protection mode register 0 0 0 Low On Static Normal Off Dynamic Supply voltage detection data Supply voltage detection circuit On/Off LCD drive switch *5 *5 *5 *5 *5 *5 *5 *5 0 0 Out 2 kHz In 4 kHz I/O port I/O control register Buzzer frequency control *5 FOUT frequency control FOUT frequency control 0 0 *6 *6 *5 *5 *5 0 EPSON 65 kHz 32 kHz A/D clock selection 65 kHz/32 kHz S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.2 Oscillation Circuit The S1C62N51 Series have a built-in oscillation circuit. For the oscillation circuit, eiter crystal oscillation or CR oscillation may be selected by a mask option. Crystal oscillation circuit The crystal oscillation circuit generates the operating clock for the CPU and peripheral circuit on connection to an external crystal oscillator (typ. 32.768 kHz) and trimmer capacitor (5-25 pF). Figure 4.2.1 is the block diagram of the crystal oscillation circuit. V DD CG OSC2 Fig. 4.2.1 RD To CPU and peripheral circuits Rf X'tal OSC1 V DD CD The S1C62N51 Series Crystal oscillation circuit As Figure 4.2.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) between the OSC1 and OSC2 pins and the trimmer capacitor (CG) between the OSC1 and VDD pins. S1C62N51 TECHNICAL HARDWARE EPSON I-15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) CR oscillation circuit For the S1C62N51 Series, CR oscillation circuit (typ. 65 kHz) may be selected by a mask option. Figure 4.2.2 is the block diagram of the CR oscillation circuit. OSC1 To CPU and peripheral circuits RCR OSC2 Fig. 4.2.2 CR oscillation circuit C The S1C62N51 Series As Figure 4.2.2 indicates, the CR oscillation circuit can be configured simply by connecting the register (RCR) between pins OSC1 and OSC2 since capacity (C) is built-in. See Chapter 6, "ELECTRICAL CHARACTERISTICS" for R value. I-16 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3 Input Ports (K00-K03) Configuration of input ports The S1C62N51 Series have a general-purpose input (4 bits). Each of the input port pins (K00-K03) has an internal pulldown resistance. The pull-down resistance can be selected for each bit with the mask option. Figure 4.3.1 shows the configuration of input port. Interrupt request Kxx Data bus VDD Address VSS Fig. 4.3.1 Configuration of input port Mask option Selecting "pull-down resistance enabled" with the mask option allows input from a push button, key matrix, and so forth. When "pull-down resistance disabled" is selected, the port can be used for slide switch input and interfacing with other LSIs. S1C62N51 TECHNICAL HARDWARE EPSON I-17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Input comparison registers and interrupt function All four input port bits (K00-K03) provide the interrupt function. The conditions for issuing an interrupt can be set by the software for the four bits. Also, whether to mask the interrupt function can be selected individually for all four bits by the software. Figure 4.3.2 shows the configuration of K00-K03. Kxx One for each pin series Data bus Address Noise rejector Interrupt factor flag (IK) Interrupt request Address Mask option (K00-K03) Interrupt mask register (EIK) Address Fig. 4.3.2 Input interrupt circuit configuration (K00-K03) The interrupt mask registers (EIK00-EIK03) enable the interrupt mask to be selected individually for K00-K03. An interrupt occurs when the input value which are not masked change and the interrupt factor flag (IK0) is set to "1". I-18 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) The contents that can be selected with the input port mask option are as follows: Mask option (1) An internal pull-down resistance can be selected for each of the four bits of the input ports (K00-K03). Having selected "pull-down resistance disabled", take care that the input does not float. Select "pull-down resistance enabled" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring through noise. The mask option enables selection of the noise rejection circuit for each separate pin series. When "use" is selected, a maximum delay of 0.5 ms (fosc = 32 kHz) occurs from the time an interrupt condition is established until the interrupt factor flag (IK) is set to "1". Control of input ports Table 4.3.1 list the input port control bits and their addresses. Table 4.3.1 Input port control bits Address D3 Register D2 D1 D0 K03 K02 K01 K00 EIK01 EIK00 0E0H R EIK03 EIK02 0E8H R/W 0 0 0 0EDH R *1 *2 *3 *4 *5 *6 IK0 Name K03 K02 K01 K00 EIK03 EIK02 EIK01 EIK00 0 0 0 IK0 Init *1 - *2 - *2 - *2 - *2 0 0 0 0 1 High High High High Enable Enable Enable Enable 0 Low Low Low Low Mask Mask Mask Mask Comment Input port data K03 Input port data K02 Input port data K01 Input port data K00 Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual S1C62N51 TECHNICAL HARDWARE EPSON I-19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K00-K03 Input port data (0E0H) The input data of the input port pins can be read with these registers. When "1" is read: When "0" is read: Writing: High level Low level Invalid The value read is "1" when the pin voltage of the four bits of the input ports (K00-K03) goes high (VDD), and "0" when the voltage goes low (VSS). These bits are reading, so writing cannot be done. EIK00-EIK03 Interrupt mask registers (0E8H) Masking the interrupt of the input port pins can be done with these registers. When "1" is written: When "0" is written: Reading: Enable Mask Valid With these registers, masking of the input port bits can be done for each of the four bits. After an initial reset, these registers are all set to "0". IK0 Interrupt factor flags (0EDH D0) These flags indicate the occurrence of an input interrupt. When "1" is read: When "0" is read: Interrupt has occurred Interrupt has not occurred Writing: Invalid The interrupt factor flag IK0 is associated with K00-K03, respectively. From the status of these flags, the software can decide whether an input interrupt has occurred. These flags are reset when the software has read them. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. After an initial reset, these flags are set to "0". I-20 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.4 Output Ports (R00-R03) Configuration of output ports The S1C62N51 Series have 4 bits for general output ports (R00-R03). Output specifications of the output ports can be selected individually with the mask option. Three kinds of output specifications are available: complementary output and Pch open drain output. Also, the mask option enables the output ports R00 and R01 to be used as special output ports. Figure 4.4.1 shows the configuration of the output ports. Data bus VDD Register Rxx Complementary Pch open drain Address VSS Fig. 4.4.1 Configuration of output ports S1C62N51 TECHNICAL HARDWARE Mask option EPSON I-21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) The mask option enables the following output port selection. Mask option (1) Output specifications of output ports The output specifications for the output ports (R00-R03) may be either complementary output or Pch open drain output for each of the four bits. However, even when Pch open drain output is selected, a voltage exceeding the source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for output ports R00 and R01, as shown in Table 4.4.1. Figure 4.4.2 shows the structure of output ports R00-R03. Data bus Table 4.4.1 Special output Pin name When special output is selected R00 FOUT or BUZZER R01 BUZZER Register (R03) R03 Register (R02) R02 BUZZER Register (R01) R01 BUZZER Register (R00) Fig. 4.4.2 Structure of output port R00-R03 I-22 R00 FOUT Address (0F3H) Mask option EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) FOUT (R00) When output port R00 is set for FOUT output, this port will generate fosc (CPU operating clock frequency) or clock frequency divided into fosc. Clock frequency may be selected individually for F1-F4, from among 5 types by mask option; one among F1-F4 is selected by software and used. The types of frequency which may be selected are shown in Table 4.4.2. Table 4.4.2 FOUT clock frequency Clock frequency (Hz) Setting value fosc = 32,768 F1 F2 F3 F4 (D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1) 1 256 (fosc/128) 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 2 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 3 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 4 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 5 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 32,768 (fosc/1) (D1, D0) = (XFOUT1, XFOUT0) Note A hazard may occur when the FOUT signal is turned on or off. BUZZER, BUZZER Output ports R01 and R00 may be set to BUZZER output (R01, R00) and BUZZER output (BUZZER reverse output), respectively, allowing for direct driving of the piezo-electric buzzer. BUZZER output (R00) may only be set if R01 is set to BUZZER output. In such case, whether ON/OFF of the BUZZER output is done through R00 register or is controlled through R01 simultaneously with BUZZER output is also selected by mask option. The frequency of buzzer output may be selected by software to be either 2 kHz or 4 kHz. S1C62N51 TECHNICAL HARDWARE EPSON I-23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Control of output ports Table 4.4.3 lists the output port control bits and their addresses. Table 4.4.3 Control bits of output ports Address D3 R03 0F3H XBZR 0FDH R/W *1 *2 *3 *4 *5 *6 Register D2 D1 D0 Name R03 R00 R01 R02 R02 BUZZER FOUT R01 BUZZER R/W R00 FOUT XBZR 0 XFOUT1 XFOUT0 0 XFOUT1 R R/W XFOUT0 Init *1 0 0 0 0 0 0 0 1 High High High On High On 2 kHz 0 Low Low Low Off Low Off 4 kHz Comment Output port data R03 Output port data R02 Output port data R01 Buzzer On/Off control register Output port data R00 Frequency output control register Buzzer frequency control *5 0 0 FOUT frequency control FOUT frequency control *6 *6 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual R00-R03 Output port data (0F3H) Sets the output data for the output ports. When "1" is written: When "0" is written: Reading: High output Low output Valid The output port pins output the data written to the corresponding registers (R00-R03) without changing it. When "1" is written to the register, the output port pin goes high (VDD), and when "0" is written, the output port pin goes low (VSS). After an initial reset, all registers are set to "0". I-24 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00 (when FOUT Special output port data (0F3H D0) is selected) Controls the FOUT (clock) output. When "1" is written: When "0" is written: Reading: Clock output Low level (DC) output Valid FOUT output can be controlled by writing data to R00. After an initial reset, this register is set to "0". Figure 4.4.3 shows the output waveform for FOUT output. R00 register Fig. 4.4.3 FOUT output waveform 0 1 FOUT output waveform XFOUT0, XFOUT1 FOUT frequency control (0FDH D0, 0FDH D1) Selects the output frequency when R00 port is set for FOUT output. Table 4.4.4 FOUT frequency selection XFOUT1 XFOUT0 Frequency selection 0 0 F1 0 1 F2 1 0 F3 1 1 F4 After an initial reset, these registers are set to "0". S1C62N51 TECHNICAL HARDWARE EPSON I-25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00, R01 (when BUZZER Special output port data (0F3H D0, 0F3H D1) and BUZZER Controls the buzzer output. is selected) When "1" is written: Buzzer output When "0" is written: Low level (DC) output Reading: Valid BUZZER and BUZZER output can be controlled by writing data to R00 and R01. When BUZZER output by R01 register control is selected by mask option, BUZZER output and BUZZER output can be controlled simultaneously by writing data to R01 register. After an initial reset, these registers are set to "0". Figure 4.4.4 shows the output waveform for buzzer output. R01 (R00) register 0 1 BUZZER output waveform Fig. 4.4.4 Buzzer output waveform BUZZER output waveform XBZR Buzzer frequency control (0FDH D3) Selects the frequency of the buzzer signal. When "1" is written: When "0" is written: Reading: 2 kHz 4 kHz Valid When R00 and R01 port is set to buzzer output, the frequency of the buzzer signal can be selected by this register. When "1" is written to this register, the frequency is set in 2 kHz, and in 4 kHz when "0" is written. After an initial reset, this register is set to "0". I-26 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.5 I/O Ports (P00-P03) The S1C62N51 Series have a 4-bit general-purpose I/O port. Figure 4.5.1 shows the configuration of the I/O port. The four bits of the I/O port P00-P03 can be set to either input mode or output mode. The mode can be set by writing data to the I/O control register (IOC). Data bus Configuration of I/O ports Input control Register Pxx Address Fig. 4.5.1 Configuration of I/O port I/O control register and I/O mode Address I/O control register (IOC) VSS Input or output mode can be set for the four bits of I/O port P00-P03 by writing data into I/O control register IOC. To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, its impedance becomes high and it works as an input port. However, the input line is pulled down when input data is read. The output mode is set when "1" is written to the I/O control register (IOC). When an I/O port set to output mode works as an output port, it outputs a high signal (VDD) when the port output data is "1", and a low signal (VSS) when the port output data is "0". After an initial reset, the I/O control register is set to "0", and the I/O port enters the input mode. S1C62N51 TECHNICAL HARDWARE EPSON I-27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Mask option The output specification during output mode (IOC = "1") of the I/O port can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of the I/O port. However, when Pch open drain output has been selected, voltage in excess of the supply voltage must not be applied to the port. Control of I/O ports Table 4.5.1 lists the I/O port control bits and their addresses. Table 4.5.1 I/O port control bits Address D3 Register D2 D1 D0 P03 P02 P01 P00 0 IOC 0F4H R/W 0 0 0FCH R *1 *2 *3 *4 *5 *6 R/W Name P03 P02 P01 P00 0 0 0 IOC Init *1 - *2 - *2 - *2 - *2 1 High High High High 0 Low Low Low Low Comment I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 *5 *5 *5 0 Out In I/O port I/O control register Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual P00-P03 I/O port data (0F4H) I/O port data can be read and output data can be written through the port. * When writing data When "1" is written: When "0" is written: High level Low level When an I/O port is set to the output mode, the written data is output from the I/O port pin unchanged. When "1" is written as the port data, the port pin goes high (VDD), and when "0" is written, the level goes low (VSS). Port data can also be written in the input mode. * When reading data When "1" is read: When "0" is read: I-28 EPSON High level Low level S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) The pin voltage level of the I/O port is read. When the I/ O port is in the input mode the voltage level being input to the port pin can be read; in the output mode the output voltage level can be read. When the pin voltage is high (VDD) the port data read is "1", and when the pin voltage is low (VSS) the data is "0". Also, the built-in pulldown resistance functions during reading, so the I/O port pin is pulled down. Note - - When the I/O port is set to the output mode and a low-impedance load is connected to the port pin, the data written to the register may differ from the data read. When the I/O port is set to the input mode and a low-level voltage (Vss) is input by the built-in pull-down resistance, an erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistance load is greater than the read-out time. When the input data is being read, the time that the input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the pins must settle within 0.5 cycles. If this condition cannot be met, some measure must be devised, such as arranging a pull-down resistance externally, or performing multiple read-outs. IOC I/O control register (0FCH D0) The input or output I/O port mode can be set with this register. When "1" is written: When "0" is written: Reading: Output mode Input mode Valid The input or output mode of the I/O port is set in units of four bits. For instance, IOC sets the mode for P00-P03. Writing "1" to the I/O control register makes the I/O port enter the output mode, and writing "0", the input mode. After an initial reset, the IOC register is set to "0", so the I/O port is in the input mode. S1C62N51 TECHNICAL HARDWARE EPSON I-29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6 LCD Driver (COM0-COM3, SEG0-SEG25) Configuration of LCD The S1C62N51 Series have four common pins and 26 (SEG0-SEG25) segment pins, so that an LCD with a maxidriver mum of 104 (26 x 4) segments can be driven. The power for driving the LCD is generated by the CPU internal circuit, so there is no need to supply power externally. The driving method is 1/4 duty (1/3 or 1/2 duty by mask option) dynamic drive, adopting the four types of potential, VDD, VL1, VL2 and VL3. The frame frequency is 32 Hz for 1/ 4 duty, 42.7 Hz for 1/3 duty, and 32 Hz for 1/2 duty (in the case of fosc = 32,768 Hz). Figure 4.6.1 shows the drive waveform for 1/4 duty, Figure 4.6.2 shows the drive waveform for 1/3 duty, and Figure 4.6.3 shows the drive waveform for 1/2 duty. Note fosc indicates the oscillation frequency of the oscillation circuit. I-30 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VC3 VC2 VC1 VSS COM0 COM1 COM2 LCD lighting status COM0 COM1 COM2 COM3 SEG0~25 COM3 VC3 VC2 VC1 VSS Not lit Lit SEG0 ~SEG25 Fig. 4.6.1 Frame freqency Drive waveform for 1/4 duty S1C62N51 TECHNICAL HARDWARE EPSON I-31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VC3 VC2 VC1 VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0~25 COM2 Not lit Lit COM3 VC3 VC2 VC1 VSS SEG0 ~SEG25 Fig. 4.6.2 Drive waveform Frame freqency for 1/3 duty VC3 VC2 VC1 VSS COM0 COM1 LCD lighting status COM0 COM1 SEG0~25 COM2 COM3 VC3 VC2 VC1 VSS Not lit Lit SEG0 ~SEG25 Fig. 4.6.3 Drive waveform for 1/2 duty I-32 Frame freqency EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Switching between dynamic and static drive The S1C62N51 Series members allow software setting of the LCD static drive. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the OSC circuit. The procedure for executing of the LCD static drive is as follows: Write "1" to the CSDC register at address "0FBH D3". Write the same value to all registers corresponding to COM0-COM3 of the display memory. Note - Even when l/3 or 1/2 duty is selected, the display data corresponding to COM3 is valid for static drive. Hence, for static drive, set the same value to all display memory corresponding COM0-COM3. - For cadence adjustment, set the display data including display data corresponding to COM3, so that all the LCD segments go on. Figure 4.6.4 shows the drive waveform for static drive. LCD lighting status -V DD -V L1 -V L2 -V L3 COM 0-3 COM0 COM1 COM2 COM3 SEG0-25 Frame frequency -V DD -V L1 -V L2 -V L3 Not lit Lit SEG 0-25 -V DD -V L1 -V L2 -V L3 Fig. 4.6.4 LCD static drive waveform S1C62N51 TECHNICAL HARDWARE EPSON I-33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (1) Segment allocation Mask option (segment allocation) As shown in Figure 4.l.1, the S1C62N51 Series display data is decided by the display data written to the display memory (write-only) at address "090H-0AFH". The address and bits of the display memory can be made to correspond to the segment pins (SEG0-SEG25) in any combination through mask option. This simplifies design by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.6.5 shows an example of the relationship between the LCD segments (on the panel) and the display memory in the case of 1/3 duty. Address Common 0 Common 1 Common 2 9A, D0 9B, D1 9B, D0 (a) (f) (e) SEG11 9A, D1 9B, D2 9A, D3 (b) (g) (d) SEG12 9D, D1 9A, D2 9B, D3 (f') (c) (p) Data D3 D2 D1 D0 09AH d c b a 09BH p g f e 09CH d' c' b' a' 09DH p' g' f' e' SEG10 Display data memory allocation Pin address allocation a a' b f e g' c c' e' p d SEG10 b' f' g SEG11 p' d' SEG12 Common 0 Common 1 Fig. 4.6.5 Common 2 Segment allocation I-34 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (2) Drive duty According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty. Table 4.6.1 shows the differences in the number of segments according to the selected duty. Table 4.6.1 Differences according to selected duty Duty Pins used in common Maximum number of segments Frame frequency (when fosc = 32 kHz) 1/4 1/3 1/2 COM0-3 COM0-2 COM0, 1 104 (26 x 4) 78 (26 x 3) 52 (26 x 2) 32 Hz 42.7 Hz 32 Hz (3) Output specification The segment pins (SEG0-SEG25) are selected by mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment pin is output. When DC output is selected, either complementary output or Pch open drain output can be selected for each pin by mask option. Note The pin pairs are the combination of SEG (2*n) and SEG (2*n + 1) (where n is an integer from 0 to 12). S1C62N51 TECHNICAL HARDWARE EPSON I-35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Table 4.6.2 shows the control bits of the LCD driver and their addresses. Figure 4.6.6 shows the display memory map. Control of LCD driver Table 4.6.2 Control bits of LCD driver Address D3 CSDC Register D2 D1 0 D0 0 0 0FBH R/W *1 *2 *3 *4 *5 *6 Init *1 0 Name CSDC 0 0 0 R 1 Static Comment 0 Dynamic LCD drive switch *5 *5 *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual Address Fig. 4.6.6 Display 090 memory map 0A0 0 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (Write only) 32 words x 4 bits CSDC LCD drive switch (0FBH D3) The LCD drive format can be selected with this switch. When "1" is written: When "0" is written: Reading: Static drive Dynamic drive Valid After an initial reset, dynamic drive (CSDC = "0") is selected. Display memory (090H-0AFH) The LCD segments are turned on or off according to this data. When "1" is written: When "0" is written: Reading: On Off Invalid By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be turned on or off. After an initial reset, the contents of the display memory are undefined. I-36 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.7 Clock Timer Configuration of clock timer The S1C62N51 Series have a built-in clock timer driven by the source oscillator. The clock timer is configured as a seven-bit binary counter that serves as a frequency divider taking a 256 Hz source clock from a prescaler. The four high-order bits (16 Hz-2 Hz) can be read by the software. Figure 4.7.1 is the block diagram of the clock timer. Data bus OSC 256 Hz (oscillation circuit) 128 Hz-32 Hz 16 Hz-2 Hz 32 Hz, 8 Hz, 2 Hz Fig. 4.7.1 Block diagram of Clock timer reset signal clock timer Interrupt control Interrupt request Normally, this clock timer is used for all kinds of timing purpose, such as clocks. S1C62N51 TECHNICAL HARDWARE EPSON I-37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) The clock timer can interrupt on the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The software can mask any of these interrupt signals. Figure 4.7.2 is the timing chart of the clock timer. Interrupt function Address 0E3H Register Frequency bits D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz Clock timer timing chart Occurrence of 32 Hz interrupt request Occurrence of 8 Hz interrupt request Occurrence of 2 Hz interrupt request Fig. 4.7.2 Timing chart of the clock timer As shown in Figure 4.7.2, an interrupt is generated on the falling edge of the 32 Hz, 8 Hz, and 2 Hz frequencies. When this happens, the corresponding interrupt event flag (IT32, IT8, IT2) is set to "1". Masking the separate interrupts can be done with the interrupt mask register (EIT32, EIT8, EIT2). However, regardless of the interrupt mask register setting, the interrupt event flags will be set to "1" on the falling edge of their corresponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to "1"). Note Write to the interrupt mask register (EIT32, EIT8, EIT2) only in the DI status (interrupt flag = "0"). Otherwise, it causes malfunction. I-38 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Table 4.7.1 shows the clock timer control bits and their addresses. Control of clock timer Table 4.7.1 Control bits of clock timer Address D3 Register D2 D1 D0 TM3 TM2 TM1 TM0 EIT8 EIT32 0E3H R 0 EIT2 0EBH R 0 R/W IT2 IT8 IT32 0EFH R 0 0 0 TMRST 0F9H R *1 *2 *3 *4 *5 *6 W Name TM3 TM2 TM1 TM0 0 EIT2 EIT8 EIT32 0 IT2 IT8 IT32 0 0 0 TMRST Init *1 - *3 - *3 - *3 - *3 Comment 1 High High High High 0 Low Low Low Low Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz 0 0 0 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz 0 0 0 Yes Yes Yes No No No *5 *5 Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *4 *4 *5 *5 *5 Reset Reset - Clock timer reset *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual TM0-TM3 Timer data (0E3H) The l6 Hz to 2 Hz timer data of the clock timer can be read from this register. These four bits are read-only, and write operations are invalid. After an initial reset, the timer data is initialized to "0H". EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0-D2) These registers are used to mask the clock timer interrupt. When "1" is written: When "0" is written: Reading: Enabled Masked Valid The interrupt mask register bits (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz). After an initial reset, these registers are all set to "0". S1C62N51 TECHNICAL HARDWARE EPSON I-39 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) IT32, IT8, IT2 Interrupt factor flags (0EFH D0-D2) These flags indicate the status of the clock timer interrupt. When "1" is read: When "0" is read: Writing: Interrupt has occurred Interrupt has not occurred Invalid The interrupt factor flags (IT32, IT8, IT2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can determine from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" on the falling edge of the signal. These flags can be reset when the register is read by the software. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. After an initial reset, these flags are set to "0". TMRST Clock timer reset (0F9H D0) This bit resets the clock timer. When "1" is written: When "0" is written: Reading: Clock timer reset No operation Always "0" The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" when read. I-40 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) 4.8 A/D Converter Configuration of A/D The S1C62N51 Series have a CR oscillation type A/D converter. This A/D converter is equipped with two CR oscillaconverter tion circuit systems and a counter that measures their oscillation frequency. Counted values represent connected resistance values converted into digital values. Connect a reference resistance that does not change oscillation frequency according to temperature between the RS and CS terminals and a sensor that does change resistance values according to temperature between the TH and CS terminals. Then, oscillate them alternately. The difference in the counted value can be evaluated as the difference between the respective oscillation frequencies. Therefore, various sensor circuit such as a temperature-measuring circuit using a thermistor can be easily created, for example. The configuration of the A/D converter is shown in Figure 4.8.1. OSC1 clock Up/down counter 32 kHz or 65 kHz Multiplying circuit ADCLK TC15 TC11 -TC12 -TC8 Up/Down control TC7 -TC4 TC3 -TC0 Start/Stop control Data bus ADRUN IAD C15 -C12 Start/Stop C11 -C8 C7 -C4 EIAD Interrupt controller C3 -C0 Interrupt request Up-counter Start/Stop control Controller VSS Fig. 4.8.1 ADOUT Tr3 VSS CAD Configuration of A/D converter S1C62N51 TECHNICAL HARDWARE Tr1 RS CS Tr2 VDD TH R1 R2 EPSON I-41 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Connect a reference resistance that only slightly changes resistance values according to environmental conditions between the oscillating I/O terminals RS and CS. Connect a sensor that changes resistance values between the TH and CS terminals. Furthermore, by connecting a condenser between the CS and VSS, a CR oscillation circuit is completed. Operation of A/D converter This A/D converter performs CR oscillation using one of the two resistances connected to external devices. Their oscillation frequency serves as a clock from which the oscillation frequency is counted. Difference in counted oscillation frequency can be evaluated in terms of the difference between the respective resistance values. Measurement results can be obtained from the changes in resistance values after correcting the difference according to the program. (1) External resistances and condenser Connect a sensor (a variable resistance element such as a thermistor) between the TH and CS terminals. Next, set the reference value of the item to be measured (e.g. reference temperature in the case of temperature measurement) and connect the reference resistance equivalent to the sensor resistance value at the above reference value between the RS and CS terminals. An element that does not change due to temperature or other environmental conditions must be used as the reference resistance. Connect an oscillating condenser that is used for CR oscillation of both the reference resistance and the sensor between the CS and VSS terminals. I-42 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) (2) Oscillation circuit The CR oscillation circuit is designed so that either the reference resistance side or the sensor side can be operated independently by the oscillation control circuit. A/D conversion begins when "1" is written in the ADRUN register (0F1H D0). At the same time, the oscillation circuit also turns on. At first, the circuit of the reference resistance side (RS) is operated by the oscillation control circuit. Then, the circuit of the sensor side (TH) turns on when counting by the oscillation clock of the reference resistance is terminated. Each circuit performs the same oscillating operation as follows: The Tr1 (Tr2) turns on first, and the condenser connected between the CS and VSS terminals is charged through the reference resistance (sensor). If the voltage level of the CS terminal decreases, the Tr1 (Tr2) turns off and the Tr3 turns on. As a result, the condenser becomes discharged, and oscillation is performed according to CR time constant. The time constant changes as the sensor resistance value fluctuates, producing a difference from the oscillation frequency of the reference resistance. Oscillation waveforms are shaped by the Schmitt trigger and transmitted to counter. The clock transmitted to the counter is also output from the ADOUT terminal. As a result, oscillation frequency can be identified by the oscilloscope. Since this monitor has no effect on oscillation frequency, it can be used to adjust CR oscillation frequency. Oscillation waveforms and waveforms output from the ADOUT terminal are shown in Figure 4.8.2. VDD CS terminal Fig. 4.8.2 Oscillation waveforms S1C62N51 TECHNICAL HARDWARE VSS VDD ADOUT VSS EPSON I-43 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) (3) Counter The A/D converter incorporates two types of 16-bit counters. One is the up-counter C0-C15 that counts the aforementioned oscillation clock, and the other is up/ down counter TC0-TC15 that counts the internal clock for reference counting. Each counter permits reading and writing on a 4-bit basis. The input unit of the up/down counter TC0-TC15 incorporates a multiplying circuit so that either the OSC1 clock (Typ. 32.768 kHz) or its multiplication clock (Typ. 65.536 kHz) can be selected as an input clock. When A/D conversion is initiated by the ADRUN register, oscillation by the reference resistance begins first, and the up-counter C0-C15 starts counting up according to the oscillation clock. At the same time, the up/down counter TC0-TC15 starts counting up. Timing in starting oscillation and starting counting up are shown in Figure 4.8.3. The up-counter becomes ENABLE at the falling edge of the first clock after CR oscillation is initiated and starts counting up from the falling edge of the next clock. The up/down counter becomes ENABLE at the falling edge of the internal clock which is input immediately after the first CR oscillation clock has fallen. Then, it starts counting up from the falling edge of the next internal clock. ADRUN register CS terminal ADOUT Up-counter enable Start Up-counter (C0) Clock (Up/down counter) Fig. 4.8.3 Counting up start timing I-44 Up/down counter enable Start Up/down counter (TC0) EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) If the up-counter C0-C15 becomes "0000H" due to overflow, the sensor side of the oscillation circuit turns on, and the up-counter starts counting up according to the oscillation clock on the sensor side. The up/down counter TC0-TC15 shifts to the countingdown mode at this point and starts counting down from the value measured as a result of oscillation by the reference resistance. Timing in starting counting when oscillation is switched, is same as Figure 4.8.3. When the up/down counter TC0-TC15 has counted down to "0000H", the counting operation of both counters and CR oscillation stops, and an interrupt occurs. At the same time, the ADRUN register is set to "0", and the A/D converter circuit stops operation completely. The sensor is oscillated for the same period of time as the reference resistance is oscillated after the up/down counter TC0-TC15 is set to "0000H" prior to A/D conversion. Therefore, the difference in oscillation frequency can be measured from the values counted by the up-counter C0-C15. Since the reference resistance is oscillated until the upcounter C0-C15 overflows, an appropriate initial value needs to be set before A/D conversion is started. If a smaller initial value is set, a longer counting period is possible, thereby ensuring more accurate detection. Likewise, if the input clock of the up/down counter TC0- TC15 is set at 65 kHz, the degree of precision is reduced. However, since CR oscillation frequency is normally set lower than the clock frequency of the up/down counter TC0-TC15 to ensure accurate measurement, the up/ down counter TC0-TC15 may overflow while counting the oscillation frequency of the reference resistance. If an overflow occurs, CR oscillation and A/D conversion is terminated immediately. Also in such cases, the up/ down counter indicates "0000H", and interrupt occurs. However, it is impossible to judge whether the interrupt has occurred due to an overflow or normal termination. S1C62N51 TECHNICAL HARDWARE EPSON I-45 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Note that correct measurement is impossible if an overflow occurs. The initial value to be set depends on the measurable range by the sensor or where to set the reference resistance value within that range. The initial value must be set taking the above into consideration. Convert the initial value into a complement (value subtracted from 0000H) before setting it on the up-counter C0-C15. Since the data output from the up-counter C0- C15 after A/D conversion matches data detected by the sensor, process the difference between that value and the initial value before it is converted into a complement according to the program and calculate the target value. The above operations are shown in Figure 4.8.4. Setting by software Up-counter (C0-C15) Up/down counter (TC0-TC15) (1) Set the initial value (0000H-n) (0000H-n) (2) Start A/D conversion (Set "1" on the ADRUN) Count up Count up FFFFH : 0 x 0 x Count up Count down : 0001H m 0000H 0000H 0000H (3) Read the up-counter and process the m-n value acoording to the program Set the complement of the initial value n on the up-counter Set "0000H" on the up /down counter Oscillation by reference resistance Switch CR oscillation when the up-counter overflows and shift the up/down counter to the counting-down mode Oscillation by sensor When the value of the up/down counter reaches 0000H, oscillation and conting stops, and an interruption occurs. Fig. 4.8.4 Sequence of A/D conversion I-46 Note - Set the initial value of the up-counter C0-C15 taking into account the measurable range and the overflow of the up/down counter TC0-TC15. - If the up/down counter TC0-TC15 is measured after A/D conversion, it may not indicate "0000H". This is not due to incorrect timing in terminating A/D conversion but because the counting down clock is input after the control signal is output to the up-counter to terminate counting. EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Interrupt function The A/D converter has a function which allows interrupt to occur after A/D conversion. When the up/down counter TC0-TC15 is counted down to "0000H", both counters stop counting. The interrupt factor flag IAD is set to "1" at the falling edge of the next clock. If the up/down counter TC0-TC15 overflow during countingup operation, the interrupt factor flag is set to "1" at the rising edge of the clock immediately after the counter reaches "0000H". This interrupt factor allows masking by the interrupt mask register EIAD. If the EIAD is set at "1", an interrupt occurs in the CPU. If the EIAD is set at "0", the interrupt factor flag is set to "1". However, no interrupt will occur in the CPU. The interrupt factor flag is reset to "0" by a reading operation. Timing of interrupt by the A/D converter is shown in Figure 4.8.5. ADRUN register ADOUT Up-counter data n n+1 n+2 FFFE FFFF 0 1 2 m-1 m Up/down counter clock Up/down counter data 0 1 2 3 x-3 x-2 x-1 x x-1 x-2 x-3 3 2 1 0 Interrupt Oscillation with reference resistor Fig. 4.8.5 Oscillation with sensor Timing of A/D converter interrupt Usage example of the A/D converter Temperature measurement is possible with the A/D converter in which a thermistor is used as a sensor. Elements to be connected and counter setting in the case of temperature measurement are as follows: Example: S1C62N51 TECHNICAL HARDWARE Temperature measurement at -20C to 70C Reference resistance ....... 49.8 k thermistor ....................... 50 k Oscillating condenser ...... 2,200 pF EPSON I-47 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) When the above elements are connected, the oscillation frequency of the reference resistance becomes about 10 kHz, and the oscillation frequency of the thermistor varies within the range of about 1 kHz to 50 kHz at -20C to 70C. Reference resistance is adjusted to the thermistor resistance value at 25C. In addition, Figure 4.8.6 indicates the resistance and oscillation frequency ratio TYP at the time of A/D conversion. 5.0 Oscillation frequency ratio Resistance and oscillation frequency ratio of A/D conversion circuit For 50 k , set the oscillation frequency to 1. 1.0 0.1 10 k 50 k Fig. 4.8.6 Resistance and oscillation 100 k Resistance value 500 k ( ) frequency ratio I-48 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Table 4.8.2 shows the A/D converter control bits and their addresses. Control of A/D converter Table 4.8.2 Control bits of clock timer Address D3 Register D2 D1 D0 TC3 TC2 TC1 TC0 TC5 TC4 TC9 TC8 TC13 TC12 C1 C0 C5 C4 C9 C8 C13 C12 0 ADRUN 0E4H R/W TC7 TC6 0E5H R/W TC11 TC10 0E6H R/W TC15 TC14 0E7H R/W C3 C2 0F5H R/W C7 C6 0F6H R/W C11 C10 0F7H R/W C15 C14 0F8H R/W 0 0 0F1H R 0 R/W 0 0 ADCLK 0FEH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 0F0H R IAD Name TC3 TC2 TC1 TC0 TC7 TC6 TC5 TC4 TC11 TC10 TC9 TC8 TC15 TC14 TC13 TC12 C3 C2 C1 C0 C7 C6 C5 C4 C11 C10 C9 C8 C15 C14 C13 C12 0 0 0 ADRUN 0 0 0 ADCLK 0 0 0 EIAD 0 0 0 IAD *1 Initial value following initial reset *2 Not set in the circuit *3 Undefined S1C62N51 TECHNICAL HARDWARE Init *1 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Comment Up/down counter data TC3 Up/down counter data TC2 Up/down counter data TC1 Up/down counter data TC0 (LSB) Up/down counter data TC7 Up/down counter data TC6 Up/down counter data TC5 Up/down counter data TC4 Up/down counter data TC11 Up/down counter data TC10 Up/down counter data TC9 Up/down counter data TC8 Up/down counter data TC15 (MSB) Up/down counter data TC14 Up/down counter data TC13 Up/down counter data TC12 Up-counter data C3 Up-counter data C2 Up-counter data C1 Up-counter data C0 (LSB) Up-counter data C7 Up-counter data C6 Up-counter data C5 Up-counter data C4 Up-counter data C11 Up-counter data C10 Up-counter data C9 Up-counter data C8 Up-counter data C15 (MSB) Up-counter data C14 Up-counter data C13 Up-counter data C12 *5 *5 *5 Start 0 Stop A/D conversion Start/Stop *5 *5 *5 65 kHz 0 32 kHz A/D clock selection 65 kHz/32 kHz *5 *5 *5 Enable 0 Mask Interrupt mask register (A/D) *5 *5 *5 Yes 0 No Interrupt factor flag (A/D) *4 *4 Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual EPSON I-49 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) TC0-TC15 Up/down counter (0E4H-0E7H) Writing and reading is possible on a 4-bit basis by the up/ down counter that is used to adjust the CR oscillation time between the reference resistance and the variable resistance elements. The up/down counter counts up during oscillation of the reference resistance and counts down from the value it reached when counting up to "0000H" during oscillation of the sensor. "0000H" needs to be entered in the counter prior to A/D conversion in order to adjust the counting time of both counts. After an initial reset, data in this counter become indefinite. C0-C15 Up-counter (0F5H-0F8H) This counter counts up according to the CR oscillation clock. It permits writing and reading on a 4-bit basis. The complement of the number of clocks to be counted by the oscillation of the reference resistance, must be entered in this counter prior to A/D conversion. If A/D conversion is initiated, the counter counts up from the set initial value, first according to the oscillation clock of the reference resistance. When the counter reaches "0000H" due to overflow, the oscillation of the reference resistance stops, and the sensor starts oscillating. The counter continues counting according to the sensor oscillation clock. Counting time during the oscillation of the reference resistance is calculated by the up/down counter TC0-TC15. Upcounter C0-C15 stops counting when the same period of time elapses. Difference from the reference resistance can be evaluated from the value indicated by the counter when it stops. Calculate the target value by processing the above difference according to the program. Measurable range and the overflow of the up/down counter TC0-TC15 must be taken into account when setting an initial value to be entered prior to A/D conversion. After an initial reset, data in this counter become indefinite. I-50 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) ADCLK Input clock selection (0FEH D0) Select the input clock of the up/down counter TC0-TC15. When "1" is written: When "0" is written: Reading: 65 kHz 32 kHz Valid Select the output clock of the multiplying circuit for the counting operation of the up/down counter TC0-TC15. When "1" is written in the ADCLK, 65 kHz, a multitude of the OSC1 clock is selected. When "0" is written, the OSC1 clock is selected at 32 kHz. If 65 kHz is selected, A/D conversion becomes more accurate. However, the initial value must be set on the upcounter C0-C15 so that the up/down counter TC0-TC15 will not overflow while CR oscillation is being counted. After an initial reset, ADCLK is set to "0". ADRUN A/D conversion START/STOP (0F1H D0) Start A/D conversion. When "1" is written: When "0" is written: Reading: A/D conversion starts A/D conversion stops Valid When "1" is written in the ADRUN, A/D conversion begins. The register remains at "1" during A/D conversion and is set to "0" when A/D conversion is terminated. When "0" is written in the ADRUN during A/D conversion, A/D conversion is paused. ADRUN is set to "0" at initial reset, when the up/down counter overflows or when measurement is finished. EIAD Interrupt mask register (0ECH D0) Select whether to mask interrupt with the A/D converter. When "1" is written: When "0" is written: Reading: Enable Mask Valid The A/D converter interrupt is permitted when "1" is written in the EIAD. When "0" is written, interrupt is masked. After an initial reset, this register is set to "0". S1C62N51 TECHNICAL HARDWARE EPSON I-51 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) IAD Interrupt factor flag (0F0H D0) This flag indicates interrupt caused by the A/D converter. When "1" is read: When "0" is read: Writing: Interrupt has occurred Interrupt has not occurred Invalid IAD is set to "1" when A/D conversion is terminated (when the up/down counter counted up or down to "0000H"). From the status of this flag, the software can decide whether an A/D converter interrupt has occurred. This flag is reset when the software has read it. Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. After an initial reset, this flag is set to "0". I-52 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) 4.9 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function Configuration of SVD circuit and heavy load protection function The S1C62N51 Series have a built-in supply voltage detection (SVD) circuit and a heavy load protection function. Figure 4.9.1 shows the configuration of the circuit. SVD circuit The SVD circuit monitors the conditions of the supply voltage (battery voltage), and software can check whether the supply voltage has dropped below the detecting voltage level of the SVD circuit: 2.4 V when supply voltage is 3.0 V (S1C62N51), or 1.2 V when supply voltage is 1.5 V (S1C62L51). Registers SVDON (SVD control on/off) and SVDDT (SVD data) are used for the SVD circuit. The software can turn SVD operation on and off. When SVD is on, the IC draws a large current, so keep SVD off unless it is. Since supply voltage detection is automatically performed by the hardware every 2 Hz (0.5 sec) when the heavy load protection function operates, do not permit the operation of the SVD circuit by the software in order to minimize power current consumption. Heavy load protection function Note that the heavy load protection function on the S1C62L51 is different from the S1C62N51. (1) In case of S1C62L51 The S1C62L51 has the heavy load protection function for when the battery load becomes heavy and the source voltage drops, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. In this mode, operation with a lower voltage than normal is possible. The normal mode changes to the heavy load protection mode in the following two cases: When the software changes the mode to the heavy load protection mode (HLMOD = "1") When supply voltage drop (SVDDT = "1") in the SVD circuit is detected, the mode will automatically shift to the heavy load protection mode until the supply voltage is recovered (SVTDT = "0") S1C62N51 TECHNICAL HARDWARE EPSON I-53 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal driver source output VL2 so as to operate the internal circuit. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Also, to reduce current consumption, do not set the SVDON to ON in the heavy load protection mode. (2) In case of S1C62N51 The S1C62N51 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. Compared with the normal operation mode, this mode can reduce the output voltage variation of the constant voltage/booster voltage circuit of the LCD system. The normal mode changes to the heavy load protection mode in the following case: * When the software changes the mode to the heavy load protection mode (HLMOD = "1") The heavy load protection mode switches the constant voltage circuit of the LCD system to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Note that in S1C62L51, the range of operating pressure differs during CR oscillation and during crystal oscillation. Regurated voltage circuit VS1 V L1 Vss Fig. 4.9.1 Configuration of SVD and SVD sampling control Vss SVDDT SVDON heavy load protection circuits I-54 Address 0FAH HLMOD EPSON D3 D1 D0 Data bus SVD circuit S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Operation of SVD detection timing The following explains the timing when the SVD circuit writes the result of supply voltage detection to the SVDDT register. The result of supply voltage detection is written to the SVDDT register by the SVD circuit, and this data can be read by the software to determine the supply voltage. There are two methods, explained below, for executing the detection by the SVD circuit. (1) Sampling with HLMOD set to "1" When HLMOD is set to "1" and SVD sampling is executed, the detection results can be written to the SVDDT register with the following timing: Immediately after sampling with the 2 Hz cycle output by the oscillation circuit while HLMOD = "1" (sampling time is 122 s in the case of fosc = 32,768 Hz). Consequently, after HLMOD has been set to "1", the new detection result is written in a 2 Hz. (2) Sampling with SVDON set to "1" When SVDON is set to "1", SVD detection is executed. As soon as SVDON is reset to "0", the result is loaded to in the SVDDT register. To obtain a stable SVD detection result, the SVD circuit must be on for at least 100 s. So, to obtain the SVD detection result, follow the programming sequence below. Set SVDON to "1" Maintain for 100 s minimum Set SVDON to "0" Read SVDDT However, at 32 kHz for the S1C62N51 and S1C62L51, the instruction cycles are long enough, so there is no need to worry about maintaining 100 s for SVDON = "1" in the software. Notice that even if the SVD circuit detects a drop in the supply voltage (1.2 V/2.4 V or less) and invokes the heavy load protection mode, this will be the same as when the software invokes the heavy load protection mode, in that the SVD circuit will be sampled with a timing synchronized to the 2 Hz output from the prescaler. If the SVD circuit detects a voltage drop and enters the heavy load protection mode, it will return to the normal mode once the supply voltage recovers and the SVD circuit determines that the supply voltage is 1.2 V/2.4 V or more. S1C62N51 TECHNICAL HARDWARE EPSON I-55 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Operation of heavy load protection function The S1C62N51 has a heavy load protection function for when the battery load becomes heavy and the supply voltage drops, such as when a melody is played or an external lamp lights. This functions works in the heavy load protection mode. (1) In cace of S1C62L51 The normal mode changes to the heavy load protection mode in the following two cases: When the software changes the mode to the heavy load protection mode When the SVD circuit detects a supply voltage less than 1.2 V, in which case the mode is automatically changed to the heavy load protection mode (2) In case of S1C62N51 The normal mode changes to the heavy load protection mode in the following case: * When the software changes the mode to the heavy load protection mode (HLMOD = "1") Based on the operation of the SVD circuit and the heavy load protection function, the S1C62L51 obtains an operation supply voltage as low as 0.9 V. See the electrical characteristics for the precision of voltage detection by the SVD circuit. In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal driver supply output, VL2, in order to operate the internal circuit (S1C62L51). Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless necessary, do not select the heavy load protection mode with the software. Note Activation of the SVD circuit by software in the heavy load protection mode causes a malfunction. Avoid such activation if possible. I-56 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Table 4.9.1 shows the control bits and their addresses for the SVD circuit and the heavy load protection function. Control of SVD circuit and heavy load protection function Table 4.9.1 Control bits for SVD circuit and heavy load protection function Address D3 HLMOD Register D2 D1 0 SVDDT D0 SVDON 0FAH R/W *1 *2 *3 *4 *5 *6 R R/W Name HLMOD 0 SVDDT SVDON Init *1 0 Comment 1 Heavy 0 Normal Heavy load protection mode register Low On Normal Off Supply voltage detection data Supply voltage detection circuit On/Off *5 0 0 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual HLMOD Heavy load protection mode on/off (0FAH D3) When "1" is written: When "0" is written: Reading: Heavy load protection mode on Heavy load protection mode off Valid When HLMOD is set to "1", the IC enters the heavy load protection mode, and sampling control is executed for the time the SVD circuit is on. The sampling timing is as follows: Sampling in cycles of 2 Hz output by the oscillation circuit while HLMOD = "1" (sampling time is 122 s in the case of fosc = 32,768 Hz). When SVD sampling is done with HLMOD set to "1", the results are written to the SVDDT register with the as following timing: Immediately on completion of sampling in cycles of 2 Hz output by the oscillation circuit while HLMOD = "1". Consequently, after HLMOD is set to "1", the new detected result is written in 2 Hz. In the heavy load protection mode, the consumed current becomes larger. Unless necessary, do not select the heavy load protection mode with the software. S1C62N51 TECHNICAL HARDWARE EPSON I-57 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) SVDON SVD control on/off (0FAH D0) When "0" is written: When "1" is written: Reading: SVD detection off SVD detection on Valid When this bit is written, the SVD detection on/off operation is controlled. Large current is drawn during SVD detection, so keep SVD detection off except when necessary. When SVDON is set to "1", SVD detection is executed. As soon as SVDON is reset to "0", the detected result is loaded into the SVDDT register. SVDDT SVD data (0FAH D1) When "0" is read: When "1" is read: Supply voltage Criteria voltage Supply voltage < Criteria voltage When SVDDT is "1", the S1C62N51 enters the heavy load protection mode. In this mode, the detection operation of the SVD circuit is sampled in 2 Hz cycles and the respective detection results are written to the SVDDT register. I-58 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.10 Interrupt and HALT The S1C62N51 Series provide the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input interrupt (one) Timer interrupt (one) A/D converter interrupt (one) To enable interrupts, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask registers must be set to "1" (enable). When an interrupt occurs, the interrupt flag is automatically reset to "0" (DI) and interrupts after that are inhibited. When a HALT instruction is input, the CPU operating clock stops and the CPU enters the halt state. The CPU is reactivated from the halt state when an interrupt request occurs. Figure 4.10.1 shows the configuration of the interrupt circuit. Interrupt vector (MSB) K00 : EIK00 : K01 (LSB) Program counter of CPU (three low-order bits) EIK01 IK0 INT (Interrupt request) K02 EIK02 Interrupt flag K03 EIK03 IAD EIAD IT2 Interrupt factor flag EIT2 IT8 Interrupt mask register EIT8 IT32 EIT32 Fig. 4.10.1 Configuration of interrupt circuit S1C62N51 TECHNICAL HARDWARE EPSON I-59 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.10.1 shows the factors that generate interrupt requests. Interrupt factors The interrupt factor flags are set to "1" depending on the corresponding interrupt factors. The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to "1". * The corresponding mask register is "1" (enabled) * The interrupt flag is "1" (EI) The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read. After an initial reset, the interrupt factor flags are reset to "0". Note Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. Table 4.10.1 Interrupt factors Interrupt factor IT2 (0EFH D2) Colck timer 8 Hz falling edge IT8 (0EFH D1) Colck timer 32 Hz falling edge IT32 (0EFH D0) IAD (0F0H D0) IK0 (0EDH D0) A/D converter A/D conversion completion Input data (K00-K03) Rising edge I-60 Interrrupt factor flag Colck timer 2 Hz falling edge EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Specific masks and factor flags for interrupt Table 4.10.2 Interrupt mask registers and interrupt factor flags The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt enabled) when "1" is written to them, and masked (interrupt disabled) when "0" is written to them. After an initial reset, the interrupt mask register is set to "0". Table 4.10.2 shows the correspondence between interrupt mask registers and interrupt factor flags. Interrupt mask register Interrrupt factor flag EIT2 (0EBH D2) IT2 (0EFH D2) EIT8 (0EBH D1) IT8 (0EFH D1) EIT32 (0EBH D0) IT32 (0EFH D0) EIAD (0ECH D0) IAD (0F0H D0) EIK03* (0E8H D3) EIK02* (0E8H D2) EIK01* (0E8H D1) IK0 (0EDH D0) EIK00* (0E8H D0) * There is an interrupt mask register for each input port pin. When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is suspended, interrupt processing is executed in the following order: Interrupt vectors The address data (value of the program counter) of the program step to be executed next is saved on the stack (RAM). The interrupt request causes the value of the interrupt vector (page 1, 01H-07H) to be loaded into the program counter. The program at the specified address is executed (execution of interrupt processing routine). Note The processing in steps 1 and 2, above, takes 12 cycles of the CPU system clock. S1C62N51 TECHNICAL HARDWARE EPSON I-61 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.10.4 shows the interrupt control bits and their addresses. Control of interrupt Table 4.10.4 Interrupt control bits Address D3 EIK03 Register D2 D1 EIK02 EIK01 D0 EIK00 0E8H R/W 0 EIT2 EIT8 EIT32 0EBH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 IK0 0EDH R 0 IT2 IT8 IT32 0EFH R 0 0 0 0F0H R *1 *2 *3 *4 *5 *6 IAD Name EIK03 EIK02 EIK01 EIK00 0 EIT2 EIT8 EIT32 0 0 0 EIAD 0 0 0 IK0 0 IT2 IT8 IT32 0 0 0 IAD Init *1 0 0 0 0 Comment 1 Enable Enable Enable Enable 0 Mask Mask Mask Mask Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz *5 0 0 0 *5 *5 *5 0 Enable Mask Interrupt mask register (A/D) *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) 0 0 0 Yes Yes Yes No No No Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *5 *4 *4 *4 *5 *5 *5 0 Yes No Interrupt factor flag (A/D) *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0-D2) IT32, IT8, IT2 Interrupt factor flags (0EFH D0-D2) See 4.7, "Clock Timer". EIAD Interrupt mask register (0ECH D0) IAD Interrupt factor flag (0F0H D0) See 4.8, "A/D Converter". EIK00-EIK03 Interrupt mask registers (0E8H) IK0 Interrupt factor flag (0EDH D0) See 4.3, "Input Ports". I-62 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM (1) Piezo Buzzer Single Terminal Driving COM3 I COM0 K00 SEG25 SEG0 LCD PANEL K03 P00 I/O P03 CA CB CC V L1 V L2 V L3 V DD OSC1 S1C62N51/62L51 OSC2 V S1 RESET R00 R02 R03 R01 CS TH TEST RS O C2 C3 C4 C5 CG X'tal C6 1.5V or 3.0V Cp Vss Piezo Buzzer R1 R2 CAD S1C62N51 TECHNICAL HARDWARE C1 Coil X'tal Crystal oscillator 32,768 Hz CG Trimmer capacitor 5-25 pF C1-C6 Capacitor 0.1 F Cp Capacitor 3.3 F R2 Thermistor 50 k R1 Resistor 49.8 k CAD Capacitor 2,200 pF EPSON CI(MAX) = 35 k I-63 CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM (2) Piezo Buzzer Direct Driving COM3 COM0 K00 I SEG25 SEG0 LCD PANEL CA CB CC V L1 V L2 V L3 K03 P00 I/O P03 V DD OSC1 S1C62N51/62L51 OSC2 V S1 RESET R02 R03 C4 C5 CG X'tal C6 1.5V or 3.0V Cp Vss R00 R01 CS TH TEST RS O C1 C2 C3 R1 R2 CAD I-64 Piezo Buzzer X'tal Crystal oscillator 32,768 Hz CG Trimmer capacitor 5-25 pF C1-C6 Capacitor 0.1 F Cp Capacitor 3.3 F R2 Thermistor 50 k R1 Resistor 49.8 k CAD Capacitor 2,200 pF EPSON CI(MAX) = 35 k S1C62N51 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating S1C62N51 (VDD =0V) Item Symbol Rated value Unit Power voltage VSS -5.0 to 0.5 V Input voltage (1) VI Vss-0.3 to 0.5 V Input voltage (2) VIOSC Vss-0.3 to 0.5 V Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Tsol 260C, 10sec (lead section) - PD 250 mW Soldering temperature / Time Allowable dissipation *1 *1 In case of QFP6-64 pin plastic package S1C62L51 (VDD =0V) Item Symbol Rated value Unit Power voltage VSS -5.0 to 0.5 V Input voltage (1) VI Vss-0.3 to 0.5 V Input voltage (2) VIOSC Vss-0.3 to 0.5 V Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Tsol 260C, 10sec (lead section) - PD 250 mW Soldering temperature / Time Allowable dissipation *1 *1 In case of QFP6-64 pin plastic package S1C62N51 TECHNICAL HARDWARE EPSON I-65 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.2 Recommended Operating Conditions S1C62N51 Item Power voltage Oscillation frequency Oscillation frequency Booster capacitor (1) Booster capacitor (2) Capacitor between VDD and VL1 Capacitor between VDD and VL2 Capacitor between VDD and VL3 Capacitor between VDD and VS1 Symbol VSS fOSC1 fOSC1 fOSC2 C1 C2 C3 C4 C5 C6 Condition VDD=0V Crystal oscillation Crystal oscillation CR oscillation, R=420k Min -3.5 Typ -3.0 32,768 32,768 65 0.1 0.1 0.1 0.1 0.1 0.1 (Ta=-20 to 70C) Max Unit -1.8 V Hz Hz 80 kHz F F F F F F S1C62L51 Item Power voltage Oscillation frequency Oscillation frequency Booster capacitor (1) Booster capacitor (2) Capacitor between VDD and VL1 Capacitor between VDD and VL2 Capacitor between VDD and VL3 Capacitor between VDD and VS1 Symbol Condition VSS VDD=0V *3 VDD=0V, With software correspondence *1 fOSC1 Crystal oscillation fOSC1 Crystal oscillation fOSC2 CR oscillation, R=420k C1 C2 C3 C4 C5 C6 Min -2.0 -2.0 Typ -1.5 -1.5 32,768 32,768 65 0.1 0.1 0.1 0.1 0.1 0.1 (Ta=-20 to 70C) Max Unit -1.1 V -0.9 *2 V 80 Hz Hz kHz F F F F F F *1 When switching to the heavy load protection mode. The SVD circuit is turned OFF. (For details, refer to Section 4.9). *2 The voltage which can be displayed on the LCD panel will differ according to the characteristics of the LCD panel. *3 When there is no software correspondence during CR oscillation or crystal oscillation. I-66 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics S1C62N51 Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F Item Symbol Condition High level input voltage (1) VIH1 K00-K03, P00-P03 High level input voltage (2) VIH2 RESET, TEST Low level input voltage (1) K00~K03, P00-P03 VIL1 Low level input voltage (2) RESET, TEST VIL2 High level input current (1) K00-K03, P00-P03 IIH1 VIH1=0V Without pull down resistor High level input current (2) K00-K03 IIH2 VIH2=0V With pull down resistor High level input current (3) P00-P03 IIH3 VIH3=0V RESET, TEST With pull down resistor Low level input current K00-K03, P00-P03 VIL=VSS IIL RESET, TEST High level output current (1) IOH1 VOH1=0.1*VSS R02, R03, P00-P03 High level output current (2) IOH2 VOH2=0.1*VSS R00, R01 (built-in protection resistance) High level output current (3) IOH3 VOH3=-1.0V ADOUT Low level output current (1) IOL1 VOL1=0.9*VSS R02, R03, P00-P03 Low level output current (2) IOL2 VOL2=0.9*VSS R00, R01 (built-in protection resistance) Low level output current (3) IOL3 VOL3=-2.0V ADOUT Common output current COM0-COM3 IOH4 VOH4=-0.05V IOL4 VOL4=VL3+0.05V Segment output current SEG0-SEG25 IOH5 VOH5=-0.05V (during LCD output) IOL5 VOL5=VL3+0.05V Segment output current SEG0-SEG25 IOH6 VOH6=0.1*VSS (during DC output) IOL6 VOL6=0.9*VSS S1C62N51 TECHNICAL HARDWARE EPSON Max Typ Unit Min 0 0.2*Vss V 0 0.15*Vss V 0.8*Vss V Vss 0.85*Vss V Vss 0.5 A 0 5 16 A 30 100 A -0.5 0 A -1.0 -1.0 mA mA -100 3.0 3.0 -10 A mA mA 10 100 -3 A A A A A A A 3 -3 3 -300 300 I-67 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C62L51 Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F Item Symbol Condition High level input voltage (1) VIH1 K00-K03, P00-P03 High level input voltage (2) VIH2 RESET, TEST Low level input voltage (1) K00~K03, P00-P03 VIL1 Low level input voltage (2) RESET, TEST VIL2 High level input current (1) K00-K03, P00-P03 IIH1 VIH1=0V Without pull down resistor High level input current (2) K00-K03 IIH2 VIH2=0V With pull down resistor High level input current (3) P00-P03 IIH3 VIH3=0V RESET, TEST With pull down resistor Low level input current K00-K03, P00-P03 VIL=VSS IIL RESET, TEST High level output current (1) IOH1 VOH1=0.1*VSS R02, R03, P00-P03 High level output current (2) IOH2 VOH2=0.1*VSS R00, R01 (built-in protection resistance) High level output current (3) IOH3 VOH3=-1.5V ADOUT Low level output current (1) IOL1 VOL1=0.9*VSS R02, R03, P00-P03 Low level output current (2) IOL2 VOL2=0.9*VSS R00, R01 (built-in protection resistance) Low level output current (3) IOL3 VOL3=-1.0V ADOUT Common output current COM0-COM3 IOH4 VOH4=-0.05V IOL4 VOL4=VL3+0.05V Segment output current SEG0-SEG25 IOH5 VOH5=-0.05V (during LCD output) IOL5 VOL5=VL3+0.05V Segment output current SEG0-SEG25 IOH6 VOH6=0.1*VSS (during DC output) IOL6 VOL6=0.9*VSS I-68 EPSON Max Typ Unit Min 0 V 0.2*Vss 0 0.15*Vss V 0.8*Vss V Vss 0.85*Vss V Vss 0.5 0 A 2.0 16 A 9.0 100 A -0.5 0 A -200 -200 A A -100 700 700 -10 A A A 10 100 -3 A A A A A A A 3 -3 3 -100 130 S1C62N51 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Analog Circuit Characteristics and Power Current Consumption S1C62N51 (Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F (During A/D conversion: R1=49.8 k, R2=50 k, CAD=2,200 pF) Item Internal voltage Symbol Condition VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 VL3 (without panel load) VSVD SVD voltage SVD circuit response time tSVD Current consumption IOP Min -1.15 Typ -1.05 Max -0.95 2*VL1 2*VL1 -0.1 x 0.9 3*VL1 3*VL1 -0.1 x 0.9 -2.55 -2.40 -2.25 100 2.5 During HALT 1.0 5.0 During execution *1 Without panel load 2.5 40 30 During A/D conversion (HALT) Unit V V V V s A A A *1 The SVD circuit is turned OFF. S1C62N51 (Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F (During A/D conversion: R1=49.8 k, R2=50 k, CAD=2,200 pF) Symbol Min Typ Max Unit Condition V VL1 Connect 1M load resistor between VDD and VL1 -1.15 -1.05 -0.95 (without panel load) 2*VL1 V Connect 1M load resistor between VDD and VL2 2*VL1 VL2 (without panel load) -0.1 x 0.85 Connect 1M load resistor between VDD and VL3 3*VL1 3*VL1 V VL3 (without panel load) -0.1 x 0.85 V -2.55 -2.40 -2.25 SVD voltage VSVD 100 s SVD circuit response time tSVD 5.5 A Current consumption IOP During HALT 2.0 10.0 A During execution *1 Without panel load 5.5 41.5 A 31 During A/D conversion (HALT) Item Internal voltage *1 The SVD circuit is turned OFF. S1C62N51 TECHNICAL HARDWARE EPSON I-69 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C62L51 (Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F (During A/D conversion: R1=49.8 k, R2=50 k, CAD=2,200 pF) Symbol Min Typ Max Unit Condition V VL1 Connect 1M load resistor between VDD and VL1 -1.15 -1.05 -0.95 (without panel load) 2*VL1 V Connect 1M load resistor between VDD and VL2 2*VL1 VL2 (without panel load) -0.1 x 0.9 Connect 1M load resistor between VDD and VL3 3*VL1 3*VL1 V VL3 (without panel load) -0.1 x 0.9 -1.30 -1.20 -1.10 V SVD voltage VSVD 100 s SVD circuit response time tSVD 2.5 A Current consumption IOP During HALT 1.0 5.0 A During execution *1 Without panel load 2.5 40 A 30 During A/D conversion (HALT) Item Internal voltage *1 The SVD circuit is turned OFF. S1C62L51 (Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F (During A/D conversion: R1=49.8 k, R2=50 k, CAD=2,200 pF) Item Internal voltage Symbol Condition VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 VL3 (without panel load) VSVD SVD voltage SVD circuit response time tSVD Current consumption IOP During HALT During execution *1 Without panel load During A/D conversion (HALT) Min -1.15 Typ -1.05 2*VL1 -0.1 3*VL1 -0.1 -1.30 -1.20 2.0 5.5 31 Max -0.95 Unit V 2*VL1 V x 0.85 3*VL1 V x 0.85 -1.10 100 5.5 10.0 41.5 V s A A A *1 The SVD circuit is turned OFF. I-70 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C62N51 (CR, Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F, Recommended external resistance for CR oscillation = 420 k (During A/D conversion: R1=49.8 k, R2=50 k, CAD=2,200 pF) Item Internal voltage Symbol Condition VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 VL3 (without panel load) VSVD SVD voltage SVD circuit response time tSVD Current consumption IOP Min -1.15 Typ -1.05 Max -0.95 2*VL1 2*VL1 -0.1 x 0.9 3*VL1 3*VL1 -0.1 x 0.9 -2.55 -2.40 -2.25 100 15.0 During HALT 8.0 During execution *1 Without panel load 15.0 20.0 52.5 37 During A/D conversion (HALT) Unit V V V V s A A A *1 The SVD circuit is turned OFF. S1C62N51 (CR, Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F, Recommended external resistance for CR oscillation = 420 k (During A/D conversion: R1=49.8 k, R2=50 k, CAD=2,200 pF) Item Internal voltage Symbol Condition VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 VL3 (without panel load) VSVD 2*VL1 -0.1 3*VL1 -0.1 -2.55 -2.40 During HALT During execution *1 Without panel load During A/D conversion (HALT) 16.0 30.0 45 SVD voltage SVD circuit response time tSVD Current consumption IOP Min -1.15 Typ -1.05 Max -0.95 Unit V 2*VL1 V x 0.85 3*VL1 V x 0.85 -2.25 100 30.0 40.0 57.5 V s A A A *1 The SVD circuit is turned OFF. S1C62N51 TECHNICAL HARDWARE EPSON I-71 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C62L51 (CR, Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F, Recommended external resistance for CR oscillation = 420 k (During A/D conversion: R1=49.8 k, R2=50 k, CAD=2,200 pF) Symbol Min Typ Max Unit Condition V VL1 Connect 1M load resistor between VDD and VL1 -1.15 -1.05 -0.95 (without panel load) 2*VL1 V Connect 1M load resistor between VDD and VL2 2*VL1 VL2 (without panel load) -0.1 x 0.9 Connect 1M load resistor between VDD and VL3 3*VL1 3*VL1 V VL3 (without panel load) -0.1 x 0.9 -1.30 -1.20 -1.10 V SVD voltage VSVD 100 s SVD circuit response time tSVD A 15.0 Current consumption IOP During HALT 8.0 A During execution *1 Without panel load 15.0 20.0 52.5 A 37 During A/D conversion (HALT) Item Internal voltage *1 The SVD circuit is turned OFF. S1C62L51 (CR, Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 F, Recommended external resistance for CR oscillation = 420 k (During A/D conversion: R1=49.8 k, R2=50 k, CAD=2,200 pF) Item Internal voltage Symbol Condition VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 VL3 (without panel load) VSVD 2*VL1 -0.1 3*VL1 -0.1 -1.30 -1.20 During HALT During execution *1 Without panel load During A/D conversion (HALT) 16.0 30.0 45 SVD voltage SVD circuit response time tSVD Current consumption IOP Min -1.15 Typ -1.05 Max -0.95 Unit V 2*VL1 V x 0.85 3*VL1 V x 0.85 -1.10 100 30.0 40.0 57.5 V s A A A *1 The SVD circuit is turned OFF. I-72 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.5 Oscillation Characteristics Oscillation characteristics will vary according to different conditions. Use the following characteristics are as reference values. S1C62N51 Unless otherwise specified VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25C Symbol Vsta (Vss) Vstp Oscillation stop voltage (Vss) CD Built-in capacity (drain) Frequency voltage deviation f/V f/IC Frequency IC deviation Frequency adjustment range f/CG Higher harmonic oscillation Vhho start voltage (Vss) Allowable leak resistance Rleak Item Oscillation start voltage tsta5sec Condition Min -1.8 tstp10sec -1.8 Typ 5 10 -10 40 -3.5 Between OSC1 and VDD, and between VSS and OSC1 Unit V V 20 Including the parasitic capacity inside the IC Vss=-1.8 to -3.5V CG=5-25pF CG=5pF Max pF ppm ppm ppm V M 200 S1C62L51 Unless otherwise specified VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25C Symbol Vsta (Vss) Vstp Oscillation stop voltage (Vss) CD Built-in capacity (drain) Frequency voltage deviation f/V f/IC Frequency IC deviation Frequency adjustment range f/CG Higher harmonic oscillation Vhho start voltage (Vss) Allowable leak resistance Rleak Item Oscillation start voltage Condition tsta5sec tstp10sec Min -1.1 Typ Max V -1.1 (-0.9)*1 20 Including the parasitic capacity inside the IC Vss=-1.1 to -2.0V (-0.9) *1 -10 40 CG=5-25pF CG=5pF 5 10 -2.0 Between OSC1 and VDD, and between VSS and OSC1 Unit V 200 pF ppm ppm ppm V M *1 Items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. S1C62N51 TECHNICAL HARDWARE EPSON I-73 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C62N51 (CR) Unless otherwise specified VDD=0 V, VSS=-3.0 V, RCR=420 k, Ta=25C Symbol Item Condition Min fosc Oscillation frequency dispersion -20 Vsta Oscillation start voltage -1.8 Oscillation start time tsta Vss=-1.8 to -3.5V Oscillation stop voltage Vstp -1.8 Typ 65kHz Max 20 Unit % V ms V Max 20 Unit % V ms V 3 S1C62L51 (CR) Unless otherwise specified VDD=0 V, VSS=-1.5 V, RCR=420 k, Ta=25C Symbol Item Condition Min fosc Oscillation frequency dispersion -20 Vsta Oscillation start voltage -1.1 Oscillation start time tsta Vss=-1.1 to -2.0V Oscillation stop voltage Vstp -1.1 I-74 EPSON Typ 65kHz 3 S1C62N51 TECHNICAL HARDWARE CHAPTER 7: PACKAGE CHAPTER 7 PACKAGE 7.1 Plastic Package QFP6-64 pin 16.8 14.0 0.4 0.2 48 33 16.8 14.0 0.4 32 0.2 49 Index 64 17 1 16 2.7 0.1 0.35 0.15 0.15 0.05 0.8 0.15 0~12 0.6 0.3 1.4 S1C62N51 TECHNICAL HARDWARE EPSON I-75 CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples QFP6-60 pin 17.6 14.0 0.3 0.2 30 60 16 14.0 0.2 46 0.3 31 1 15 0.15 0.35 0.15 2.7 0.2 0.8 1.0 0.15 0.05 17.6 45 5 5 0.7 0.2 1.8 I-76 EPSON S1C62N51 TECHNICAL HARDWARE CHAPTER 8: PAD LAYOUT CHAPTER 8 PAD LAYOUT 8.1 Diagram of Pad Layout DIE No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 59 58 16 57 17 56 18 55 19 20 21 Y 54 22 52 24 (0, 0) 25 X 3.93 mm 53 23 26 27 51 28 50 49 29 48 30 47 46 31 32 33 34 35 36 37 38 39 40 41 42 43 45 44 3.58 mm S1C62N51 TECHNICAL HARDWARE EPSON I-77 CHAPTER 8: PAD LAYOUT 8.2 Pad Coordinates Pad No Pad name 1 COM3 2 SEG0 3 X Y Pad No Pad name X Y 1,340.4 1,808.4 31 P00 -1,584.8 -1,808.0 745.2 1,808.4 32 P01 -1,424.0 -1,808.0 SEG1 585.2 1,808.4 33 P02 -1,260.8 -1,808.0 4 SEG2 425.2 1,808.4 34 P03 -1,100.0 -1,808.0 5 SEG3 265.2 1,808.4 35 RESET -904.4 -1,808.0 6 SEG4 105.2 1,808.4 36 K00 -744.8 -1,808.0 7 SEG5 -54.8 1,808.4 37 K01 -579.2 -1,808.0 8 SEG6 -214.8 1,808.4 38 K02 -418.4 -1,808.0 9 SEG7 -374.8 1,808.4 39 K03 -252.8 -1,808.0 10 SEG8 -534.8 1,808.4 40 R00 -17.2 -1,808.0 11 SEG9 -694.8 1,808.4 41 R01 282.8 -1,808.0 12 SEG10 -854.8 1,808.4 42 R02 508.8 -1,808.0 13 SEG11 -1,014.8 1,808.4 43 R03 668.4 -1,808.0 14 SEG12 -1,174.8 1,808.4 44 CS 1,630.4 -1,784.8 15 TEST -1,630.8 1,612.4 45 RS 1,630.4 -1,624.8 16 SEG13 -1,630.8 1,367.6 46 TH 1,630.4 -1,464.8 17 SEG14 -1,630.8 1,207.6 47 18 SEG15 -1,630.8 1,047.6 48 VDD 19 SEG16 -1,630.8 887.6 49 OSC1 1,630.4 -787.2 20 SEG17 -1,630.8 727.6 50 OSC2 1,630.4 -627.6 21 SEG18 -1,630.8 567.6 51 V SS 1,630.4 -467.6 22 SEG19 -1,630.8 407.6 52 CA 1,630.4 175.6 23 SEG20 -1,630.8 247.6 53 CB 1,630.4 335.6 24 SEG21 -1,630.8 87.6 54 CC 1,630.4 495.6 25 SEG22 -1,630.8 -152.8 55 V L1 1,630.4 954.4 26 SEG23 -1,630.8 -312.8 56 V L2 1,630.4 1,114.4 27 SEG24 -1,630.8 -472.8 57 V L3 1,630.4 1,274.4 28 SEG25 -1,630.8 -632.8 58 COM0 1,630.4 1,434.0 ADOUT 1,630.4 -1,264.8 1,630.4 -1,014.8 29 VDD -1,630.8 -933.6 59 COM1 1,630.4 1,595.6 30 V S1 -1,630.8 -1,093.2 60 COM2 1,630.4 1,755.2 Chip size X: 3.58 (mm) Y: 3.93 (mm) I-78 EPSON S1C62N51 TECHNICAL HARDWARE Software II. S1C62N51 Technical Software CONTENTS CONTENTS CHAPTER 2 CHAPTER 3 CONFIGURATION ........................................................... II-1 1.1 S1C62N51 Block Diagram ............................................. II-1 1.2 ROM Map ....................................................................... II-2 1.3 Interrupt Vectors ............................................................. II-3 1.4 Data Memory Map .......................................................... II-4 INITIAL RESET ................................................................... II-7 2.1 Internal Register Status on Initial Reset ......................... II-7 2.2 Initialize Program Example ............................................. II-9 PERIPHERAL CIRCUITS .................................................... II-11 3.1 Input Ports ..................................................................... II-11 Input port memory map .......................................... II-11 Control of the input port ......................................... II-12 Examples of input port control program .................. II-12 3.2 Output Ports .................................................................. II-14 Output port memory map ........................................ II-14 Control of the output port ....................................... II-14 Examples of output port control program ................ II-14 3.3 Special Use Output Ports .............................................. II-16 Special use output port memory map ...................... II-16 Control of the special use output port ..................... II-16 Examples of special use output port control program . II-17 S1C62N51 TECHNICAL SOFTWARE EPSON II-i Software CHAPTER 1 CONTENTS 3.4 I/O Ports ........................................................................ II-19 I/O port memory map ............................................. II-19 Control of the I/O port ............................................ II-19 Examples of I/O port control program ..................... II-20 3.5 LCD Driver ..................................................................... II-23 LCD driver memory map ......................................... II-23 Control of the LCD driver ........................................ II-23 Examples of LCD driver control program ................. II-25 3.6 Timer ............................................................................. II-27 Timer memory map ................................................. II-27 Control of the timer ................................................. II-28 Examples of timer control program .......................... II-29 3.7 A/D Converter ................................................................ II-31 A/D converter memory map .................................... II-31 Control of the A/D converter ................................... II-32 Examples of A/D converter control program ............ II-35 3.8 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function ............................ II-48 SVD circuit and heavy load protection function memory map ............................................. Control of the SVD circuit ....................................... Example of SVD circuit control program .................. Heavy load protection function ................................ Examples of heavy load protection function control program ......................................... 3.9 II-48 II-49 II-49 II-50 II-52 Interrupt and Halt ........................................................... II-55 Interrupt memory map ............................................ II-55 Control of interrupts and halt ................................. II-56 Examples of interrupt and halt control program ...... II-63 II-ii EPSON S1C62N51 TECHNICAL SOFTWARE CONTENTS SUMMARY OF PROGRAMMING POINTS....................... II-66 APPENDIX A Table of Instructions ...................................................... II-70 B RAM Map ...................................................................... II-75 C Table of the ICE Commands ......................................... II-77 D Cross-assembler Pseudo-instruction List ...................... II-79 Software CHAPTER 4 S1C62N51 TECHNICAL SOFTWARE EPSON II-iii CHAPTER 1: CONFIGURATION CHAPTER 1 CONFIGURATION ROM 1,024 words x 12 bits RESET OSC1 OSC2 1.1 S1C62N51 Block Diagram OSC System Reset Control Core CPU S1C6200A RAM 80 words x 4 bits COM0-3 SEG0-25 Interrupt Generator LCD Driver VDD VL1-3 CA-CC VS1 VSS Power Controller SVD Input Port Test Port K00-03 I/O Port P00-03 Output Port R00-03 Timer FOUT / BUZZER BUZZER TEST Fout & Buzzer A/D Converter ADOUT RS TH CS Fig. 1.1.1 S1C62N51 block diagram S1C62N51 TECHNICAL SOFTWARE EPSON II-1 CHAPTER 1: CONFIGURATION 1.2 ROM Map The S1C62N51 has a built-in mask ROM with a capacity of 1,024 steps x 12 bits for program storage. The configuration of the ROM is shown in Figure 1.2.1. Bank 0 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 07H step 08H step Program area FFH step Fig. 1.2.1 Configuration of built-in ROM II-2 12 bits EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 1: CONFIGURATION 1.3 Interrupt Vectors When an interrupt request is received by the CPU, the CPU initiates the following interrupt processing after completing the instruction being executed. (1) The address of the next instruction to be executed (the value of the program counter) is saved on the stack (RAM). (2) The interrupt vector address corresponding to the interrupt request is loaded into the program counter. (3) The branch instruction written in the vector is executed to branch to the software interrupt processing routine. Note Steps 1 and 2 require 12 cycles of the CPU system clock. The interrupt vectors are shown in Table 1.3.1. Table 1.3.1 Page Interrupt requests and vectors 1 Step Interrupt vector 00H Initial reset 01H Clock timer interrupt 02H A/D interrupt 03H Clock timer interrupt and A/D interrupt 04H Input (K00-K03) interrupt 05H Input interrupt and clock timer interrupt 06H Input interrupt and A/D interrupt 07H Generation of all interrupt Addresses (start address of interrupt processing routines) to jump to are written into the addresses available for interrupt vector allocation. S1C62N51 TECHNICAL SOFTWARE EPSON II-3 CHAPTER 1: CONFIGURATION 1.4 Data Memory Map The S1C62N51 built-in RAM has 80 words of data memory, 32 words of display memory for the LCD, and I/O memory for controlling the peripheral circuit. When writing programs, note the following: (1) Since the stack area is in the data memory area, take care not to overwrite the stack with data. Subroutine calls or interrupts use 3 words on the stack. (2) Data memory addresses 000H-00FH are memory register areas that are addressed with register pointer RP. Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 RAM area (000H-04FH) 80 words x 4 bits (R/W) 3 4 5 6 0 7 8 Display memory area (090H-0AFH) 32 words x 4 bits (Write only) 9 A B C D E F I/O memory area Table 4.1.1(a), (b) Fig. 1.4.1 Data memory map Unused area Note Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. II-4 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 1: CONFIGURATION Table 1.4.1(a) I/O memory map 1 D3 Register D2 D1 D0 K03 K02 K01 K00 TM1 TM0 TC1 TC0 TC5 TC4 TC9 TC8 TC13 TC12 EIK01 EIK00 Address 0E0H R TM3 TM2 0E3H R TC3 TC2 0E4H R/W TC7 TC6 0E5H R/W TC11 TC10 0E6H R/W TC15 TC14 0E7H R/W EIK03 EIK02 0E8H R/W 0 EIT2 EIT8 EIT32 0EBH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 IK0 0EDH R 0 IT2 IT8 0EFH R *1 *2 *3 *4 *5 *6 IT32 Name K03 K02 K01 K00 TM3 TM2 TM1 TM0 TC3 TC2 TC1 TC0 TC7 TC6 TC5 TC4 TC11 TC10 TC9 TC8 TC15 TC14 TC13 TC12 EIK03 EIK02 EIK01 EIK00 0 EIT2 EIT8 EIT32 0 0 0 EIAD 0 0 0 IK0 0 IT2 IT8 IT32 Init *1 - *2 - *2 - *2 - *2 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 0 0 0 0 Comment 1 High High High High High High High High 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 Low Low Low Low Low Low Low Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mask Mask Mask Mask Input port data K03 Input port data K02 Input port data K01 Input port data K00 Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz Up/down counter data TC3 Up/down counter data TC2 Up/down counter data TC1 Up/down counter data TC0 (LSB) Up/down counter data TC7 Up/down counter data TC6 Up/down counter data TC5 Up/down counter data TC4 Up/down counter data TC11 Up/down counter data TC10 Up/down counter data TC9 Up/down counter data TC8 Up/down counter data TC15 (MSB) Up/down counter data TC14 Up/down counter data TC13 Up/down counter data TC12 Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz *5 0 0 0 *5 *5 *5 0 Enable Mask Interrupt mask register (A/D) *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) 0 0 0 Yes Yes Yes No No No Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *5 *4 *4 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual S1C62N51 TECHNICAL SOFTWARE EPSON II-5 CHAPTER 1: CONFIGURATION Table 1.4.1(b) I/O memory map 2 Address D3 0 Register D2 D1 0 D0 0 IAD 0F0H R 0 0 0 ADRUN 0F1H R R03 R/W R01 R00 BUZZER FOUT R02 0F3H R/W P03 P02 P00 P01 0F4H R/W C3 C2 C0 C1 0F5H R/W C7 C6 C4 C5 0F6H R/W C11 C10 C8 C9 0F7H R/W C15 C14 C12 C13 0F8H R/W 0 0 0 TMRST 0F9H R HLMOD W 0 SVDDT SVDON 0FAH R/W CSDC R/W R 0 0 0 0FBH R/W 0 R 0 0 IOC 0FCH R XBZR 0 R/W XFOUT1 XFOUT0 0FDH R/W R 0 0 R/W 0 ADCLK 0FEH R II-6 R/W Name 0 0 0 IAD 0 0 0 ADRUN R03 R02 R01 BUZZER R00 FOUT P03 P02 P01 P00 C3 C2 C1 C0 C7 C6 C5 C4 C11 C10 C9 C8 C15 C14 C13 C12 0 0 0 TMRST HLMOD 0 SVDDT SVDON CSDC 0 0 0 0 0 0 IOC XBZR 0 XFOUT1 XFOUT0 0 0 0 ADCLK Init *1 1 0 Comment *5 *5 *5 Yes 0 No Interrupt factor flag (A/D) *4 *5 *5 *5 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - - - - - *2 *2 *2 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 Start High High High On High On High High High High 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Stop Low Low Low Off Low Off Low Low Low Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A/D conversion Start/Stop Output port data R03 Output port data R02 Output port data R01 Buzzer On/Off control register Output port data R00 Frequency output control register I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 Up-counter data C3 Up-counter data C2 Up-counter data C1 Up-counter data C0 (LSB) Up-counter data C7 Up-counter data C6 Up-counter data C5 Up-counter data C4 Up-counter data C11 Up-counter data C10 Up-counter data C9 Up-counter data C8 Up-counter data C15 (MSB) Up-counter data C14 Up-counter data C13 Up-counter data C12 *5 *5 *5 Reset 0 Reset Heavy - Normal Clock timer reset Heavy load protection mode register 0 0 0 Low On Static Normal Off Dynamic Supply voltage detection data Supply voltage detection circuit On/Off LCD drive switch *5 *5 *5 *5 *5 *5 *5 *5 0 0 Out 2 kHz In 4 kHz I/O port I/O control register Buzzer frequency control *5 FOUT frequency control FOUT frequency control 0 0 *6 *6 *5 *5 *5 0 EPSON 65 kHz 32 kHz A/D clock selection 65 kHz/32 kHz S1C62N51 TECHNICAL SOFTWARE CHAPTER 2: INITIAL RESET CHAPTER 2 INITIAL RESET 2.1 Internal Register Status on Initial Reset Following an initial reset, the internal registers and internal data memory area are initialized to the values shown in Tables 2.1.1 and 2.1.2. Table 2.1.1 Initial values of internal registers Table 2.1.2 Initial values of internal data memory area S1C62N51 TECHNICAL SOFTWARE Internal register Program counter step Program counter page New page pointer Stack pointer Index register Index register Register pointer General register General register Interrupt flag Decimal flag Zero flag Carry flag Internal data memory area Bit length Initial value following reset 8 4 4 8 8 8 4 4 4 1 1 1 1 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined PCS PCP NPP SP X Y RP A B I D Z C Bit length RAM data Display memory Internal I/O register EPSON Initial value following reset 4 x 80 Undefined 4 x 32 Undefined See Tables 1.4.1(a) and (b) Address 000H-04FH 090H-0AFH 0E0H-0FEH II-7 CHAPTER 2: INITIAL RESET After an initial reset, the program counter page (PCP) is initialized to 1H, and the program counter step (PCS), to 00H. This is why the program is executed from step 00H of the first page. The initial values of some internal registers and internal data memory area locations are undefined after a reset. Set them as necessary to the proper initial values in the program. The peripheral I/O functions (memory-mapped I/O) are assigned to internal data memory area addresses 0E0H to 0FEH. Each address represents a 4-bit internal I/O register, allowing access to the peripheral functions in 1-word (4-bit) read/write units. II-8 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 2: INITIAL RESET 2.2 Initialize Program Example The following is a program that clears the RAM, LCD, Up/ down counter and Up-counter, resets the flags, registers and timer, and sets the stack pointer immediately after resetting the system. Label Mnemonic/operand Comment ORG JP 100H INIT ;Jump to "INIT" ORG RST 110H F,0011B LD LDPX CP JP LD LDPX CP JP X,0 MX,0 XH,5H NZ,RAMCLR X,90H MX,0 XH,0BH NZ,LCDCLR ; ; ; ; ; ; ; ; LD LD LD LD A,0 B,4 SPL,A SPH,B ; ; ; ; Set stack pointer to 40H LD OR X,0F9H MX,0001B ; ; Reset clock timer X,0E4H MX,0 XL,8H NZ,UDCNTCLR X,0F5H MX,0 XL,9H NZ,UCLR ; ; ; ; ; ; ; ; X,0EBH MX,0111B ; ; Enable timer interrupt X,0E8H MX,1111B ; ; Enable input interrupt (K03-K00) X,0 Y,0 A,0 B,0 F,0 ; ; ; Reset register flags ; ; ;Enable interrupt ; INIT ;Interrupt mask, decimal ;adjustment off ; RAMCLR LCDCLR Clear RAM (00H-4FH) Clear LCD (90H-AFH) ; ; ; LD UDCNTCLR LDPX CP JP LD UCLR LDPX CP JP ; LD OR ; LD OR ; LD LD LD LD RST EI S1C62N51 TECHNICAL SOFTWARE EPSON Clear Up/down counter (0E4H-0E7H) Clear Up-counter (0F5H-0F8H) II-9 CHAPTER 2: INITIAL RESET The above program is a basic initialization program for the S1C62N51. Figure 2.2.1 is the flow chart for this program. The setting data are all initialized as shown in the flow chart by executing this program. When using this program, add setting items necessary for each specific application. Initialization Reset I (Interrupt flag) D (Decimal adjustment flag) Clear RAM Set SP I : Interrupt flag D : Decimal adjustment flag Clear data RAM (00H to 04FH) Clear segment RAM (90H to 0AFH) Set stack pointer to 40H Reset clock timer Clear Up/down counter, Up-counter Enable timer interrupt Enable timer interrupt 2 Hz, 8 Hz, 32 Hz Enable input interrupt Enable K03-K00 input port interrupt Reset registers (X, Y, A, B) flags (I, Z, D, C) EI (enable interrupt) Fig. 2.2.1 Flow chart of the initialization To next process program II-10 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) CHAPTER 3 PERIPHERAL CIRCUITS Details on how to control the S1C62N51 peripheral circuit is given in this chapter. 3.1 Input Ports Input port memory map Table 3.1.1 I/O memory map Address D3 K03 Register D2 D1 D0 K01 K00 EIK01 EIK00 K02 0E0H R EIK03 EIK02 0E8H R/W 0 0 0 0EDH R *1 *2 *3 *4 *5 *6 IK0 Name K03 K02 K01 K00 EIK03 EIK02 EIK01 EIK00 0 0 0 IK0 Init *1 - *2 - *2 - *2 - *2 0 0 0 0 1 High High High High Enable Enable Enable Enable 0 Low Low Low Low Mask Mask Mask Mask Comment Input port data K03 Input port data K02 Input port data K01 Input port data K00 Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual S1C62N51 TECHNICAL SOFTWARE EPSON II-11 CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) The S1C62N51 has one 4-bit input port (K00-K03). Input port data can be read as a 4-bit unit (K00-K03). Control of the input port The state of the input ports can be obtained by reading the data (bits D3, D2, D1, D0) of address 0E0H. The input ports can be used to send an interrupt request to the CPU via the input interrupt condition flag. See Section 3.9 "Interrupt and Halt", for details. Examples of input port control program * Loading K00-K03 into the A register Label Mnemonic/operand Comment LD LD ;Set address of port ;A register K00-K03 Y,0E0H A,MY As shown in Figure 3.1.1, the two instruction steps above load the data of the input port into the A register. A register D3 D2 D1 D0 K03 K02 K01 K00 Fig. 3.1.1 Loading the A register The data of the input port can be loaded into the B register or MX instead of the A register. II-12 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) * Bit-unit checking of input ports Label Mnemonic/operand DI LD INPUT1: FAN JP INPUT2: FAN JP Y,0E0H MY,0010B NZ,INPUT1 MY,0010B Z,INPUT2 Comment ;Disable interrupt ;Set address of port ; ;Loop until K01 becomes "0" ; ;Loop until K01 becomes "1" This program loopes until a rising edge is input to input port K01. The input port can be addressed using the X register instead of the Y register. Note When the input port is changed from high level to low level with a pull-down resistor, the signal falls following a certain delay caused by the time constants of the pull-down resistance and the input gate capacitance. It is therefore necessary to observe a proper wait time before the input port data is read. S1C62N51 TECHNICAL SOFTWARE EPSON II-13 CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports) 3.2 Output Ports Output port memory map Table 3.2.1 I/O memory map Address D3 Register D2 D1 D0 R01 R00 R03 R02 BUZZER FOUT 0F3H R/W *1 *2 *3 *4 *5 *6 Name R03 R02 R01 BUZZER R00 FOUT Init *1 0 0 0 0 0 0 1 High High High On High On 0 Low Low Low Off Low Off Comment Output port data R03 Output port data R02 Output port data R01 Buzzer On/Off control register Output port data R00 Frequency output control register Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual Control of the output port The S1C62N51 has 4 bits for general output ports (R00- R03). R00 and R01 although can be use for special use output port as shown in later of this section. The output port is a read/write register, output pins provide the contents of the register. The states of the output ports (R00- R03) are decided by the data of address 0F3H. Output ports can also be read, and output control is possible using the operation instructions (AND, OR, etc.). The output ports are all initialized to low level (0) after an initial reset. Examples of output port control program * Loading B register data into R00-R03 Label Mnemonic/operand Comment LD LD ;Set address of port ;R00-R03 B register Y,0F3H MY,B As shown in Figure 3.2.1, the two instruction steps above load the data of the B register into the output ports. II-14 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports) B register D3 D2 D1 D0 Fig. 3.2.1 Data register R00 Data register R01 Data register R02 Data register R03 Control of the output port The output data can be taken from the A register, MX, or immediate data instead of the B register. * Bit-unit operation of output ports Label Mnemonic/operand Comment LD OR AND ;Set address of port ;Set R01 to 1 ;Set R02 to 0 Y,0F3H MY,0010B MY,1011B The three instruction steps above cause the output port to be set, as shown in Figure 3.2.2. Address 0F3H D3 R03 D2 R02 D1 R01 D0 R00 No change Sets "1" Sets "0" No change Fig. 3.2.2 Setting of the output port S1C62N51 TECHNICAL SOFTWARE EPSON II-15 CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) 3.3 Special Use Output Ports Special use output port memory map Table 3.3.1 I/O memory map Address D3 R03 0F3H XBZR 0FDH R/W *1 *2 *3 *4 *5 *6 Register D2 D1 Name R03 R00 R01 R02 R02 BUZZER FOUT R01 BUZZER R/W R00 FOUT XBZR 0 XFOUT1 XFOUT0 0 XFOUT1 R R/W XFOUT0 1 High High High On High On 2 kHz 0 Low Low Low Off Low Off 4 kHz Comment Output port data R03 Output port data R02 Output port data R01 Buzzer On/Off control register Output port data R00 Frequency output control register Buzzer frequency control *5 FOUT frequency control FOUT frequency control 0 0 *6 *6 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual Control of the special use output port Table 3.3.2 Special output II-16 Init *1 0 0 0 0 0 0 0 D0 In addition to the regular DC, special output can be selected for output ports R00 and R01, as shown in Table 3.3.2. Figure 3.3.1 shows the structure of output ports R00-R03. Pin name When special output is selected R00 FOUT or BUZZER R01 BUZZER EPSON S1C62N51 TECHNICAL SOFTWARE Data bus CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) Register (R03) R03 Register (R02) R02 BUZZER Register (R01) R01 BUZZER Register (R00) Fig. 3.3.1 Structure of output ports R00-R03 Examples of special use output port control program FOUT Address (0F3H) Mask option * Buzzer driver output (BUZZER) When output port R01 is set for BUZZER and R00 is set for BUZZER, it performs 2,048 Hz or 4,096 Hz selected by register XBZR (0FDH D3). Label S1C62N51 TECHNICAL SOFTWARE R00 Mnemonic/operand Comment LD Y,0FDH LD LD OR : AND MY,1000B Y,0F3H MY,0010B : MY,1101B ;Set address of BUZZER ;frequency control register ;Select 2,048 Hz ;Set address of output port ;Turn on BUZZER EPSON ;Turn off BUZZER II-17 CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) * Internal divided frequency output (FOUT) When output port R00 is set to FOUT output, fosc or clock frequency divided into fosc is generated. Clock frequency may be selected individually for F1-F4, from among 5 types by mask option; a clock frequency is then selected from 4 types (i.e., F1-F4) through XFOUT0 and XFOUT1 (0FDH D0 and D1) registers and is generated. The clock frequency types are shown in Table 3.3.3. Table 3.3.3 Mask option and register selection Mask option sets Clock frequency (Hz) fosc = 32,768 F1 F2 F3 F4 (D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1) Set 1 256 (fosc/128) 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) Set 2 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) Set 3 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) Set 4 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) Set 5 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 32,768 (fosc/1) For example mask option is set to Set 4: Label II-18 Mnemonic/operand Comment LD Y,0FDH LD LD OR : AND MY,0011B Y,0F3H MY,0001B : MY,1110B ;Set address of FOUT ;frequency control register ;Select 16,384 Hz ;Set address of output port ;Turn on FOUT EPSON ;Turn off FOUT S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) 3.4 I/O Ports I/O port memory map Table 3.4.1 I/O memory map Address D3 Register D2 D1 D0 P03 P02 P01 P00 0 IOC 0F4H R/W 0 0 0FCH R *1 *2 *3 *4 *5 *6 R/W Name P03 P02 P01 P00 0 0 0 IOC Init *1 - *2 - *2 - *2 - *2 1 High High High High 0 Low Low Low Low Comment I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 *5 *5 *5 0 Out In I/O port I/O control register Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual Control of the I/O port The S1C62N51 contains a 4-bit general I/O port (4 bits x 1). This port can be used as an input port or an output port, according to I/O port control register IOC. When IOC is "0", the port is set for input, when it is "1", the port is set for output. * How to set an input port Set "0" in the I/O port control register (D0 of address 0FCH), and the I/O port is set as an input port. The state of the I/O port (P00-P03) is decided by the data of address 0F4H. (In the input mode, the port level is read directly.) S1C62N51 TECHNICAL SOFTWARE EPSON II-19 CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) * How to set an output port Set "1" in the I/O port control register, and the I/O port is set as an output port. The state of the I/O port is decided by the data of address 0F4H. This data is held by the register, and can be set regardless of the contents of the I/O control register. (The data can be set whether P00 to P03 ports are input ports or output ports.) The I/O control registers are cleared to "0" (input/output ports are set as input ports), and the data registers are also cleared to "0" after an initial reset. Examples of I/O port * Loading P00-P03 input data into A register control program Label Mnemonic/operand Comment LD AND LD LD ;Set address of I/O control port ;Set port as input port ;Set address of port ;A regiser P00-P03 Y,0FCH MY,1110B Y,0F4H A,MY As shown in Figure 3.4.1, the four instruction steps above load the data of the I/O ports into the A register. A register Fig. 3.4.1 D3 D2 D1 D0 P03 P02 P01 P00 Loading into the A register II-20 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) * Loading P00-P03 output data into A register Label Mnemonic/operand Comment LD Y,0FCH OR LD LD MY,0001B Y,0F4H A,MY ;Set the address of input/output ;port control register ;Set as output port ;Set the address of port ;A register P00-P03 As shown in Figure 3.4.2, the four instruction steps above load the data of the I/O ports into the A register. A register D3 D2 D1 D0 P03 P02 P01 P00 Fig. 3.4.2 Control of I/O port (input) Data register P00 Data register P01 Data register P02 Data register P03 Data can be loaded from the I/O port into the B register or MX instead of the A register. S1C62N51 TECHNICAL SOFTWARE EPSON II-21 CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) * Loading contents of B register into P00-P03 Label Mnemonic/operand Comment LD Y,0FCH OR LD LD MY,0001B Y,0F4H MY,B ;Set the address of input/output ;port control register ;Set port as output port ;Set the address of port ;P00-P03 B register As shown in Figure 3.4.3, the four instruction steps above load the data of the B register into the I/O ports. B register D3 D2 Fig. 3.4.3 D1 D0 Data register P00 Data register P01 Data register P02 Data register P03 Control of the I/O port (output) The output data can be taken from the A register, MX, or immediate data instead of the B register. Bit-unit operation for the I/O port is identical to that for the input ports (K00-K03) or output ports (R00-R03). II-22 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) 3.5 LCD Driver LCD driver memory map Table 3.5.1 I/O memory map Address D3 CSDC Register D2 D1 0 D0 0 0 0FBH R/W *1 *2 *3 *4 *5 *6 R Init *1 0 Name CSDC 0 0 0 1 Static 0 Dynamic Comment LCD drive switch *5 *5 *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual Address Fig. 3.5.1 090 Display memory map 0A0 Control of the LCD driver S1C62N51 TECHNICAL SOFTWARE 0 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (write only) 32 words x 4 bits The S1C62N51 contains 128 bits of display memory in addresses 090H to 0AFH of the data memory. Each display memory can be assigned to any 104 bits of the 128 bits for the LCD driver (26 SEG x 4 COM), 78 bits of the 128 bits (26 SEG x 3 COM) or 52 bits of the 128 bits (26 SEG x 2 COM) by using a mask option. The remaining 24 bits, 50 bits or 76 bits of display memory are not connected to the LCD driver, and are not output even when data is written. An LCD segment is on with "1" set in the display memory, and off with "0" set in the display memory. Note that the display memory is a write-only. EPSON II-23 CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) * LCD drive control register (CSDC) The LCD drive control register (CSDC: address 0FBH, D3) can be set either for dynamic drive or for static drive. Set "0" in CSDC for 1/2, 1/3 or 1/4 duty (time-shared) dynamic drive. Set "1" in CSDC and the same value in the registers corresponding to COM0 to COM1 (1/2), COM0 to COM2 (1/ 3) or COM0 to COM3 (1/4) for static drive. Figure 3.5.2 is the static drive control of the LCD, and Figure 3.5.3 is an example of the 7-segment LCD assignment. LCD lighting status -V DD -V L1 -V L2 -V L3 COM 0-3 COM0 COM1 COM2 COM3 SEG0-25 Frame frequency Not lit -V DD -V L1 -V L2 -V L3 Lit SEG 0-25 -V DD -V L1 -V L2 -V L3 Fig. 3.5.2 LCD static drive control a f b g Address 090H e c 091H Register D3 D2 D1 D0 d c g b f a e Fig. 3.5.3 7-segment LCD assignment d In the assignment shown in Figure 3.5.3, the 7-segment display pattern is controlled by writing data to display memory addresses 090H and 091H. II-24 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) Examples of LCD driver control program * Displaying 7-segment The LCD display routine using the assignment of Figure 3.5.3 can be programmed as follows. Label Mnemonic/operand Comment ORG RETD RETD RETD RETD RETD RETD RETD RETD RETD RETD 000H 3FH 06H 5BH 4FH 66H 6DH 7DH 27H 7FH 6FH ;0 is displayed ;1 is displayed ;2 is displayed ;3 is displayed ;4 is displayed ;5 is displayed ;6 is displayed ;7 is displayed ;8 is displayed ;9 is displayed B,0 X,090H ;Set the address of jump ;Set address of display memory SEVENS: LD LD JPBA When the above routine is called (by the CALL or CALZ instruction) with any number from "0" to "9" set in the A register for the assignment of Figure 3.5.4, seven segments are displayed according to the contents of the A register. Fig. 3.5.4 Data set in A register and displayed patterns A register Display A register Display A register Display A register Display A register 0 2 4 6 8 1 3 5 7 9 Display The RETD instruction can be used to write data to the display memory only if it is addressed using the X register. (Addressing using the Y register is invalid.) Note that the stack pointer must be set to a proper value before the CALL (CALZ) instruction is executed. S1C62N51 TECHNICAL SOFTWARE EPSON II-25 CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) * Bit-unit operation of the display memory Address Fig. 3.5.5 Example of segment assignment Data D3 D2 090H Label D1 D0 : SEG-A : SEG-B Mnemonic/operand Comment LD X,SEGBUF LD LD LD AND LD AND LD Y,090H MX,3 MY,MX MX,1110B MY,MX MX,1101B MY,MX ;Set address display ;memory buffer ;Set address display memory ;Set buffer data ;SEG-A, B ON ( , ) ;Change buffer data ;SEG-B OFF ( ,) ;Change buffer data ;SEG-A OFF (,) For manipulation of the display memory in bit-units for the assignment of Figure 3.5.5, a buffer must be provided in RAM to hold data. Note that, since the display memory is write-only, data cannot be changed directly using an ALU instruction (for example, AND or OR). After manipulating the data in the buffer, write it into the corresponding display memory using the transfer command. II-26 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Timer) 3.6 Timer Timer memory map Table 3.6.1 I/O memory map Address D3 TM3 Register D2 D1 TM2 D0 TM1 TM0 EIT8 EIT32 0E3H R 0 EIT2 0EBH R 0 R/W IT2 IT8 IT32 0EFH R 0 0 0 TMRST 0F9H R *1 *2 *3 *4 *5 *6 W Name TM3 TM2 TM1 TM0 0 EIT2 EIT8 EIT32 0 IT2 IT8 IT32 0 0 0 TMRST Init *1 - *3 - *3 - *3 - *3 Comment 1 High High High High 0 Low Low Low Low Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz 0 0 0 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz 0 0 0 Yes Yes Yes No No No *5 *5 Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *4 *4 *5 *5 *5 Reset Reset - Clock timer reset *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual S1C62N51 TECHNICAL SOFTWARE EPSON II-27 CHAPTER 3: PERIPHERAL CIRCUITS (Timer) Control of the timer Address 0E3H Register Frequency bits D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz The S1C62N51 contains a timer with a basic oscillation of 32.768 kHz (typical). This timer is a 4-bit binary counter, and the counter data can be read as necessary. The counter data of the 16 Hz clock can be read by reading TM3 to TM0 (address 0E3H, D3 to D0). ("1" to "0" are set in TM3 to TM0, corresponding to the high-low levels of the 2 Hz, 4 Hz, 8 Hz, and 16 Hz 50 % duty waveform. See Figure 3.6.1.) The timer can also interrupt the CPU on the falling edges of the 32 Hz, 8 Hz, and 2 Hz signals. For details, see Section 3.9, "Interrupt and Halt". Clock timer timing chart Occurrence of 32 Hz interrupt request Occurrence of 8 Hz interrupt request Occurrence of 2 Hz interrupt request Fig. 3.6.1 Output waveform of timer and interrupt timing The timer is reset by setting "1" in TMRST (address 0F9H, D0). Note The 128 Hz to 2 Hz of the internal divider is initialized by resetting the clock timer. II-28 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Timer) Examples of timer control program * Initializing the timer Label Mnemonic/operand Comment LD Y,0F9H OR MY,0001B ;Set address of the timer ;reset register ;Reset the timer The two instruction steps above are used to reset (clear TM0-TM3 to "0") and restart the timer. The TMRST register is cleared to "0" by hardware 1 clock after it is set to "1". * Loading the timer Label Mnemonic/operand Comment LD Y,0E3H LD A,MY ;Set address of ;the timer data (TM0 to TM3) ;Load the data of ;TM0 to TM3 into A register As shown in Table 3.6.2, the two instruction steps load the data of TM0 to TM3 into the A register. Table 3.6.2 Loading the timer data S1C62N51 TECHNICAL SOFTWARE A register D3 D2 TM3 (2 Hz) TM2 (4 Hz) EPSON D1 D0 TM1 (8 Hz) TM0 (16 Hz) II-29 CHAPTER 3: PERIPHERAL CIRCUITS (Timer) * Checking timer edge Label Mnemonic/operand Comment LD CP X,TMSTAT MX,0 JP LD LD Z,RETURN Y,0E3H A,MY LD XOR Y,TMDTBF MY,A FAN LD MX,0100B MY,A JP ADD Z,RETURN MX,0FH ;Set address of the timer edge counter ;Check whether the timer edge ;counter is "0" ;Jump if "0" (Z-flag is "1") ;Set address of the timer ;Read the data of TM0 to TM3 ;into A register ;Set address of the timer data buffer ;Did the count on the timer ;change? ;Check bit D2 of the timer data buffer ;Set the data of A register into ;the timer data buffer ;Jump, if the Z-flag is "1" ;Decrement the timer edge counter ; RETURN: RET ;Return This program takes a subroutine form. It is called at short intervals, and decrements the data at address TMSTAT every 125 ms until the data reaches "0". The timing chart is shown in Figure 3.6.2. The timer can be addressed using the X register instead of the Y register. Note TMSTAT and TMDTBF may be any address in RAM and not involve a hardware function. TM2 125 ms Fig. 3.6.2 Timing of the timer edge counter II-30 Timer edge counter (TMSTAT) decrementing timing EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) 3.7 A/D Converter A/D converter memory map Table 3.7.1 I/O memory map Address D3 TC3 Register D2 D1 TC2 D0 TC1 TC0 TC5 TC4 TC9 TC8 TC13 TC12 C1 C0 C5 C4 C9 C8 C13 C12 0 ADRUN 0E4H R/W TC7 TC6 0E5H R/W TC11 TC10 0E6H R/W TC15 TC14 0E7H R/W C3 C2 0F5H R/W C7 C6 0F6H R/W C11 C10 0F7H R/W C15 C14 0F8H R/W 0 0 0F1H R 0 R/W 0 0 ADCLK 0FEH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 0F0H R IAD Name TC3 TC2 TC1 TC0 TC7 TC6 TC5 TC4 TC11 TC10 TC9 TC8 TC15 TC14 TC13 TC12 C3 C2 C1 C0 C7 C6 C5 C4 C11 C10 C9 C8 C15 C14 C13 C12 0 0 0 ADRUN 0 0 0 ADCLK 0 0 0 EIAD 0 0 0 IAD *1 Initial value following initial reset *2 Not set in the circuit *3 Undefined S1C62N51 TECHNICAL SOFTWARE Init *1 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Comment Up/down counter data TC3 Up/down counter data TC2 Up/down counter data TC1 Up/down counter data TC0 (LSB) Up/down counter data TC7 Up/down counter data TC6 Up/down counter data TC5 Up/down counter data TC4 Up/down counter data TC11 Up/down counter data TC10 Up/down counter data TC9 Up/down counter data TC8 Up/down counter data TC15 (MSB) Up/down counter data TC14 Up/down counter data TC13 Up/down counter data TC12 Up-counter data C3 Up-counter data C2 Up-counter data C1 Up-counter data C0 (LSB) Up-counter data C7 Up-counter data C6 Up-counter data C5 Up-counter data C4 Up-counter data C11 Up-counter data C10 Up-counter data C9 Up-counter data C8 Up-counter data C15 (MSB) Up-counter data C14 Up-counter data C13 Up-counter data C12 *5 *5 *5 Start 0 Stop A/D conversion Start/Stop *5 *5 *5 65 kHz 0 32 kHz A/D clock selection 65 kHz/32 kHz *5 *5 *5 Enable 0 Mask Interrupt mask register (A/D) *5 *5 *5 Yes 0 *4 *5 *6 EPSON No Interrupt factor flag (A/D) *4 Reset (0) immediately after being read Always "0" when being read Refer to main manual II-31 CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) The S1C62N51 has a CR oscillation type A/D converter. This A/D converter is equipped with two CR oscillation circuit systems and a counter that measures their oscillation frequency. Counted values represent connected resistance values converted into digital values. Control of the A/D converter The A/D converter incorporates two types of 16-bit counters. One is the up-counter C0-C15 that counts the aforementioned oscillation clock, and the other is up/down counter TC0-TC15 that counts the internal clock for reference count. Each counter permits reading and writing on a 4-bit basis. Figure 3.7.1 shows the operation and control flow of A/D converter. Figure 3.7.2 shows the Timing chart of the A/D conversion. A/D conversion Reset the two counter memories Reset the up/down counter TC0-TC15 (0E4H-0E7H) and the up-counter C0-C15 (0F5H-0F8H) to "0000H" A Reset I (Interrupt) flag Up/down counter TC counts down A/D interrupt necessary ? NO YES Set the interrupt mask register to ENABLE Set an initial value in the up-counter C Start A/D conversion Up-counter C counts up Set the EIAD (0ECH D0) to "1" Set an initial value (complement) in the C0-C15 (0F5H-0F8H) NO Counter TC : 0 YES Both counter finish counting Set "1" in the ADRUN (0F1H D0) Set the interrupt factor flag IAD to "1" Up-counter C counts up Up/down counter TC counts up NO Is A/D interrupt set to ENABLE ? YES NO Counter C : 0 Interrupt process YES Read the C0-C15 (0F5H-0F8H) and process the measurement results END A Fig. 3.7.1 Control flow of A/D converter II-32 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) ADRUN register ADOUT Up-counter data n n+1 n+2 FFFE FFFF 0 1 2 m-1 m Up/down counter clock Up/down counter data 0 1 2 3 x-3 x-2 x-1 x x-1 x-2 x-3 3 2 1 0 Interrupt Oscillation with reference resistor Oscillation with sensor Fig. 3.7.2 Timing of A/D conversion Basic control and operation of the A/D converter are described in the flowchart in Figure 3.7.1. In order to prepare a program, add items required according to application. After A/D conversion, the value counted during oscillation of the sensor connected between the TH and CS terminals is set on the up-counter C0-C15. This value is the sensor oscillation clock number during a time period equal to that during which the reference resistance connected between the RS and CS terminals is oscillated according to the initial value set on the up-counter. The difference between the reference resistance and the sensor resistance value can be obtained indirectly from the initial value and results. Correct it according to the characteristics of the connected elements and calculate the target measurement results. Note Depending on the initial value of the up-counter C0-C15, the up/ down counter TC0-TC15 may overflow while the CR oscillation clock is being counted. When setting the initial value, pay attention to CR oscillation frequency, its fluctuation range and the input clock frequency of the up/down counter. If the up/down counter overflows, A/D conversion is terminated immediately, and correct measurement is impossible. S1C62N51 TECHNICAL SOFTWARE EPSON II-33 CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) Set "0000H" on the up/down counter prior to A/D conversion. No other reading or writing operation is necessary. This counter is provided in order to adjust the oscillation time of the two external resistance. Note If the up/down counter TC0-TC15 is measured after A/D conversion, it may not indicate "0000H". This is not due to incorrect timing in terminating A/D conversion but because the counting down clock is input after the control signal is output to the up-counter to terminate counting. Since interruption is possible after A/D conversion, reading of the up-counter and data processing are basically performed using the interrupt function. If interrupt is not used, A/D converter operation can be checked by reading the ADRUN register. After "1" is entered in this register to start A/D conversion, the register remains at "1" during A/D conversion and is reset to "0" when A/D conversion is finished. II-34 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) Examples of A/D converter control program In this section, we will explain, for an example of an A/D converter, a method of temperature measurement and its program. When performing temperature measurement, connect a reference resistance to the RS terminal, a thermistor to the TH terminal and a condenser to the CS terminal, respectively. The ideal reference resistance to be connected to the RS terminal should be one which shows no change in its resistance value as a result of fluctuations in temperature. The thermistor has a characteristic against temperature resistance and the resistance value R at a certain temperature T (K) can be represented by the following formula: R = R0 EXP{ B (1/T - 1/T0) } R0: Resistance value of the thermistor at the reference temperature (T0K) B: Constant of the thermistor By using the reference resistance and the temperature resistance characteristic of the thermistor, temperature measurement is performed. One method sets the reference resistance and the thermistor in an alternating state of CR oscillation, using the same condenser only in the same time interval. A numerical comparison of each oscillating frequency is performed by a counter, and the counter values are converted to the temperature by way of the characteristics of the thermistor. After the A/D conversion, the counter value of 16 bits will have been set in the up-counter from C15 (0F8H, MSB) to C0 (0F5H, LSB). This counter value represents the amount of CR oscillation of the thermistor against duration when it is oscillated with CR of the reference resistance for a specified number of times. The relationship between the amount of oscillation of the thermistor and the temperature is shown in Figure 3.7.3. S1C62N51 TECHNICAL SOFTWARE EPSON II-35 CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) 60 50 Temperature (C) 40 30 20 10 0 -10 Fig. 3.7.3 Counter value characteristics of the temperature and the upcounter -20 -30 1000 2000 3000 4000 5000 6000 7000 8000 Counter value of up-counter As shown in Figure 3.7.3, the temperature and the counter values do not form a straight line. Therefore, it is necessary to drive the range of measurement temperature into several sections and to calculate in advance the counter values at the temperature of its division points, according to the characteristics of the thermistor. As for the divided sections, the temperature coefficient (fluctuation in temperature by unit counter) which approximates to a straight line between the sections is calculated and stored into the ROM in conjunction with the counter value of such division point. With this value and the counter value calculated, the temperature can then be calculated. The following is a sample program which controls the A/D converter and converts the counter value to the temperature when performing temperature measurement with this method. In this program, 49.9 k are used for the external reference resistance, 2,200 pF for the condenser and one with a temperature characteristic as shown in Table 3.7.2 for the thermistor. II-36 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) Table 3.7.2 Temperature [C] Temperature characteristics of the thermistor in the TH resistance [k] -30 -20 -10 0 10 20 30 40 50 60 sample program 872.20 484.00 277.40 164.00 99.97 62.56 40.20 26.43 17.75 12.16 Up-counter value 006B[HEX] 00CD[HEX] 0166[HEX] 025E[HEX] 03E1[HEX] 061D[HEX] 094F[HEX] 0DCC[HEX] 1412[HEX] 1F16[HEX] 107[DEC] 205[DEC] 358[DEC] 606[DEC] 993[DEC] 1565[DEC] 2383[DEC] 3532[DEC] 5138[DEC] 7958[DEC] The counter value of the up-counter shows the amount of CR oscillation of the thermistor when the reference resistance is oscillated with CR 2,000 times. Label HEXDEC Mnemonic/operand Comment MACRO ARG1, ARG2, ARG3 LOCAL HXDC1, HXDC2 ;******************************************************* ;* * ;* HEX --> DEC 1 -- 13 DIGIT * ;* * ;******************************************************* RST LD ADD ;***** ;***** LD LD LD CP JP ADD INC LDPY JP INC LDPY ADD JP LD CP JP S1C62N51 TECHNICAL SOFTWARE F,8 A,ARG3 A,1 ;Reset D, Z and C flags ;Digit Digit + 1 ARG2 ZERO CLEAR ***** ARG2 DATA <-- ARG1 TOP DATA ***** X,ARG1+ARG3-1 Y,ARG2 MY,MX ;ARG2 data ARG1 data MY,0AH C,$+5 ;If ARG2 data < 0AH MY,6 ;ARG2 data ARG2 data + 6 Y ;ARG2 address increment MY,1 ;ARG2 data 1 increment $+3 Y MY,0 ;Zero clear A,0FH ;Digit counter decrement NZ,$-2 ;If digit counter not = 0 B,ARG3-1 ;B-reg. Digit - 1 B,0 Z,HXDC2 ;If Digit = 1 EPSON II-37 CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) HXDC1 PUSH B ;***** LD LD LD RCF SDF ACPY PUSH ADD JP POP JP POP ADD JP ;*** B,4 Y,ARG2 A,ARG3+2 MY,MY F A,9 Z,$+3 F $-5 F B,9 NZ,$-12 ***** ;Loop counter setting ;A-reg. Digit + 2 ;Reset C flag ;Set D flag ;ARG2 data 2 * ARG2 data ;A-reg. decrement ;If A-reg. not = 0 ;Loop counter decrement ;If loop counter not = 0 ARG2 DATA <-- ARG2 DATA + ARG1 1 DIGIT DATA RST ADC ADC LD LD CP JP ADD SDF RCF ACPY ADC JP RCF SDF ACPY ADC INC PUSH ADD JP POP JP POP ;***** HXDC2 ARG2 DATA <-- ARG2 DATA * 16D POP ADD JP RDF F,8 XL,0FH XH,0FH Y,ARG2 B,ARG3+1 MX,0AH C,$+7 MX,6 MY,MX MY,1 $+5 MY,MX MY,0 Y F B,9 Z,$+3 F $-6 F ;Reset D, Z and C Flags ;ARG1 address decrement ;Digit counter setting ;If ARG1 1 digit data < 0AH ;ARG1 1 digit data + 6 ;Set D flag ;Reset C flag ;ARG2 data ARG1 1 digit data ;Reset C flag ;Set D flag ;ARG2 data ARG1 1 digit data ;If C = 1 then 1 increment ;Digit counter decrement ;If digit counter not = 0 DIGIT DECREMENT B B,9 NZ,HXDC1 **** ***** ;Digit decrement ;If digit counter not = 0 ;Reset D flag ENDM II-38 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) ORG 100H JP INIT HALT JP INAD HALT HALT HALT HALT HALT ;Initialize and mode selection ;(101H) ;A/D converter interrupt (102H) ;(103H) ;(104H) ;(105H) ;(106H) ;(107H) DI INIT LD LD LD LD LD A,05H SPH,A A,0 SPL,A X,0 ;Set stack pointer to 05H ;Clear RAM area (00H-4FH) CLRRAM LDPX MX,0 CP XH,5H JP C,CLRRAM LD LD X,0ECH MX,1 ;Set A/D interrupt to Enable LD X,0E4H ;Clear up/down counter UDCCL LDPX MX,0 CP XL,8 JP NZ,UDCCL LD LDPX LDPX LDPX LDPX EI X,0F5H MX,0H MX,3H MX,8H MX,0FH ;Set complement of 2,000 to up-counter ;Set interrupt to Enable LD X,0F1H LD MX,1 HALT ;Start A/D conversion INAD RST LD LD F,8 A,0 B,0 CALL JP LD PSET JPBA $+2 READEND X,10H 2 READKN S1C62N51 TECHNICAL SOFTWARE EPSON II-39 CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) READEND PUSH LD LD LD B B,4 X,0F8H Y,13H CP JP JP JP RCF ADC RCF ADC ADD JP JP MX,MY C,MULTI Z,$+2 NC,NEXTREAD COMP NEXTREAD POP ADD ADC JP XL,15 YL,15 B,15 NZ,COMP MULTI B A,6 B,0 READKN ;Set address of next setting value stored MULTI POP RCF SBC SBC CALL JP LD PSET JPBA LD LD LD LDPX INC ADD JP RCF LD LD SCPY INC SCPY INC SCPY INC SCPY II-40 B A,6 B,0 $+2 $+4 X,10H 2 X,0F5H Y,00H B,4 MY,MX Y B,15 NZ,$-3 X,10H Y,0H MY,MX X MY,MX X MY,MX X MY,MX EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) ;***** LD LD INITIALIZE WORK MEMORY ***** X,24H B,4 WMCLR LBPX MX,00 ADD B,15 JP NZ,WMCLR ;***** CALCURATE An X K LD LD LD LDPX INC ADD JP LD LD X,0H Y,04H B,4 MY,MX Y B,15 NZ,$-3 MY,0 B,1 LD Y,14H FAN LD PUSH JP LD LD LD CALL LD LD MY,B X,00H YL Z,MULTI02 X,04H A,2 YH,A SUBROUTADD A,1 YH,A POP INC CP JP RCF RLC JP YL Y YL,7 NZ,MULTI01 ***** MULTI00 MULTI01 MULTI02 ;***** LD RCF ACPX ACPX ACPX ACPX ACPX JP ;***** S1C62N51 TECHNICAL SOFTWARE B C,SUBTRA WORK MEMORY X 2 ***** X,04H MX,MX MX,MX MX,MX MX,MX MX,MX MULTI00 ADD Bn EPSON ***** II-41 CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) SUBTRA HEXDEC 24H,30H,10 ;Decimal 8 digit HEX LD X,17H ;Set decimal point LD A,MX SDF LD CP JP X,1BH MX,1 Z,MINUS RCF LD LD LD X,18H Y,30H YL,A PLUS PLUS1 ACPY INC PUSH CP JP POP JP POP RDF JP MINUS MY,MX X F XL,0BH Z,$+3 F PLUS1 F ENDPROG+1 RCF LD LD X,18H Y,30H PUSH LD CP JP LD POP SBC LD INC JP F B,YL B,A Z,MINUS2 B,0 F B,MY MY,B Y MINUS1 POP SBC LD INC INC F MX,MY MY,MX X Y PUSH CP JP JP POP RDF F XL,0BH Z,$+2 MINUS2 F JP ENDPROG+1 MINUS1 MINUS2 II-42 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) ;***** 16-BIT ADDITION SUBROUTADD RCF ACPY INC ACPY INC ACPY INC ACPY INC ***** MY,MX X MY,MX X MY,MX X MY,MX X ACPY MY,MX ENDPROG RET ORG 200H ;************************* ;* * ;* Kn, An, Bn SETTINGS * ;* * ;************************* SETCON ;-30C TO -20C LBPX MX,6BH LBPX MX,00H LBPX MX,66H LBPX MX,30H LBPX MX,30H RETD 10H ;-20C TO -10C LBPX MX,0CDH LBPX MX,00H LBPX MX,8DH LBPX MX,42H LBPX MX,20H RETD 10H ;-10C TO 0C LBPX MX,66H LBPX MX,01H LBPX MX,93H LBPX MX,41H LBPX MX,10H RETD 10H ;0C TO 10C LBPX LBPX LBPX LBPX S1C62N51 TECHNICAL SOFTWARE MX,5EH MX,02H MX,02H MX,41H EPSON ;K1 = 06BH (107) ;A1 = 3066H (0.102) ;B1 = 1030 (-30C) ;K1 = 0CDH (205) ;A1 = 428DH (0.0653) ;B1 = 1020 (-20C) ;K1 = 166H (358) ;A1 = 4193H (0.0403) ;B1 = 1010 (-10C) ;K2 = 25EH (606) ;A2 = 4102H (0.0258) II-43 CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) LBPX MX,00H RETD 00H ;10C TO 20C LBPX MX,0E1H LBPX MX,03H LBPX MX,0AFH LBPX MX,40H LBPX MX,10H RETD 00H ;20C TO 30C LBPX MX,1DH LBPX MX,06H LBPX MX,7AH LBPX MX,40H LBPX MX,20H RETD 00H ;30C TO 40C LBPX MX,4FH LBPX MX,09H LBPX MX,66H LBPX MX,53H LBPX MX,30H RETD 00H ;40C TO 50C LBPX MX,0CCH LBPX MX,0DH LBPX MX,6FH LBPX MX,52H LBPX MX,40H RETD 00H ;50C TO 60C LBPX MX,12H LBPX MX,14H LBPX MX,63H LBPX MX,51H LBPX MX,50H RETD 00H ;B2 = 0000 (0C) ;K2 = 3E1H (993) ;A2 = 40AFH (0.0175) ;B2 = 0010 (10C) ;K2 = 61DH (1565) ;A2 = 407AH (0.0122) ;B2 = 0020 (20C) ;K2 = 94FH (2383) ;A2 = 5366H (0.00870) ;B2 = 0030 (30C) ;K2 = 0DCCH (3532) ;A2 = 526FH (0.00623) ;B2 = 0040 (40C) ;K2 = 1412H (5138) ;A2 = 5163H (0.00355) ;B2 = 0050 (50C) ;60C LBPX MX,16H LBPX MX,1FH ;K2 = 1F16H (7958) RET II-44 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) Figure 3.7.4 indicates a flowchart for the sample program. This sample program sets the amount of oscillation, as the reference of the counter value, to 2,000 times (decimal), but determines the amount of oscillation in accordance with the measurement range and purposes. in addition, as this program only aims at conversion of temperature, only the A/D interrupt is set. When using this program, set the other interrupts according to desired application. Start 1 Set the stack pointer to 50H Set the data of the previous sector, to 10H-1BH Clear RAM area (00H-4FH) Set the difference between the the up-counter value and the count number, to 00H-03H Set the A/D interrupt mask register to "Enable" Clear 24H-2BH Clear the up/down counter (E4H-E7H) Calculate the product of the difference between the count numbers and the coefficient of the linear approximation, to 24H-2BH Set the reference count in the up-counter (F5H-F8H) (set complement, F830H of 2,000 [DEC] times) Set the hexadecimal number of 24H-2BH, converting it to the decimal number, to 30H-39H Interrupt admitted Start of A/D conversion N HALT The minimum temperature of the sector is minus Occurrence of the interrupt Y Set the number for counting in the range divided into 10H-1BH, the coefficient of the linear approximation of the sector and the minimum temperature When adjusting the position of the decimal point, reduce the product calculated from the absolute value of the minimum temperature and then terminate the conversion to the desired temperature N Y When adjusting the position of the decimal point, add the minimum temperature and then terminate the conversion to the desired temperature Termination The up-counter value being within the division range Y 1 N Set the address of the next division sector data to a PC Fig. 3.7.4 Flowchart S1C62N51 TECHNICAL SOFTWARE EPSON II-45 CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) The following explains the ROM data involved in the temperature division sector used in this program. Label Mnemonic/operand SETCON ;-30C TO -20C LBPX MX,6BH LBPX MX,00H LBPX MX,66H LBPX MX,30H LBPX MX,30H RETD 10H ;-20C TO -10C LBPX MX,0CDH LBPX MX,00H LBPX MX,8DH LBPX MX,42H LBPX MX,20H RETD 10H : : Comment ;K1 = 06BH (107) ;A1 = 3066H (0.102) ;B1 = 1030 (-30C) ;K1 = 0CDH (205) ;A1 = 428DH (0.0653) ;B1 = 1020 (-20C) The first 16-bit data (K1) is the amount of oscillation of the thermistor against the number of oscillation (2,000 times) of the reference resistance in the minimum temperature between the division sector, that is, the counter value of the up-counter after the A/D converter control. This value can be calculated through the characteristics of the external reference resistance, the thermistor, the condenser and the A/D converter. The sample program is 107 times (6BH) at 30C. The data are written in the hexadecimal system. The next 16-bit data (A1) is the temperature coefficient which linearly approximates between the division sector. The temperature coefficient represents the changing quantity of the temperature by one count. For example, when the counter value of -30C and -20C are 107 (6BH) and 205 (0CDH), respectively, the temperature coefficient of the sector can be calculated using the following formula: { (-20) - (-30) } / {205 - 107 } = 0.102 [C/count] Minimum counter number within the sector Minimum counter number of the next sector Minimum temperature within the sector Minimum temperature of the next sector II-46 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter) This value is converted to a hexadecimal number including the position of the decimal point. The lower 12 bits represent 066H which indicates 102 and the upper 4 bits represent the number 3 for the times the position of the decimal point shifts to the left (1/103). The temperature coefficient at -30C to -20C will be 3066H after conversion to a hexadecimal number. This similarly applies to other coefficients between the temperature sectors. The last 16-bit data (B1) indicates the minimum temperature of the sector concerned. The data at the temperature of -30C represent 1030H. The upper 4 bits are minus flag, indicating a minus number if they are 1. The lower 12 bits represent the absolute value of the temperature. Incidentally, as the lower 12 bits operate based on the decimal arithmetic system, they are expressed in the decimal system. Thus far, we have explained an example of temperature measurement which calculates the temperature from the linear approximation using an A/D converter. When using this program, you should add items necessary for the desired applications and modify as necessary through the characteristics of the external element. In addition, one should exercise caution when using the A/D converter for other purposes. S1C62N51 TECHNICAL SOFTWARE EPSON II-47 CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) 3.8 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function The S1C62N51 Series has built-in supply voltage detection circuit and drop in supply voltage may be detected by controlling the register on the I/O memory. Criteria voltages are as follows: Model Criteria Voltage S1C62N51 S1C62L51 2.4 V 0.15 V 1.2 V 0.10 V Moreover, when the battery load becomes heavy, such as during external piezo buzzer driving or external lamp lighting, heavy load protection function is built-in in case the supply voltage drops. S1C62L51 operates at 0.9 V (1.2 V when the A/D converter is operated) due to the SVD circuit and heavy load protection function. SVD circuit and heavy load protection function memory map Table 3.8.1 I/O memory map Address D3 HLMOD Register D2 D1 0 SVDDT D0 SVDON 0FAH R/W *1 *2 *3 *4 *5 *6 II-48 R R/W Init *1 0 Name HLMOD 0 SVDDT SVDON Comment 1 Heavy 0 Normal Heavy load protection mode register Low On Normal Off Supply voltage detection data Supply voltage detection circuit On/Off *5 0 0 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Control of the SVD circuit The SVD circuit will turn ON by writing "1" on the SVDON register (address 0FAH, D0, R/W) and supply voltage detection will be performed. By writing "0" on the SVDON register, the detection result is stored in the SVDDT register. However, in order to obtain a stable detection result, it is necessary to turn the SVD circuit ON for at least 100 s. Accordingly, reading out the detection result from the SVDDT register is performed through the following procedures: Set the SVDON register to "1". Provide at least 100 s waiting time. Set the SVDON register to "0". Read-out from the SVDDT register. Note, however, that when S1C62N51 is to be used with the normal system clock at fosc = 32.768 kHz, there is no need for the waiting time stated in the above procedure since 1 instruction cycle will take longer than 100 s. Because the power current consumption of the IC becomes large when the SVD circuit is operated, turn the SVD circuit OFF when not in use. The operation timing chart is shown in Figure 3.8.1. Supply voltage Criteria voltage 100 s or more Fig. 3.8.1 Timing chart of supply voltage SVDON register SVD circuit detection operation through the SVDON SVDDT register register HLMOD register Example of SVD circuit control program S1C62N51 TECHNICAL SOFTWARE Label Mnemonic/operand LD OR AND LD X,0FAH MX,0001B MX,1110B A,MX EPSON Comment ;Sets the address of SVDON ;Sets SVDON to "1" ;Sets SVDON to "0" ;Loads the detection result ;into the A register II-49 CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Heavy load protection function Note that the heavy load protection function on the S1C62L51 is different from the S1C62N51. (1) In case of S1C62L51 The S1C62L51 has the heavy load protection function for when the battery load becomes heavy and the source voltage drops, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. In this mode, operation with a lower voltage than normal is possible. The normal mode changes to the heavy load protection mode in the following two cases: When the software changes the mode to the heavy load protection mode (HLMOD = "1") When supply voltage drop (SVDDT = "1") in the SVD circuit is detected, the mode will automatically shift to the heavy load protection mode until the supply voltage is recovered (SVTDT = "0") In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal driver source output VL2 so as to operate the internal circuit. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Also, to reduce current consumption, do not set the SVDON to ON in the heavy load protection mode. (2) In case of S1C62N51 The S1C62N51 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. Compared with the normal operation mode, this mode can reduce the output voltage variation of the constant voltage/booster voltage circuit of the LCD system. II-50 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) The normal mode changes to the heavy load protection mode in the following case: * When the software changes the mode to the heavy load protection mode (HLMOD = "1") The heavy load protection mode switches the constant voltage circuit of the LCD system to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. Supply voltage Criteria voltage HLMOD register Heavy load protection mode Fig. 3.8.2 Timing chart of supply voltage detection operation 2 Hz clock SVD circuit SVDDT register through the HLMOD register SVDON register Supply voltage Criteria voltage 100 s or more SVDON register 2 Hz clock Fig. 3.8.3 Timing chart of heavy load protection SVD circuit SVDDT register function operation through the SVDON Heavy load protection mode register HLMOD register S1C62N51 TECHNICAL SOFTWARE EPSON II-51 CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Examples of heavy load protection function control program * Operation through the HLMOD register This is a sample program when lamp is driven with the R00 terminal during performance of heavy load protection. Label Mnemonic/operand Comment LD OR LD OR X,0FAH MX,1000B Y,0F3H MY,0001B ;Sets the address of HLMOD ;Sets to the heavy load protection mode ;Sets the address of R0n port ;Turns lamp ON Y,0F3H MY,1110B WT1S MX,0111B ;Sets the R0n port address ;Turns the lamp OFF ;1 second waiting time (software timer) ;Cancels the heavy load protection mode : : LD AND CALL AND In the above program, the heavy load protection mode is canceled after 1 sec waiting time provided as the time for the battery voltage to stabilize after the lamp is turned off; however, since this time varies according to the nature of the battery, time setting must be done in accordance with the actual application. II-52 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) * Operation through the SVDON register Label Mnemonic/operand Comment LD FAN JP OR AND FAN JP X,0FAH MX,1010B NZ,HLMOD MX,0001B MX,1110B A,0010B Z,HLMOD ;Sets the HLMOD/SVDDT address ;Checks the HLMOD/SVDDT bits ;Heavy load protection mode ;Sets the SVDON to "1" ;Sets the SVDON to "0" ;Checks the SVDDT bit ;Shifts the mode to ;the heavy load protection mode LD AND RET Y,FLAG MY,0 ;Resets the flag to "0" Y,FLAG MY,1 ;Sets the flag to "1" ; HLMOD: LD OR RET The above program operates the heavy load protection function by using the SVDON register. In the normal operation mode, supply voltage detection is done from the SVDON register and when the supply voltage drops below the criteria voltage, the mode shifts to the heavy load protection mode. In the heavy load protection mode, supply voltage detection by the hardware is done every 2 Hz and the detection result is stored in the SVDDT register. Because of this, the SVDDT register will be "1" during the heavy load protection mode. Moreover, in the above program, supply voltage detection by the SVDON is halted during the heavy load protection mode. If the supply voltage become grater than the criteria voltage, the SVDDT register value will become "0" and hence, supply voltage detection through the SVDON register will resume after checking the SVDDT register value. When used as a sub-routine, the above program will enable the user to determine whether the present operation mode is the normal operation mode (flag = "0") or the heavy load protection mode (flag = "1"). The flowchart for the above program is shown in the next page. S1C62N51 TECHNICAL SOFTWARE EPSON II-53 CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Start HLMOD? =1 =0 SVDDT? =1 =0 SVDON1 SVDON0 SVDDT? =1 =0 FLAG0 FLAG1 Fig. 3.8.4 Flowchart of operation through the SVDON register II-54 RET EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) 3.9 Interrupt and Halt Interrupt memory map Table 3.9.1 I/O memory map Address D3 EIK03 Register D2 D1 EIK02 EIK01 D0 EIK00 0E8H R/W 0 EIT2 EIT8 EIT32 0EBH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 IK0 0EDH R 0 IT2 IT8 IT32 0EFH R 0 0 0 0F0H R *1 *2 *3 *4 *5 *6 IAD Name EIK03 EIK02 EIK01 EIK00 0 EIT2 EIT8 EIT32 0 0 0 EIAD 0 0 0 IK0 0 IT2 IT8 IT32 0 0 0 IAD Init *1 0 0 0 0 Comment 1 Enable Enable Enable Enable 0 Mask Mask Mask Mask Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz *5 0 0 0 *5 *5 *5 0 Enable Mask Interrupt mask register (A/D) *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) 0 0 0 Yes Yes Yes No No No Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *5 *4 *4 *4 *5 *5 *5 0 Yes No Interrupt factor flag (A/D) *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual S1C62N51 TECHNICAL SOFTWARE EPSON II-55 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Control of interrupts and halt The S1C62N51 supports three types of a total of 8 interrupts. There are three timer interrupts (2 Hz, 8 Hz, 32 Hz), one A/D interrupt and four input interrupts (K00-K03). The 8 interrupts are individually enabled or masked (disabled) by interrupt mask registers. The EI and DI instructions can be used to set or reset the interrupt flag (I), which enables or disables all the interrupts at the same time. When an interrupt is accepted, the interrupt flag (I) is reset, and cannot accepts any other interrupts (DI state). Restart from the halt state created by the HALT instruction, is done by interrupt. * Interrupt factor flags IK0 This flag is set when any of the K00 to K03 input interrupts occurs. The interrupt factor flag (IK0) is set to "1" when the contents of the input (K00-K03) become "1" and the data of the corresponding interrupt mask register (EIK00-EIK03) is "1". The contents of the IK0 flag can be loaded by software to determine whether the K00-K03 input interrupts have occured. The flag is reset when loaded by software. (See Figure 3.9.1.) II-56 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Data bus K00 K01 K02 K03 Address 0E0H Input interrupt factor flag register (IK0) INT (Interrupt request) Data bus FF Interrupt flag (I) D0 D1 D2 D3 Input interrupt mask register (EIK00-EIK03) Address 0E8H Fig. 3.9.1 K00-K03 Input interrupt circuit IT32 This flag is set to "1" when a falling edge is detected in the timer TM1 (32 Hz) signal. The contents of the IT32 flag can be loaded by software to determine whether a 32 Hz timer interrupt has occured. The flag is reset, when it is loaded by software. (See Figure 3.9.2.) S1C62N51 TECHNICAL SOFTWARE EPSON II-57 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) IT8 This flag is set to "1" when a falling edge is detected in the timer TM1 (8 Hz) signal. The contents of the IT8 flag can be loaded by software to determine whether an 8 Hz timer interrupt has occured. The flag is reset, when it is loaded by software. (See Figure 3.9.2.) IT2 This flag is set to "1" when a falling edge is detected in the timer TM1 (2 Hz) signal. The contents of the IT2 flag can be loaded by software to determine whether a 2 Hz timer interrupt has occured. The flag is reset, when it is loaded by software. (See Figure 3.9.2.) Timer interrupt factor flag (IT) D0 Data bus Basic clock counter 32 Hz 8 Hz D1 2 Hz D2 Address 0EFH Timer interrupt mask register (EIT) Data bus D0 INT (Interrupt request) D1 D2 Address 0EBH Interrupt flag (I) Fig. 3.9.2 Timer interrupt circuit II-58 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) IAD When the counted value reaches "0" during the countingdown or counting-up operation of the up/down counter, this flag is set to "1" at the falling edge of the next signal during counting-down operation and at the rising edge of the next signal during counting-up operation. The contents of the IAD flag can be loaded by software to determine whether an A/D interrupt has occurred. A/D converter factor flag (IAD) Data bus Up/down counter The flag is reset, when it is loaded by software. D0 Address 0F0H Fig. 3.9.3 A/D interrupt circuit Data bus A/D converter mask register (EIAD) INT (Interrupt request) D0 Address 0ECH Interrupt flag (I) Note Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. S1C62N51 TECHNICAL SOFTWARE EPSON II-59 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) * Interrupt mask registers The interrupt mask registers are registers that individually specify whether to enable or mask the timer interrupt (2 Hz, 8 Hz, 32 Hz), A/D interrupt, or input interrupt (K00-K03). The following are descriptions of the interrupt mask registers. EIK00 to EIK03 This register enables or masks the K00-K03 input interrupt. The interrupt factor flag (IK0) is set to "1" when the contents of the input (K00-K03) become "1" and the data of the corresponding interrupt mask register (EIK00-EIK03) is "1". The CPU is interrupted if it is in the EI state (interrupt flag [I] = "1"). (See Figure 3.9.1.) EIT32 This register enables or masks the 32 Hz timer interrupt. The CPU is interrupted if it is in the EI state when the interrupt mask register (EIT32) is set to "1" and the interrupt factor flag (IT32) is "1". (See Figure 3.9.2.) EIT8 This register enables or masks the 8 Hz timer interrupt. The CPU is interrupted if it is in the EI state when the interrupt mask register (EIT8) is set to "1" and the interrupt factor flag (IT8) is "1". (See Figure 3.9.2.) EIT2 This register enables or masks the 2 Hz timer interrupt. The CPU is interrupted if it is in the EI state when the interrupt mask register (EIT2) is set to "1" and the interrupt factor flag (IT2) is "1". (See Figure 3.9.2.) EIAD This register enables or masks the A/D interrupt. The CPU is interrupted if it is in the EI state when the interrupt mask register (EIAD) is set to "1" and the interrupt factor flag (IAD) is "1". (See Figure 3.9.3.) II-60 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) * Interrupt vector address The S1C62N51 interrupt vector address is made up of the low-order 3 bits of the program counter (12 bits), each of which is assigned a specific function as shown in Figure 3.9.4. PCP3 PCP2 PCP1 PCP0 PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 0 0 0 1 0 0 0 Fig. 3.9.4 Assignment of the Input (K00-K03) interrupt interrupt vector address Clock timer interrupt 0 0 x x x A/D interrupt Note that all of the three timer interrupts have the same vector address, and software must be used to judge whether or not a given timer interrupt has occurred. For instance, when the 32 Hz timer interrupt and the 8 Hz timer interrupt are enabled at the same time, the accepted timer interrupt must be identified by software. (Similarly, the K00-K03 input interrupts and A/D interrupt must be identified by software.) When an interrupt is generated, the hardware resets the interrupt flag (I) to enter the DI state. Execute the EI instruction as necessary to recover the EI state after interrupt processing. Set the EI state at the start of the interrupt processing routine to allow nesting of the interrupts. The interrupt factor flags must always be reset before setting the EI status in the corresponding interrupt processing routine. (The flag is reset when the interrupt factor flag is read by software.) S1C62N51 TECHNICAL SOFTWARE EPSON II-61 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) If the EI instruction is executed without resetting the interrupt factor flag after generating the timer interrupt or A/D interrupt, and if the corresponding interrupt mask register is still "1", the same interrupt is generated once more. (See Figure 3.9.5.) If the EI state is set without resetting the interrupt factor flag after generating the input interrupt (K00-K03), the same interrupt is generated once more. (See Figure 3.9.5.) The interrupt factor flag must always be read (reset) in the DI state (interrupt flag [I] = "0"). There may be an operation error if read in the EI state. The timer interrupt factor flags (IT32, IT8, IT2) and A/D interrupt factor flag (IAD) are set whether the corresponding interrupt mask register is set or not. The input interrupt factor flag (IK0) is allowed to be set in the condition when the corresponding interrupt mask register (EIK00-EIK03) is set to "1" (interrupt is enabled). (See Figure 3.9.5.) Table 3.9.2 shows the interrupt vector map. Table 3.9.2 Interrupt vector map Page 1 Step Interrupt vector 00H Initial reset 01H Clock timer interrupt 02H A/D interrupt 03H Clock timer interrupt and A/D interrupt 04H Input (K00-K03) interrupt 05H Input interrupt and clock timer interrupt 06H Input interrupt and A/D interrupt 07H Generation of all interrupt Addresses (start address of interrupt processing routines) to jump to are written into the addresses available for interrupt vector allocation. II-62 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Interrupt vector (MSB) K00 : EIK00 : K01 (LSB) Program counter of CPU (three low-order bits) EIK01 IK0 INT (Interrupt request) K02 EIK02 Interrupt flag K03 EIK03 IAD EIAD IT2 Interrupt factor flag EIT2 IT8 Interrupt mask register EIT8 Fig. 3.9.5 Internal interrupt circuit IT32 EIT32 Examples of interrupt * Restart from halt state by interrupt and halt control Main routine program Label Mnemonic/operand Comment ;Set address of K00 to K03 ;interrupt mask register ;Enable K00 to K03 ;input interrupt LD X,0E8H OR MX,1111B LD X,0ECH OR MX,0001B LD X,0EBH ;Set address of timer interrupt ;mask register MX,0111B ;Enable timer interrupt ;(32 Hz, 8 Hz, 2 Hz) ;Set interrupt flag (EI state is set) ;Halt mode MAIN ;Jump to MAIN ; ;Set address of A/D interrupt ;mask register ;Enable A/D interrupt ; OR MAIN: S1C62N51 TECHNICAL SOFTWARE EI HALT JP EPSON II-63 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Interruption vector routine Label Mnemonic/operand Comment ORG JP JP JP JP ;Timer interrupt is generated ;A/D interrupt is generated ;Timer interrupt, A/D interrupt 100H INIT INTR INTR INTR JP JP INTR INTR JP INTR JP INTR ;are generated ;K00 to K03 interrupt is generated ;Timer interrupt, K00 to K03 interrupt ;are generated ;A/D interrupt, K00 to K03 interrupt ;are generated ;Timer interrupt, A/D interrupt, ;K00 to K03 interrupt are generated ; INTR: LD LD LD FAN JP CALL X,0EFH Y,TMFSK MY,MX MY,0100B Z,TI8RQ TINT2 ;Address of timer interrupt factor flag ;Address of timer interrupt factor flag buffer LD FAN JP CALL Y,TMFSK MY,0010B Z,TI32RQ TINT8 ;Address of timer factor flag buffer ;Check 8 Hz timer interrupt ;Jump if not 8 Hz timer interrupt ;Call 8 Hz timer interrupt service routine LD FAN JP CALL Y,TMFSK MY,0001B Z,ADRQ TINT32 ;Address of timer factor flag buffer ;Check 8 Hz timer interrupt ;Jump if not 32 Hz timer interrupt ;Call 32 Hz timer interrupt service routine LD FAN JP CALL X,0F0H MX,0001B Z,IK0RQ ADIN ;Address of A/D interrupt factor flag ;Check A/D interrupt factor flag ;Jump if not A/D interrupt ;Call A/D interrupt service routine ;Check 2 Hz timer interrupt ;Jump if not 2 Hz timer interrupt ;Call 2 Hz timer interrupt service routine TI8RQ: TI32RQ: ADRQ: II-64 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) IK0RQ: LD FAN JP CALL X,0EDH MX,0001B Z,INTEND IK0INT ;Address of K00 to K03 input interrupt flag ;Check K00 to K03 input interrupt ;Jump if not K00 to K03 input interrupt ;Call K00 to K03 input interrupt service ;routine INTEND: EI RET The above program is normally used to restart the CPU when in the halt state by interrupt and to return it to the halt state again after the interrupt processing is completed. The processing proceeds by repeating the halt interrupt halt interrupt cycle. The interrupt factor flag is reset when load by the software. Thus, when using interrupts which interrupt factor flags are in the same address at the same time, flag check must be done after storing the data. For example, store the 1 word including the factor flag in the RAM. (If check is directly done by the FAN instruction, the factor flags of the same address are all reset.) Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. S1C62N51 TECHNICAL SOFTWARE EPSON II-65 CHAPTER 4: SUMMARY OF PROGRAMMING POINTS CHAPTER 4 SUMMARY OF PROGRAMMING POINTS * Core CPU After the system reset, only the program counter (PC), new page pointer (NPP) and interrupt flag (I) are initialized by the hardware. The other internal circuits whose settings are undefined must be initialized with the program. * Power Supply External load driving through the output voltage of constant voltage circuit or booster circuit is not permitted. * Data Memory - Since some portions of the RAM are also used as stack area during subroutine call or register saving, see to it that the data area and the stack area do not overlap. - The stack area consumes 3 words during a subroutine call or interrupt. - Address 00H-0FH in the RAM is the memory register area addressed by the register pointer RP. - Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. * Initial Reset - Maintain the initial reset circuit at high level for at least 4 seconds (in case of oscillation frequency fosc = 32 kHz) because noise rejector is built-in. - When utilizing the simultaneous high input reset function of the input ports (K00-K03), take care not to make the ports specified during normal operation to go high simultaneously. * II-66 Input Port When modifying the input port from high level to low level with pull-down resistance, a delay will occur at the rise of the waveform due to time constant of the pull-down resistance and input gate capacities. Provide appropriate waiting time in the program when performing input port reading. EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 4: SUMMARY OF PROGRAMMING POINTS * Output Port * I/O Port The FOUT and BUZZER output signal may produce hazards when the output ports R00 and R01 are turned on or off. - When the I/O port is set to the output mode and a lowimpedance load is connected to the port pin, the data written to the register may differ from the data read. - When the I/O port is set to the input mode and a lowlevel voltage (VSS) is input by the built-in pull-down resistance, an erroneous input results if the time constant of the capacitive load of the input line and the builtin pull-down resistance load is greater than the read-out time. When the input data is being read, the time that the input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the pins must settle within 0.5 cycles. If this condition cannot be met, some measure must be devised, such as arranging a pull-down resistance externally, or performing multiple read-outs. * LCD Driver - Because the display memory is for writing only, re-writing the contents with computing instructions (e.g., AND, OR, etc.) which come with read-out operations is not possible. To perform bit operations, a buffer to hold the display data is required on the RAM. - Even when 1/2 duty is selected, the display data corresponding to COM2 and COM3 are valid for static drive. Hence, for static drive set the same value to all display memory corresponding COM0-COM3. - Even when 1/3 duty is selected, the display data corresponding to COM3 is valid for static drive. Hence, for static drive set the same value to all display memory corresponding COM0-COM3. - For cadence adjustment, set the display data including display data corresponding to COM3. - fosc indicates the oscillation frequency of the oscillation circuit. S1C62N51 TECHNICAL SOFTWARE EPSON II-67 CHAPTER 4: SUMMARY OF PROGRAMMING POINTS * A/D Converter - Depending on the initial value of the up-counter C0-C15, the up/down counter TC0-TC15 may overflow while the CR oscillation clock is being counted. When setting the initial value, pay attention to CR oscillation frequency, its fluctuation range and the input clock frequency of the up/down counter. If the up/down counter overflows, A/D conversion is terminated immediately, and correct measurement is impossible. - If the up/down counter TC0-TC15 is measured after A/D conversion, it may not indicate "0000H". This is not due to incorrect timing in terminating A/D conversion but because the counting down clock is input after the control signal is output to the up-counter to terminate counting. * Supply Voltage Detection (SVD) Circuit Since supply voltage detection is automatically performed by the hardware every 2 Hz (0.5 sec) when the heavy load protection function operates, do not permit the operation of the SVD circuit by the software in order to minimize power current consumption. * Heavy Load Protection Function In the heavy load protection function (heavy load protection mode flag = "1"), supply voltage detection through the SVDON register is not permitted in order to minimize power current consumption. * Interrupt - Restart from the HALT state is performed by the interrupt. The return address after completion of the interrupt processing in this case will be the address following the HALT instruction. - When interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI state. After completion of the interrupt processing, set to the EI state through the software as needed. Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning of the interrupt processing routine. II-68 EPSON S1C62N51 TECHNICAL SOFTWARE CHAPTER 4: SUMMARY OF PROGRAMMING POINTS - Be sure to reset the interrupt factor flag before setting to the EI state on the interrupt processing routine. The interrupt factor flag is reset by reading through the software. Not resetting the interrupt factor flag and interrupt mask register being "1", will cause the same interrupt to occur again. - The interrupt factor flag will be reset by reading through the software. Because of this, when multiple interrupt factor flags are to be assigned to the same address, perform the flag check after the contents of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the interrupt factor flag to be reset. - Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. * Vacant Register and Read/Write S1C62N51 TECHNICAL SOFTWARE Writing data into the addresses where read/write bits and read only bits are mixed in 1 word (4 bits) does not affect the read only bits. EPSON II-69 APPENDIX A TABLE OF INSTRUCTIONS APPENDIX A Table of Instructions Operation Code Flag Classification Mnemonic Operand Branch PSET p 1 1 1 0 0 1 0 p4 p3 p2 p1 p0 5 NBP p4, NPP p3~p0 s 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 C, s 0 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if C=1 NC, s 0 0 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if C=0 Z, s 0 1 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if Z=1 instructions JP B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation NZ, s 0 1 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if Z=0 JPBA 1 1 1 1 1 1 1 0 1 0 0 0 5 PCB NBP, PCP NPP, PCSH B, PCSL A CALL s 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 7 M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1 CALZ s 0 1 0 1 s7 s6 s5 s4 s3 s2 s1 s0 7 RET 1 1 1 1 1 1 0 1 1 1 1 1 7 RETS 1 1 1 1 1 1 0 1 1 1 1 0 12 SP SP-3, PCP NPP, PCS s7~s0 M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1 SP SP-3, PCP 0, PCS s7~s0 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3, PC PC+1 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) RETD l 0 0 0 1 l7 l6 l5 l4 l3 l2 l1 l0 12 System NOP5 1 1 1 1 1 1 1 1 1 0 1 1 5 No operation (5 clock cycles) control NOP7 1 1 1 1 1 1 1 1 1 1 1 1 7 No operation (7 clock cycles) SP SP+3, M(X) i3~i0, M(X+1) l7~l4, X X+2 instructions HALT 1 1 1 1 1 1 1 1 1 0 0 0 5 Halt (stop clock) X 1 1 1 0 1 1 1 0 0 0 0 0 5 X X+1 operation Y 1 1 1 0 1 1 1 1 0 0 0 0 5 Y Y+1 instructions LD X, x 1 0 1 1 x7 x6 x5 x4 x3 x2 x1 x0 5 XH x7~x4, XL x3~x0 Y, y 1 0 0 0 y7 y6 y5 y4 y3 y2 y1 y0 5 YH y7~y4, YL y3~y0 XH, r 1 1 1 0 1 0 0 0 0 1 r1 r0 5 XH r XL, r Index INC ADC II-70 1 1 1 0 1 0 0 0 1 0 r1 r0 5 XL r YH, r 1 1 1 0 1 0 0 1 0 1 r1 r0 5 YH r YL, r 1 1 1 0 1 0 0 1 1 0 r1 r0 5 YL r r, XH 1 1 1 0 1 0 1 0 0 1 r1 r0 5 r XH r, XL 1 1 1 0 1 0 1 0 1 0 r1 r0 5 r XL r, YH 1 1 1 0 1 0 1 1 0 1 r1 r0 5 r YH r, YL 5 r YL 1 1 1 0 1 0 1 1 1 0 r1 r0 XH, i 1 0 1 0 0 0 0 0 i3 i2 i1 i0 7 XH XH+i3~i0+C XL, i 1 0 1 0 0 0 0 1 i3 i2 i1 i0 7 XL XL+i3~i0+C YH, i 1 0 1 0 0 0 1 0 i3 i2 i1 i0 7 YH YH+i3~i0+C YL, i 7 YL YL+i3~i0+C 1 0 1 0 0 0 1 1 i3 i2 i1 i0 EPSON S1C62N51 TECHNICAL SOFTWARE APPENDIX A TABLE OF INSTRUCTIONS Operation Code Flag Classification Mnemonic Operand Index CP XH, i 1 0 1 0 0 1 0 0 i3 i2 i1 i0 7 XH-i3~i0 operation XL, i 1 0 1 0 0 1 0 1 i3 i2 i1 i0 7 XL-i3~i0 instructions YH, i 1 0 1 0 0 1 1 0 i3 i2 i1 i0 7 YH-i3~i0 YL, i 1 0 1 0 0 1 1 1 i3 i2 i1 i0 7 YL-i3~i0 r, i 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 5 r i3~i0 transfer r, q 1 1 1 0 1 1 0 0 r1 r0 q1 q0 5 r q instructions A, Mn 1 1 1 1 1 0 1 0 n3 n2 n1 n0 5 A M(n3~n0) B, Mn 1 1 1 1 1 0 1 1 n3 n2 n1 n0 5 B M(n3~n0) Mn, A 1 1 1 1 1 0 0 0 n3 n2 n1 n0 5 M(n3~n0) A Mn, B 1 1 1 1 1 0 0 1 n3 n2 n1 n0 5 M(n3~n0) B LDPX MX, i 1 1 1 0 0 1 1 0 i3 i2 i1 i0 5 M(X) i3~i0, X X+1 1 1 1 0 1 1 1 0 r1 r0 q1 q0 5 r q, X X+1 LDPY MY, i 1 1 1 0 0 1 1 1 i3 i2 i1 i0 Data LD r, q B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation 5 M(Y) i3~i0, Y Y+1 1 1 1 0 1 1 1 1 r1 r0 q1 q0 5 r q, Y Y+1 LBPX MX, l 1 0 0 1 l7 l6 l5 l4 l3 l2 l1 l0 5 M(X) l3~l0, M(X+1) l7~l4, X X+2 r, q Flag SET F, i 1 1 1 1 0 1 0 0 i3 i2 i1 i0 7 F F i3~i0 operation RST F, i 1 1 1 1 0 1 0 1 i3 i2 i1 i0 7 F F i3~i0 instructions SCF 1 1 1 1 0 1 0 0 0 0 0 1 7 C 1 RCF 1 1 1 1 0 1 0 1 1 1 1 0 7 C 0 SZF 1 1 1 1 0 1 0 0 0 0 1 0 7 Z 1 RZF 1 1 1 1 0 1 0 1 1 1 0 1 7 Z 0 SDF 1 1 1 1 0 1 0 0 0 1 0 0 7 D 1 (Decimal Adjuster ON) RDF 1 1 1 1 0 1 0 1 1 0 1 1 7 D 0 (Decimal Adjuster OFF) EI 1 1 1 1 0 1 0 0 1 0 0 0 7 I 1 (Enables Interrupt) DI 1 1 1 1 0 1 0 1 0 1 1 1 7 I 0 (Disables Interrupt) Stack INC SP 1 1 1 1 1 1 0 1 1 0 1 1 5 SP SP+1 operation DEC SP 1 1 1 1 1 1 0 0 1 0 1 1 5 SP SP-1 1 1 1 1 1 1 0 0 0 0 r1 r0 5 SP SP-1, M(SP) r XH 1 1 1 1 1 1 0 0 0 1 0 1 5 SP SP-1, M(SP) XH XL 1 1 1 1 1 1 0 0 0 1 1 0 5 SP SP-1, M(SP) XL YH 1 1 1 1 1 1 0 0 1 0 0 0 5 SP SP-1, M(SP) YH YL 1 1 1 1 1 1 0 0 1 0 0 1 5 SP SP-1, M(SP) YL F 1 1 1 1 1 1 0 0 1 0 1 0 5 SP SP-1, M(SP) F r 1 1 1 1 1 1 0 1 0 0 r1 r0 5 r M(SP), SP SP+1 XH 1 1 1 1 1 1 0 1 0 1 0 1 5 XH M(SP), SP SP+1 XL 1 1 1 1 1 1 0 1 0 1 1 0 5 XL M(SP), SP SP+1 instructions PUSH r POP S1C62N51 TECHNICAL SOFTWARE EPSON II-71 APPENDIX A TABLE OF INSTRUCTIONS Operation Code Flag Classification Mnemonic Operand Stack POP YH 1 1 1 1 1 1 0 1 1 0 0 0 5 YH M(SP), SP SP+1 operation YL 1 1 1 1 1 1 0 1 1 0 0 1 5 YL M(SP), SP SP+1 instructions F 1 1 1 1 1 1 0 1 1 0 1 0 5 F M(SP), SP SP+1 SPH, r 1 1 1 1 1 1 1 0 0 0 r1 r0 5 SPH r SPL, r 1 1 1 1 1 1 1 1 0 0 r1 r0 5 SPL r r, SPH 1 1 1 1 1 1 1 0 0 1 r1 r0 5 r SPH r, SPL 1 1 1 1 1 1 1 1 0 1 r1 r0 5 r SPL LD Arithmetic Clock Operation r, i 1 1 0 0 0 0 r1 r0 i3 i2 i1 i0 7 r r+i3~i0 r, q 1 0 1 0 1 0 0 0 r1 r0 q1 q0 7 r r+q r, i 1 1 0 0 0 1 r1 r0 i3 i2 i1 i0 7 r r+i3~i0+C r, q 1 0 1 0 1 0 0 1 r1 r0 q1 q0 7 r r+q+C SUB r, q 1 0 1 0 1 0 1 0 r1 r0 q1 q0 7 r r-q SBC r, i 1 1 0 1 0 1 r1 r0 i3 i2 i1 i0 7 r r-i3~i0-C r, q 1 0 1 0 1 0 1 1 r1 r0 q1 q0 7 r r-q-C r, i 1 1 0 0 1 0 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 0 0 r1 r0 q1 q0 7 r r q r, i 1 1 0 0 1 1 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 0 1 r1 r0 q1 q0 7 r r q r, i 1 1 0 1 0 0 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 1 0 r1 r0 q1 q0 7 r r q r, i 1 1 0 1 1 1 r1 r0 i3 i2 i1 i0 7 r-i3~i0 r, q 1 1 1 1 0 0 0 0 r1 r0 q1 q0 7 r-q r, i 1 1 0 1 1 0 r1 r0 i3 i2 i1 i0 7 r i3~i0 ADD instructions ADC AND OR XOR CP FAN r, q 1 1 1 1 0 0 0 1 r1 r0 q1 q0 7 r q RLC r 1 0 1 0 1 1 1 1 r1 r0 r1 r0 7 d3 d2, d2 d1, d1 d0, d0 C, C d3 RRC r 1 1 1 0 1 0 0 0 1 1 r1 r0 5 d3 C, d2 d3, d1 d2, d0 d1, C d0 INC Mn 1 1 1 1 0 1 1 0 n3 n2 n1 n0 7 M(n3~n0) M(n3~n0)+1 DEC Mn 1 1 1 1 0 1 1 1 n3 n2 n1 n0 7 M(n3~n0) M(n3~n0)-1 ACPX MX, r 1 1 1 1 0 0 1 0 1 0 r1 r0 7 M(X) M(X)+r+C, X X+1 ACPY MY, r 1 1 1 1 0 0 1 0 1 1 r1 r0 7 M(Y) M(Y)+r+C, Y Y+1 SCPX MX, r 1 1 1 1 0 0 1 1 1 0 r1 r0 7 M(X) M(X)-r-C, X X+1 SCPY MY, r 1 1 1 1 0 0 1 1 1 1 r1 r0 7 M(Y) M(Y)-r-C, Y Y+1 7 r r NOT II-72 B A 9 8 7 6 5 4 3 2 1 0 I D Z C r 1 1 0 1 0 0 r1 r0 1 1 1 1 EPSON S1C62N51 TECHNICAL SOFTWARE APPENDIX A TABLE OF INSTRUCTIONS Abbreviations used in the explanations have the following meanings. Symbols associated with A .............. A register registers and memory B .............. B register X .............. XHL register (low order eight bits of index register IX) Y .............. YHL register (low order eight bits of index register IY) XH ........... XH register (high order four bits of XHL register) XL ............ XL register (low order four bits of XHL register) YH ............ YH register (high order four bits of YHL register) YL ............ YL register (low order four bits of YHL register) XP ............ XP register (high order four bits of index register IX) YP ............ YP register (high order four bits of index register IY) SP ............ Stack pointer SP SPH .......... High-order four bits of stack pointer SP SPL .......... Low-order four bits of stack pointer SP MX, M(X) .. Data memory whose address is specified with index register IX MY, M(Y) ... Data memory whose address is specified with index register IY Mn, M(n) .. Data memory address 000H-00FH (address specified with immediate data n of 00H-0FH) M(SP) ....... Data memory whose address is specified with stack pointer SP r, q ........... Two-bit register code r, q is two-bit immediate data; according to the contents of these bits, they indicate registers A, B, and MX and MY (data memory whose addresses are specified with index registers IX and IY) r S1C62N51 TECHNICAL SOFTWARE q r1 r0 q1 q0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 EPSON Registers specified A B MX MY II-73 APPENDIX A TABLE OF INSTRUCTIONS Symbols associated with NBP ..... program counter NPP ..... PCB ..... PCP ..... PCS ..... PCSH .. PCSL ... New bank pointer New page pointer Program counter bank Program counter page Program counter step Four high order bits of PCS Four low order bits of PCS Symbols associated with F ......... Flag register (I, D, Z, C) flags C ......... Carry flag Z ......... Zero flag D ......... Decimal flag I .......... Interrupt flag ............. Flag reset ............. Flag set .......... Flag set or reset Associated with p ......... immediate data s .......... l .......... i .......... Five-bit immediate data or label Eight-bit immediate data or label Eight-bit immediate data Four-bit immediate data 00H-1FH 00H-0FFH 00H-0FFH 00H-0FH Associated with + ......... Add arithmetic and other - .......... Subtract operations ............. Logical AND ............. Logical OR ............ Exclusive-OR ......... Add-subtract instruction for decimal operation when the D flag is set II-74 EPSON S1C62N51 TECHNICAL SOFTWARE S1C62N51 TECHNICAL SOFTWARE EPSON LSB MAME MSB 4 LSB LSB MAME MSB MSB LSB MAME 3 2 LSB MAME MSB 0 1 2 3 4 5 6 7 8 9 A B C D E / F B 1 H L 0 MAME MSB APPENDIX P 0 PROGRAM NAME: C251_____ APPENDIX B RAM MAP RAM Map II-75 II-76 P 0 EPSON LSB LSB F MAME MSB LSB E MAME MSB MSB LSB A MAME H L 9 MAME MSB -- -- -- -- -- -- -- ZADRUN -- -- -- ZIAD -- -- -- -- -- ZK01 -- -- -- ZK02 -- -- -- ZK00 -- -- 2 -- 1 ZK03 0 PROGRAM NAME: C251_____ ZR00 ZR01 ZR02 ZR03 -- ZTM0 ZTM1 ZTM2 ZTM3 -- 3 ZP00 ZP01 ZP02 ZP03 -- ZTC0 ZTC1 ZTC2 ZTC3 -- 4 ZC0 ZC1 ZC2 ZC3 -- ZTC4 ZTC5 ZTC6 ZTC7 -- 5 ZC4 ZC5 ZC6 ZC7 -- ZTC8 ZTC9 ZTC10 ZTC11 -- 6 ZC8 ZC9 ZC10 ZC11 -- ZTC12 ZTC13 ZTC14 ZTC15 -- 7 ZC12 ZC13 ZC14 ZC15 -- ZEIK00 ZEIK01 ZEIK02 ZEIK03 -- 8 -- ZEIT32 ZEIT8 ZEIT2 -- -- B ZSVDDT -- -- -- -- ZHLMOD ZCSDC -- -- -- -- -- -- A ZTMRST ZSVDON -- -- -- -- -- -- -- -- -- 9 ZIOC -- -- -- -- ZEIAD -- -- -- -- C -- -- -- -- -- -- -- -- -- E ZFOUT0 ZADCLK ZFOUT1 -- ZXBZR -- ZIK0 -- -- -- -- D / -- -- -- -- -- ZIT32 ZIT8 ZIT2 -- -- F APPENDIX B RAM MAP S1C62N51 TECHNICAL SOFTWARE APPENDIX C TABLE OF THE ICE COMMANDS APPENDIX C Item No. Function 1 2 3 Assemble Disassemble Dump 4 Fill 5 Set Run Mode 6 Trace 7 Break Table of the ICE Commands Command Format #A,a #L,a1,a2 #DP,a1,a2 #DD,a1,a2 #FP,a1,a2,d #FD,a1,a2,d #G,a #TIM #OTF #T,a,n #U,a,n #BA,a #BAR,a #BD #BDR #BR #BRR #BM #BMR 8 Move #BRES #BC #BE #BSYN #BT #BRKSEL,REM #MP,a1,a2,a3 #MD,a1,a2,a3 9 Data Set 10 Change CPU Internal Registers #SP,a #SD,a #DR #SR #I #DXY #SXY S1C62N51 TECHNICAL SOFTWARE Outline of Operation Assemble command mnemonic code and store at address "a" Contents of addresses a1 to a2 are disassembled and displayed Contents of program area a1 to a2 are displayed Content of data area a1 to a2 are displayed Data d is set in addresses a1 to a2 (program area) Data d is set in addresses a1 to a2 (data area) Program is executed from the "a" address Execution time and step counter selection On-the-fly display selection Executes program while displaying results of step instruction from "a" address Displays only the final step of #T,a,n Sets Break at program address "a" Breakpoint is canceled Break condition is set for data RAM Breakpoint is canceled Break condition is set for Evaluation Board CPU internal registers Breakpoint is canceled Combined break conditions set for program data RAM address and registers Cancel combined break conditions for program data ROM address and registers All break conditions canceled Break condition displayed Enter break enable mode Enter break disable mode Set break stop/trace modes Set BA condition clear/remain modes Contents of program area addresses a1 to a2 are moved to addresses a3 and after Contents of data area addresses a1 to a2 are moved to addresses a3 and after Data from program area address "a" are written to memory Data from data area address "a" are written to memory Display Evaluation Board CPU internal registers Set Evaluation Board CPU internal registers Reset Evaluation Board CPU Display X, Y, MX and MY Set data for X and Y display and MX, MY EPSON II-77 APPENDIX C TABLE OF THE ICE COMMANDS Item No. 11 Function History Command Format #HSW,a #HSR,a #RF,file #RFD,file #VF,file #VFD,file #WF,file #WFD,file #CL,file #CS,file #CVD #CVR #RP #VP #ROM #Q #HELP Display ICE instruction #CHK Report results of ICE self diagnostic test #HA,a1,a2 #HAR,a1,a2 #HAD #HS,a 12 File 13 Coverage 14 ROM Access 15 Terminate ICE Command Display Self Diagnosis 16 17 Outline of Operation Display history data for pointer 1 and pointer 2 Display upstream history data Display 21 line history data Display history pointer Set history pointer Sets up the history information acquisition before (S), before/after (C) and after (E) Sets up the history information acquisition from program area a1 to a2 Sets up the prohibition of the history information acquisition from program area a1 to a2 Indicates history acquisition program area Retrieves and indicates the history information which executed a program address "a" Retrieves and indicates the history information which wrote or read the data area address "a" Move program file to memory Move data file to memory Compare program file and contents of memory Compare data file and contents of memory Save contents of memory to program file Save contents of memory to data file Load ICE set condition from file Save ICE set condition to file Indicates coverage information Clears coverage information Move contents of ROM to program memory Compare contents of ROM with contents of program memory Set ROM type Terminate ICE and return to operating system control #H,p1,p2 #HB #HG #HP #HPS,a #HC,S/C/E means press the RETURN key. II-78 EPSON S1C62N51 TECHNICAL SOFTWARE APPENDIX D CROSS-ASSEMBLER PSEUDO-INSTRUCTION LIST APPENDIX D Cross-assembler Pseudo-instruction List Item No. Pseudo-instruction 1 EQU Meaning Example of Use To allocate data to label (Equation) 2 ORG ABC EQU 9 BCD EQU ABC+1 ORG 100H ORG 256 To define location counter (Origin) 3 4 SET To allocate data to label ABC SET 0001H (Set) (data can be changed) ABC SET 0002H DW To define ROM data ABC DW 'AB' BCD DW 0FFBH PAGE 1H PAGE 3 (Define Word) 5 PAGE To define boundary of page (Page) 6 SECTION To define boundary of section SECTION To terminate assembly END (Section) 7 END (End) 8 MACRO To define macro (Macro) 9 10 CHECK MACRO DATA LOCAL To make local specification of label LOCAL LOOP (Local) during macro definition LOOP CP MX,DATA JP NZ,LOOP ENDM To end macro definition ENDM (End Macro) CHECK S1C62N51 TECHNICAL SOFTWARE EPSON 1 II-79 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. 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FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C62N51 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue February, 1992 Printed March, 2001 in Japan M A