S1C62N51D - Seiko Epson Corporation

MF616-03

Technical Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C62N51 Technical Hardware/S1C62N51 Technical Software

S1C62N51

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko

Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or

circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such

as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there

is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright

infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic

products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from

the Ministry of International Trade and Industry or other approval from another government agency.

PREFACE

This manual is individualy described about the hardware and the software

of the S1C62N51.

II. S1C62N51 Technical Software

This part explains the programming method of the S1C62N51.

I. S1C62N51 Technical Hardware

This part explains the function of the S1C62N51, the circuit configu-

rations, and details the controlling method.

Hardware

Software

The information of the product number change

Configuration of product number

Devices

Comparison table between new and previous number

S1C60 Family processors

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales

representative.

S1 C60N01 F0A01 Packing specification

Specification

Package (D: die form; F: QFP)

Model number

Model name (C: microcomputer, digital products)

Product classification (S1: semiconductor)

Development tools

S5U1 C60R08 D1 1Packing specification

Version (1: Version 1 ∗2)

Tool type (D1: Development Tool ∗1)

Corresponding model number (60R08: for S1C60R08)

Tool classification (C: microcomputer use)

Product classification

(S5U1: development tool for semiconductor products)

∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)

∗2: Actual versions are not written in the manuals.

Previous No.

E0C6001

E0C6002

E0C6003

E0C6004

E0C6005

E0C6006

E0C6007

E0C6008

E0C6009

E0C6011

E0C6013

E0C6014

E0C60R08

New No.

S1C60N01

S1C60N02

S1C60N03

S1C60N04

S1C60N05

S1C60N06

S1C60N07

S1C60N08

S1C60N09

S1C60N11

S1C60N13

S1C60140

S1C60R08

S1C62 Family processors

Previous No.

E0C621A

E0C6215

E0C621C

E0C6S27

E0C6S37

E0C623A

E0C623E

E0C6S32

E0C6233

E0C6235

E0C623B

E0C6244

E0C624A

E0C6S46

New No.

S1C621A0

S1C62150

S1C621C0

S1C6S2N7

S1C6S3N7

S1C6N3A0

S1C6N3E0

S1C6S3N2

S1C62N33

S1C62N35

S1C6N3B0

S1C62440

S1C624A0

S1C6S460

Previous No.

E0C6247

E0C6248

E0C6S48

E0C624C

E0C6251

E0C6256

E0C6292

E0C6262

E0C6266

E0C6274

E0C6281

E0C6282

E0C62M2

E0C62T3

New No.

S1C62470

S1C62480

S1C6S480

S1C624C0

S1C62N51

S1C62560

S1C62920

S1C62N62

S1C62660

S1C62740

S1C62N81

S1C62N82

S1C62M20

S1C62T30

Comparison table between new and previous number of development tools

Development tools for the S1C60/62 Family

Previous No.

ASM62

DEV6001

DEV6002

DEV6003

DEV6004

DEV6005

DEV6006

DEV6007

DEV6008

DEV6009

DEV6011

DEV60R08

DEV621A

DEV621C

DEV623B

DEV6244

DEV624A

DEV624C

DEV6248

DEV6247

New No.

S5U1C62000A

S5U1C60N01D

S5U1C60N02D

S5U1C60N03D

S5U1C60N04D

S5U1C60N05D

S5U1C60N06D

S5U1C60N07D

S5U1C60N08D

S5U1C60N09D

S5U1C60N11D

S5U1C60R08D

S5U1C621A0D

S5U1C621C0D

S5U1C623B0D

S5U1C62440D

S5U1C624A0D

S5U1C624C0D

S5U1C62480D

S5U1C62470D

Previous No.

DEV6262

DEV6266

DEV6274

DEV6292

DEV62M2

DEV6233

DEV6235

DEV6251

DEV6256

DEV6281

DEV6282

DEV6S27

DEV6S32

DEV6S37

EVA6008

EVA6011

EVA621AR

EVA621C

EVA6237

EVA623A

New No.

S5U1C62620D

S5U1C62660D

S5U1C62740D

S5U1C62920D

S5U1C62M20D

S5U1C62N33D

S5U1C62N35D

S5U1C62N51D

S5U1C62560D

S5U1C62N81D

S5U1C62N82D

S5U1C6S2N7D

S5U1C6S3N2D

S5U1C6S3N7D

S5U1C60N08E

S5U1C60N11E

S5U1C621A0E2

S5U1C621C0E

S5U1C62N37E

S5U1C623A0E

Previous No.

EVA623B

EVA623E

EVA6247

EVA6248

EVA6251R

EVA6256

EVA6262

EVA6266

EVA6274

EVA6281

EVA6282

EVA62M1

EVA62T3

EVA6S27

EVA6S32R

ICE62R

KIT6003

KIT6004

KIT6007

New No.

S5U1C623B0E

S5U1C623E0E

S5U1C62470E

S5U1C62480E

S5U1C62N51E1

S5U1C62N56E

S5U1C62620E

S5U1C62660E

S5U1C62740E

S5U1C62N81E

S5U1C62N82E

S5U1C62M10E

S5U1C62T30E

S5U1C6S2N7E

S5U1C6S3N2E2

S5U1C62000H

S5U1C60N03K

S5U1C60N04K

S5U1C60N07K

Hardware

S1C62N51

Technical Hardware

Hardware

S1C62N51 TECHNICAL HARDWARE EPSON I-i

CONTENTS

CHAPTER 1 INTRODUCTION............................................................... I-1

1.1 Configuration ................................................................... I-1

1.2 Features .......................................................................... I-2

1.3 Block Diagram ................................................................. I-3

1.4 Pin Layout Diagram......................................................... I-4

1.5 Pin Description ................................................................ I-5

CHAPTER 2 POWER SUPPLY AND INITIAL RESET ................................ I-6

2.1 Power Supply .................................................................. I-6

2.2 Initial Reset...................................................................... I-7

Oscillation detection circuit...................................... I-8

Reset pin (RESET) .................................................... I-8

Simultaneous high input to input ports (K00–K03) ... I-8

Internal register following initialization..................... I-9

2.3 Test Pin (TEST)............................................................... I-9

CHAPTER 3 CPU, ROM, RAM ............................................................ I-10

3.1 CPU................................................................................ I-10

3.2 ROM ............................................................................... I-11

3.3 RAM ............................................................................... I-11

I-ii EPSON S1C62N51 TECHNICAL HARDWARE

CONTENTS

CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-12

4.1 Memory Map .................................................................. I-12

4.2 Oscillation Circuit............................................................ I-15

Crystal oscillation circuit......................................... I-15

CR oscillation circuit ............................................... I-16

4.3 Input Ports (K00–K03).................................................... I-17

Configuration of input ports .................................... I-17

Input comparison registers and interrupt function .. I-18

Mask option ............................................................ I-19

Control of input ports.............................................. I-19

4.4 Output Ports (R00–R03)................................................. I-21

Configuration of output ports .................................. I-21

Mask option ............................................................ I-22

Control of output ports............................................ I-24

4.5 I/O Ports (P00–P03) ....................................................... I-27

Configuration of I/O ports....................................... I-27

I/O control register and I/O mode........................... I-27

Mask option ............................................................ I-28

Control of I/O ports ................................................ I-28

4.6 LCD Driver (COM0–COM3, SEG0–SEG25) .................. I-30

Configuration of LCD driver..................................... I-30

Switching between dynamic and static drive............ I-33

Mask option (segment allocation)............................. I-34

Control of LCD driver .............................................. I-36

4.7 Clock Timer .................................................................... I-37

Configuration of clock timer .................................... I-37

Interrupt function ................................................... I-38

Control of clock timer.............................................. I-39

Hardware

S1C62N51 TECHNICAL HARDWARE EPSON I-iii

CONTENTS

4.8 A/D Converter................................................................. I-41

Configuration of A/D converter ............................... I-41

Operation of A/D converter ..................................... I-42

Interrupt function ................................................... I-47

Usage example of the A/D converter........................ I-47

Control of A/D converter ......................................... I-49

4.9 Supply Voltage Detection (SVD) Circuit

and Heavy Load Protection Function ............................. I-53

Configuration of SVD circuit

and heavy load protection function.......................... I-53

Operation of SVD detection timing .......................... I-55

Operation of heavy load protection function ............ I-56

Control of SVD circuit

and heavy load protection function.......................... I-57

4.10 Interrupt and HALT......................................................... I-59

Interrupt factors...................................................... I-60

Specific masks and factor flags for interrupt............ I-61

Interrupt vectors ..................................................... I-61

Control of interrupt ................................................. I-62

CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM............................ I-63

CHAPTER 6 ELECTRICAL CHARACTERISTICS .................................... I-65

6.1 Absolute Maximum Rating ............................................. I-65

6.2 Recommended Operating Conditions ............................ I-66

6.3 DC Characteristics ......................................................... I-67

6.4 Analog Circuit Characteristics

and Power Current Consumption ................................... I-69

6.5 Oscillation Characteristics .............................................. I-73

I-iv EPSON S1C62N51 TECHNICAL HARDWARE

CONTENTS

CHAPTER 7 PACKAGE ...................................................................... I-75

7.1 Plastic Package.............................................................. I-75

7.2 Ceramic Package for Test Samples............................... I-76

CHAPTER 8 PAD LAYOUT .................................................................. I-77

8.1 Diagram of Pad Layout................................................... I-77

8.2 Pad Coordinates............................................................. I-78

S1C62N51 TECHNICAL HARDWARE EPSON I-1

CHAPTER 1: INTRODUCTION

CHAPTER 1

1.1

Table 1.1.1

Configuration of the

S1C62N51 Series

INTRODUCTION

Each member of the S1C62N51 Series of single chip micro-

computers feature a 4-bit S1C6200A core CPU, 1,024 words

of ROM (12 bits per word), 80 words of RAM (4 bits per

word), an LCD driver, 4 bits for input ports (K00–K03), 4

bits for output ports (R00–R03), one 4-bit I/O port (P00–

P03), clock timer and A/D converter.

Because of their low voltage operation and low power con-

sumption, the S1C62N51 Series are ideal for a wide range of

applications.

Configuration

The S1C62N51 Series are configured as follows, depending

on the supply voltage.

Model Supply voltage Oscillation circuits

3.0 V

1.5 V

S1C62N51

S1C62L51

Crystal or CR

I-2 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

Features

1.5 V / 3 V

Crystal or CR oscillation circuit, 32,768 Hz (typ.)

100 instructions

1,024 words × 12 bits

80 words × 4 bits

4 bits (Supplementary pull-down resistors may be used)

4 bits (Piezo buzzer and programmable frequency output

can be driven directry by mask option)

4 bits

26 segments × 4 common duty (or 3 and 2 common duty)

Clock timer

CR oscillation type A/D converter built-in

1.2 V / 2.4 V

Input port interrupt 1 system

Timer interrupt 1 system

A/D converter interrupt 1 system

1.5 V (0.9–2.0 V) S1C62L51

1.5 V (1.2–2.0 V) S1C62L51 (During A/D conversion)

3.0 V (1.8–3.5 V) S1C62N51

1.0 µA (Crystal oscillation CLK = 32,768 Hz, when halted)

2.5 µA

(Crystal oscillation CLK = 32,768 Hz, when executing)

64-pin QFP (plastic) or chip

1.2

Supply voltage

Built-in oscillation circuit

Instruction set

ROM capacity

RAM capacity (data RAM)

Input port

Output port

Input/output port

LCD driver

Timer

A/D converter

Supply voltage detection

circuit (SVD)

Interrupts:External interrupt

Internal interrupt

Supply voltage

Current consumption (typ.)

Supply form

S1C62N51 TECHNICAL HARDWARE EPSON I-3

CHAPTER 1: INTRODUCTION

SVD

COM0–3

K00–03

P00–03

R00–03

OSC1

OSC2

RESET

SEG0–25 TEST

VL1–3

CA–CC

VS1

VSS

Power

Controller

LCD Driver

RAM

80 words x 4 bits

ROM

1,024 words x 12 bits OSC System Reset

Control

Fout & Buzzer

Interrupt

Generator

Input Port

Test Port

I/O Port

Output Port

Timer

A/D Converter

Core CPU S1C6200A

FOUT / BUZZER

BUZZER

ADOUT

1.3

Fig. 1.3.1

Block diagram

Block Diagram

I-4 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 1: INTRODUCTION

115

45 31

116

48 33

Index

1.4

QFP6-60 pin

(ceramic)

QFP6-64 pin

(plastic)

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

P00

P01

P02

P03

RESET

K00

K01

K02

K03

R00

R01

R02

R03

Pin No Pin name Pin No Pin name Pin No Pin No Pin namePin name

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

TEST

ADOUT

OSC1

OSC2

COM0

COM1

COM2

TEST

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

P00

P01

P02

P03

RESET

K00

K01

K02

K03

R00

R01

R02

R03

N.C.

Pin No Pin name Pin No Pin name Pin No Pin No Pin namePin name

COM2

COM3

N.C.

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

ADOUT

OSC1

OSC2

COM0

COM1

N.C. = No connection

Fig. 1.4.1

Pin assignment

Pin Layout Diagram

S1C62N51 TECHNICAL HARDWARE EPSON I-5

CHAPTER 1: INTRODUCTION

1.5

Table 1.5.1 Pin description

Terminal name

CA–CC

OSC1

OSC2

K00–K03

P00–P03

R00–R03

SEG0–25

COM0–3

ADOUT

RESET

TEST

QFP6-64 pin

(plastic)

31, 53

57–59

38–41

33–36

42–45

4–16

18–30

63, 64, 1, 2

Input/Output

(I)

–

I/O

Function

Power source (+) terminal

Power source (-) terminal

Oscillation and internal logic system regulated

voltage output terminal

LCD system regulated voltage output terminal

(approx. -1.05V)

LCD system booster output terminal (V 2)

LCD system booster output terminal (V 3)

Booster capacitor connecting terminal

Crystal or CR oscillation input terminal

Crystal or CR oscillation output terminal

Input terminal

I/O terminal

Output terminal

LCD segment output terminal

(convertible to DC output terminal by mask option)

LCD common output terminal

A/D converter CR oscillation input terminal

A/D converter CR oscillation output terminal

A/D converter oscillation frequency output terminal

Initial setting input terminal

Test input terminal

QFP6-60 pin

(ceramic)

29, 48

52–54

36–39

31–34

40–43

2–14

16–28

58–60, 1

Pin No.

Pin Description

I-6 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

POWER SUPPLY AND INITIAL RESETCHAPTER 2

2.1

Note

Fig. 2.1.1

Configuration of

power supply

External

power

supply

Internal

circuit

Oscillation

circuit

LCD driver

LCD

voltage

booster

LCD regulated

voltage circuit

Internal system

regulated voltage

circuit

VDD

VL1

VL2

VL3

Vss

VL1

VL2

VL3

VL1

OSC1, 2

COM0–3

SEG0–25

Power Supply

With a single external power supply (*1) supplied to VDD

through VSS, the S1C62N51 Series generate the necessary

internal voltages with the regulated voltage circuit (<VS1> for

oscillators and internal circuit, <VL1> for LCDs) and the

voltage booster (<VL2, VL3> for LCDs).

Figure 2.1.1 shows the power supply configuration.

*1 Supply voltage: 62N51...3 V, 62L51...1.5 V

- External loads cannot be driven by the output voltage of the

regulated voltage circuit and voltage booster circuit.

- See Chapter 6, "ELECTRICAL CHARACTERISTICS", for

voltage values.

S1C62N51 TECHNICAL HARDWARE EPSON I-7

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Initial Reset

To initialize the S1C62N51 Series circuits, an initial reset

must be executed. There are three ways of doing this.

(1)Initial reset by the oscillation detection circuit (

Note

)

(2)External initial reset via the RESET pin

(3)External initial reset by simultaneous high input to pins

K00–K03 (depending on mask option)

Figure 2.2.1 shows the configuration of the initial reset

circuit.

2.2

Vss

RESET

K03

K02

K01

K00

OSC2

OSC1

Oscillation

circuit

Vss

Oscillation

detection

circuit Noise

rejection

circuit

Initial

reset

Noise

rejection

circuit

Fig. 2.2.1

Configuration of

initial reset circuit

Since the circuit may sometimes not operate normally with the

initial resetting by the oscillation detection circuit indicated in

number (1), depending on the method of making the power, you

should utilize one of the initial resetting methods mentioned in

numbers (2) and (3).

Note

I-8 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

When the oscillation circuit has been stopped until the

oscillation circuit begins to oscillate when the power is

turned on or for any other reason, the oscillation detection

circuit will output an initial reset signal, but since the

circuit may sometimes not operate normally with the initial

resetting due to the oscillation detection circuit, depending

on the method of making the power, you should utilize one

of the initial resetting methods indicated hereafter.

An initial reset can be invoked externally by making the

reset pin high. This high level must be maintained for at

least 5 ms (when oscillating frequency, fosc = 32 kHz),

because the initial reset circuit contains a noise rejection

circuit. When the reset pin goes low the CPU begins to

operate.

Another way of invoking an initial reset externally is to input

a high signal simultaneously to the input ports (K00–K03)

selected with the mask option. The specified input port pins

must be kept high for at least 4 sec (when oscillating fre-

quency fosc = 32 kHz), because of the noise rejection circuit.

Table 2.2.1 shows the combinations of input ports (K00–

K03) that can be selected with the mask option.

ANot used

BK00*K01

CK00*K01*K02

DK00*K01*K02*K03

When, for instance, mask option D (K00*K01*K02*K03) is

selected, an initial reset is executed when the signals input

to the four ports K00–K03 are all high at the same time.

If you use this function, make sure that the specified ports

do not go high at the same time during normal operation.

Oscillation detection

circuit

Reset pin (RESET)

Table 2.2.1

Input port combinations

Simultaneous high

input to input ports

(K00–K03)

S1C62N51 TECHNICAL HARDWARE EPSON I-9

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Internal register fol-

lowing initialization

An initial reset initializes the CPU as shown in the table

below.

CPU Core

Name

Program counter step

Program counter page

New page pointer

Stack pointer

Index register X

Index register Y

General register A

General register B

Interrupt flag

Decimal flag

Zero flag

Carry flag

Signal

PCS

PCP

NPP

Number of bits

Setting value

00H

Undefined

Table 2.2.2

Initial values

2.3

Peripheral circuits

Name

RAM

Display memory

Other peripheral circuit

Number of bits

80 × 4

26 × 4

–

Setting value

Undefined

*1: See Section 4.1, "Memory Map"

Test Pin (TEST)

This pin is used when IC is inspected for shipment.

During normal operation connect it to VSS.

I-10 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 3: CPU, ROM, RAM

CPU, ROM, RAM

CPU

The S1C62N51 Series employs the S1C6200A core CPU, so

that register configuration, instructions, and so forth are

virtually identical to those in other processors in the family

using the S1C6200A. Refer to the "S1C6200/6200A Core

CPU Manual" for details of the S1C6200A.

Note the following points with regard to the S1C62N51

Series:

(1)The SLEEP operation is not provided, so the SLP instruc-

tion cannot be used.

(2)Because the ROM capacity is 1,024 words, 12 bits per

word, bank bits are unnecessary, and PCB and NBP are

not used.

(3)The RAM page is set to 0 only, so the page part (XP, YP)

of the index register that specifies addresses is invalid.

PUSH XP PUSH YP

POP XP POP YP

LD XP,r LD YP,r

LD r,XP LD r,YP

CHAPTER 3

3.1

S1C62N51 TECHNICAL HARDWARE EPSON I-11

CHAPTER 3: CPU, ROM, RAM

ROM

The built-in ROM, a mask ROM for the program, has a

capacity of 1,024 × 12-bit steps. The program area is 4

pages (0–3), each consisting of 256 steps (00H–FFH). After

an initial reset, the program start address is page 1, step

00H. The interrupt vector is allocated to page l, steps 01H–

07H.

3.2

RAM

The RAM, a data memory for storing a variety of data, has a

capacity of 80 words, 4-bit words. When programming,

keep the following points in mind:

(1)Part of the data memory is used as stack area when

saving subroutine return addresses and registers, so be

careful not to overlap the data area and stack area.

(2)Subroutine calls and interrupts take up three words on

the stack.

(3)Data memory 000H–00FH is the memory area pointed by

the register pointer (RP).

3.3

Fig. 3.2.1

ROM configuration

00H step

07H step

08H step

FFH step

12 bits

Program start address

Interrupt vector area

Bank 0

Program area

0 page

1 page

2 page

3 page

01H step

I-12 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

PERIPHERAL CIRCUITS AND

OPERATION

Peripheral circuits (timer, I/O, and so on) of the S1C62N51

Series are memory mapped. Thus, all the peripheral circuits

can be controlled by using memory operations to access the

I/O memory. The following sections describe how the pe-

ripheral circuits operate.

CHAPTER 4

Memory Map

The data memory of the S1C62N51 Series has an address

space of 154 words, of which 32 words are allocated to

display memory and 26 words, to I/O memory. Figure 4.1.1

show the overall memory map for the S1C62N51 Series, and

Tables 4.1.1(a) and (b), the memory maps for the peripheral

circuits (I/O space).

4.1

Address

Page High

Low 0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

RAM area (000H–04FH)

80 words x 4 bits (R/W)

Display memory area (090H–0AFH)

32 words x 4 bits (Write only)

Unused area

I/O memory area Table 4.1.1(a), (b)

Fig. 4.1.1

Memory map

Note Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

S1C62N51 TECHNICAL HARDWARE EPSON I-13

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(a) I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E0H

K00

K03

K02

K01

K00

–

Input port data K03

Input port data K02

Input port data K01

Input port data K00

High

Low

K01K02K03

0E3H

TM0

TM3

TM2

TM1

TM0

–

Clock timer data 2 Hz

Clock timer data 4 Hz

Clock timer data 8 Hz

Clock timer data 16 Hz

High

Low

TM1TM2TM3

0E4H

TC0

R/W

TC3

TC2

TC1

TC0

Up/down counter data TC3

Up/down counter data TC2

Up/down counter data TC1

Up/down counter data TC0 (LSB)

TC1TC2TC3 –

–

TC4

R/W

TC7

TC6

TC5

TC4

–

Up/down counter data TC7

Up/down counter data TC6

Up/down counter data TC5

Up/down counter data TC4

TC5TC6TC7

0E5H

0E6H

TC8

R/W

TC11

TC10

TC9

TC8

–

Up/down counter data TC11

Up/down counter data TC10

Up/down counter data TC9

Up/down counter data TC8

TC9TC10TC11

0E7H

TC12

R/W

TC15

TC14

TC13

TC12

–

Up/down counter data TC15 (MSB)

Up/down counter data TC14

Up/down counter data TC13

Up/down counter data TC12

TC13TC14TC15

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

I-14 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(b) I/O memory map

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F4H

P00

R/W

P03

P02

P01

P00

–

I/O port data P03

I/O port data P02

I/O port data P01

I/O port data P00

High

Low

P01P02P03

0F5H

R/W

Up-counter data C3

Up-counter data C2

Up-counter data C1

Up-counter data C0 (LSB)

C1C2C3 –

–

R/W

–

Up-counter data C7

Up-counter data C6

Up-counter data C5

Up-counter data C4

C5C6C7

0F6H

0F7H

R/W

C11

C10

–

Up-counter data C11

Up-counter data C10

Up-counter data C9

Up-counter data C8

C9C10C11

0F8H

C12

R/W

C15

C14

C13

C12

–

Up-counter data C15 (MSB)

Up-counter data C14

Up-counter data C13

Up-counter data C12

C13C14C15

0F9H

TMRST

TMRST Reset

Clock timer reset

Reset –

0FBH

0CSDC

LCD drive switch

Static Dynamic

0CSDC

R/W

0FDH

XFOUT0

R/W

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

FOUT frequency control

2 kHz 4 kHz

XFOUT10

XBZR

R/W

0FCH

IOC

R/W

IOC 0

I/O port I/O control register

Out In

0FEH

ADCLK

R/W

ADCLK 0

A/D clock selection 65 kHz/32 kHz

65 kHz 32 kHz

0F1H

ADRUN

R/W

ADRUN 0

A/D conversion Start/Stop

Start Stop

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

0F3H

R00

FOUT

R03

R02

R01

BUZZER

R00

FOUT

Output port data R03

Output port data R02

Output port data R01

Buzzer On/Off control register

Output port data R00

Frequency output control register

High

Low

Off

Low

Off

R01

BUZZER

R02R03

R/W

0FAH

SVDON

R/W

HLMOD

SVDDT

SVDON

Heavy load protection mode register

Supply voltage detection data

Supply voltage detection circuit On/Off

Heavy

Low

Normal

Off

SVDDT0HLMOD

R/W

S1C62N51 TECHNICAL HARDWARE EPSON I-15

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Oscillation Circuit

The S1C62N51 Series have a built-in oscillation circuit.

For the oscillation circuit, eiter crystal oscillation or CR

oscillation may be selected by a mask option.

The crystal oscillation circuit generates the operating clock

for the CPU and peripheral circuit on connection to an

external crystal oscillator (typ. 32.768 kHz) and trimmer

capacitor (5–25 pF).

Figure 4.2.1 is the block diagram of the crystal oscillation

circuit.

4.2

Crystal oscillation

circuit

Fig. 4.2.1

Crystal oscillation circuit

X'tal

OSC2

OSC1

To CPU and

peripheral circuits

The S1C62N51 Series

As Figure 4.2.1 indicates, the crystal oscillation circuit can

be configured simply by connecting the crystal oscillator

(X'tal) between the OSC1 and OSC2 pins and the trimmer

capacitor (CG) between the OSC1 and VDD pins.

I-16 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

For the S1C62N51 Series, CR oscillation circuit (typ. 65

kHz) may be selected by a mask option. Figure 4.2.2 is the

block diagram of the CR oscillation circuit.

CR oscillation circuit

Fig. 4.2.2

CR oscillation circuit

OSC2

OSC1

To CPU and

peripheral circuits

The S1C62N51 Series

RCR

As Figure 4.2.2 indicates, the CR oscillation circuit can be

configured simply by connecting the register (RCR) between

pins OSC1 and OSC2 since capacity (C) is built-in.

See Chapter 6, "ELECTRICAL CHARACTERISTICS" for R

value.

S1C62N51 TECHNICAL HARDWARE EPSON I-17

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Input Ports (K00–K03)

The S1C62N51 Series have a general-purpose input (4 bits).

Each of the input port pins (K00–K03) has an internal pull-

down resistance. The pull-down resistance can be selected

for each bit with the mask option.

Figure 4.3.1 shows the configuration of input port.

Kxx

Mask option

Address

Interrupt

request

Data bus

Selecting "pull-down resistance enabled" with the mask

option allows input from a push button, key matrix, and so

forth. When "pull-down resistance disabled" is selected, the

port can be used for slide switch input and interfacing with

other LSIs.

4.3

Configuration of

input ports

Fig. 4.3.1

Configuration of input port

I-18 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Input comparison

registers and inter-

rupt function

The interrupt mask registers (EIK00–EIK03) enable the

interrupt mask to be selected individually for K00–K03. An

interrupt occurs when the input value which are not

masked change and the interrupt factor flag (IK0) is set to

"1".

Fig. 4.3.2

Input interrupt circuit

configuration (K00–K03)

All four input port bits (K00–K03) provide the interrupt

function. The conditions for issuing an interrupt can be set

by the software for the four bits. Also, whether to mask the

interrupt function can be selected individually for all four

bits by the software. Figure 4.3.2 shows the configuration of

K00–K03.

Data bus

Address

Interrupt mask

Kxx

Address

Mask option

(K00–K03)

Noise

rejector

One for each pin series

Interrupt

request

Address

Interrupt factor

flag (IK)

S1C62N51 TECHNICAL HARDWARE EPSON I-19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

The contents that can be selected with the input port mask

option are as follows:

(1) An internal pull-down resistance can be selected for each

of the four bits of the input ports (K00–K03). Having

selected "pull-down resistance disabled", take care that

the input does not float. Select "pull-down resistance

enabled" for input ports that are not being used.

(2) The input interrupt circuit contains a noise rejection

circuit to prevent interrupts form occurring through

noise. The mask option enables selection of the noise

rejection circuit for each separate pin series. When "use"

is selected, a maximum delay of 0.5 ms (fosc = 32 kHz)

occurs from the time an interrupt condition is established

until the interrupt factor flag (IK) is set to "1".

Table 4.3.1 list the input port control bits and their ad-

dresses.

Mask option

Control of input ports

Table 4.3.1 Input port control bits

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E0H

K00

K03

K02

K01

K00

–

Input port data K03

Input port data K02

Input port data K01

Input port data K00

High

Low

K01K02K03

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

I-20 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Input port data (0E0H)

The input data of the input port pins can be read with these

registers.

When "1" is read: High level

When "0" is read: Low level

Writing: Invalid

The value read is "1" when the pin voltage of the four bits of

the input ports (K00–K03) goes high (VDD), and "0" when the

voltage goes low (VSS). These bits are reading, so writing

cannot be done.

Interrupt mask registers (0E8H)

Masking the interrupt of the input port pins can be done

with these registers.

When "1" is written: Enable

When "0" is written: Mask

Reading: Valid

With these registers, masking of the input port bits can be

done for each of the four bits. After an initial reset, these

registers are all set to "0".

Interrupt factor flags (0EDH D0)

These flags indicate the occurrence of an input interrupt.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flag IK0 is associated with K00–K03,

respectively. From the status of these flags, the software

can decide whether an input interrupt has occurred.

These flags are reset when the software has read them.

Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to "1", an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated.

After an initial reset, these flags are set to "0".

K00–K03

IK0

EIK00–EIK03

S1C62N51 TECHNICAL HARDWARE EPSON I-21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Output Ports (R00–R03)

The S1C62N51 Series have 4 bits for general output ports

(R00–R03).

Output specifications of the output ports can be selected

individually with the mask option. Three kinds of output

specifications are available: complementary output and Pch

open drain output. Also, the mask option enables the

output ports R00 and R01 to be used as special output

ports. Figure 4.4.1 shows the configuration of the output

ports.

Configuration of

output ports

4.4

Data bus

Address

Rxx

Complementary

Pch open drain

Mask option

Fig. 4.4.1

Configuration of output ports

I-22 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

The mask option enables the following output port selection.

(1)Output specifications of output ports

The output specifications for the output ports (R00–R03)

may be either complementary output or Pch open drain

output for each of the four bits. However, even when Pch

open drain output is selected, a voltage exceeding the

source voltage must not be applied to the output port.

(2)Special output

In addition to the regular DC output, special output can

be selected for output ports R00 and R01, as shown in

Table 4.4.1. Figure 4.4.2 shows the structure of output

ports R00–R03.

Mask option

Table 4.4.1

Special output

FOUT or BUZZER

BUZZER

R00

R01

Pin name When special output is selected

Fig. 4.4.2

Structure of output port

R00–R03

Address

(0F3H)

FOUT

Data bus

Mask option

R02

R01

BUZZER

(R03) R03

R00

BUZZER

(R02)

(R01)

(R00)

S1C62N51 TECHNICAL HARDWARE EPSON I-23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

FOUT (R00) When output port R00 is set for FOUT output, this port will

generate fosc (CPU operating clock frequency) or clock

frequency divided into fosc. Clock frequency may be se-

lected individually for F1–F4, from among 5 types by mask

option; one among F1–F4 is selected by software and used.

The types of frequency which may be selected are shown in

Table 4.4.2.

Output ports R01 and R00 may be set to BUZZER output

and BUZZER output (BUZZER reverse output), respectively,

allowing for direct driving of the piezo-electric buzzer.

BUZZER output (R00) may only be set if R01 is set to

BUZZER output. In such case, whether ON/OFF of the

BUZZER output is done through R00 register or is control-

led through R01 simultaneously with BUZZER output is

also selected by mask option.

The frequency of buzzer output may be selected by software

to be either 2 kHz or 4 kHz.

Table 4.4.2

FOUT clock frequency

A hazard may occur when the FOUT signal is turned on or off.Note

(D1, D0) = (XFOUT1, XFOUT0)

Setting

value

Clock frequency (Hz)

256

(fosc/128) 512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

8,192

(fosc/4)

1,024

(fosc/32) 2,048

(fosc/16) 4,096

(fosc/8)

4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

4,096

(fosc/8)

32,768

(fosc/1)

2,048

(fosc/16) 4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)

F1 F2 F3 F4

fosc = 32,768

BUZZER, BUZZER

(R01, R00)

I-24 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Output port data (0F3H)

Sets the output data for the output ports.

When "1" is written: High output

When "0" is written: Low output

Reading: Valid

The output port pins output the data written to the corre-

sponding registers (R00–R03) without changing it. When "1"

is written to the register, the output port pin goes high

(VDD), and when "0" is written, the output port pin goes low

(VSS). After an initial reset, all registers are set to "0".

R00–R03

Table 4.4.3 Control bits of output ports

Control of output

ports

Table 4.4.3 lists the output port control bits and their ad-

dresses.

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F3H

R00

FOUT

R03

R02

R01

BUZZER

R00

FOUT

Output port data R03

Output port data R02

Output port data R01

Buzzer On/Off control register

Output port data R00

Frequency output control register

High

Low

Off

Low

Off

R01

BUZZER

R02R03

R/W

0FDH

XFOUT0

R/W

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

FOUT frequency control

2 kHz 4 kHz

XFOUT10

XBZR

R/W

S1C62N51 TECHNICAL HARDWARE EPSON I-25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Special output port data (0F3H D0)

Controls the FOUT (clock) output.

When "1" is written: Clock output

When "0" is written: Low level (DC) output

Reading: Valid

FOUT output can be controlled by writing data to R00. After

an initial reset, this register is set to "0".

Figure 4.4.3 shows the output waveform for FOUT output.

R00 (when FOUT

is selected)

Fig. 4.4.3

FOUT output waveform

FOUT frequency control (0FDH D0, 0FDH D1)

Selects the output frequency when R00 port is set for FOUT

output.

XFOUT0, XFOUT1

Table 4.4.4

FOUT frequency selection

XFOUT1

XFOUT0

Frequency selection

After an initial reset, these registers are set to "0".

R00 register

FOUT output

waveform

I-26 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Special output port data (0F3H D0, 0F3H D1)

Controls the buzzer output.

When "1" is written: Buzzer output

When "0" is written: Low level (DC) output

Reading: Valid

BUZZER and BUZZER output can be controlled by writing

data to R00 and R01.

When BUZZER output by R01 register control is selected by

mask option, BUZZER output and BUZZER output can be

controlled simultaneously by writing data to R01 register.

After an initial reset, these registers are set to "0".

Figure 4.4.4 shows the output waveform for buzzer output.

R00, R01 (when BUZZER

and BUZZER

is selected)

Fig. 4.4.4

Buzzer output waveform

Buzzer frequency control (0FDH D3)

Selects the frequency of the buzzer signal.

When "1" is written: 2 kHz

When "0" is written: 4 kHz

Reading: Valid

When R00 and R01 port is set to buzzer output, the fre-

quency of the buzzer signal can be selected by this register.

When "1" is written to this register, the frequency is set in 2

kHz, and in 4 kHz when "0" is written.

After an initial reset, this register is set to "0".

XBZR

R01 (R00) register

BUZZER output

waveform

BUZZER output

waveform

S1C62N51 TECHNICAL HARDWARE EPSON I-27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

I/O Ports (P00–P03)

The S1C62N51 Series have a 4-bit general-purpose I/O port.

Figure 4.5.1 shows the configuration of the I/O port. The

four bits of the I/O port P00–P03 can be set to either input

mode or output mode. The mode can be set by writing data

to the I/O control register (IOC).

4.5

Configuration of I/O

ports

Fig. 4.5.1

Configuration of I/O port

Input or output mode can be set for the four bits of I/O port

P00–P03 by writing data into I/O control register IOC.

To set the input mode, "0" is written to the I/O control

ance becomes high and it works as an input port. However,

the input line is pulled down when input data is read.

The output mode is set when "1" is written to the I/O control

as an output port, it outputs a high signal (VDD) when the

port output data is "1", and a low signal (VSS) when the port

output data is "0".

After an initial reset, the I/O control register is set to "0",

and the I/O port enters the input mode.

I/O control register

and I/O mode

Address

Input

control

I/O control

(IOC)

Data bus

Pxx

VSS

Address

I-28 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

The output specification during output mode (IOC = "1") of

the I/O port can be set with the mask option for either

complementary output or Pch open drain output. This

setting can be performed for each bit of the I/O port. How-

ever, when Pch open drain output has been selected, voltage

in excess of the supply voltage must not be applied to the

port.

Table 4.5.1 lists the I/O port control bits and their ad-

dresses.

Mask option

Control of I/O ports

Table 4.5.1 I/O port control bits

I/O port data (0F4H)

I/O port data can be read and output data can be written

through the port.

• When writing data

When "1" is written: High level

When "0" is written: Low level

When an I/O port is set to the output mode, the written

data is output from the I/O port pin unchanged. When

"1" is written as the port data, the port pin goes high

(VDD), and when "0" is written, the level goes low (VSS).

Port data can also be written in the input mode.

• When reading data

When "1" is read: High level

When "0" is read: Low level

P00–P03

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F4H

P00

R/W

P03

P02

P01

P00

–

I/O port data P03

I/O port data P02

I/O port data P01

I/O port data P00

High

Low

P01P02P03

0FCH

IOC

R/W

IOC 0

I/O port I/O control register

Out In

S1C62N51 TECHNICAL HARDWARE EPSON I-29

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

The pin voltage level of the I/O port is read. When the I/

O port is in the input mode the voltage level being input

to the port pin can be read; in the output mode the

output voltage level can be read. When the pin voltage is

high (VDD) the port data read is "1", and when the pin

voltage is low (VSS) the data is "0". Also, the built-in pull-

down resistance functions during reading, so the I/O port

pin is pulled down.

- When the I/O port is set to the output mode and a low-imped-

ance load is connected to the port pin, the data written to the

- When the I/O port is set to the input mode and a low-level

voltage (Vss) is input by the built-in pull-down resistance, an

erroneous input results if the time constant of the capacitive

load of the input line and the built-in pull-down resistance load is

greater than the read-out time. When the input data is being

read, the time that the input line is pulled down is equivalent to

0.5 cycles of the CPU system clock. Hence, the electric poten-

tial of the pins must settle within 0.5 cycles. If this condition

cannot be met, some measure must be devised, such as

arranging a pull-down resistance externally, or performing

multiple read-outs.

I/O control register (0FCH D0)

The input or output I/O port mode can be set with this

When "1" is written: Output mode

When "0" is written: Input mode

Reading: Valid

The input or output mode of the I/O port is set in units of

four bits. For instance, IOC sets the mode for P00–P03.

Writing "1" to the I/O control register makes the I/O port

enter the output mode, and writing "0", the input mode.

After an initial reset, the IOC register is set to "0", so the I/O

port is in the input mode.

Note

IOC

I-30 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD Driver (COM0–COM3, SEG0–SEG25)

The S1C62N51 Series have four common pins and 26

(SEG0–SEG25) segment pins, so that an LCD with a maxi-

mum of 104 (26 × 4) segments can be driven. The power for

driving the LCD is generated by the CPU internal circuit, so

there is no need to supply power externally.

The driving method is 1/4 duty (1/3 or 1/2 duty by mask

option) dynamic drive, adopting the four types of potential,

VDD, VL1, VL2 and VL3. The frame frequency is 32 Hz for 1/

4 duty, 42.7 Hz for 1/3 duty, and 32 Hz for 1/2 duty (in the

case of fosc = 32,768 Hz). Figure 4.6.1 shows the drive

waveform for 1/4 duty, Figure 4.6.2 shows the drive wave-

form for 1/3 duty, and Figure 4.6.3 shows the drive wave-

form for 1/2 duty.

fosc indicates the oscillation frequency of the oscillation circuit.

Configuration of LCD

driver

4.6

Note

S1C62N51 TECHNICAL HARDWARE EPSON I-31

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.6.1

Drive waveform

for 1/4 duty

COM0

COM1

COM2

COM3

SEG0

~SEG25

Frame freqency

Not lit

Lit

LCD lighting status

COM0

COM1

COM2

COM3

SEG0~25

I-32 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.6.2

Drive waveform

for 1/3 duty

Fig. 4.6.3

Drive waveform

for 1/2 duty

COM0

COM1

COM2

COM3

Not lit

Lit

SEG0

~SEG25

Frame freqency

LCD lighting status

COM0

COM1

COM2

SEG0~25

COM0

COM1

COM2

COM3

Not lit

Lit

SEG0

~SEG25

Frame freqency

LCD lighting status

SEG0~25

COM0

COM1

S1C62N51 TECHNICAL HARDWARE EPSON I-33

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

The S1C62N51 Series members allow software setting of the

LCD static drive. This function enables easy adjustment

(cadence adjustment) of the oscillation frequency of the OSC

circuit.

The procedure for executing of the LCD static drive is as

follows:

➀Write "1" to the CSDC register at address "0FBH D3".

➁Write the same value to all registers corresponding to

COM0–COM3 of the display memory.

- Even when l/3 or 1/2 duty is selected, the display data corre-

sponding to COM3 is valid for static drive. Hence, for static

drive, set the same value to all display memory corresponding

COM0–COM3.

- For cadence adjustment, set the display data including display

data corresponding to COM3, so that all the LCD segments go

on.

Figure 4.6.4 shows the drive waveform for static drive.

Switching between

dynamic and static

drive

Note

Fig. 4.6.4

LCD static drive waveform

SEG

0–25

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–25

–V

Not lit Lit

–V

I-34 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(1)Segment allocation

As shown in Figure 4.l.1, the S1C62N51 Series display

data is decided by the display data written to the display

memory (write-only) at address "090H–0AFH".

The address and bits of the display memory can be made

to correspond to the segment pins (SEG0–SEG25) in any

combination through mask option. This simplifies design

by increasing the degree of freedom with which the liquid

crystal panel can be designed.

Figure 4.6.5 shows an example of the relationship be-

tween the LCD segments (on the panel) and the display

memory in the case of 1/3 duty.

Mask option

(segment allocation)

Fig. 4.6.5

Segment allocation

aa'

ff'

ee'

dd' p'

SEG10 SEG11 SEG12

Common 2

Common 1

09AH

09BH

09CH

09DH

Address

Data

Display data memory allocation

SEG10

SEG11

SEG12

9A, D0

(a)

9A, D1

(b)

9D, D1

(f')

9B, D1

(f)

9B, D2

(g)

9A, D2

(c)

9B, D0

(e)

9A, D3

(d)

9B, D3

(p)

Pin address allocation

Common 0 Common 1 Common 2

Common 0

S1C62N51 TECHNICAL HARDWARE EPSON I-35

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(2)Drive duty

According to the mask option, either 1/4, 1/3 or 1/2

duty can be selected as the LCD drive duty.

Table 4.6.1 shows the differences in the number of seg-

ments according to the selected duty.

Pins used Maximum number Frame frequency

in common of segments (when fosc = 32 kHz)

1/4 COM0–3 104 (26 × 4) 32 Hz

1/3 COM0–2 78 (26 × 3) 42.7 Hz

1/2 COM0, 1 52 (26 × 2) 32 Hz

(3)Output specification

➀The segment pins (SEG0–SEG25) are selected by mask

option in pairs for either segment signal output or DC

output (VDD and VSS binary output). When DC output

is selected, the data corresponding to COM0 of each

segment pin is output.

➁When DC output is selected, either complementary

output or Pch open drain output can be selected for

each pin by mask option.

The pin pairs are the combination of SEG (2

n) and SEG (2

n + 1)

(where n is an integer from 0 to 12).

Duty

Note

Table 4.6.1

Differences according to

selected duty

I-36 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Table 4.6.2 shows the control bits of the LCD driver and

their addresses. Figure 4.6.6 shows the display memory

map.

Control of LCD

driver

Table 4.6.2 Control bits of LCD driver

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

LCD drive switch (0FBH D3)

The LCD drive format can be selected with this switch.

When "1" is written: Static drive

When "0" is written: Dynamic drive

Reading: Valid

After an initial reset, dynamic drive (CSDC = "0") is selected.

(090H–0AFH)

The LCD segments are turned on or off according to this

data.

When "1" is written: On

When "0" is written: Off

Reading: Invalid

By writing data into the display memory allocated to the

LCD segment (on the panel), the segment can be turned on

or off. After an initial reset, the contents of the display

memory are undefined.

Address 0123456789ABCDEF

090

0A0 Display memory (Write only)

32 words x 4 bits

Fig. 4.6.6

Display

memory map

Display memory

CSDC

Address Comment

D3 D2 D1 D0 Name Init 1 0

0FBH

0CSDC

LCD drive switch

Static Dynamic

0CSDC

R/W

S1C62N51 TECHNICAL HARDWARE EPSON I-37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Clock Timer

The S1C62N51 Series have a built-in clock timer driven by

the source oscillator. The clock timer is configured as a

seven-bit binary counter that serves as a frequency divider

taking a 256 Hz source clock from a prescaler. The four

high-order bits (16 Hz–2 Hz) can be read by the software.

Figure 4.7.1 is the block diagram of the clock timer.

4.7

Configuration of

clock timer

Fig. 4.7.1

Block diagram of

clock timer

Normally, this clock timer is used for all kinds of timing

purpose, such as clocks.

128 Hz–32 Hz

Data bus

32 Hz, 8 Hz, 2 Hz

256 Hz

Clock timer reset signal

OSC

(oscillation

circuit)

Interrupt

request

Interrupt

control

16 Hz–2 Hz

I-38 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Interrupt function The clock timer can interrupt on the falling edge of the 32

Hz, 8 Hz, and 2 Hz signals. The software can mask any of

these interrupt signals.

Figure 4.7.2 is the timing chart of the clock timer.

Fig. 4.7.2 Timing chart of the clock timer

As shown in Figure 4.7.2, an interrupt is generated on the

falling edge of the 32 Hz, 8 Hz, and 2 Hz frequencies. When

this happens, the corresponding interrupt event flag (IT32,

IT8, IT2) is set to "1". Masking the separate interrupts can

be done with the interrupt mask register (EIT32, EIT8,

EIT2). However, regardless of the interrupt mask register

setting, the interrupt event flags will be set to "1" on the

falling edge of their corresponding signal (e.g. the falling

edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to

"1").

Write to the interrupt mask register (EIT32, EIT8, EIT2) only in the

DI status (interrupt flag = "0"). Otherwise, it causes malfunction.

Note

Clock timer timing chartFrequency

bits

Address

0E3H

D0 16 Hz

8 Hz

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

S1C62N51 TECHNICAL HARDWARE EPSON I-39

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Table 4.7.1 shows the clock timer control bits and their

addresses.

Control of clock

timer

Table 4.7.1 Control bits of clock timer

Timer data (0E3H)

The l6 Hz to 2 Hz timer data of the clock timer can be read

from this register. These four bits are read-only, and write

operations are invalid.

After an initial reset, the timer data is initialized to "0H".

Interrupt mask registers (0EBH D0–D2)

These registers are used to mask the clock timer interrupt.

When "1" is written: Enabled

When "0" is written: Masked

Reading: Valid

The interrupt mask register bits (EIT32, EIT8, EIT2) mask

the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz).

After an initial reset, these registers are all set to "0".

TM0–TM3

EIT32, EIT8, EIT2

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E3H

TM0

TM3

TM2

TM1

TM0

–

Clock timer data 2 Hz

Clock timer data 4 Hz

Clock timer data 8 Hz

Clock timer data 16 Hz

High

Low

TM1TM2TM3

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0F9H

TMRST

TMRST Reset

Clock timer reset

Reset –

I-40 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Interrupt factor flags (0EFH D0–D2)

These flags indicate the status of the clock timer interrupt.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags (IT32, IT8, IT2) correspond to the

clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can

determine from these flags whether there is a clock timer

interrupt. However, even if the interrupt is masked, the

flags are set to "1" on the falling edge of the signal. These

flags can be reset when the register is read by the software.

Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to "1", an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated. Be

very careful when interrupt factor flags are in the same

address.

After an initial reset, these flags are set to "0".

Clock timer reset (0F9H D0)

This bit resets the clock timer.

When "1" is written: Clock timer reset

When "0" is written: No operation

Reading: Always "0"

The clock timer is reset by writing "1" to TMRST. The clock

timer starts immediately after this. No operation results

when "0" is written to TMRST.

This bit is write-only, and so is always "0" when read.

IT32, IT8, IT2

TMRST

S1C62N51 TECHNICAL HARDWARE EPSON I-41

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Configuration of A/D

converter

4.8

Fig. 4.8.1

Configuration of

A/D converter

A/D Converter

The S1C62N51 Series have a CR oscillation type A/D con-

verter. This A/D converter is equipped with two CR oscilla-

tion circuit systems and a counter that measures their

oscillation frequency. Counted values represent connected

resistance values converted into digital values. Connect a

reference resistance that does not change oscillation fre-

quency according to temperature between the RS and CS

terminals and a sensor that does change resistance values

according to temperature between the TH and CS terminals.

Then, oscillate them alternately. The difference in the

counted value can be evaluated as the difference between

the respective oscillation frequencies. Therefore, various

sensor circuit such as a temperature-measuring circuit

using a thermistor can be easily created, for example.

The configuration of the A/D converter is shown in Figure

4.8.1.

Tr2

Multiplying

circuit

Interrupt

request

OSC1

clock 32 kHz or 65 kHz TC15

–TC12 TC11

–TC8 TC7

–TC4 TC3

–TC0

Up/down counter

ADCLK

C15

–C12 C11

–C8 C7

–C4 C3

–C0

Start/Stop

ADRUN

Controller

Up-counter

Start/Stop

control

Up/Down

control Data bus

Start/Stop

control

Interrupt

controller

IAD EIAD

Tr1Tr3

THRS

CS R

ADOUT V

I-42 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Connect a reference resistance that only slightly changes

resistance values according to environmental conditions

between the oscillating I/O terminals RS and CS. Connect a

sensor that changes resistance values between the TH and

CS terminals. Furthermore, by connecting a condenser

between the CS and VSS, a CR oscillation circuit is com-

pleted.

This A/D converter performs CR oscillation using one of the

two resistances connected to external devices. Their oscilla-

tion frequency serves as a clock from which the oscillation

frequency is counted. Difference in counted oscillation

frequency can be evaluated in terms of the difference be-

tween the respective resistance values. Measurement results

can be obtained from the changes in resistance values after

correcting the difference according to the program.

(1)External resistances and condenser

Connect a sensor (a variable resistance element such as a

thermistor) between the TH and CS terminals.

Next, set the reference value of the item to be measured

(e.g. reference temperature in the case of temperature

measurement) and connect the reference resistance

equivalent to the sensor resistance value at the above

reference value between the RS and CS terminals. An

element that does not change due to temperature or other

environmental conditions must be used as the reference

resistance.

Connect an oscillating condenser that is used for CR

oscillation of both the reference resistance and the sensor

between the CS and VSS terminals.

Operation of A/D

converter

S1C62N51 TECHNICAL HARDWARE EPSON I-43

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

(2)Oscillation circuit

The CR oscillation circuit is designed so that either the

reference resistance side or the sensor side can be oper-

ated independently by the oscillation control circuit.

A/D conversion begins when "1" is written in the ADRUN

circuit also turns on. At first, the circuit of the reference

resistance side (RS) is operated by the oscillation control

circuit. Then, the circuit of the sensor side (TH) turns on

when counting by the oscillation clock of the reference

resistance is terminated.

Each circuit performs the same oscillating operation as

follows:

The Tr1 (Tr2) turns on first, and the condenser connected

between the CS and VSS terminals is charged through the

reference resistance (sensor). If the voltage level of the CS

terminal decreases, the Tr1 (Tr2) turns off and the Tr3

turns on. As a result, the condenser becomes discharged,

and oscillation is performed according to CR time con-

stant. The time constant changes as the sensor resist-

ance value fluctuates, producing a difference from the

oscillation frequency of the reference resistance.

Oscillation waveforms are shaped by the Schmitt trigger

and transmitted to counter. The clock transmitted to the

counter is also output from the ADOUT terminal. As a

result, oscillation frequency can be identified by the

oscilloscope. Since this monitor has no effect on oscilla-

tion frequency, it can be used to adjust CR oscillation

frequency.

Oscillation waveforms and waveforms output from the

ADOUT terminal are shown in Figure 4.8.2.

Fig. 4.8.2

Oscillation waveforms

CS terminal

ADOUT VDD

VSS

VDD

VSS

I-44 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

(3)Counter

The A/D converter incorporates two types of 16-bit

counters. One is the up-counter C0–C15 that counts the

aforementioned oscillation clock, and the other is up/

down counter TC0–TC15 that counts the internal clock

for reference counting. Each counter permits reading and

writing on a 4-bit basis.

The input unit of the up/down counter TC0–TC15 incor-

porates a multiplying circuit so that either the OSC1

clock (Typ. 32.768 kHz) or its multiplication clock (Typ.

65.536 kHz) can be selected as an input clock.

When A/D conversion is initiated by the ADRUN register,

oscillation by the reference resistance begins first, and

the up-counter C0–C15 starts counting up according to

the oscillation clock. At the same time, the up/down

counter TC0–TC15 starts counting up.

Timing in starting oscillation and starting counting up

are shown in Figure 4.8.3.

The up-counter becomes ENABLE at the falling edge of

the first clock after CR oscillation is initiated and starts

counting up from the falling edge of the next clock.

The up/down counter becomes ENABLE at the falling

edge of the internal clock which is input immediately

after the first CR oscillation clock has fallen. Then, it

starts counting up from the falling edge of the next inter-

nal clock.

Fig. 4.8.3

Counting up start

timing

ADRUN register

CS terminal

ADOUT

Up-counter enable

Up-counter (C0)

Clock (Up/down counter)

Up/down counter enable

Up/down counter (TC0)

Start

S1C62N51 TECHNICAL HARDWARE EPSON I-45

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

If the up-counter C0–C15 becomes "0000H" due to over-

flow, the sensor side of the oscillation circuit turns on,

and the up-counter starts counting up according to the

oscillation clock on the sensor side.

The up/down counter TC0–TC15 shifts to the counting-

down mode at this point and starts counting down from

the value measured as a result of oscillation by the

reference resistance.

Timing in starting counting when oscillation is switched,

is same as Figure 4.8.3.

When the up/down counter TC0–TC15 has counted down

to "0000H", the counting operation of both counters and

CR oscillation stops, and an interrupt occurs. At the

same time, the ADRUN register is set to "0", and the A/D

converter circuit stops operation completely.

The sensor is oscillated for the same period of time as the

reference resistance is oscillated after the up/down

counter TC0–TC15 is set to "0000H" prior to A/D conver-

sion. Therefore, the difference in oscillation frequency can

be measured from the values counted by the up-counter

C0–C15.

Since the reference resistance is oscillated until the up-

counter C0–C15 overflows, an appropriate initial value

needs to be set before A/D conversion is started. If a

smaller initial value is set, a longer counting period is

possible, thereby ensuring more accurate detection.

Likewise, if the input clock of the up/down counter TC0–

TC15 is set at 65 kHz, the degree of precision is reduced.

However, since CR oscillation frequency is normally set

lower than the clock frequency of the up/down counter

TC0–TC15 to ensure accurate measurement, the up/

down counter TC0–TC15 may overflow while counting the

oscillation frequency of the reference resistance.

If an overflow occurs, CR oscillation and A/D conversion

is terminated immediately. Also in such cases, the up/

down counter indicates "0000H", and interrupt occurs.

However, it is impossible to judge whether the interrupt

has occurred due to an overflow or normal termination.

I-46 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Note that correct measurement is impossible if an over-

flow occurs. The initial value to be set depends on the

measurable range by the sensor or where to set the

reference resistance value within that range.

The initial value must be set taking the above into con-

sideration.

Convert the initial value into a complement (value sub-

tracted from 0000H) before setting it on the up-counter

C0–C15. Since the data output from the up-counter C0–

C15 after A/D conversion matches data detected by the

sensor, process the difference between that value and the

initial value before it is converted into a complement

according to the program and calculate the target value.

The above operations are shown in Figure 4.8.4.

Note - Set the initial value of the up-counter C0–C15 taking into

account the measurable range and the overflow of the up/down

counter TC0–TC15.

- If the up/down counter TC0–TC15 is measured after A/D

conversion, it may not indicate "0000H". This is not due to

incorrect timing in terminating A/D conversion but because the

counting down clock is input after the control signal is output to

the up-counter to terminate counting.

Fig. 4.8.4

Sequence of A/D conversion

Up-counter

(C0–C15)

(0000H-n)(1) Set the initial value (0000H-n)

Count up

FFFFH

Count up

Up/down counter

(TC0–TC15)

0000H0000H

Count up

Count down

0001H

0000H

(2) Start A/D conversion

(Set "1" on the ADRUN)

(3) Read the up-counter and process the m–n value acoording to the program

Setting by software Set the complement of the initial

value n on the up-counter

Set "0000H" on the up /down

counter

Oscillation by

reference resistance

Switch CR oscillation when

the up-counter overflows and

shift the up/down counter to

the counting-down mode

When the value of the up/down

counter reaches 0000H, oscillation

and conting stops, and

an interruption occurs.

Oscillation by

sensor

S1C62N51 TECHNICAL HARDWARE EPSON I-47

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

The A/D converter has a function which allows interrupt to

occur after A/D conversion.

When the up/down counter TC0–TC15 is counted down to

"0000H", both counters stop counting. The interrupt factor

flag IAD is set to "1" at the falling edge of the next clock. If

the up/down counter TC0–TC15 overflow during counting-

up operation, the interrupt factor flag is set to "1" at the

rising edge of the clock immediately after the counter

reaches "0000H".

This interrupt factor allows masking by the interrupt mask

in the CPU. If the EIAD is set at "0", the interrupt factor flag

is set to "1". However, no interrupt will occur in the CPU.

The interrupt factor flag is reset to "0" by a reading opera-

tion.

Timing of interrupt by the A/D converter is shown in Figure

4.8.5.

Interrupt function

Fig. 4.8.5

Timing of A/D

converter interrupt

Temperature measurement is possible with the A/D con-

verter in which a thermistor is used as a sensor. Elements

to be connected and counter setting in the case of tempera-

ture measurement are as follows:

Example: Temperature measurement at -20°C to 70°C

Reference resistance .......49.8 kΩ

thermistor.......................50 kΩ

Oscillating condenser......2,200 pF

Usage example of

the A/D converter

ADRUN register

ADOUT

Up-counter data

Up/down counter clock

Up/down counter data

Interrupt

n n+1 n+2

0 123

FFFE FFFF

x-1 x-2x-1x-2x-3 x-3

3210

m-1

Oscillation with reference resistor Oscillation with sensor

I-48 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

When the above elements are connected, the oscillation

frequency of the reference resistance becomes about 10 kHz,

and the oscillation frequency of the thermistor varies within

the range of about 1 kHz to 50 kHz at -20°C to 70°C.

Reference resistance is adjusted to the thermistor resistance

value at 25°C.

In addition, Figure 4.8.6 indicates the resistance and oscil-

lation frequency ratio TYP at the time of A/D conversion.

Fig. 4.8.6

Resistance and oscillation

frequency ratio

10 k

0.1

( )

50 k 100 k 500 k

1.0

5.0

Resistance value

Oscillation frequency ratio

Ω

Resistance and oscillation frequency ratio

of A/D conversion circuit

For 50 k , set the oscillation frequency to 1.

S1C62N51 TECHNICAL HARDWARE EPSON I-49

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Table 4.8.2 shows the A/D converter control bits and their

addresses.

Control of A/D

converter

Table 4.8.2 Control bits of clock timer

*1 Initial value following initial reset *4 Reset (0) immediately after being read

*2 Not set in the circuit *5 Always "0" when being read

*3 Undefined *6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E4H

TC0

R/W

TC3

TC2

TC1

TC0

Up/down counter data TC3

Up/down counter data TC2

Up/down counter data TC1

Up/down counter data TC0 (LSB)

TC1TC2TC3 –

–

TC4

R/W

TC7

TC6

TC5

TC4

–

Up/down counter data TC7

Up/down counter data TC6

Up/down counter data TC5

Up/down counter data TC4

TC5TC6TC7

0E5H

0E6H

TC8

R/W

TC11

TC10

TC9

TC8

–

Up/down counter data TC11

Up/down counter data TC10

Up/down counter data TC9

Up/down counter data TC8

TC9TC10TC11

0E7H

TC12

R/W

TC15

TC14

TC13

TC12

–

Up/down counter data TC15 (MSB)

Up/down counter data TC14

Up/down counter data TC13

Up/down counter data TC12

TC13TC14TC15

0F5H

R/W

Up-counter data C3

Up-counter data C2

Up-counter data C1

Up-counter data C0 (LSB)

C1C2C3 –

–

R/W

–

Up-counter data C7

Up-counter data C6

Up-counter data C5

Up-counter data C4

C5C6C7

0F6H

0F7H

R/W

C11

C10

–

Up-counter data C11

Up-counter data C10

Up-counter data C9

Up-counter data C8

C9C10C11

0F8H

C12

R/W

C15

C14

C13

C12

–

Up-counter data C15 (MSB)

Up-counter data C14

Up-counter data C13

Up-counter data C12

C13C14C15

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

0F1H

ADRUN

R/W

ADRUN 0

A/D conversion Start/Stop

Start Stop

0FEH

ADCLK

R/W

ADCLK 0

A/D clock selection 65 kHz/32 kHz

65 kHz 32 kHz

I-50 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Up/down counter (0E4H–0E7H)

Writing and reading is possible on a 4-bit basis by the up/

down counter that is used to adjust the CR oscillation time

between the reference resistance and the variable resistance

elements.

The up/down counter counts up during oscillation of the

reference resistance and counts down from the value it

reached when counting up to "0000H" during oscillation of

the sensor.

"0000H" needs to be entered in the counter prior to A/D

conversion in order to adjust the counting time of both

counts.

After an initial reset, data in this counter become indefinite.

Up-counter (0F5H–0F8H)

This counter counts up according to the CR oscillation

clock. It permits writing and reading on a 4-bit basis.

The complement of the number of clocks to be counted by

the oscillation of the reference resistance, must be entered

in this counter prior to A/D conversion.

If A/D conversion is initiated, the counter counts up from

the set initial value, first according to the oscillation clock of

the reference resistance. When the counter reaches "0000H"

due to overflow, the oscillation of the reference resistance

stops, and the sensor starts oscillating. The counter contin-

ues counting according to the sensor oscillation clock.

Counting time during the oscillation of the reference resist-

ance is calculated by the up/down counter TC0–TC15. Up-

counter C0–C15 stops counting when the same period of

time elapses. Difference from the reference resistance can be

evaluated from the value indicated by the counter when it

stops. Calculate the target value by processing the above

difference according to the program.

Measurable range and the overflow of the up/down counter

TC0–TC15 must be taken into account when setting an

initial value to be entered prior to A/D conversion.

After an initial reset, data in this counter become indefinite.

TC0–TC15

C0–C15

S1C62N51 TECHNICAL HARDWARE EPSON I-51

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Input clock selection (0FEH D0)

Select the input clock of the up/down counter TC0–TC15.

When "1" is written: 65 kHz

When "0" is written: 32 kHz

Reading: Valid

Select the output clock of the multiplying circuit for the

counting operation of the up/down counter TC0–TC15.

When "1" is written in the ADCLK, 65 kHz, a multitude of

the OSC1 clock is selected. When "0" is written, the OSC1

clock is selected at 32 kHz.

If 65 kHz is selected, A/D conversion becomes more accu-

rate. However, the initial value must be set on the up-

counter C0–C15 so that the up/down counter TC0–TC15

will not overflow while CR oscillation is being counted.

After an initial reset, ADCLK is set to "0".

A/D conversion START/STOP (0F1H D0)

Start A/D conversion.

When "1" is written: A/D conversion starts

When "0" is written: A/D conversion stops

Reading: Valid

When "1" is written in the ADRUN, A/D conversion begins.

The register remains at "1" during A/D conversion and is set

to "0" when A/D conversion is terminated.

When "0" is written in the ADRUN during A/D conversion,

A/D conversion is paused.

ADRUN is set to "0" at initial reset, when the up/down

counter overflows or when measurement is finished.

Interrupt mask register (0ECH D0)

Select whether to mask interrupt with the A/D converter.

When "1" is written: Enable

When "0" is written: Mask

Reading: Valid

The A/D converter interrupt is permitted when "1" is written

in the EIAD. When "0" is written, interrupt is masked.

After an initial reset, this register is set to "0".

ADRUN

EIAD

ADCLK

I-52 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

IAD Interrupt factor flag (0F0H D0)

This flag indicates interrupt caused by the A/D converter.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

IAD is set to "1" when A/D conversion is terminated (when

the up/down counter counted up or down to "0000H"). From

the status of this flag, the software can decide whether an

A/D converter interrupt has occurred.

This flag is reset when the software has read it.

Reading of interrupt factor flag is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flag to be read is set to "1", an interrupt

request will be generated by the interrupt factor flag set

timing, or an interrupt request will not be generated.

After an initial reset, this flag is set to "0".

S1C62N51 TECHNICAL HARDWARE EPSON I-53

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

4.9

Configuration of SVD

circuit and heavy

load protection

function

Supply Voltage Detection (SVD) Circuit and

Heavy Load Protection Function

The S1C62N51 Series have a built-in supply voltage detec-

tion (SVD) circuit and a heavy load protection function.

Figure 4.9.1 shows the configuration of the circuit.

SVD circuit

The SVD circuit monitors the conditions of the supply

voltage (battery voltage), and software can check whether

the supply voltage has dropped below the detecting voltage

level of the SVD circuit: 2.4 V when supply voltage is 3.0 V

(S1C62N51), or 1.2 V when supply voltage is 1.5 V

(S1C62L51). Registers SVDON (SVD control on/off) and

SVDDT (SVD data) are used for the SVD circuit. The soft-

ware can turn SVD operation on and off. When SVD is on,

the IC draws a large current, so keep SVD off unless it is.

Since supply voltage detection is automatically performed by

the hardware every 2 Hz (0.5 sec) when the heavy load

protection function operates, do not permit the operation of

the SVD circuit by the software in order to minimize power

current consumption.

Heavy load protection function

Note that the heavy load protection function on the

S1C62L51 is different from the S1C62N51.

(1)In case of S1C62L51

The S1C62L51 has the heavy load protection function for

when the battery load becomes heavy and the source

voltage drops, such as when an external buzzer sounds

or an external lamp lights. The state where the heavy

load protection function is in effect is called the heavy

load protection mode. In this mode, operation with a

lower voltage than normal is possible.

The normal mode changes to the heavy load protection

mode in the following two cases:

➀When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

➁When supply voltage drop (SVDDT = "1") in the SVD

circuit is detected, the mode will automatically shift to

the heavy load protection mode until the supply volt-

age is recovered (SVTDT = "0")

I-54 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

In the heavy load protection mode, the internally regu-

lated voltage is generated by the liquid crystal driver

source output VL2 so as to operate the internal circuit.

Consequently, more current is consumed in the heavy

load protection mode than in the normal mode. Unless it

is necessary, be careful not to set the heavy load protec-

tion mode with the software. Also, to reduce current

consumption, do not set the SVDON to ON in the heavy

load protection mode.

(2)In case of S1C62N51

The S1C62N51 has the heavy load protection function for

when the battery load becomes heavy and the source

voltage changes, such as when an external buzzer sounds

or an external lamp lights. The state where the heavy

load protection function is in effect is called the heavy

load protection mode. Compared with the normal opera-

tion mode, this mode can reduce the output voltage

variation of the constant voltage/booster voltage circuit of

the LCD system.

The normal mode changes to the heavy load protection

mode in the following case:

• When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

The heavy load protection mode switches the constant

voltage circuit of the LCD system to the high-stability

mode from the low current consumption mode. Conse-

quently, more current is consumed in the heavy load

protection mode than in the normal mode. Unless it is

necessary, be careful not to set the heavy load protection

mode with the software.

Note that in S1C62L51, the range of operating pressure

differs during CR oscillation and during crystal oscilla-

tion.

Fig. 4.9.1

Configuration of SVD and

heavy load protection circuits

Vss

HLMOD

SVDDT

Vss SVDON

SVD circuit Regurated

voltage circuit

Data bus

Address 0FAH

SVD sampling

control

S1C62N51 TECHNICAL HARDWARE EPSON I-55

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

The following explains the timing when the SVD circuit

writes the result of supply voltage detection to the SVDDT

The result of supply voltage detection is written to the

SVDDT register by the SVD circuit, and this data can be

read by the software to determine the supply voltage.

There are two methods, explained below, for executing the

detection by the SVD circuit.

(1)Sampling with HLMOD set to "1"

When HLMOD is set to "1" and SVD sampling is ex-

ecuted, the detection results can be written to the SVDDT

Immediately after sampling with the 2 Hz cycle output by

the oscillation circuit while HLMOD = "1" (sampling time

is 122 µs in the case of fosc = 32,768 Hz).

Consequently, after HLMOD has been set to "1", the new

detection result is written in a 2 Hz.

(2)Sampling with SVDON set to "1"

When SVDON is set to "1", SVD detection is executed. As

soon as SVDON is reset to "0", the result is loaded to in

the SVDDT register. To obtain a stable SVD detection

result, the SVD circuit must be on for at least 100 µs.

So, to obtain the SVD detection result, follow the pro-

gramming sequence below.

➀Set SVDON to "1"

➁Maintain for 100 µs minimum

➂Set SVDON to "0"

➃Read SVDDT

However, at 32 kHz for the S1C62N51 and S1C62L51,

the instruction cycles are long enough, so there is no

need to worry about maintaining 100 µs for SVDON = "1"

in the software.

Notice that even if the SVD circuit detects a drop in the

supply voltage (1.2 V/2.4 V or less) and invokes the heavy

load protection mode, this will be the same as when the

software invokes the heavy load protection mode, in that the

SVD circuit will be sampled with a timing synchronized to

the 2 Hz output from the prescaler. If the SVD circuit

detects a voltage drop and enters the heavy load protection

mode, it will return to the normal mode once the supply

voltage recovers and the SVD circuit determines that the

supply voltage is 1.2 V/2.4 V or more.

Operation of SVD

detection timing

I-56 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

The S1C62N51 has a heavy load protection function for

when the battery load becomes heavy and the supply voltage

drops, such as when a melody is played or an external lamp

lights. This functions works in the heavy load protection

mode.

(1)In cace of S1C62L51

The normal mode changes to the heavy load protection

mode in the following two cases:

➀When the software changes the mode to the heavy load

protection mode

➁When the SVD circuit detects a supply voltage less

than 1.2 V, in which case the mode is automatically

changed to the heavy load protection mode

(2)In case of S1C62N51

The normal mode changes to the heavy load protection

mode in the following case:

• When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

Based on the operation of the SVD circuit and the heavy

load protection function, the S1C62L51 obtains an opera-

tion supply voltage as low as 0.9 V. See the electrical char-

acteristics for the precision of voltage detection by the SVD

circuit.

In the heavy load protection mode, the internally regulated

voltage is generated by the liquid crystal driver supply

output, VL2, in order to operate the internal circuit

(S1C62L51). Consequently, more current is consumed in

the heavy load protection mode than in the normal mode.

Unless necessary, do not select the heavy load protection

mode with the software.

Operation of heavy

load protection

function

Activation of the SVD circuit by software in the heavy load protec-

tion mode causes a malfunction. Avoid such activation if possible.

Note

S1C62N51 TECHNICAL HARDWARE EPSON I-57

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

Table 4.9.1 shows the control bits and their addresses for

the SVD circuit and the heavy load protection function.

Table 4.9.1 Control bits for SVD circuit and heavy load protection function

Control of SVD cir-

cuit and heavy load

protection function

Heavy load protection mode on/off (0FAH D3)

When "1" is written: Heavy load protection mode on

When "0" is written: Heavy load protection mode off

Reading: Valid

When HLMOD is set to "1", the IC enters the heavy load

protection mode, and sampling control is executed for the

time the SVD circuit is on. The sampling timing is as fol-

lows:

Sampling in cycles of 2 Hz output by the oscillation circuit

while HLMOD = "1" (sampling time is 122 µs in the case of

fosc = 32,768 Hz).

When SVD sampling is done with HLMOD set to "1", the

results are written to the SVDDT register with the as follow-

ing timing:

Immediately on completion of sampling in cycles of 2 Hz

output by the oscillation circuit while HLMOD = "1".

Consequently, after HLMOD is set to "1", the new detected

result is written in 2 Hz.

In the heavy load protection mode, the consumed current

becomes larger. Unless necessary, do not select the heavy

load protection mode with the software.

HLMOD

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0FAH

SVDON

R/W

HLMOD

SVDDT

SVDON

Heavy load protection mode register

Supply voltage detection data

Supply voltage detection circuit On/Off

Heavy

Low

Normal

Off

SVDDT0HLMOD

R/W

I-58 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

SVD control on/off (0FAH D0)

When "0" is written: SVD detection off

When "1" is written: SVD detection on

Reading: Valid

When this bit is written, the SVD detection on/off operation

is controlled. Large current is drawn during SVD detection,

so keep SVD detection off except when necessary. When

SVDON is set to "1", SVD detection is executed. As soon as

SVDON is reset to "0", the detected result is loaded into the

SVDDT register.

SVD data (0FAH D1)

When "0" is read: Supply voltage ≥ Criteria voltage

When "1" is read: Supply voltage < Criteria voltage

When SVDDT is "1", the S1C62N51 enters the heavy load

protection mode. In this mode, the detection operation of

the SVD circuit is sampled in 2 Hz cycles and the respective

detection results are written to the SVDDT register.

SVDDT

SVDON

S1C62N51 TECHNICAL HARDWARE EPSON I-59

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Interrupt and HALT

The S1C62N51 Series provide the following interrupt set-

tings, each of which is maskable.

External interrupt: Input interrupt (one)

Internal interrupt: Timer interrupt (one)

A/D converter interrupt (one)

To enable interrupts, the interrupt flag must be set to "1"

(EI) and the necessary related interrupt mask registers must

be set to "1" (enable). When an interrupt occurs, the inter-

rupt flag is automatically reset to "0" (DI) and interrupts

after that are inhibited.

When a HALT instruction is input, the CPU operating clock

stops and the CPU enters the halt state. The CPU is reacti-

vated from the halt state when an interrupt request occurs.

Figure 4.10.1 shows the configuration of the interrupt

circuit.

4.10

Fig. 4.10.1

Configuration of

interrupt circuit

K00

EIK00

K01

EIK01

K02

EIK02

K03

EIK03

IAD

EIAD

IT2

EIT2

IT8

EIT8

IT32

EIT32

IK0

(MSB)

(LSB)

Program counter of CPU

(three low-order bits)

Interrupt vector

Interrupt factor flag

Interrupt mask register

Interrupt flag

INT

(Interrupt request)

I-60 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.10.1 shows the factors that generate interrupt

requests.

The interrupt factor flags are set to "1" depending on the

corresponding interrupt factors.

The CPU is interrupted when the following two conditions

occur and an interrupt factor flag is set to "1".

• The corresponding mask register is "1" (enabled)

• The interrupt flag is "1" (EI)

The interrupt factor flag is a read-only register, but can be

reset to "0" when the register data is read.

After an initial reset, the interrupt factor flags are reset to

"0".

Interrupt factors

Reading of interrupt factor flags is available at EI, but be careful in

the following cases.

If the interrupt mask register value corresponding to the interrupt

factor flags to be read is set to "1", an interrupt request will be

generated by the interrupt factor flags set timing, or an interrupt

request will not be generated. Be very careful when interrupt factor

flags are in the same address.

Note

Table 4.10.1

Interrupt factors Interrupt factor

Colck timer 2 Hz falling edge

Colck timer 8 Hz falling edge

Colck timer 32 Hz falling edge

A/D converter

A/D conversion completion

Input data (K00–K03)

Rising edge

Interrrupt factor flag

IT2

IT8

IT32

IAD

IK0

(0F0H D0)

(0EDH D0)

(0EFH D2)

(0EFH D1)

(0EFH D0)

S1C62N51 TECHNICAL HARDWARE EPSON I-61

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

The interrupt factor flags can be masked by the correspond-

ing interrupt mask registers. The interrupt mask registers

are read/write registers. They are enabled (interrupt en-

abled) when "1" is written to them, and masked (interrupt

disabled) when "0" is written to them. After an initial reset,

the interrupt mask register is set to "0".

Table 4.10.2 shows the correspondence between interrupt

mask registers and interrupt factor flags.

Specific masks and

factor flags for inter-

rupt

Table 4.10.2

Interrupt mask registers and

interrupt factor flags

Interrupt mask register Interrrupt factor flag

(0EBH D2)

(0EBH D1)

(0EBH D0)

(0ECH D0)

(0E8H D3)

(0E8H D2)

(0E8H D1)

(0E8H D0)

IT2

IT8

IT32

IAD

(0EFH D2)

(0EFH D1)

(0EFH D0)

(0F0H D0)

IK0 (0EDH D0)

EIT2

EIT8

EIT32

EIAD

EIK03*

EIK02*

EIK01*

EIK00*

* There is an interrupt mask register for each input port pin.

When an interrupt request is input to the CPU, the CPU

begins interrupt processing. After the program being exe-

cuted is suspended, interrupt processing is executed in the

following order:

➀The address data (value of the program counter) of the

program step to be executed next is saved on the stack

(RAM).

➁The interrupt request causes the value of the interrupt

vector (page 1, 01H–07H) to be loaded into the program

counter.

➂The program at the specified address is executed (execu-

tion of interrupt processing routine).

The processing in steps 1 and 2, above, takes 12 cycles of the

CPU system clock.

Interrupt vectors

Note

I-62 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Control of interrupt Table 4.10.4 shows the interrupt control bits and their

addresses.

Table 4.10.4 Interrupt control bits

EIT32, EIT8, EIT2

IT32, IT8, IT2

EIAD

IAD

EIK00–EIK03

IK0

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Interrupt mask registers (0EBH D0–D2)

Interrupt factor flags (0EFH D0–D2)

See 4.7, "Clock Timer".

Interrupt mask register (0ECH D0)

Interrupt factor flag (0F0H D0)

See 4.8, "A/D Converter".

Interrupt mask registers (0E8H)

Interrupt factor flag (0EDH D0)

See 4.3, "Input Ports".

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

S1C62N51 TECHNICAL HARDWARE EPSON I-63

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

BASIC EXTERNAL WIRING DIAGRAM

(1) Piezo Buzzer Single Terminal Driving

CHAPTER 5

OSC1

OSC2

RESET

TEST

Vss

X'tal

1.5V

3.0V

Piezo

Buzzer

R01

K00

K03

P00

P03

R00

R02

R03

I/O

SEG0

SEG25

COM0

COM3

LCD

PANEL

S1C62N51/62L51

Coil

X'tal

–C

Crystal oscillator

Trimmer capacitor

Capacitor

Thermistor

Resistor

Capacitor

32,768 Hz CI(MAX) = 35 kΩ

5–25 pF

0.1 µF

3.3 µF

50 kΩ

49.8 kΩ

2,200 pF

I-64 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

OSC1

OSC2

RESET

TEST

Vss

X'tal

1.5V

3.0V

Piezo

Buzzer

R00

K00

K03

P00

P03

R02

R03

I/O

SEG0

SEG25

COM0

COM3

LCD

PANEL

S1C62N51/62L51

R01

(2) Piezo Buzzer Direct Driving

X'tal

–C

Crystal oscillator

Trimmer capacitor

Capacitor

Thermistor

Resistor

Capacitor

32,768 Hz CI(MAX) = 35 kΩ

5–25 pF

0.1 µF

3.3 µF

50 kΩ

49.8 kΩ

2,200 pF

S1C62N51 TECHNICAL HARDWARE EPSON I-65

CHAPTER 6: ELECTRICAL CHARACTERISTICS

CHAPTER 6 ELECTRICAL CHARACTERISTICS

6.1 Absolute Maximum Rating

S1C62L51

S1C62N51

Power voltage

Input voltage (1)

Input voltage (2)

Operating temperature

Storage temperature

Soldering temperature / Time

Allowable dissipation

Item Symbol

VSS

VIOSC

Topr

Tstg

Tsol

Rated value

-5.0 to 0.5

Vss-0.3 to 0.5

-20 to 70

-65 to 150

260°C, 10sec (lead section)

250

Unit

°C

–

(V =0V)DD

Power voltage

Input voltage (1)

Input voltage (2)

Operating temperature

Storage temperature

Soldering temperature / Time

Allowable dissipation

Item Symbol

VSS

VIOSC

Topr

Tstg

Tsol

Rated value

-5.0 to 0.5

Vss-0.3 to 0.5

-20 to 70

-65 to 150

260°C, 10sec (lead section)

250

Unit

°C

–

(V =0V)DD

*1 In case of QFP6-64 pin plastic package

I-66 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.2 Recommended Operating Conditions

S1C62N51

S1C62L51

*1 When switching to the heavy load protection mode.

The SVD circuit is turned OFF.

(For details, refer to Section 4.9).

*2 The voltage which can be displayed on the LCD panel will differ according to the

characteristics of the LCD panel.

*3 When there is no software correspondence during CR oscillation or crystal oscilla-

tion.

Item

Power voltage

Oscillation frequency

Booster capacitor (1)

Booster capacitor (2)

Capacitor between V

and V

Capacitor between V

and V

Capacitor between V

and V

Capacitor between V

and V

Symbol

OSC1

OSC2

Condition

=0V

Crystal oscillation

CR oscillation, R=420kΩ

Min

-3.5

0.1

Typ

-3.0

32,768

Unit

kHz

µF

Max

-1.8

(Ta=-20 to 70°C)

Item

Power voltage

Oscillation frequency

Booster capacitor (1)

Booster capacitor (2)

Capacitor between V

and V

Capacitor between V

and V

Capacitor between V

and V

Capacitor between V

and V

Symbol

OSC1

OSC2

Condition

=0V

=0V, With software

correspondence

Crystal oscillation

CR oscillation, R=420kΩ

Min

-2.0

0.1

Typ

-1.5

32,768

Unit

kHz

µF

Max

-1.1

-0.9

(Ta=-20 to 70°C)

S1C62N51 TECHNICAL HARDWARE EPSON I-67

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.3 DC Characteristics

S1C62N51

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal

voltages, and C1=C2=C3=C4=C5=C6=0.1 µF

Item Symbol

VIH1

VIH2

VIL1

VIL2

IIH1

IIH2

IIH3

IIL

IOH1

IOH2

IOH3

IOL1

IOL2

IOL3

IOH4

IOL4

IOH5

IOL5

IOH6

IOL6

Condition Min

0.2•Vss

0.15•Vss

Vss

-0.5

-100

3.0

300

Typ Unit

µA

Max

0.8•Vss

0.85•Vss

0.5

100

-1.0

-10

100

-3

-300

K00–K03, P00–P03

RESET, TEST

K00~K03, P00–P03

RESET, TEST

K00–K03, P00–P03

K00–K03

P00–P03

RESET, TEST

K00–K03, P00–P03

RESET, TEST

R02, R03, P00–P03

R00, R01

ADOUT

R02, R03, P00–P03

R00, R01

ADOUT

COM0–COM3

SEG0–SEG25

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

High level output current (1)

High level output current (2)

High level output current (3)

Low level output current (1)

Low level output current (2)

Low level output current (3)

Common output current

Segment output current

(during LCD output)

Segment output current

(during DC output)

VIH1=0V

Without pull down resistor

VIH2=0V

With pull down resistor

VIH3=0V

With pull down resistor

VIL=VSS

VOH1=0.1•VSS

VOH2=0.1•VSS

(built-in protection resistance)

VOH3=-1.0V

VOL1=0.9•VSS

VOL2=0.9•VSS

(built-in protection resistance)

VOL3=-2.0V

VOH4=-0.05V

VOL4=VL3+0.05V

VOH5=-0.05V

VOL5=VL3+0.05V

VOH6=0.1•VSS

VOL6=0.9•VSS

I-68 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C62L51

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal

voltages, and C1=C2=C3=C4=C5=C6=0.1 µF

Item

Symbol

IH1

IH2

IL1

IL2

IH1

IH2

IH3

OH1

OH2

OH3

OL1

OL2

OL3

OH4

OL4

OH5

OL5

OH6

OL6

Condition Min

0.2•Vss

0.15•Vss

Vss

2.0

9.0

-0.5

-100

700

130

Typ Unit

µA

Max

0.8•Vss

0.85•Vss

0.5

100

-200

-10

100

-3

-100

K00–K03, P00–P03

RESET, TEST

K00~K03, P00–P03

RESET, TEST

K00–K03, P00–P03

K00–K03

P00–P03

RESET, TEST

K00–K03, P00–P03

RESET, TEST

R02, R03, P00–P03

R00, R01

ADOUT

R02, R03, P00–P03

R00, R01

ADOUT

COM0–COM3

SEG0–SEG25

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

High level output current (1)

High level output current (2)

High level output current (3)

Low level output current (1)

Low level output current (2)

Low level output current (3)

Common output current

Segment output current

(during LCD output)

Segment output current

(during DC output)

IH1

=0V

Without pull down resistor

IH2

=0V

With pull down resistor

IH3

=0V

With pull down resistor

OH1

=0.1•V

OH2

=0.1•V

(built-in protection resistance)

OH3

=-1.5V

OL1

=0.9•V

OL2

=0.9•V

(built-in protection resistance)

OL3

=-1.0V

OH4

=-0.05V

OL4

+0.05V

OH5

=-0.05V

OL5

+0.05V

OH6

=0.1•V

OL6

=0.9•V

S1C62N51 TECHNICAL HARDWARE EPSON I-69

CHAPTER 6: ELECTRICAL CHARACTERISTICS

Analog Circuit Characteristics and Power Current Con-

sumption

S1C62N51 (Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3

are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF

(During A/D conversion: R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)

*1 The SVD circuit is turned OFF.

S1C62N51 (Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3

are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF

(During A/D conversion: R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)

*1 The SVD circuit is turned OFF.

6.4

Item

Internal voltage

SVD voltage

SVD circuit response time

Current consumption

Symbol

VL1

VL2

VL3

VSVD

tSVD

IOP

Condition

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

Min

-1.15

2•VL1

-0.1

3•VL1

-0.1

-2.55

Typ

-1.05

-2.40

1.0

2.5

Unit

µs

µA

Max

-0.95

2•VL1

× 0.9

3•VL1

× 0.9

-2.25

100

2.5

5.0

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

Internal voltage

SVD voltage

SVD circuit response time

Current consumption

Symbol

SVD

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

-1.15

2•V

-0.1

3•V

-0.1

-2.55

Typ

-1.05

-2.40

2.0

5.5

Unit

µs

µA

Max

-0.95

2•V

0.85

3•V

0.85

-2.25

100

5.5

10.0

41.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

I-70 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C62L51 (Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3

are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF

(During A/D conversion: R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)

*1 The SVD circuit is turned OFF.

S1C62L51 (Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3

are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF

(During A/D conversion: R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)

*1 The SVD circuit is turned OFF.

Item

Internal voltage

SVD voltage

SVD circuit response time

Current consumption

Symbol

SVD

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

-1.15

2•V

-0.1

3•V

-0.1

-1.30

Typ

-1.05

-1.20

1.0

2.5

Unit

µs

µA

Max

-0.95

2•V

0.9

3•V

0.9

-1.10

100

2.5

5.0

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

Internal voltage

SVD voltage

SVD circuit response time

Current consumption

Symbol

VL1

VL2

VL3

VSVD

tSVD

IOP

Condition

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

Min

-1.15

2•VL1

-0.1

3•VL1

-0.1

-1.30

Typ

-1.05

-1.20

2.0

5.5

Unit

µs

µA

Max

-0.95

2•VL1

× 0.85

3•VL1

× 0.85

-1.10

100

5.5

10.0

41.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

S1C62N51 TECHNICAL HARDWARE EPSON I-71

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C62N51 (CR, Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF, Recommended external resis-

tance for CR oscillation = 420 kΩ

(During A/D conversion: R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)

*1 The SVD circuit is turned OFF.

S1C62N51 (CR, Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF, Recommended external resis-

tance for CR oscillation = 420 kΩ

(During A/D conversion: R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)

*1 The SVD circuit is turned OFF.

Item

Internal voltage

SVD voltage

SVD circuit response time

Current consumption

Symbol

VL1

VL2

VL3

VSVD

tSVD

IOP

Condition

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

Min

-1.15

2•VL1

-0.1

3•VL1

-0.1

-2.55

Typ

-1.05

-2.40

8.0

15.0

Unit

µs

µA

Max

-0.95

2•VL1

× 0.9

3•VL1

× 0.9

-2.25

100

15.0

20.0

52.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

Internal voltage

SVD voltage

SVD circuit response time

Current consumption

Symbol

VL1

VL2

VL3

VSVD

tSVD

IOP

Condition

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

Min

-1.15

2•VL1

-0.1

3•VL1

-0.1

-2.55

Typ

-1.05

-2.40

16.0

30.0

Unit

µs

µA

Max

-0.95

2•VL1

× 0.85

3•VL1

× 0.85

-2.25

100

30.0

40.0

57.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

I-72 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C62L51 (CR, Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF, Recommended external resis-

tance for CR oscillation = 420 kΩ

(During A/D conversion: R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)

*1 The SVD circuit is turned OFF.

S1C62L51 (CR, Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF, Recommended external resis-

tance for CR oscillation = 420 kΩ

(During A/D conversion: R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)

*1 The SVD circuit is turned OFF.

Item

Internal voltage

SVD voltage

SVD circuit response time

Current consumption

Symbol

SVD

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

-1.15

2•V

-0.1

3•V

-0.1

-1.30

Typ

-1.05

-1.20

8.0

15.0

Unit

µs

µA

Max

-0.95

2•V

0.9

3•V

0.9

-1.10

100

15.0

20.0

52.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

Internal voltage

SVD voltage

SVD circuit response time

Current consumption

Symbol

VL1

VL2

VL3

VSVD

tSVD

IOP

Condition

Connect 1MΩ load resistor between VDD and VL1

(without panel load)

Connect 1MΩ load resistor between VDD and VL2

(without panel load)

Connect 1MΩ load resistor between VDD and VL3

(without panel load)

Min

-1.15

2•VL1

-0.1

3•VL1

-0.1

-1.30

Typ

-1.05

-1.20

16.0

30.0

Unit

µs

µA

Max

-0.95

2•VL1

× 0.85

3•VL1

× 0.85

-1.10

100

30.0

40.0

57.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

S1C62N51 TECHNICAL HARDWARE EPSON I-73

CHAPTER 6: ELECTRICAL CHARACTERISTICS

Oscillation Characteristics

Oscillation characteristics will vary according to different conditions. Use the

following characteristics are as reference values.

S1C62N51

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25°C

6.5

S1C62L51

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25°C

*1 Items enclosed in parentheses ( ) are those used when operating at heavy load

protection mode.

Item

Oscillation start voltage

Oscillation stop voltage

Built-in capacity (drain)

Frequency voltage deviation

Frequency IC deviation

Frequency adjustment range

Higher harmonic oscillation

start voltage

Allowable leak resistance

Symbol

Vsta

(Vss)

Vstp

(Vss)

f/V

f/IC

f/C

hho

(Vss)

leak

Condition Min

-1.8

-10

200

Typ

Unit

ppm

MΩ

Max

-3.5

sta≤5sec

stp≤10sec

Including the parasitic capacity inside the IC

Vss=-1.8 to -3.5V

=5–25pF

=5pF

Between OSC1 and V

and between V

and OSC1

Item

Oscillation start voltage

Oscillation stop voltage

Built-in capacity (drain)

Frequency voltage deviation

Frequency IC deviation

Frequency adjustment range

Higher harmonic oscillation

start voltage

Allowable leak resistance

Symbol

Vsta

(Vss)

Vstp

(Vss)

f/V

f/IC

f/C

hho

(Vss)

leak

Condition Min

-1.1

(-0.9)

-10

200

Typ

Unit

ppm

MΩ

Max

-2.0

sta≤5sec

stp≤10sec

Including the parasitic capacity inside the IC

Vss=-1.1 to -2.0V (-0.9)

=5–25pF

=5pF

Between OSC1 and V

and between V

and OSC1

I-74 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C62N51 (CR)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, RCR=420 kΩ, Ta=25°C

S1C62L51 (CR)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, RCR=420 kΩ, Ta=25°C

Item

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

Oscillation stop voltage

Symbol

fosc

Vsta

sta

Vstp

Condition

Vss=-1.8 to -3.5V

Min

-20

-1.8

Typ

65kHz

Unit

Max

Item

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

Oscillation stop voltage

Symbol

fosc

Vsta

sta

Vstp

Condition

Vss=-1.1 to -2.0V

Min

-20

-1.1

Typ

65kHz

Unit

Max

S1C62N51 TECHNICAL HARDWARE EPSON I-75

CHAPTER 7: PACKAGE

CHAPTER 7 PACKAGE

7.1 Plastic Package

116

48 33

14.0

16.8

±0.2

±0.4

14.0

16.8

±0.2

±0.4

0.35

±0.15

0.8

±0.15

0.15

±0.05

2.7

±0.1

±0.3

1.4

0.6

0~12°

Index

QFP6-64 pin

I-76 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 7: PACKAGE

Ceramic Package for Test Samples

7.2

115

45 31

14.0

17.6

±0.2

±0.3

14.0

17.6

±0.2

±0.3

0.35

±0.15

0.8

±0.15

0.15

±0.05

2.7

±0.2

0.7

1.8

1.0

5°

±5°

QFP6-60 pin

S1C62N51 TECHNICAL HARDWARE EPSON I-77

CHAPTER 8: PAD LAYOUT

CHAPTER 8 PAD LAYOUT

8.1 Diagram of Pad Layout

(0, 0)

1234567891011121314

DIE No.

31 32 33 34 35 36 37 38 39 40 41 42 43 44

3.93 mm

3.58 mm

I-78 EPSON S1C62N51 TECHNICAL HARDWARE

CHAPTER 8: PAD LAYOUT

8.2 Pad Coordinates

Chip size X: 3.58 (mm)

Y: 3.93 (mm)

Pad No

Pad name

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

TEST

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

Pad name

P00

P01

P02

P03

RESET

K00

K01

K02

K03

R00

R01

R02

R03

ADOUT

OSC1

OSC2

COM0

COM1

COM2

1,340.4

745.2

585.2

425.2

265.2

105.2

-54.8

-214.8

-374.8

-534.8

-694.8

-854.8

-1,014.8

-1,174.8

-1,630.8

-1,584.8

-1,424.0

-1,260.8

-1,100.0

-904.4

-744.8

-579.2

-418.4

-252.8

-17.2

282.8

508.8

668.4

1,630.4

1,808.4

1,612.4

1,367.6

1,207.6

1,047.6

887.6

727.6

567.6

407.6

247.6

87.6

-152.8

-312.8

-472.8

-632.8

-933.6

-1,093.2

-1,808.0

-1,784.8

-1,624.8

-1,464.8

-1,264.8

-1,014.8

-787.2

-627.6

-467.6

175.6

335.6

495.6

954.4

1,114.4

1,274.4

1,434.0

1,595.6

1,755.2

Software

S1C62N51

II.

Technical Software

Software

S1C62N51 TECHNICAL SOFTWARE EPSON II-i

CONTENTS

CHAPTER 1 CONFIGURATION ........................................................... II-1

1.1 S1C62N51 Block Diagram ............................................. II-1

1.2 ROM Map ....................................................................... II-2

1.3 Interrupt Vectors............................................................. II-3

1.4 Data Memory Map.......................................................... II-4

CHAPTER 2 INITIAL RESET ................................................................... II-7

2.1 Internal Register Status on Initial Reset ......................... II-7

2.2 Initialize Program Example............................................. II-9

CHAPTER 3 PERIPHERAL CIRCUITS.................................................... II-11

3.1 Input Ports ..................................................................... II-11

Input port memory map .......................................... II-11

Control of the input port ......................................... II-12

Examples of input port control program .................. II-12

3.2 Output Ports .................................................................. II-14

Output port memory map........................................ II-14

Control of the output port ....................................... II-14

Examples of output port control program ................ II-14

3.3 Special Use Output Ports .............................................. II-16

Special use output port memory map ...................... II-16

Control of the special use output port ..................... II-16

Examples of special use output port control program. II-17

II-ii EPSON S1C62N51 TECHNICAL SOFTWARE

CONTENTS

3.4 I/O Ports ........................................................................ II-19

I/O port memory map ............................................. II-19

Control of the I/O port ............................................ II-19

Examples of I/O port control program ..................... II-20

3.5 LCD Driver..................................................................... II-23

LCD driver memory map ......................................... II-23

Control of the LCD driver ........................................ II-23

Examples of LCD driver control program ................. II-25

3.6 Timer ............................................................................. II-27

Timer memory map ................................................. II-27

Control of the timer................................................. II-28

Examples of timer control program.......................... II-29

3.7 A/D Converter................................................................ II-31

A/D converter memory map .................................... II-31

Control of the A/D converter ................................... II-32

Examples of A/D converter control program ............ II-35

3.8 Supply Voltage Detection (SVD) Circuit

and Heavy Load Protection Function ............................ II-48

SVD circuit and heavy load protection

function memory map ............................................. II-48

Control of the SVD circuit ....................................... II-49

Example of SVD circuit control program.................. II-49

Heavy load protection function ................................ II-50

Examples of heavy load protection

function control program......................................... II-52

3.9 Interrupt and Halt........................................................... II-55

Interrupt memory map ............................................ II-55

Control of interrupts and halt ................................. II-56

Examples of interrupt and halt control program ...... II-63

Software

S1C62N51 TECHNICAL SOFTWARE EPSON II-iii

CONTENTS

CHAPTER 4 SUMMARY OF PROGRAMMING POINTS....................... II-66

APPENDIX A Table of Instructions ...................................................... II-70

B RAM Map ...................................................................... II-75

C Table of the ICE Commands ......................................... II-77

D Cross-assembler Pseudo-instruction List...................... II-79

S1C62N51 TECHNICAL SOFTWARE EPSON II-1

CHAPTER 1: CONFIGURATION

CHAPTER 1

1.1

CONFIGURATION

S1C62N51 Block Diagram

Fig. 1.1.1

S1C62N51 block diagram

SVD

COM0–3

K00–03

P00–03

R00–03

OSC1

OSC2

RESET

SEG0–25 TEST

L1–3

CA–CC

Power

Controller

LCD Driver

RAM

80 words x 4 bits

ROM

1,024 words x 12 bits

OSC

System Reset

Control

Fout & Buzzer

Interrupt

Generator

Input Port

Test Port

I/O Port

Output Port

Timer

A/D Converter

Core CPU S1C6200A

FOUT / BUZZER

BUZZER

ADOUT

II-2 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

ROM Map

The S1C62N51 has a built-in mask ROM with a capacity of

1,024 steps × 12 bits for program storage. The configuration

of the ROM is shown in Figure 1.2.1.

1.2

Fig. 1.2.1

Configuration of built-in ROM

00H step

07H step

08H step

FFH step

12 bits

Program start address

Interrupt vector area

Bank 0

Program area

0 page

1 page

2 page

3 page

01H step

S1C62N51 TECHNICAL SOFTWARE EPSON II-3

CHAPTER 1: CONFIGURATION

Interrupt Vectors

When an interrupt request is received by the CPU, the CPU

initiates the following interrupt processing after completing

the instruction being executed.

(1)The address of the next instruction to be executed (the

value of the program counter) is saved on the stack

(RAM).

(2)The interrupt vector address corresponding to the inter-

rupt request is loaded into the program counter.

(3)The branch instruction written in the vector is executed

to branch to the software interrupt processing routine.

Steps 1 and 2 require 12 cycles of the CPU system clock.

The interrupt vectors are shown in Table 1.3.1.

1.3

Note

Table 1.3.1

Interrupt requests and vectors Step Interrupt vector

Initial reset

Clock timer interrupt

A/D interrupt

Clock timer interrupt and A/D interrupt

Input (K00–K03) interrupt

Input interrupt and clock timer interrupt

Input interrupt and A/D interrupt

Generation of all interrupt

Page

00H

01H

02H

03H

04H

05H

06H

07H

Addresses (start address of interrupt processing routines) to

jump to are written into the addresses available for interrupt

vector allocation.

II-4 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Data Memory Map

The S1C62N51 built-in RAM has 80 words of data memory,

32 words of display memory for the LCD, and I/O memory

for controlling the peripheral circuit. When writing pro-

grams, note the following:

(1)Since the stack area is in the data memory area, take

care not to overwrite the stack with data. Subroutine

calls or interrupts use 3 words on the stack.

(2)Data memory addresses 000H–00FH are memory register

areas that are addressed with register pointer RP.

1.4

Fig. 1.4.1

Data memory map

Address

Page High

Low 0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

RAM area (000H–04FH)

80 words x 4 bits (R/W)

Display memory area (090H–0AFH)

32 words x 4 bits (Write only)

Unused area

I/O memory area Table 4.1.1(a), (b)

Note Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

S1C62N51 TECHNICAL SOFTWARE EPSON II-5

CHAPTER 1: CONFIGURATION

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Table 1.4.1(a) I/O memory map 1

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E0H

K00

K03

K02

K01

K00

–

Input port data K03

Input port data K02

Input port data K01

Input port data K00

High

Low

K01K02K03

0E3H

TM0

TM3

TM2

TM1

TM0

–

Clock timer data 2 Hz

Clock timer data 4 Hz

Clock timer data 8 Hz

Clock timer data 16 Hz

High

Low

TM1TM2TM3

0E4H

TC0

R/W

TC3

TC2

TC1

TC0

Up/down counter data TC3

Up/down counter data TC2

Up/down counter data TC1

Up/down counter data TC0 (LSB)

TC1TC2TC3 –

–

TC4

R/W

TC7

TC6

TC5

TC4

–

Up/down counter data TC7

Up/down counter data TC6

Up/down counter data TC5

Up/down counter data TC4

TC5TC6TC7

0E5H

0E6H

TC8

R/W

TC11

TC10

TC9

TC8

–

Up/down counter data TC11

Up/down counter data TC10

Up/down counter data TC9

Up/down counter data TC8

TC9TC10TC11

0E7H

TC12

R/W

TC15

TC14

TC13

TC12

–

Up/down counter data TC15 (MSB)

Up/down counter data TC14

Up/down counter data TC13

Up/down counter data TC12

TC13TC14TC15

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

II-6 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F4H

P00

R/W

P03

P02

P01

P00

–

I/O port data P03

I/O port data P02

I/O port data P01

I/O port data P00

High

Low

P01P02P03

0F5H

R/W

Up-counter data C3

Up-counter data C2

Up-counter data C1

Up-counter data C0 (LSB)

C1C2C3 –

–

R/W

–

Up-counter data C7

Up-counter data C6

Up-counter data C5

Up-counter data C4

C5C6C7

0F6H

0F7H

R/W

C11

C10

–

Up-counter data C11

Up-counter data C10

Up-counter data C9

Up-counter data C8

C9C10C11

0F8H

C12

R/W

C15

C14

C13

C12

–

Up-counter data C15 (MSB)

Up-counter data C14

Up-counter data C13

Up-counter data C12

C13C14C15

0F9H

TMRST

TMRST Reset

Clock timer reset

Reset –

0FBH

0CSDC

LCD drive switch

Static Dynamic

0CSDC

R/W

0FDH

XFOUT0

R/W

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

FOUT frequency control

2 kHz 4 kHz

XFOUT10

XBZR

R/W

0FCH

IOC

R/W

IOC 0

I/O port I/O control register

Out In

0FEH

ADCLK

R/W

ADCLK 0

A/D clock selection 65 kHz/32 kHz

65 kHz 32 kHz

0F1H

ADRUN

R/W

ADRUN 0

A/D conversion Start/Stop

Start Stop

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

0F3H

R00

FOUT

R03

R02

R01

BUZZER

R00

FOUT

Output port data R03

Output port data R02

Output port data R01

Buzzer On/Off control register

Output port data R00

Frequency output control register

High

Low

Off

Low

Off

R01

BUZZER

R02R03

R/W

0FAH

SVDON

R/W

HLMOD

SVDDT

SVDON

Heavy load protection mode register

Supply voltage detection data

Supply voltage detection circuit On/Off

Heavy

Low

Normal

Off

SVDDT0HLMOD

R/W

Table 1.4.1(b) I/O memory map 2

S1C62N51 TECHNICAL SOFTWARE EPSON II-7

CHAPTER 2: INITIAL RESET

INITIAL RESET

Internal Register Status on Initial Reset

Following an initial reset, the internal registers and internal

data memory area are initialized to the values shown in

Tables 2.1.1 and 2.1.2.

Internal register Bit length Initial value following reset

Program counter step PCS 8 00H

Program counter page PCP 4 1H

New page pointer NPP 4 1H

Stack pointer SP 8 Undefined

Index register X 8 Undefined

Index register Y 8 Undefined

General register A 4 Undefined

General register B 4 Undefined

Interrupt flag I 1 0

Decimal flag D 1 0

Zero flag Z 1 Undefined

Carry flag C 1 Undefined

Internal data Initial value

memory area following reset

RAM data 4 × 80 Undefined 000H–04FH

Display memory 4 × 32 Undefined 090H–0AFH

Internal I/O register See Tables 1.4.1(a) and (b) 0E0H–0FEH

2.1

Table 2.1.1

Initial values of internal

registers

CHAPTER 2

Bit length Address

Table 2.1.2

Initial values of internal data

memory area

II-8 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 2: INITIAL RESET

After an initial reset, the program counter page (PCP) is

initialized to 1H, and the program counter step (PCS), to

00H. This is why the program is executed from step 00H of

the first page.

The initial values of some internal registers and internal

data memory area locations are undefined after a reset. Set

them as necessary to the proper initial values in the pro-

gram.

The peripheral I/O functions (memory-mapped I/O) are

assigned to internal data memory area addresses 0E0H to

0FEH. Each address represents a 4-bit internal I/O register,

allowing access to the peripheral functions in 1-word (4-bit)

read/write units.

S1C62N51 TECHNICAL SOFTWARE EPSON II-9

CHAPTER 2: INITIAL RESET

Initialize Program Example

The following is a program that clears the RAM, LCD, Up/

down counter and Up-counter, resets the flags, registers and

timer, and sets the stack pointer immediately after resetting

the system.

Label Mnemonic/operand Comment

ORG 100H

JP INIT ;Jump to "INIT"

;ORG 110H

INIT RST F,0011B ;Interrupt mask, decimal

;adjustment off

;LD X,0 ;

RAMCLR LDPX MX,0 ;

CP XH,5H ;

JP NZ,RAMCLR ;

LD X,90H ;

LCDCLR LDPX MX,0 ;

CP XH,0BH ;

JP NZ,LCDCLR ;

;LD A,0 ;

LD B,4 ;

LD SPL,A ;

LD SPH,B ;

;LD X,0F9H ;

OR MX,0001B ;

;LD X,0E4H ;

UDCNTCLR LDPX MX,0 ;

CP XL,8H ;

JP NZ,UDCNTCLR ;

LD X,0F5H ;

UCLR LDPX MX,0 ;

CP XL,9H ;

JP NZ,UCLR ;

;LD X,0EBH ;

OR MX,0111B ;

;LD X,0E8H ;

OR MX,1111B ;

;LD X,0 ;

LD Y,0 ;

LD A,0 ; Reset register flags

LD B,0 ;

RST F,0 ;

EI ;Enable interrupt

2.2

Clear RAM (00H–4FH)

Set stack pointer to 40H

Reset clock timer

Clear LCD (90H–AFH)

Enable timer interrupt

Clear Up-counter

(0F5H–0F8H)

Clear Up/down counter

(0E4H–0E7H)

Enable input interrupt

(K03–K00)

II-10 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 2: INITIAL RESET

The above program is a basic initialization program for the

S1C62N51. Figure 2.2.1 is the flow chart for this program.

The setting data are all initialized as shown in the flow chart

by executing this program. When using this program, add

setting items necessary for each specific application.

Fig. 2.2.1

Flow chart of the initialization

program

Initialization

Reset

I (Interrupt flag)

D (Decimal adjustment flag)

Clear RAM

Reset clock timer

Clear Up/down counter,

Up-counter

Enable timer interrupt

Enable input interrupt

Reset registers (X, Y, A, B)

flags (I, Z, D, C)

EI (enable interrupt)

I : Interrupt flag

D : Decimal adjustment flag

Clear data RAM (00H to 04FH)

Clear segment RAM (90H to 0AFH)

Enable timer interrupt 2 Hz, 8 Hz, 32 Hz

Enable K03–K00 input port interrupt

To next process

Set SP Set stack pointer to 40H

S1C62N51 TECHNICAL SOFTWARE EPSON II-11

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

CHAPTER 3

3.1

PERIPHERAL CIRCUITS

Details on how to control the S1C62N51 peripheral circuit is

given in this chapter.

Input Ports

Input port memory

map

Table 3.1.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E0H

K00

K03

K02

K01

K00

–

Input port data K03

Input port data K02

Input port data K01

Input port data K00

High

Low

K01K02K03

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

II-12 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

The S1C62N51 has one 4-bit input port (K00–K03). Input

port data can be read as a 4-bit unit (K00–K03).

The state of the input ports can be obtained by reading the

data (bits D3, D2, D1, D0) of address 0E0H. The input ports

can be used to send an interrupt request to the CPU via the

input interrupt condition flag. See Section 3.9 "Interrupt

and Halt", for details.

• Loading K00–K03 into the A register

Label Mnemonic/operand Comment

LD Y,0E0H ;Set address of port

LD A,MY ;A register ← K00–K03

As shown in Figure 3.1.1, the two instruction steps above

load the data of the input port into the A register.

Control of

the input port

Examples of input

port control

program

The data of the input port can be loaded into the B register

or MX instead of the A register.

Fig. 3.1.1

Loading the A register

K03 D2

K02 D1

K01 D0

K00

A register

S1C62N51 TECHNICAL SOFTWARE EPSON II-13

CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)

Note

• Bit-unit checking of input ports

Label Mnemonic/operand Comment

DI ;Disable interrupt

LD Y,0E0H ;Set address of port

INPUT1: FAN MY,0010B ;

JP NZ,INPUT1 ;Loop until K01 becomes "0"

INPUT2: FAN MY,0010B ;

JP Z,INPUT2 ;Loop until K01 becomes "1"

This program loopes until a rising edge is input to input port

K01.

The input port can be addressed using the X register instead

of the Y register.

When the input port is changed from high level to low level with a

pull-down resistor, the signal falls following a certain delay caused

by the time constants of the pull-down resistance and the input

gate capacitance. It is therefore necessary to observe a proper

wait time before the input port data is read.

II-14 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

Output Ports3.2

Output port

memory map

Table 3.2.1 I/O memory map

The S1C62N51 has 4 bits for general output ports (R00–

R03). R00 and R01 although can be use for special use

output port as shown in later of this section. The output

port is a read/write register, output pins provide the con-

tents of the register. The states of the output ports (R00–

R03) are decided by the data of address 0F3H. Output ports

can also be read, and output control is possible using the

operation instructions (AND, OR, etc.). The output ports are

all initialized to low level (0) after an initial reset.

• Loading B register data into R00–R03

Label Mnemonic/operand Comment

LD Y,0F3H ;Set address of port

LD MY,B ;R00–R03 ← B register

As shown in Figure 3.2.1, the two instruction steps above

load the data of the B register into the output ports.

Control of

the output port

Examples of output

port control

program

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F3H

R00

FOUT

R03

R02

R01

BUZZER

R00

FOUT

Output port data R03

Output port data R02

Output port data R01

Buzzer On/Off control register

Output port data R00

Frequency output control register

High

Low

Off

Low

Off

R01

BUZZER

R02R03

R/W

S1C62N51 TECHNICAL SOFTWARE EPSON II-15

CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)

The output data can be taken from the A register, MX, or

immediate data instead of the B register.

• Bit-unit operation of output ports

Label Mnemonic/operand Comment

LD Y,0F3H ;Set address of port

OR MY,0010B ;Set R01 to 1

AND MY,1011B ;Set R02 to 0

The three instruction steps above cause the output port to

be set, as shown in Figure 3.2.2.

Fig. 3.2.1

Control of the output port

Fig. 3.2.2

Setting of the output port

D3 D2 D1 D0

Data register R00

Data register R01

Data register R02

Data register R03

B register

R03 R02 R01 R00

No change

Sets "1"

Sets "0"

No change

Address 0F3H D3 D2 D1 D0

II-16 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

Special Use Output Ports3.3

Special use output

port memory map

Table 3.3.1 I/O memory map

In addition to the regular DC, special output can be selected

for output ports R00 and R01, as shown in Table 3.3.2.

Figure 3.3.1 shows the structure of output ports R00–R03.

Control of the spe-

cial use output port

Table 3.3.2

Special output

FOUT or BUZZER

BUZZER

R00

R01

Pin name When special output is selected

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F3H

R00

FOUT

R03

R02

R01

BUZZER

R00

FOUT

Output port data R03

Output port data R02

Output port data R01

Buzzer On/Off control register

Output port data R00

Frequency output control register

High

Low

Off

Low

Off

R01

BUZZER

R02R03

R/W

0FDH

XFOUT0

R/W

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

FOUT frequency control

2 kHz 4 kHz

XFOUT10

XBZR

R/W

S1C62N51 TECHNICAL SOFTWARE EPSON II-17

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

• Buzzer driver output (BUZZER)

When output port R01 is set for BUZZER and R00 is set for

BUZZER, it performs 2,048 Hz or 4,096 Hz selected by

Label Mnemonic/operand Comment

LD Y,0FDH ;Set address of BUZZER

;frequency control register

LD MY,1000B ;Select 2,048 Hz

LD Y,0F3H ;Set address of output port

OR MY,0010B ;Turn on BUZZER

: :

AND MY,1101B ;Turn off BUZZER

Examples of special

use output port

control program

Fig. 3.3.1

Structure of output ports

R00–R03

Address

(0F3H)

FOUT

Data bus

Mask option

R02

R01

BUZZER

(R03) R03

R00

BUZZER

(R02)

(R01)

(R00)

II-18 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)

• Internal divided frequency output (FOUT)

When output port R00 is set to FOUT output, fosc or clock

frequency divided into fosc is generated. Clock frequency

may be selected individually for F1–F4, from among 5 types

by mask option; a clock frequency is then selected from 4

types (i.e., F1–F4) through XFOUT0 and XFOUT1 (0FDH D0

and D1) registers and is generated.

The clock frequency types are shown in Table 3.3.3.

Table 3.3.3

Mask option and register

selection

Mask

option

sets

Clock frequency (Hz)

Set 4

256

(fosc/128) 512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

8,192

(fosc/4)

1,024

(fosc/32) 2,048

(fosc/16) 4,096

(fosc/8)

4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

4,096

(fosc/8)

32,768

(fosc/1)

2,048

(fosc/16) 4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

Set 1

Set 2

Set 3

Set 5

(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)

F1 F2 F3 F4

fosc = 32,768

For example mask option is set to Set 4:

Label Mnemonic/operand Comment

LD Y,0FDH ;Set address of FOUT

;frequency control register

LD MY,0011B ;Select 16,384 Hz

LD Y,0F3H ;Set address of output port

OR MY,0001B ;Turn on FOUT

: :

AND MY,1110B ;Turn off FOUT

S1C62N51 TECHNICAL SOFTWARE EPSON II-19

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

3.4 I/O Ports

I/O port memory

map

Table 3.4.1 I/O memory map

The S1C62N51 contains a 4-bit general I/O port (4 bits × 1).

This port can be used as an input port or an output port,

according to I/O port control register IOC. When IOC is "0",

the port is set for input, when it is "1", the port is set for

output.

• How to set an input port

Set "0" in the I/O port control register (D0 of address 0FCH),

and the I/O port is set as an input port. The state of the I/O

port (P00–P03) is decided by the data of address 0F4H. (In

the input mode, the port level is read directly.)

Control of

the I/O port

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F4H

P00

R/W

P03

P02

P01

P00

–

I/O port data P03

I/O port data P02

I/O port data P01

I/O port data P00

High

Low

P01P02P03

0FCH

IOC

R/W

IOC 0

I/O port I/O control register

Out In

II-20 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• How to set an output port

Set "1" in the I/O port control register, and the I/O port is

set as an output port. The state of the I/O port is decided by

the data of address 0F4H. This data is held by the register,

and can be set regardless of the contents of the I/O control

input ports or output ports.)

The I/O control registers are cleared to "0" (input/output

ports are set as input ports), and the data registers are also

cleared to "0" after an initial reset.

• Loading P00–P03 input data into A register

Label Mnemonic/operand Comment

LD Y,0FCH ;Set address of I/O control port

AND MY,1110B ;Set port as input port

LD Y,0F4H ;Set address of port

LD A,MY ;A regiser ← P00–P03

As shown in Figure 3.4.1, the four instruction steps above

load the data of the I/O ports into the A register.

Examples of I/O port

control program

Fig. 3.4.1

Loading into the A register

P03 D2

P02 D1

P01 D0

P00

A register

S1C62N51 TECHNICAL SOFTWARE EPSON II-21

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loading P00–P03 output data into A register

Label Mnemonic/operand Comment

LD Y,0FCH ;Set the address of input/output

;port control register

OR MY,0001B ;Set as output port

LD Y,0F4H ;Set the address of port

LD A,MY ;A register ← P00–P03

As shown in Figure 3.4.2, the four instruction steps above

load the data of the I/O ports into the A register.

Data can be loaded from the I/O port into the B register or

MX instead of the A register.

Fig. 3.4.2

Control of I/O port (input)

P03 P02 P01 P00

Data register P00

Data register P01

Data register P02

Data register P03

A register D3 D2 D1 D0

II-22 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)

• Loading contents of B register into P00–P03

Label Mnemonic/operand Comment

LD Y,0FCH ;Set the address of input/output

;port control register

OR MY,0001B ;Set port as output port

LD Y,0F4H ;Set the address of port

LD MY,B ;P00–P03 ← B register

As shown in Figure 3.4.3, the four instruction steps above

load the data of the B register into the I/O ports.

Fig. 3.4.3

Control of the I/O port (output)

The output data can be taken from the A register, MX, or

immediate data instead of the B register.

Bit-unit operation for the I/O port is identical to that for the

input ports (K00–K03) or output ports (R00–R03).

D3 D2 D1 D0

Data register P00

Data register P01

Data register P02

Data register P03

B register

S1C62N51 TECHNICAL SOFTWARE EPSON II-23

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

LCD Driver3.5

LCD driver memory

map

Table 3.5.1 I/O memory map

Control of the LCD

driver

The S1C62N51 contains 128 bits of display memory in

addresses 090H to 0AFH of the data memory. Each display

memory can be assigned to any 104 bits of the 128 bits for

the LCD driver (26 SEG × 4 COM), 78 bits of the 128 bits (26

SEG × 3 COM) or 52 bits of the 128 bits (26 SEG × 2 COM)

by using a mask option. The remaining 24 bits, 50 bits or 76

bits of display memory are not connected to the LCD driver,

and are not output even when data is written. An LCD

segment is on with "1" set in the display memory, and off

with "0" set in the display memory. Note that the display

memory is a write-only.

Address 0123456789ABCDEF

090

0A0 Display memory (write only)

32 words x 4 bits

Fig. 3.5.1

Display memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0FBH

0CSDC

LCD drive switch

Static Dynamic

0CSDC

R/W

II-24 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

• LCD drive control register (CSDC)

The LCD drive control register (CSDC: address 0FBH, D3)

can be set either for dynamic drive or for static drive. Set "0"

in CSDC for 1/2, 1/3 or 1/4 duty (time-shared) dynamic

drive. Set "1" in CSDC and the same value in the registers

corresponding to COM0 to COM1 (1/2), COM0 to COM2 (1/

3) or COM0 to COM3 (1/4) for static drive. Figure 3.5.2 is

the static drive control of the LCD, and Figure 3.5.3 is an

example of the 7-segment LCD assignment.

Fig. 3.5.3

7-segment LCD assignment

In the assignment shown in Figure 3.5.3, the 7-segment

display pattern is controlled by writing data to display

memory addresses 090H and 091H.

Fig. 3.5.2

LCD static drive control

SEG

0–25

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–25

–V

Not lit Lit

–V

g f e

091H

dcba

090H D3 D2 D1 D0

Address Register

S1C62N51 TECHNICAL SOFTWARE EPSON II-25

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

• Displaying 7-segment

The LCD display routine using the assignment of Figure

3.5.3 can be programmed as follows.

Label Mnemonic/operand Comment

ORG 000H

RETD 3FH ;0 is displayed

RETD 06H ;1 is displayed

RETD 5BH ;2 is displayed

RETD 4FH ;3 is displayed

RETD 66H ;4 is displayed

RETD 6DH ;5 is displayed

RETD 7DH ;6 is displayed

RETD 27H ;7 is displayed

RETD 7FH ;8 is displayed

RETD 6FH ;9 is displayed

SEVENS: LD B,0 ;Set the address of jump

LD X,090H ;Set address of display memory

JPBA

When the above routine is called (by the CALL or CALZ

instruction) with any number from "0" to "9" set in the A

are displayed according to the contents of the A register.

Examples of

LCD driver control

program

The RETD instruction can be used to write data to the

display memory only if it is addressed using the X register.

(Addressing using the Y register is invalid.)

Note that the stack pointer must be set to a proper value

before the CALL (CALZ) instruction is executed.

Fig. 3.5.4

Data set in A register and

displayed patterns

DisplayA register

II-26 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)

Fig. 3.5.5

Example of segment

assignment

• Bit-unit operation of the display memory

Label Mnemonic/operand Comment

LD X,SEGBUF ;Set address display

;memory buffer

LD Y,090H ;Set address display memory

LD MX,3 ;Set buffer data

LD MY,MX ;SEG-A, B ON (▲▲,●●)

AND MX,1110B ;Change buffer data

LD MY,MX ;SEG-B OFF (▲▲,●)

AND MX,1101B ;Change buffer data

LD MY,MX ;SEG-A OFF (▲,●)

For manipulation of the display memory in bit-units for the

assignment of Figure 3.5.5, a buffer must be provided in

RAM to hold data. Note that, since the display memory is

write-only, data cannot be changed directly using an ALU

instruction (for example, AND or OR).

After manipulating the data in the buffer, write it into the

corresponding display memory using the transfer command.

▲●

090H D3 D2 D1 D0

Address Data

▲

●: SEG-A

: SEG-B

S1C62N51 TECHNICAL SOFTWARE EPSON II-27

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

3.6 Timer

Timer memory map

Table 3.6.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E3H

TM0

TM3

TM2

TM1

TM0

–

Clock timer data 2 Hz

Clock timer data 4 Hz

Clock timer data 8 Hz

Clock timer data 16 Hz

High

Low

TM1TM2TM3

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0F9H

TMRST

TMRST Reset

Clock timer reset

Reset –

II-28 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

The S1C62N51 contains a timer with a basic oscillation of

32.768 kHz (typical). This timer is a 4-bit binary counter,

and the counter data can be read as necessary. The counter

data of the 16 Hz clock can be read by reading TM3 to TM0

(address 0E3H, D3 to D0). ("1" to "0" are set in TM3 to TM0,

corresponding to the high-low levels of the 2 Hz, 4 Hz, 8 Hz,

and 16 Hz 50 % duty waveform. See Figure 3.6.1.) The timer

can also interrupt the CPU on the falling edges of the 32 Hz,

8 Hz, and 2 Hz signals. For details, see Section 3.9, "Inter-

rupt and Halt".

Control of the timer

Fig. 3.6.1 Output waveform of timer and interrupt timing

Note

The timer is reset by setting "1" in TMRST (address 0F9H,

D0).

The 128 Hz to 2 Hz of the internal divider is initialized by resetting

the clock timer.

Clock timer timing chartFrequency

bits

Address

0E3H

D0 16 Hz

8 Hz

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

S1C62N51 TECHNICAL SOFTWARE EPSON II-29

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

• Initializing the timer

Label Mnemonic/operand Comment

LD Y,0F9H ;Set address of the timer

;reset register

OR MY,0001B ;Reset the timer

The two instruction steps above are used to reset (clear

TM0–TM3 to "0") and restart the timer. The TMRST register

is cleared to "0" by hardware 1 clock after it is set to "1".

• Loading the timer

Label Mnemonic/operand Comment

LD Y,0E3H ;Set address of

;the timer data (TM0 to TM3)

LD A,MY ;Load the data of

;TM0 to TM3 into A register

As shown in Table 3.6.2, the two instruction steps load the

data of TM0 to TM3 into the A register.

Examples of timer

control program

Table 3.6.2

Loading the timer data

TM3 (2 Hz)

D3 TM2 (4 Hz)

D2 TM1 (8 Hz)

D1 TM0 (16 Hz)

A register

II-30 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Timer)

• Checking timer edge

Label Mnemonic/operand Comment

LD X,TMSTAT ;Set address of the timer edge counter

CP MX,0 ;Check whether the timer edge

;counter is "0"

JP Z,RETURN ;Jump if "0" (Z-flag is "1")

LD Y,0E3H ;Set address of the timer

LD A,MY ;Read the data of TM0 to TM3

;into A register

LD Y,TMDTBF ;Set address of the timer data buffer

XOR MY,A ;Did the count on the timer

;change?

FAN MX,0100B ;Check bit D2 of the timer data buffer

LD MY,A ;Set the data of A register into

;the timer data buffer

JP Z,RETURN ;Jump, if the Z-flag is "1"

ADD MX,0FH ;Decrement the timer edge counter

;

RETURN: RET ;Return

This program takes a subroutine form. It is called at short

intervals, and decrements the data at address TMSTAT every

125 ms until the data reaches "0". The timing chart is

shown in Figure 3.6.2. The timer can be addressed using

the X register instead of the Y register.

TMSTAT and TMDTBF may be any address in RAM and not

involve a hardware function.

Note

Fig. 3.6.2

Timing of the timer

edge counter

125 ms

Timer edge counter (TMSTAT) decrementing timing

TM2

S1C62N51 TECHNICAL SOFTWARE EPSON II-31

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

3.7 A/D Converter

A/D converter mem-

ory map

Table 3.7.1 I/O memory map

*1 Initial value following initial reset *4 Reset (0) immediately after being read

*2 Not set in the circuit *5 Always "0" when being read

*3 Undefined *6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E4H

TC0

R/W

TC3

TC2

TC1

TC0

Up/down counter data TC3

Up/down counter data TC2

Up/down counter data TC1

Up/down counter data TC0 (LSB)

TC1TC2TC3 –

–

TC4

R/W

TC7

TC6

TC5

TC4

–

Up/down counter data TC7

Up/down counter data TC6

Up/down counter data TC5

Up/down counter data TC4

TC5TC6TC7

0E5H

0E6H

TC8

R/W

TC11

TC10

TC9

TC8

–

Up/down counter data TC11

Up/down counter data TC10

Up/down counter data TC9

Up/down counter data TC8

TC9TC10TC11

0E7H

TC12

R/W

TC15

TC14

TC13

TC12

–

Up/down counter data TC15 (MSB)

Up/down counter data TC14

Up/down counter data TC13

Up/down counter data TC12

TC13TC14TC15

0F5H

R/W

Up-counter data C3

Up-counter data C2

Up-counter data C1

Up-counter data C0 (LSB)

C1C2C3 –

–

R/W

–

Up-counter data C7

Up-counter data C6

Up-counter data C5

Up-counter data C4

C5C6C7

0F6H

0F7H

R/W

C11

C10

–

Up-counter data C11

Up-counter data C10

Up-counter data C9

Up-counter data C8

C9C10C11

0F8H

C12

R/W

C15

C14

C13

C12

–

Up-counter data C15 (MSB)

Up-counter data C14

Up-counter data C13

Up-counter data C12

C13C14C15

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

0F1H

ADRUN

R/W

ADRUN 0

A/D conversion Start/Stop

Start Stop

0FEH

ADCLK

R/W

ADCLK 0

A/D clock selection 65 kHz/32 kHz

65 kHz 32 kHz

II-32 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

Control of the A/D

converter

The S1C62N51 has a CR oscillation type A/D converter.

This A/D converter is equipped with two CR oscillation

circuit systems and a counter that measures their

oscillation frequency. Counted values represent connected

resistance values converted into digital values.

The A/D converter incorporates two types of 16-bit count-

ers. One is the up-counter C0–C15 that counts the afore-

mentioned oscillation clock, and the other is up/down

counter TC0–TC15 that counts the internal clock for refer-

ence count. Each counter permits reading and writing on a

4-bit basis.

Figure 3.7.1 shows the operation and control flow of A/D

converter. Figure 3.7.2 shows the Timing chart of the A/D

conversion.

Fig. 3.7.1

Control flow of A/D

converter

YES

Reset the two

counter memories

Reset I (Interrupt) flag

A/D interrupt

necessary ?

Set the interrupt mask

Set an initial value

in the up-counter C

Start A/D conversion

Up-counter C counts up

Up/down counter TC

counts up

Counter C : 0

YES

Up/down counter TC

counts down

Up-counter C counts up

Both counter

finish counting

Set the interrupt factor

flag IAD to "1"

Interrupt process

Is A/D interrupt

set to ENABLE ?

Counter TC : 0

A/D conversion

END

Reset the up/down counter TC0–TC15 (0E4H–0E7H)

and the up-counter C0–C15 (0F5H–0F8H) to "0000H"

Set the EIAD

(0ECH D0) to "1"

Set an initial value

(complement) in

the C0–C15 (0F5H–0F8H)

Set "1" in

the ADRUN (0F1H D0)

Read the C0–C15

(0F5H–0F8H)

and process the

measurement results

S1C62N51 TECHNICAL SOFTWARE EPSON II-33

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

Basic control and operation of the A/D converter are de-

scribed in the flowchart in Figure 3.7.1. In order to prepare

a program, add items required according to application.

After A/D conversion, the value counted during oscillation of

the sensor connected between the TH and CS terminals is

set on the up-counter C0–C15. This value is the sensor

oscillation clock number during a time period equal to that

during which the reference resistance connected between

the RS and CS terminals is oscillated according to the initial

value set on the up-counter. The difference between the

reference resistance and the sensor resistance value can be

obtained indirectly from the initial value and results. Correct

it according to the characteristics of the connected elements

and calculate the target measurement results.

Depending on the initial value of the up-counter C0–C15, the up/

down counter TC0–TC15 may overflow while the CR oscillation

clock is being counted. When setting the initial value, pay attention

to CR oscillation frequency, its fluctuation range and the input clock

frequency of the up/down counter. If the up/down counter over-

flows, A/D conversion is terminated immediately, and correct

measurement is impossible.

Fig. 3.7.2

Timing of A/D conversion

Note

ADRUN register

ADOUT

Up-counter data

Up/down counter clock

Up/down counter data

Interrupt

n n+1 n+2

0 123

FFFE FFFF

x-1 x-2x-1x-2x-3 x-3

3210

m-1

Oscillation with reference resistor Oscillation with sensor

II-34 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

Set "0000H" on the up/down counter prior to A/D conver-

sion. No other reading or writing operation is necessary.

This counter is provided in order to adjust the oscillation

time of the two external resistance.

If the up/down counter TC0–TC15 is measured after A/D conver-

sion, it may not indicate "0000H". This is not due to incorrect timing

in terminating A/D conversion but because the counting down clock

is input after the control signal is output to the up-counter to termi-

nate counting.

Since interruption is possible after A/D conversion, reading

of the up-counter and data processing are basically per-

formed using the interrupt function.

If interrupt is not used, A/D converter operation can be

checked by reading the ADRUN register. After "1" is entered

in this register to start A/D conversion, the register remains

at "1" during A/D conversion and is reset to "0" when A/D

conversion is finished.

Note

S1C62N51 TECHNICAL SOFTWARE EPSON II-35

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

Examples of A/D

converter control

program

In this section, we will explain, for an example of an A/D

converter, a method of temperature measurement and its

program.

When performing temperature measurement, connect a

reference resistance to the RS terminal, a thermistor to the

TH terminal and a condenser to the CS terminal, respec-

tively. The ideal reference resistance to be connected to the

RS terminal should be one which shows no change in its

resistance value as a result of fluctuations in temperature.

The thermistor has a characteristic against temperature

resistance and the resistance value Rγ at a certain tempera-

ture T (°K) can be represented by the following formula:

Rγ =R0 EXP{ B (1/T - 1/T0) }

R0:

Resistance value of the thermistor at the reference temperature (T

°K)

B: Constant of the thermistor

By using the reference resistance and the temperature

resistance characteristic of the thermistor, temperature

measurement is performed.

One method sets the reference resistance and the thermistor

in an alternating state of CR oscillation, using the same

condenser only in the same time interval. A numerical

comparison of each oscillating frequency is performed by a

counter, and the counter values are converted to the tem-

perature by way of the characteristics of the thermistor.

After the A/D conversion, the counter value of 16 bits will

have been set in the up-counter from C15 (0F8H, MSB) to

C0 (0F5H, LSB). This counter value represents the amount

of CR oscillation of the thermistor against duration when it

is oscillated with CR of the reference resistance for a speci-

fied number of times.

The relationship between the amount of oscillation of the

thermistor and the temperature is shown in Figure 3.7.3.

II-36 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

As shown in Figure 3.7.3, the temperature and the counter

values do not form a straight line. Therefore, it is necessary

to drive the range of measurement temperature into several

sections and to calculate in advance the counter values at

the temperature of its division points, according to the

characteristics of the thermistor. As for the divided sections,

the temperature coefficient (fluctuation in temperature by

unit counter) which approximates to a straight line between

the sections is calculated and stored into the ROM in con-

junction with the counter value of such division point. With

this value and the counter value calculated, the temperature

can then be calculated.

The following is a sample program which controls the A/D

converter and converts the counter value to the temperature

when performing temperature measurement with this

method.

In this program, 49.9 kΩ are used for the external reference

resistance, 2,200 pF for the condenser and one with a

temperature characteristic as shown in Table 3.7.2 for the

thermistor.

Fig. 3.7.3

Counter value characteristics

of the temperature and the up-

counter

-10

-20

-30

1000 2000 3000 4000 5000 6000 7000 8000

Counter value of up-counter

Temperature (°C)

S1C62N51 TECHNICAL SOFTWARE EPSON II-37

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

Temperature [°C] TH resistance [kΩ] Up-counter value

-30 872.20 006B[HEX] 107[DEC]

-20 484.00 00CD[HEX] 205[DEC]

-10 277.40 0166[HEX] 358[DEC]

0 164.00 025E[HEX] 606[DEC]

10 99.97 03E1[HEX] 993[DEC]

20 62.56 061D[HEX] 1565[DEC]

30 40.20 094F[HEX] 2383[DEC]

40 26.43 0DCC[HEX] 3532[DEC]

50 17.75 1412[HEX] 5138[DEC]

60 12.16 1F16[HEX] 7958[DEC]

The counter value of the up-counter shows the amount of CR

oscillation of the thermistor when the reference resistance is

oscillated with CR 2,000 times.

Label Mnemonic/operand Comment

HEXDEC MACROARG1, ARG2, ARG3

LOCALHXDC1, HXDC2

;*******************************************************

;* *

;* HEX --> DEC 1 -- 13 DIGIT *

;* *

;*******************************************************

RST F,8 ;Reset D, Z and C flags

LD A,ARG3

ADD A,1 ;Digit ← Digit + 1

;***** ARG2 ZERO CLEAR *****

;***** ARG2 DATA <-- ARG1 TOP DATA *****

LD X,ARG1+ARG3-1

LD Y,ARG2

LD MY,MX ;ARG2 data ← ARG1 data

CP MY,0AH

JP C,$+5 ;If ARG2 data < 0AH

ADD MY,6 ;ARG2 data ← ARG2 data + 6

INC Y ;ARG2 address increment

LDPY MY,1 ;ARG2 data 1 increment

JP $+3

INC Y

LDPY MY,0 ;Zero clear

ADD A,0FH ;Digit counter decrement

JP NZ,$-2 ;If digit counter not = 0

LD B,ARG3-1 ;B-reg. ← Digit - 1

CP B,0

JP Z,HXDC2 ;If Digit = 1

Table 3.7.2

Temperature characteristics

of the thermistor in the

sample program

II-38 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

HXDC1 PUSH B

;***** ARG2 DATA <-- ARG2 DATA * 16D *****

LD B,4 ;Loop counter setting

LD Y,ARG2

LD A,ARG3+2 ;A-reg. ← Digit + 2

RCF ;Reset C flag

SDF ;Set D flag

ACPY MY,MY ;ARG2 data ← 2 * ARG2 data

PUSH F

ADD A,9 ;A-reg. decrement

JP Z,$+3 ;If A-reg. not = 0

POP F

JP $-5

POP F

ADD B,9 ;Loop counter decrement

JP NZ,$-12 ;If loop counter not = 0

;*** ARG2 DATA <-- ARG2 DATA + ARG1 1 DIGIT DATA ****

RST F,8 ;Reset D, Z and C Flags

ADC XL,0FH

ADC XH,0FH ;ARG1 address decrement

LD Y,ARG2

LD B,ARG3+1 ;Digit counter setting

CP MX,0AH

JP C,$+7 ;If ARG1 1 digit data < 0AH

ADD MX,6 ;ARG1 1 digit data + 6

SDF ;Set D flag

RCF ;Reset C flag

ACPY MY,MX

ADC MY,1 ;ARG2 data ← ARG1 1 digit data

JP $+5

RCF ;Reset C flag

SDF ;Set D flag

ACPY MY,MX ;ARG2 data ← ARG1 1 digit data

ADC MY,0 ;If C = 1 then 1 increment

INC Y

PUSH F

ADD B,9 ;Digit counter decrement

JP Z,$+3 ;If digit counter not = 0

POP F

JP $-6

POP F

;***** DIGIT DECREMENT *****

POP B

ADD B,9 ;Digit decrement

JP NZ,HXDC1 ;If digit counter not = 0

HXDC2 RDF ;Reset D flag

ENDM

S1C62N51 TECHNICAL SOFTWARE EPSON II-39

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

ORG 100H

JP INIT ;Initialize and mode selection

HALT ;(101H)

JP INAD ;A/D converter interrupt (102H)

HALT ;(103H)

HALT ;(104H)

HALT ;(105H)

HALT ;(106H)

HALT ;(107H)

INIT LD A,05H ;Set stack pointer to 05H

LD SPH,A

LD A,0

LD SPL,A

LD X,0 ;Clear RAM area (00H–4FH)

CLRRAM LDPX MX,0

CP XH,5H

JP C,CLRRAM

LD X,0ECH ;Set A/D interrupt to Enable

LD MX,1

LD X,0E4H ;Clear up/down counter

UDCCL LDPX MX,0

CP XL,8

JP NZ,UDCCL

LD X,0F5H ;Set complement of 2,000 to up-counter

LDPX MX,0H

LDPX MX,3H

LDPX MX,8H

LDPX MX,0FH

EI ;Set interrupt to Enable

LD X,0F1H ;Start A/D conversion

LD MX,1

HALT

INAD RST F,8

LD A,0

LD B,0

READKN CALL $+2

JP READEND

LD X,10H

PSET 2

JPBA

II-40 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

READEND PUSH B

LD B,4

LD X,0F8H

LD Y,13H

COMP CP MX,MY

JP C,MULTI

JP Z,$+2

JP NC,NEXTREAD

RCF

ADC XL,15

RCF

ADC YL,15

ADD B,15

JP NZ,COMP

JP MULTI

NEXTREADPOP B

ADD A,6 ;Set address of next setting value stored

ADC B,0

JP READKN

MULTI POP B

RCF

SBC A,6

SBC B,0

CALL $+2

JP $+4

LD X,10H

PSET 2

JPBA

LD X,0F5H

LD Y,00H

LD B,4

LDPX MY,MX

INC Y

ADD B,15

JP NZ,$-3

RCF

LD X,10H

LD Y,0H

SCPY MY,MX

INC X

SCPY MY,MX

INC X

SCPY MY,MX

INC X

SCPY MY,MX

S1C62N51 TECHNICAL SOFTWARE EPSON II-41

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

;***** INITIALIZE WORK MEMORY *****

LD X,24H

LD B,4

WMCLR LBPX MX,00

ADD B,15

JP NZ,WMCLR

;***** CALCURATE An X K *****

LD X,0H

LD Y,04H

LD B,4

LDPX MY,MX

INC Y

ADD B,15

JP NZ,$-3

LD MY,0

LD B,1

MULTI00 LD Y,14H

MULTI01 FAN MY,B

LD X,00H

PUSH YL

JP Z,MULTI02

LD X,04H

LD A,2

LD YH,A

CALL SUBROUTADD

LD A,1

LD YH,A

MULTI02 POP YL

INC Y

CP YL,7

JP NZ,MULTI01

RCF

RLC B

JP C,SUBTRA

;***** WORK MEMORY X 2 *****

LD X,04H

RCF

ACPX MX,MX

JP MULTI00

;***** ADD Bn *****

II-42 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

SUBTRA HEXDEC 24H,30H,10 ;Decimal ← 8 digit HEX

LD X,17H ;Set decimal point

LD A,MX

SDF

LD X,1BH

CP MX,1

JP Z,MINUS

PLUS RCF

LD X,18H

LD Y,30H

LD YL,A

PLUS1 ACPY MY,MX

INC X

PUSH F

CP XL,0BH

JP Z,$+3

POP F

JP PLUS1

POP F

RDF

JP ENDPROG+1

MINUS RCF

LD X,18H

LD Y,30H

MINUS1 PUSH F

LD B,YL

CP B,A

JP Z,MINUS2

LD B,0

POP F

SBC B,MY

LD MY,B

INC Y

JP MINUS1

MINUS2 POP F

SBC MX,MY

LD MY,MX

INC X

INC Y

PUSH F

CP XL,0BH

JP Z,$+2

JP MINUS2

POP F

RDF

JP ENDPROG+1

S1C62N51 TECHNICAL SOFTWARE EPSON II-43

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

;***** 16-BIT ADDITION *****

SUBROUTADD

RCF

ACPY MY,MX

INC X

ACPY MY,MX

INC X

ACPY MY,MX

INC X

ACPY MY,MX

INC X

ACPY MY,MX

ENDPROG RET

ORG 200H

;*************************

;* *

;* Kn, An, Bn SETTINGS *

;* *

;*************************

SETCON

;-30°C TO -20°C

LBPX MX,6BH

LBPX MX,00H ;K1 = 06BH (107)

LBPX MX,66H

LBPX MX,30H ;A1 = 3066H (0.102)

LBPX MX,30H

RETD 10H ;B1 = 1030 (-30°C)

;-20°C TO -10°C

LBPX MX,0CDH

LBPX MX,00H ;K1 = 0CDH (205)

LBPX MX,8DH

LBPX MX,42H ;A1 = 428DH (0.0653)

LBPX MX,20H

RETD 10H ;B1 = 1020 (-20°C)

;-10°C TO 0°C

LBPX MX,66H

LBPX MX,01H ;K1 = 166H (358)

LBPX MX,93H

LBPX MX,41H ;A1 = 4193H (0.0403)

LBPX MX,10H

RETD 10H ;B1 = 1010 (-10°C)

;0°C TO 10°C

LBPX MX,5EH

LBPX MX,02H ;K2 = 25EH (606)

LBPX MX,02H

LBPX MX,41H ;A2 = 4102H (0.0258)

II-44 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

LBPX MX,00H

RETD 00H ;B2 = 0000 (0°C)

;10°C TO 20°C

LBPX MX,0E1H

LBPX MX,03H ;K2 = 3E1H (993)

LBPX MX,0AFH

LBPX MX,40H ;A2 = 40AFH (0.0175)

LBPX MX,10H

RETD 00H ;B2 = 0010 (10°C)

;20°C TO 30°C

LBPX MX,1DH

LBPX MX,06H ;K2 = 61DH (1565)

LBPX MX,7AH

LBPX MX,40H ;A2 = 407AH (0.0122)

LBPX MX,20H

RETD 00H ;B2 = 0020 (20°C)

;30°C TO 40°C

LBPX MX,4FH

LBPX MX,09H ;K2 = 94FH (2383)

LBPX MX,66H

LBPX MX,53H ;A2 = 5366H (0.00870)

LBPX MX,30H

RETD 00H ;B2 = 0030 (30°C)

;40°C TO 50°C

LBPX MX,0CCH

LBPX MX,0DH ;K2 = 0DCCH (3532)

LBPX MX,6FH

LBPX MX,52H ;A2 = 526FH (0.00623)

LBPX MX,40H

RETD 00H ;B2 = 0040 (40°C)

;50°C TO 60°C

LBPX MX,12H

LBPX MX,14H ;K2 = 1412H (5138)

LBPX MX,63H

LBPX MX,51H ;A2 = 5163H (0.00355)

LBPX MX,50H

RETD 00H ;B2 = 0050 (50°C)

;60°C LBPX MX,16H

LBPX MX,1FH ;K2 = 1F16H (7958)

RET

S1C62N51 TECHNICAL SOFTWARE EPSON II-45

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

Figure 3.7.4 indicates a flowchart for the sample program.

This sample program sets the amount of oscillation, as the

reference of the counter value, to 2,000 times (decimal), but

determines the amount of oscillation in accordance with the

measurement range and purposes.

in addition, as this program only aims at conversion of

temperature, only the A/D interrupt is set. When using this

program, set the other interrupts according to desired

application.

Fig. 3.7.4

Flowchart

Clear RAM area (00H–4FH)

Set the stack pointer to 50H

Set the A/D interrupt mask

Clear the up/down counter

(E4H–E7H)

Set the reference count in the

up-counter (F5H–F8H)

(set complement, F830H of

2,000 [DEC] times)

Interrupt admitted

Start of A/D conversion

HALT

Occurrence of

the interrupt

Set the number for counting in

the range divided into 10H–1BH,

the coefficient of the linear

approximation of the sector

and the minimum temperature

The up-counter

value being within the

division range

Set the address of the next

division sector data to a PC

Set the data of the previous

sector, to 10H–1BH

Set the difference between the

the up-counter value and the

count number, to 00H–03H

Clear 24H–2BH

Calculate the product of the

difference between the count

numbers and the coefficient

of the linear approximation,

to 24H–2BH

Set the hexadecimal number of

24H–2BH, converting it to the

decimal number, to 30H–39H

The minimum

temperature of the

sector is minus

When adjusting the position of

the decimal point, reduce the

product calculated from the

absolute value of the minimum

temperature and then terminate

the conversion to the desired

temperature

When adjusting the position of

the decimal point, add the mini-

mum temperature and then

terminate the conversion to the

desired temperature

Start 1

Termination

II-46 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

The following explains the ROM data involved in the tem-

perature division sector used in this program.

Label Mnemonic/operand Comment

SETCON

;-30°C TO -20°C

LBPX MX,6BH

LBPX MX,00H ;K1 = 06BH (107)

LBPX MX,66H

LBPX MX,30H ;A1 = 3066H (0.102)

LBPX MX,30H

RETD 10H ;B1 = 1030 (-30°C)

;-20°C TO -10°C

LBPX MX,0CDH

LBPX MX,00H ;K1 = 0CDH (205)

LBPX MX,8DH

LBPX MX,42H ;A1 = 428DH (0.0653)

LBPX MX,20H

RETD 10H ;B1 = 1020 (-20°C)

: :

The first 16-bit data (K1) is the amount of oscillation of the

thermistor against the number of oscillation (2,000 times) of

the reference resistance in the minimum temperature be-

tween the division sector, that is, the counter value of the

up-counter after the A/D converter control. This value can

be calculated through the characteristics of the external

reference resistance, the thermistor, the condenser and the

A/D converter. The sample program is 107 times (6BH) at -

30°C. The data are written in the hexadecimal system.

The next 16-bit data (A1) is the temperature coefficient

which linearly approximates between the division sector.

The temperature coefficient represents the changing quan-

tity of the temperature by one count. For example, when the

counter value of -30°C and -20°C are 107 (6BH) and 205

(0CDH), respectively, the temperature coefficient of the

sector can be calculated using the following formula:

{ (-20) - (-30) } / {205 - 107 } = 0.102 [°C/count]

Minimum counter number within the sector

Minimum counter number of the next sector

Minimum temperature within the sector

Minimum temperature of the next sector

S1C62N51 TECHNICAL SOFTWARE EPSON II-47

CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)

This value is converted to a hexadecimal number including

the position of the decimal point. The lower 12 bits repre-

sent 066H which indicates 102 and the upper 4 bits repre-

sent the number 3 for the times the position of the decimal

point shifts to the left (1/103). The temperature coefficient

at -30°C to -20°C will be 3066H after conversion to a hexa-

decimal number. This similarly applies to other coefficients

between the temperature sectors.

The last 16-bit data (B1) indicates the minimum tempera-

ture of the sector concerned. The data at the temperature of

-30°C represent 1030H.

The upper 4 bits are minus flag, indicating a minus number

if they are 1. The lower 12 bits represent the absolute value

of the temperature. Incidentally, as the lower 12 bits operate

based on the decimal arithmetic system, they are expressed

in the decimal system.

Thus far, we have explained an example of temperature

measurement which calculates the temperature from the

linear approximation using an A/D converter. When using

this program, you should add items necessary for the de-

sired applications and modify as necessary through the

characteristics of the external element. In addition, one

should exercise caution when using the A/D converter for

other purposes.

II-48 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

3.8 Supply Voltage Detection (SVD) Circuit and

Heavy Load Protection Function

The S1C62N51 Series has built-in supply voltage detection

circuit and drop in supply voltage may be detected by con-

trolling the register on the I/O memory. Criteria voltages are

as follows:

Model Criteria Voltage

S1C62N51 2.4 V ± 0.15 V

S1C62L51 1.2 V ± 0.10 V

Moreover, when the battery load becomes heavy, such as

during external piezo buzzer driving or external lamp light-

ing, heavy load protection function is built-in in case the

supply voltage drops. S1C62L51 operates at 0.9 V (1.2 V

when the A/D converter is operated) due to the SVD circuit

and heavy load protection function.

SVD circuit and

heavy load protec-

tion function mem-

ory map

Table 3.8.1 I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always 0 when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0FAH

SVDON

R/W

HLMOD

SVDDT

SVDON

Heavy load protection mode register

Supply voltage detection data

Supply voltage detection circuit On/Off

Heavy

Low

Normal

Off

SVDDT0HLMOD

R/W

S1C62N51 TECHNICAL SOFTWARE EPSON II-49

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Control of the SVD

circuit

The SVD circuit will turn ON by writing "1" on the SVDON

tion will be performed. By writing "0" on the SVDON register,

the detection result is stored in the SVDDT register. How-

ever, in order to obtain a stable detection result, it is neces-

sary to turn the SVD circuit ON for at least 100 µs. Accord-

ingly, reading out the detection result from the SVDDT

➀Set the SVDON register to "1".

➁Provide at least 100 µs waiting time.

➂Set the SVDON register to "0".

➃Read-out from the SVDDT register.

Note, however, that when S1C62N51 is to be used with the

normal system clock at fosc = 32.768 kHz, there is no need

for the waiting time stated in the above procedure ➁ since 1

instruction cycle will take longer than 100 µs.

Because the power current consumption of the IC becomes

large when the SVD circuit is operated, turn the SVD circuit

OFF when not in use. The operation timing chart is shown

in Figure 3.8.1.

Label Mnemonic/operand Comment

LD X,0FAH ;Sets the address of SVDON

OR MX,0001B ;Sets SVDON to "1"

AND MX,1110B ;Sets SVDON to "0"

LD A,MX ;Loads the detection result

;into the A register

Example of SVD

circuit control

program

Fig. 3.8.1

Timing chart of

supply voltage

detection operation

through the SVDON

Supply voltage

Criteria voltage

SVDON register

SVD circuit

SVDDT register

HLMOD register

100 µs or more

II-50 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Heavy load protec-

tion function

Note that the heavy load protection function on the

S1C62L51 is different from the S1C62N51.

(1)In case of S1C62L51

The S1C62L51 has the heavy load protection function for

when the battery load becomes heavy and the source

voltage drops, such as when an external buzzer sounds

or an external lamp lights. The state where the heavy

load protection function is in effect is called the heavy

load protection mode. In this mode, operation with a

lower voltage than normal is possible.

The normal mode changes to the heavy load protection

mode in the following two cases:

➀When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

➁When supply voltage drop (SVDDT = "1") in the SVD

circuit is detected, the mode will automatically shift to

the heavy load protection mode until the supply volt-

age is recovered (SVTDT = "0")

In the heavy load protection mode, the internally regu-

lated voltage is generated by the liquid crystal driver

source output VL2 so as to operate the internal circuit.

Consequently, more current is consumed in the heavy

load protection mode than in the normal mode. Unless it

is necessary, be careful not to set the heavy load protec-

tion mode with the software. Also, to reduce current

consumption, do not set the SVDON to ON in the heavy

load protection mode.

(2)In case of S1C62N51

The S1C62N51 has the heavy load protection function for

when the battery load becomes heavy and the source

voltage changes, such as when an external buzzer sounds

or an external lamp lights. The state where the heavy

load protection function is in effect is called the heavy

load protection mode. Compared with the normal opera-

tion mode, this mode can reduce the output voltage

variation of the constant voltage/booster voltage circuit of

the LCD system.

S1C62N51 TECHNICAL SOFTWARE EPSON II-51

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

The normal mode changes to the heavy load protection

mode in the following case:

• When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

The heavy load protection mode switches the constant

voltage circuit of the LCD system to the high-stability

mode from the low current consumption mode. Conse-

quently, more current is consumed in the heavy load

protection mode than in the normal mode. Unless it is

necessary, be careful not to set the heavy load protection

mode with the software.

Fig. 3.8.3

Timing chart of heavy

load protection

function operation

through the SVDON

Fig. 3.8.2

Timing chart of

supply voltage

detection operation

through the HLMOD

Supply voltage

Criteria voltage

HLMOD register

Heavy load

protection mode

2 Hz clock

SVD circuit

SVDDT register

SVDON register

100 µs or more

Supply voltage

Criteria voltage

SVDON register

2 Hz clock

SVD circuit

SVDDT register

Heavy load

protection mode

HLMOD register

II-52 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Examples of heavy

load protection

function control

program

• Operation through the HLMOD register

This is a sample program when lamp is driven with the

R00 terminal during performance of heavy load protec-

tion.

Label Mnemonic/operand Comment

LD X,0FAH ;Sets the address of HLMOD

OR MX,1000B ;Sets to the heavy load protection mode

LD Y,0F3H ;Sets the address of R0n port

OR MY,0001B ;Turns lamp ON

LD Y,0F3H ;Sets the R0n port address

AND MY,1110B ;Turns the lamp OFF

CALL WT1S ;1 second waiting time (software timer)

AND MX,0111B ;Cancels the heavy load protection mode

In the above program, the heavy load protection mode is

canceled after 1 sec waiting time provided as the time for

the battery voltage to stabilize after the lamp is turned

off; however, since this time varies according to the

nature of the battery, time setting must be done in accor-

dance with the actual application.

S1C62N51 TECHNICAL SOFTWARE EPSON II-53

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

• Operation through the SVDON register

Label Mnemonic/operand Comment

LD X,0FAH ;Sets the HLMOD/SVDDT address

FAN MX,1010B ;Checks the HLMOD/SVDDT bits

JP NZ,HLMOD ;Heavy load protection mode

OR MX,0001B ;Sets the SVDON to "1"

AND MX,1110B ;Sets the SVDON to "0"

FAN A,0010B ;Checks the SVDDT bit

JP Z,HLMOD ;Shifts the mode to

;the heavy load protection mode

LD Y,FLAG

AND MY,0 ;Resets the flag to "0"

RET

;

HLMOD: LD Y,FLAG

OR MY,1 ;Sets the flag to "1"

RET

The above program operates the heavy load protection

function by using the SVDON register. In the normal

operation mode, supply voltage detection is done from the

SVDON register and when the supply voltage drops below

the criteria voltage, the mode shifts to the heavy load

protection mode. In the heavy load protection mode,

supply voltage detection by the hardware is done every 2

Hz and the detection result is stored in the SVDDT regis-

ter. Because of this, the SVDDT register will be "1" during

the heavy load protection mode. Moreover, in the above

program, supply voltage detection by the SVDON is

halted during the heavy load protection mode. If the

supply voltage become grater than the criteria voltage,

the SVDDT register value will become "0" and hence,

supply voltage detection through the SVDON register will

resume after checking the SVDDT register value. When

used as a sub-routine, the above program will enable the

user to determine whether the present operation mode is

the normal operation mode (flag = "0") or the heavy load

protection mode (flag = "1").

The flowchart for the above program is shown in the next

page.

II-54 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)

Fig. 3.8.4

Flowchart of operation

through the SVDON register

Start

RET

FLAG←0

HLMOD?

SVDDT?

SVDON←1

SVDON←0

FLAG←1

S1C62N51 TECHNICAL SOFTWARE EPSON II-55

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

3.9 Interrupt and Halt

Table 3.9.1 I/O memory map

Interrupt memory

map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

II-56 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Control of interrupts

and halt

The S1C62N51 supports three types of a total of 8

interrupts. There are three timer interrupts (2 Hz, 8 Hz, 32

Hz), one A/D interrupt and four input interrupts (K00–K03).

The 8 interrupts are individually enabled or masked (dis-

abled) by interrupt mask registers. The EI and DI instruc-

tions can be used to set or reset the interrupt flag (I), which

enables or disables all the interrupts at the same time.

When an interrupt is accepted, the interrupt flag (I) is reset,

and cannot accepts any other interrupts (DI state).

Restart from the halt state created by the HALT instruction,

is done by interrupt.

• Interrupt factor flags

This flag is set when any of the K00 to K03 input interrupts

occurs. The interrupt factor flag (IK0) is set to "1" when the

contents of the input (K00–K03) become "1" and the data of

the corresponding interrupt mask register (EIK00–EIK03) is

"1".

The contents of the IK0 flag can be loaded by software to

determine whether the K00–K03 input interrupts have

occured.

The flag is reset when loaded by software. (See Figure

3.9.1.)

IK0

S1C62N51 TECHNICAL SOFTWARE EPSON II-57

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Fig. 3.9.1

K00–K03

Input interrupt circuit

This flag is set to "1" when a falling edge is detected in the

timer TM1 (32 Hz) signal.

The contents of the IT32 flag can be loaded by software to

determine whether a 32 Hz timer interrupt has occured.

The flag is reset, when it is loaded by software. (See Figure

3.9.2.)

IT32

Address 0E8H

Input interrupt mask register

(EIK00–EIK03)

Input interrupt factor

flag register (IK0)

INT

(Interrupt request)

Interrupt flag (I)

K03

K02

K01

K00

Address 0E0H

Data bus

II-58 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

This flag is set to "1" when a falling edge is detected in the

timer TM1 (8 Hz) signal.

The contents of the IT8 flag can be loaded by software to

determine whether an 8 Hz timer interrupt has occured.

The flag is reset, when it is loaded by software. (See Figure

3.9.2.)

This flag is set to "1" when a falling edge is detected in the

timer TM1 (2 Hz) signal.

The contents of the IT2 flag can be loaded by software to

determine whether a 2 Hz timer interrupt has occured.

The flag is reset, when it is loaded by software. (See Figure

3.9.2.)

IT8

IT2

Fig. 3.9.2

Timer interrupt circuit

Address 0EFH

Address 0EBH

Timer interrupt

mask register (EIT)

Timer interrupt

factor flag (IT)

INT

(Interrupt request)

Interrupt flag (I)

Data bus

Data bus Basic clock counter

32 Hz

8 Hz

2 Hz

S1C62N51 TECHNICAL SOFTWARE EPSON II-59

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

When the counted value reaches "0" during the counting-

down or counting-up operation of the up/down counter, this

flag is set to "1" at the falling edge of the next signal during

counting-down operation and at the rising edge of the next

signal during counting-up operation.

The contents of the IAD flag can be loaded by software to

determine whether an A/D interrupt has occurred.

The flag is reset, when it is loaded by software.

IAD

Reading of interrupt factor flags is available at EI, but be careful in

the following cases.

If the interrupt mask register value corresponding to the interrupt

factor flags to be read is set to "1", an interrupt request will be

generated by the interrupt factor flags set timing, or an interrupt

request will not be generated. Be very careful when interrupt factor

flags are in the same address.

Note

Fig. 3.9.3

A/D interrupt circuit

Address 0ECH

A/D converter

mask register (EIAD)

A/D converter

factor flag (IAD)

INT

(Interrupt request)

Interrupt flag (I)

Data bus

Data bus Up/down counter

Address 0F0H

II-60 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Interrupt mask registers

The interrupt mask registers are registers that individually

specify whether to enable or mask the timer interrupt (2 Hz,

8 Hz, 32 Hz), A/D interrupt, or input interrupt (K00–K03).

The following are descriptions of the interrupt mask regis-

ters.

EIK00 to EIK03 This register enables or masks the K00–K03 input interrupt.

The interrupt factor flag (IK0) is set to "1" when the contents

of the input (K00–K03) become "1" and the data of the

corresponding interrupt mask register (EIK00–EIK03) is "1".

The CPU is interrupted if it is in the EI state (interrupt flag

[I] = "1"). (See Figure 3.9.1.)

EIT32 This register enables or masks the 32 Hz timer interrupt.

The CPU is interrupted if it is in the EI state when the

interrupt mask register (EIT32) is set to "1" and the inter-

rupt factor flag (IT32) is "1". (See Figure 3.9.2.)

EIT8 This register enables or masks the 8 Hz timer interrupt. The

CPU is interrupted if it is in the EI state when the interrupt

mask register (EIT8) is set to "1" and the interrupt factor flag

(IT8) is "1". (See Figure 3.9.2.)

This register enables or masks the 2 Hz timer interrupt. The

CPU is interrupted if it is in the EI state when the interrupt

mask register (EIT2) is set to "1" and the interrupt factor flag

(IT2) is "1". (See Figure 3.9.2.)

EIT2

EIAD This register enables or masks the A/D interrupt. The CPU

is interrupted if it is in the EI state when the interrupt mask

is "1". (See Figure 3.9.3.)

S1C62N51 TECHNICAL SOFTWARE EPSON II-61

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Interrupt vector address

The S1C62N51 interrupt vector address is made up of the

low-order 3 bits of the program counter (12 bits), each of

which is assigned a specific function as shown in Figure

3.9.4.

Note that all of the three timer interrupts have the same

vector address, and software must be used to judge whether

or not a given timer interrupt has occurred. For instance,

when the 32 Hz timer interrupt and the 8 Hz timer interrupt

are enabled at the same time, the accepted timer interrupt

must be identified by software. (Similarly, the K00–K03

input interrupts and A/D interrupt must be identified by

software.)

When an interrupt is generated, the hardware resets the

interrupt flag (I) to enter the DI state. Execute the EI in-

struction as necessary to recover the EI state after interrupt

processing.

Set the EI state at the start of the interrupt processing

routine to allow nesting of the interrupts.

The interrupt factor flags must always be reset before set-

ting the EI status in the corresponding interrupt processing

routine. (The flag is reset when the interrupt factor flag is

read by software.)

Fig. 3.9.4

Assignment of the

interrupt vector address

PCP3

PCP2

PCP1

PCP0

PCS7

PCS6

PCS5

PCS4

PCS3

PCS2

PCS1

PCS0

Input (K00–K03) interrupt

A/D interrupt

Clock timer interrupt

II-62 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

If the EI instruction is executed without resetting the inter-

rupt factor flag after generating the timer interrupt or A/D

interrupt, and if the corresponding interrupt mask register

is still "1", the same interrupt is generated once more. (See

Figure 3.9.5.)

If the EI state is set without resetting the interrupt factor

flag after generating the input interrupt (K00–K03), the same

interrupt is generated once more. (See Figure 3.9.5.)

The interrupt factor flag must always be read (reset) in the

DI state (interrupt flag [I] = "0"). There may be an operation

error if read in the EI state.

The timer interrupt factor flags (IT32, IT8, IT2) and A/D

interrupt factor flag (IAD) are set whether the corresponding

interrupt mask register is set or not.

The input interrupt factor flag (IK0) is allowed to be set in

the condition when the corresponding interrupt mask regis-

ter (EIK00–EIK03) is set to "1" (interrupt is enabled). (See

Figure 3.9.5.)

Table 3.9.2 shows the interrupt vector map.

Step Interrupt vector

Initial reset

Clock timer interrupt

A/D interrupt

Clock timer interrupt and A/D interrupt

Input (K00–K03) interrupt

Input interrupt and clock timer interrupt

Input interrupt and A/D interrupt

Generation of all interrupt

Page

00H

01H

02H

03H

04H

05H

06H

07H

Table 3.9.2

Interrupt vector map

Addresses (start address of interrupt processing routines) to

jump to are written into the addresses available for interrupt

vector allocation.

S1C62N51 TECHNICAL SOFTWARE EPSON II-63

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Restart from halt state by interrupt

Main routine

Label Mnemonic/operand Comment

LD X,0E8H ;Set address of K00 to K03

;interrupt mask register

OR MX,1111B ;Enable K00 to K03

;input interrupt

;LD X,0ECH ;Set address of A/D interrupt

;mask register

OR MX,0001B ;Enable A/D interrupt

;LD X,0EBH ;Set address of timer interrupt

;mask register

OR MX,0111B ;Enable timer interrupt

;(32 Hz, 8 Hz, 2 Hz)

MAIN: EI ;Set interrupt flag (EI state is set)

HALT ;Halt mode

JP MAIN ;Jump to MAIN

Examples of interrupt

and halt control

program

Fig. 3.9.5

Internal interrupt

circuit

K00

EIK00

K01

EIK01

K02

EIK02

K03

EIK03

IAD

EIAD

IT2

EIT2

IT8

EIT8

IT32

EIT32

IK0

(MSB)

(LSB)

Program counter of CPU

(three low-order bits)

Interrupt vector

Interrupt factor flag

Interrupt mask register

Interrupt flag

INT

(Interrupt request)

II-64 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

Interruption vector routine

Label Mnemonic/operand Comment

ORG 100H

JP INIT

JP INTR ;Timer interrupt is generated

JP INTR ;A/D interrupt is generated

JP INTR ;Timer interrupt, A/D interrupt

;are generated

JP INTR ;K00 to K03 interrupt is generated

JP INTR ;Timer interrupt, K00 to K03 interrupt

;are generated

JP INTR ;A/D interrupt, K00 to K03 interrupt

;are generated

JP INTR ;Timer interrupt, A/D interrupt,

;K00 to K03 interrupt are generated

;

INTR: LD X,0EFH ;Address of timer interrupt factor flag

LD Y,TMFSK ;Address of timer interrupt factor flag buffer

LD MY,MX

FAN MY,0100B ;Check 2 Hz timer interrupt

JP Z,TI8RQ ;Jump if not 2 Hz timer interrupt

CALL TINT2 ;Call 2 Hz timer interrupt service routine

TI8RQ: LD Y,TMFSK ;Address of timer factor flag buffer

FAN MY,0010B ;Check 8 Hz timer interrupt

JP Z,TI32RQ ;Jump if not 8 Hz timer interrupt

CALL TINT8 ;Call 8 Hz timer interrupt service routine

TI32RQ: LD Y,TMFSK ;Address of timer factor flag buffer

FAN MY,0001B ;Check 8 Hz timer interrupt

JP Z,ADRQ ;Jump if not 32 Hz timer interrupt

CALL TINT32 ;Call 32 Hz timer interrupt service routine

ADRQ: LD X,0F0H ;Address of A/D interrupt factor flag

FAN MX,0001B ;Check A/D interrupt factor flag

JP Z,IK0RQ ;Jump if not A/D interrupt

CALL ADIN ;Call A/D interrupt service routine

S1C62N51 TECHNICAL SOFTWARE EPSON II-65

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

IK0RQ: LD X,0EDH ;Address of K00 to K03 input interrupt flag

FAN MX,0001B ;Check K00 to K03 input interrupt

JP Z,INTEND ;Jump if not K00 to K03 input interrupt

CALL IK0INT ;Call K00 to K03 input interrupt service

;routine

INTEND: EI

RET

The above program is normally used to restart the CPU

when in the halt state by interrupt and to return it to the

halt state again after the interrupt processing is completed.

The processing proceeds by repeating the → halt interrupt

→ halt → interrupt cycle.

The interrupt factor flag is reset when load by the software.

Thus, when using interrupts which interrupt factor flags are

in the same address at the same time, flag check must be

done after storing the data. For example, store the 1 word

including the factor flag in the RAM. (If check is directly

done by the FAN instruction, the factor flags of the same

address are all reset.)

Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to "1", an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated.

II-66 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

CHAPTER 4 SUMMARY OF PROGRAMMING

POINTS

• Core CPU After the system reset, only the program counter (PC),

new page pointer (NPP) and interrupt flag (I) are initial-

ized by the hardware. The other internal circuits whose

settings are undefined must be initialized with the pro-

gram.

• Power Supply External load driving through the output voltage of con-

stant voltage circuit or booster circuit is not permitted.

• Data Memory – Since some portions of the RAM are also used as stack

area during subroutine call or register saving, see to it

that the data area and the stack area do not overlap.

– The stack area consumes 3 words during a subroutine

call or interrupt.

– Address 00H–0FH in the RAM is the memory register area

addressed by the register pointer RP.

– Memory is not mounted in unused area within the mem-

ory map and in memory area not indicated in this man-

ual. For this reason, normal operation cannot be assured

for programs that have been prepared with access to

these areas.

• Initial Reset – Maintain the initial reset circuit at high level for at least 4

seconds (in case of oscillation frequency fosc = 32 kHz)

because noise rejector is built-in.

– When utilizing the simultaneous high input reset func-

tion of the input ports (K00–K03), take care not to make

the ports specified during normal operation to go high

simultaneously.

• Input Port When modifying the input port from high level to low level

with pull-down resistance, a delay will occur at the rise of

the waveform due to time constant of the pull-down

resistance and input gate capacities. Provide appropriate

waiting time in the program when performing input port

reading.

S1C62N51 TECHNICAL SOFTWARE EPSON II-67

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

• Output Port The FOUT and BUZZER output signal may produce

hazards when the output ports R00 and R01 are turned

on or off.

• I/O Port – When the I/O port is set to the output mode and a low-

impedance load is connected to the port pin, the data

written to the register may differ from the data read.

– When the I/O port is set to the input mode and a low-

level voltage (VSS) is input by the built-in pull-down

resistance, an erroneous input results if the time con-

stant of the capacitive load of the input line and the built-

in pull-down resistance load is greater than the read-out

time. When the input data is being read, the time that the

input line is pulled down is equivalent to 0.5 cycles of the

CPU system clock.

Hence, the electric potential of the pins must settle within

0.5 cycles. If this condition cannot be met, some measure

must be devised, such as arranging a pull-down resist-

ance externally, or performing multiple read-outs.

• LCD Driver – Because the display memory is for writing only, re-writing

the contents with computing instructions (e.g., AND, OR,

etc.) which come with read-out operations is not possible.

To perform bit operations, a buffer to hold the display

data is required on the RAM.

– Even when 1/2 duty is selected, the display data corre-

sponding to COM2 and COM3 are valid for static drive.

Hence, for static drive set the same value to all display

memory corresponding COM0–COM3.

– Even when 1/3 duty is selected, the display data corre-

sponding to COM3 is valid for static drive. Hence, for

static drive set the same value to all display memory

corresponding COM0–COM3.

– For cadence adjustment, set the display data including

display data corresponding to COM3.

– fosc indicates the oscillation frequency of the oscillation

circuit.

II-68 EPSON S1C62N51 TECHNICAL SOFTWARE

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

– Depending on the initial value of the up-counter C0–C15,

the up/down counter TC0–TC15 may overflow while the

CR oscillation clock is being counted. When setting the

initial value, pay attention to CR oscillation frequency, its

fluctuation range and the input clock frequency of the

up/down counter. If the up/down counter overflows, A/D

conversion is terminated immediately, and correct meas-

urement is impossible.

– If the up/down counter TC0–TC15 is measured after A/D

conversion, it may not indicate "0000H". This is not due

to incorrect timing in terminating A/D conversion but

because the counting down clock is input after the con-

trol signal is output to the up-counter to terminate

counting.

• A/D Converter

• Supply Voltage Detec-

tion (SVD) Circuit Since supply voltage detection is automatically performed

by the hardware every 2 Hz (0.5 sec) when the heavy load

protection function operates, do not permit the operation

of the SVD circuit by the software in order to minimize

power current consumption.

• Heavy Load Protec-

tion Function In the heavy load protection function (heavy load protec-

tion mode flag = "1"), supply voltage detection through

the SVDON register is not permitted in order to minimize

power current consumption.

• Interrupt – Restart from the HALT state is performed by the inter-

rupt. The return address after completion of the interrupt

processing in this case will be the address following the

HALT instruction.

– When interrupt occurs, the interrupt flag will be reset by

the hardware and it will become DI state. After comple-

tion of the interrupt processing, set to the EI state

through the software as needed.

Moreover, the nesting level may be set to be program-

mable by setting to the EI state at the beginning of the

interrupt processing routine.

S1C62N51 TECHNICAL SOFTWARE EPSON II-69

CHAPTER 4: SUMMARY OF PROGRAMMING POINTS

– Be sure to reset the interrupt factor flag before setting to

the EI state on the interrupt processing routine. The

interrupt factor flag is reset by reading through the

software. Not resetting the interrupt factor flag and

interrupt mask register being "1", will cause the same

interrupt to occur again.

– The interrupt factor flag will be reset by reading through

the software. Because of this, when multiple interrupt

factor flags are to be assigned to the same address,

perform the flag check after the contents of the address

has been stored in the RAM. Direct checking with the

FAN instruction will cause all the interrupt factor flag to

be reset.

– Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to "1", an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated.

• Vacant Register and

Read/Write Writing data into the addresses where read/write bits

and read only bits are mixed in 1 word (4 bits) does not

affect the read only bits.

II-70 EPSON S1C62N51 TECHNICAL SOFTWARE

APPENDIX A TABLE OF INSTRUCTIONS

APPENDIX A Table of Instructions

C, s

NC, s

Z, s

NZ, s

X, x

Y, y

XH, r

XL, r

YH, r

YL, r

r, XH

r, XL

r, YH

r, YL

XH, i

XL, i

YH, i

YL, i

PSET

JPBA

CALL

CALZ

RET

RETS

RETD

NOP5

NOP7

HALT

INC

ADC

Branch

instructions

System

control

instructions

Index

operation

instructions

Classification Operand

IDZC

↑

Clock

Operation Code Flag

NBP p4, NPP p3~p0

PCB NBP, PCP NPP, PCS s7~s0

PCB NBP, PCP NPP, PCS s7~s0 if C=1

PCB NBP, PCP NPP, PCS s7~s0 if C=0

PCB NBP, PCP NPP, PCS s7~s0 if Z=1

PCB NBP, PCP NPP, PCS s7~s0 if Z=0

←

←←

←

PCB NBP, PCP NPP, PCSH B, PCSL A

M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1

SP SP-3, PCP NPP, PCS s7~s0

M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1

SP SP-3, PCP 0, PCS s7~s0

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3, PC PC+1

PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)

SP SP+3, M(X) i3~i0, M(X+1) l7~l4, X X+2

No operation (5 clock cycles)

No operation (7 clock cycles)

Halt (stop clock)

X X+1

Y Y+1

XH x7~x4, XL x3~x0

YH y7~y4, YL y3~y0

r XH

r XL

r YH

r YL

←←

←←←

←←← ←←←

←←←

←←← ←

←← ←← ←

←←←←

←

←←

←

←←

←

Mne-

monic Operation

XH+i3~i0+C

XL+i3~i0+C

YH+i3~i0+C

YL+i3~i0+C

↓

S1C62N51 TECHNICAL SOFTWARE EPSON II-71

APPENDIX A TABLE OF INSTRUCTIONS

XH, i

XL, i

YH, i

YL, i

r, i

r, q

A, Mn

B, Mn

Mn, A

Mn, B

MX, i

r, q

MY, i

r, q

MX, l

F, i

LDPX

LDPY

LBPX

SET

RST

SCF

RCF

SZF

RZF

SDF

RDF

INC

DEC

PUSH

POP

Index

operation

instructions

Data

transfer

instructions

Flag

operation

instructions

Stack

operation

instructions

Classification Operand

IDZC

↑

↓

↑

↓

↑

↓

↑

↓

↑

↓

↑

↓

Clock

Operation Code Flag

XH-i3~i0

XL-i3~i0

YH-i3~i0

YL-i3~i0

r i3~i0

r q

M(n3~n0) A

M(n3~n0) B

M(X) i3~i0, X X+1

r q, X X+1

M(Y) i3~i0, Y Y+1

r q, Y Y+1

M(X) l3~l0, M(X+1) l7~l4, X X+2

←

←←

←

←← ←←

Mne-

monic Operation

↓

↑

↓

↑

↓

SP SP+1

SP SP-1

SP SP-1, M(SP) r

SP SP-1, M(SP) XH

SP SP-1, M(SP) XL

SP SP-1, M(SP) YH

SP SP-1, M(SP) YL

SP SP-1, M(SP) F

r M(SP), SP SP+1

←

M(n3~n0)

←

←←

←

F i3~i0

1 (Decimal Adjuster ON)

0 (Decimal Adjuster OFF)

1 (Enables Interrupt)

0 (Disables Interrupt)

←

←←

←

M(SP), SP SP+1

←

II-72 EPSON S1C62N51 TECHNICAL SOFTWARE

APPENDIX A TABLE OF INSTRUCTIONS

d3 d2, d2 d1, d1 d0, d0 C, C d3

d3 C, d2 d3, d1 d2, d0 d1, C d0

M(n3~n0) M(n3~n0)+1

M(n3~n0) M(n3~n0)-1

↓

SPH, r

SPL, r

r, SPH

r, SPL

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

r, i

r, q

MX, r

MY, r

MX, r

MY, r

POP

ADD

ADC

SUB

SBC

AND

XOR

FAN

RLC

RRC

INC

DEC

ACPX

ACPY

SCPX

SCPY

NOT

Stack

operation

instructions

Arithmetic

instructions

Classification Operand

IDZC

↑↑

↑

Clock

Operation Code Flag

F M(SP), SP SP+1

SPH

SPL

r SPH

r SPL

←

Mne-

monic Operation

↓

↑

←

↓↓

★

r r+i3~i0

r r+q

r r+i3~i0+C

r r+q+C

r r-q

r r-i3~i0-C

r r-q-C

r r i3~i0

r r q

r r i3~i0

r r q

r r i3~i0

r r q

r-i3~i0

r-q

r i3~i0

r q

M(X) M(X)+r+C, X X+1

M(Y) M(Y)+r+C, Y Y+1

M(X) M(X)-r-C, X X+1

M(Y) M(Y)-r-C, Y Y+1

r r

M(SP), SP SP+1

←

←←

←

←←← ←

←← ← ←←

←

S1C62N51 TECHNICAL SOFTWARE EPSON II-73

APPENDIX A TABLE OF INSTRUCTIONS

Abbreviations used in the explanations have the following

meanings.

A .............. A register

B .............. B register

X .............. XHL register (low order eight bits of index

Y .............. YHL register (low order eight bits of index

XH ........... XH register (high order four bits of XHL register)

XL ............ XL register (low order four bits of XHL register)

YH............ YH register (high order four bits of YHL register)

YL ............ YL register (low order four bits of YHL register)

XP ............ XP register (high order four bits of index

YP ............ YP register (high order four bits of index

SP ............ Stack pointer SP

SPH.......... High-order four bits of stack pointer SP

SPL .......... Low-order four bits of stack pointer SP

MX, M(X) .. Data memory whose address is specified with

index register IX

MY, M(Y)... Data memory whose address is specified with

index register IY

Mn, M(n) .. Data memory address 000H–00FH (address

specified with immediate data n of 00H–0FH)

M(SP) ....... Data memory whose address is specified with

stack pointer SP

r, q ........... Two-bit register code

r, q is two-bit immediate data; according to the

contents of these bits, they indicate registers A,

B, and MX and MY (data memory whose ad-

dresses are specified with index registers IX and

IY) rq

r1 r0 q1 q0

0000 A

0101 B

1010 MX

1111 MY

Registers specified

Symbols associated with

registers and memory

II-74 EPSON S1C62N51 TECHNICAL SOFTWARE

APPENDIX A TABLE OF INSTRUCTIONS

NBP..... New bank pointer

NPP ..... New page pointer

PCB..... Program counter bank

PCP ..... Program counter page

PCS ..... Program counter step

PCSH .. Four high order bits of PCS

PCSL ... Four low order bits of PCS

F ......... Flag register (I, D, Z, C)

C ......... Carry flag

Z ......... Zero flag

D......... Decimal flag

I .......... Interrupt flag

↓............. Flag reset

↑............. Flag set

↕.......... Flag set or reset

p ......... Five-bit immediate data or label 00H–1FH

s.......... Eight-bit immediate data or label 00H–0FFH

l .......... Eight-bit immediate data 00H–0FFH

i .......... Four-bit immediate data 00H–0FH

+ ......... Add

- .......... Subtract

∧............. Logical AND

∨............. Logical OR

∀ ............ Exclusive-OR

★......... Add-subtract instruction for decimal operation

when the D flag is set

Symbols associated with

program counter

Symbols associated with

flags

Associated with

immediate data

Associated with

arithmetic and other

operations

S1C62N51 TECHNICAL SOFTWARE EPSON II-75

APPENDIX B RAM MAP

APPENDIX B RAM Map

PROGRAM NAME: C251_____

MAME

MSB

LSB

MAME

MSB

LSB

MAME

MSB

LSB

MAME

MSB

LSB

MAME

MSB

LSB

0123456789ABCDEF

II-76 EPSON S1C62N51 TECHNICAL SOFTWARE

APPENDIX B RAM MAP

PROGRAM NAME: C251_____

MAME

MSB

LSB

MAME

MSB

LSB

MAME

MSB

LSB

MAME

MSB

LSB

0123456789ABCDEF

—

ZK03

ZK02

ZK01

ZK00

—

ZIAD

—

ZADRUN

—

ZTM3

ZTM2

ZTM1

ZTM0

—

ZR03

ZR02

ZR01

ZR00

—

ZTC3

ZTC2

ZTC1

ZTC0

—

ZP03

ZP02

ZP01

ZP00

—

ZTC7

ZTC6

ZTC5

ZTC4

—

ZC3

ZC2

ZC1

ZC0

—

ZTC11

ZTC10

ZTC9

ZTC8

—

ZC7

ZC6

ZC5

ZC4

—

ZTC15

ZTC14

ZTC13

ZTC12

—

ZC11

ZC10

ZC9

ZC8

—

ZTMRST

—

ZHLMOD

—

ZSVDDT

ZSVDON

—

ZEIT2

ZEIT8

ZEIT32

—

ZCSDC

—

ZEIAD

—

ZIOC

—

ZIK0

—

ZXBZR

—

ZFOUT1

ZFOUT0

—

ZADCLK

—

ZIT2

ZIT8

ZIT32

—

ZEIK03

ZEIK02

ZEIK01

ZEIK00

—

ZC15

ZC14

ZC13

ZC12

S1C62N51 TECHNICAL SOFTWARE EPSON II-77

APPENDIX C TABLE OF THE ICE COMMANDS

APPENDIX C Table of the ICE Commands

Assemble

Disassemble

Dump

Fill

Set

Run Mode

Trace

Break

Move

Data Set

Change CPU

Internal

Registers

#A,a

#L,a1,a2

#DP,a1,a2

#DD,a1,a2

#FP,a1,a2,d

#FD,a1,a2,d

#G,a

#TIM

#OTF

#T,a,n

#U,a,n

#BA,a

#BAR,a

#BD

#BDR

#BR

#BRR

#BM

#BMR

#BRES

#BC

#BE

#BSYN

#BT

#BRKSEL,REM

#MP,a1,a2,a3

#MD,a1,a2,a3

#SP,a

#SD,a

#DR

#SR

#DXY

#SXY

Assemble command mnemonic code and store at address "a"

Contents of addresses a1 to a2 are disassembled and displayed

Contents of program area a1 to a2 are displayed

Content of data area a1 to a2 are displayed

Data d is set in addresses a1 to a2 (program area)

Data d is set in addresses a1 to a2 (data area)

Program is executed from the "a" address

Execution time and step counter selection

On-the-fly display selection

Executes program while displaying results of step instruction

from "a" address

Displays only the final step of #T,a,n

Sets Break at program address "a"

Breakpoint is canceled

Break condition is set for data RAM

Breakpoint is canceled

Break condition is set for Evaluation Board CPU internal registers

Breakpoint is canceled

Combined break conditions set for program data RAM address

and registers

Cancel combined break conditions for program data ROM

address and registers

All break conditions canceled

Break condition displayed

Enter break enable mode

Enter break disable mode

Set break stop/trace modes

Set BA condition clear/remain modes

Contents of program area addresses a1 to a2 are moved to

addresses a3 and after

Contents of data area addresses a1 to a2 are moved to addresses

a3 and after

Data from program area address "a" are written to memory

Data from data area address "a" are written to memory

Item No. Function Command Format Outline of Operation

Display Evaluation Board CPU internal registers

Set Evaluation Board CPU internal registers

Reset Evaluation Board CPU

Display X, Y, MX and MY

Set data for X and Y display and MX, MY

II-78 EPSON S1C62N51 TECHNICAL SOFTWARE

APPENDIX C TABLE OF THE ICE COMMANDS

History

File

Coverage

ROM Access

Terminate

ICE

Command

Display

Self

Diagnosis

#H,p1,p2

#HB

#HG

#HP

#HPS,a

#HC,S/C/E

#HA,a1,a2

#HAR,a1,a2

#HAD

#HS,a

#HSW,a

#HSR,a

#RF,file

#RFD,file

#VF,file

#VFD,file

#WF,file

#WFD,file

#CL,file

#CS,file

#CVD

#CVR

#RP

#VP

#ROM

#HELP

#CHK

Display history data for pointer 1 and pointer 2

Display upstream history data

Display 21 line history data

Display history pointer

Set history pointer

Sets up the history information acquisition before (S),

before/after (C) and after (E)

Sets up the history information acquisition from program area

a1 to a2

Sets up the prohibition of the history information acquisition

from program area a1 to a2

Indicates history acquisition program area

Retrieves and indicates the history information which executed

a program address "a"

Retrieves and indicates the history information which wrote or

read the data area address "a"

Save contents of memory to program file

Save contents of memory to data file

Load ICE set condition from file

Save ICE set condition to file

Terminate ICE and return to operating system control

Display ICE instruction

Report results of ICE self diagnostic test

Move program file to memory

Move data file to memory

Compare program file and contents of memory

Compare data file and contents of memory

Indicates coverage information

Clears coverage information

Move contents of ROM to program memory

Compare contents of ROM with contents of program memory

Set ROM type

Item No. Function Command Format Outline of Operation

means press the RETURN key.

S1C62N51 TECHNICAL SOFTWARE EPSON II-79

APPENDIX D CROSS-ASSEMBLER PSEUDO-INSTRUCTION LIST

APPENDIX D Cross-assembler Pseudo-instruction List

Item No. Pseudo-instruction Meaning Example of Use

EQU

(Equation)

ORG

(Origin)

SET

(Set)

(Define Word)

PAGE

(Page)

SECTION

(Section)

END

(End)

MACRO

(Macro)

LOCAL

(Local)

ENDM

(End Macro)

To allocate data to label

To define location counter

To allocate data to label

(data can be changed)

To define ROM data

To define boundary of page

To define boundary of section

To terminate assembly

To define macro

To make local specification of label

during macro definition

To end macro definition

ABC EQU 9

CHECK MACRO DATA

LOCAL LOOP

LOOP CP MX,DATA

JP NZ,LOOP

ENDM

CHECK 1

BCD EQU ABC+1

ORG 100H

ORG 256

ABC SET 0001H

ABC SET 0002H

ABC DW 'AB'

BCD DW 0FFBH

PAGE 1H

PAGE 3

SECTION

END

AMERICA

EPSON ELECTRONICS AMERICA, INC.

- HEADQUARTERS -

1960 E. Grand Avenue

EI Segundo, CA 90245, U.S.A.

Phone: +1-310-955-5300 Fax: +1-310-955-5400

- SALES OFFICES -

West

150 River Oaks Parkway

San Jose, CA 95134, U.S.A.

Phone: +1-408-922-0200 Fax: +1-408-922-0238

Central

101 Virginia Street, Suite 290

Crystal Lake, IL 60014, U.S.A.

Phone: +1-815-455-7630 Fax: +1-815-455-7633

Northeast

301 Edgewater Place, Suite 120

Wakefield, MA 01880, U.S.A.

Phone: +1-781-246-3600 Fax: +1-781-246-5443

Southeast

3010 Royal Blvd. South, Suite 170

Alpharetta, GA 30005, U.S.A.

Phone: +1-877-EEA-0020 Fax: +1-770-777-2637

EUROPE

EPSON EUROPE ELECTRONICS GmbH

- HEADQUARTERS -

Riesstrasse 15

80992 Munich, GERMANY

Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110

SALES OFFICE

Altstadtstrasse 176

51379 Leverkusen, GERMANY

Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10

UK BRANCH OFFICE

Unit 2.4, Doncastle House, Doncastle Road

Bracknell, Berkshire RG12 8PE, ENGLAND

Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701

FRENCH BRANCH OFFICE

1 Avenue de l' Atlantique, LP 915 Les Conquerants

Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE

Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355

BARCELONA BRANCH OFFICE

Barcelona Design Center

Edificio Prima Sant Cugat

Avda. Alcalde Barrils num. 64-68

E-08190 Sant Cugat del Vallès, SPAIN

Phone: +34-93-544-2490 Fax: +34-93-544-2491

ASIA

EPSON (CHINA) CO., LTD.

28F, Beijing Silver Tower 2# North RD DongSanHuan

ChaoYang District, Beijing, CHINA

Phone: 64106655 Fax: 64107319

SHANGHAI BRANCH

4F, Bldg., 27, No. 69, Gui Jing Road

Caohejing, Shanghai, CHINA

Phone: 21-6485-5552 Fax: 21-6485-0775

EPSON HONG KONG LTD.

20/F., Harbour Centre, 25 Harbour Road

Wanchai, Hong Kong

Phone: +852-2585-4600 Fax: +852-2827-4346

Telex: 65542 EPSCO HX

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

10F, No. 287, Nanking East Road, Sec. 3

Taipei

Phone: 02-2717-7360 Fax: 02-2712-9164

Telex: 24444 EPSONTB

HSINCHU OFFICE

13F-3, No. 295, Kuang-Fu Road, Sec. 2

HsinChu 300

Phone: 03-573-9900 Fax: 03-573-9169

EPSON SINGAPORE PTE., LTD.

No. 1 Temasek Avenue, #36-00

Millenia Tower, SINGAPORE 039192

Phone: +65-337-7911 Fax: +65-334-2716

SEIKO EPSON CORPORATION KOREA OFFICE

50F, KLI 63 Bldg., 60 Yoido-dong

Youngdeungpo-Ku, Seoul, 150-763, KOREA

Phone: 02-784-6027 Fax: 02-767-3677

SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

Electronic Device Marketing Department

IC Marketing & Engineering Group

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624

ED International Marketing Department Europe & U.S.A.

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564

ED International Marketing Department Asia

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110

International Sales Operations

In pursuit of “Saving” Technology, Epson electronic devices.

Our lineup of semiconductors, liquid crystal displays and quartz devices

assists in creating the products of our customers’ dreams.

Epson IS energy savings.

http://www.epson.co.jp/device/

Technical Manual

S1C62N51

EPSON Electronic Devices Website

ELECTRONIC DEVICES MARKETING DIVISION

First issue February, 1992

Printed March, 2001 in Japan A