BQ4011MA-100N - Texas Instruments

Features

➤Data retention in the absence of

power

➤Automatic wr ite-protection

during power-up/power-down

cycles

➤Industry-standard 28-pin 32K x

8 pinout

➤Conventio nal SRAM operation;

unlimited write cycles

➤10-year minimum data retention

in absence of power

➤Batter y internally isolated until

power is applied

Gener al Descr ip ti on

The CMOS bq4011 is a nonvolatile

262,144-bit static RAM organized as

32,768 words by 8 bi ts. The integral

control circuitry and lithium energy

source provide reliable nonvolatility

coupled with the unlimited write

cycles of standard SRAM.

The control circuitry constantly

monitors the single 5V supply for an

out-of-tolerance condition. When

VCC falls out of tolerance, the SRAM

is unconditionally write-protected to

prevent inadvertent write ope r ation.

At this time the integral energy

source is switched on to sustain the

memory until after VCC returns valid.

The bq4011 uses an extremely low

standby current CMOS SRAM,

coupled with a small lith ium coin cell

to provide nonvolatility without long

write-cycle times and the write-cycle

limitations associated w ith EEPRO M.

The bq4011 requires no externa l cir-

cuitry and is socket-compatible with

industry-standard SRAMs and most

EPROMs and EEPROMs.

Selec tion Gui de

Part

Number

Maximum

Access

Time (ns)

Negative

Supply

Tolerance Part

Number

Maximum

Access

Time (ns)

Negative

Supply

Tolerance

bq4011Y-70 70 -10%

bq4011 -100 100 -5% bq 4011Y -100 100 -10%

bq4011 -150 150 -5% bq 4011Y -150 150 -10%

bq4011 -200 200 -5% bq 4011Y -200 200 -10%

Pin Names

A0 –A14 Address inputs

DQ0–DQ7Data input/output

CE Chip enable input

OE Output en able i nput

WE Write enable input

VCC +5 volt supply input

VSS Ground

Aug. 1993 C

32Kx8 Nonvolatile SRAM

bq4011/bq4011Y

Block DiagramPin Connections

Fu nctional Descr iption

When power is valid, the bq4011 operates as a standard

CMOS SRAM. During power-down and power-up cycles,

the bq4 011 acts as a nonvolatile memory, automatically

protecting and preserving the memory contents.

Power-down/power-up control circuitry constantly

moni tors the VCC suppl y for a power-fail-detect thre shold

VPFD. The bq4011 monitors for VPFD = 4.62V typical for

use in systems with 5% supply tolerance. The bq4011Y

mon itors for VPFD = 4.37V ty pical for use in syst em s with

10% supply tolerance.

When VCC falls below the VPFD threshold, the SRAM

automatically write-protects the data. All outputs

become high impedance, and all inputs are treated as

“don’t care.” If a valid access is in process at the time of

power-fai l detection, the memory cycle conti nues to com-

pletion. If the memory cycle fails to terminate within

time tWPT, write-p rotec tion takes place.

As VCC falls past VPFD and approaches 3V, the control

circui try switches to the internal li thium backup supply,

which provides data retention until valid VCC is appl ied.

When VCC returns to a level above the internal backup

cell voltage, the supply is switched back to VCC. After

VCC ramps above the VPFD threshold, write-protection

continues for a ti me tCER (120 ms ma ximu m) to allo w for

processor stabilization. Normal memory operation may

resume after th is time.

The internal coin cell used by the bq4011 has an

extremely long sh elf life and provides data retention for

more than 10 years in the absence of system power.

As shipped from Benchmarq, the integral lithium cell is

ele ctrica lly isol ated from the memory. (Sel f-dis charge in

this condition is approximately 0.5% per year.) Following

the first application of VCC, th is isol atio n is b rok en, a nd

the lithium backup cell provides data retention on sub-

sequent power-downs.

bq4011/bq4011Y

Trut h Table

Mode CE WE OE I/O Operation Power

Not selected H X X High Z Standby

Output disable L H H High Z Active

Read L H L DOUT Active

Write LLX D

IN Active

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V

VTDC voltage applied on any pin excluding VCC

relative to VSS -0.3 to 7.0 V VT ≤ VCC + 0.3

TOPR Operating temp eratur e 0 to +70 °C Commercial

-40 to +85 °C Industrial “N”

TSTG Stor age tempe rature -40 to +70 °C Commercial

-40 to +85 °C Industrial “N”

TBIAS Te mpe r atur e und e r bias -10 to +70 °C Commercial

-40 to +85 °C Industrial “N”

TSOLDER Sol dering temperatur e +260 °C For 10 second s

Note: Permanent d e vice damage may occur if Absol ute Maximum Ratings are exceeded. Functional operation

should be limited to the Recommended DC Operatin g Conditions det ailed in this dat a sheet . Exp o sure to

conditions bey ond the operational limits for extended pe riods of time may affect device r e liability.

Aug. 1993 C

bq4011/bq4011Y

Recommended DC Operating Conditions (TA = TOPR)

Symbol Parameter Minimum Typical Maximum Unit Notes

VCC Supply voltage 4.5 5.0 5.5 V bq4011Y/bq4011Y-xxxN

4.75 5.0 5.5 V bq4011

VSS Supply voltage 0 0 0 V

VIL I nput low vo ltage -0.3 - 0.8 V

VIH Input high voltage 2.2 - VCC + 0.3 V

Note: Ty pi ca l va lues ind i c at e ope ra t io n at TA = 25°C.

DC Electrical Characteristics (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILI Inpu t leakage cu rrent - - ± 1 µAVIN = VSS to VCC

ILO Output leakage current - - ± 1 µACE = VIH or OE = VIH or

WE = VIL

VOH Output high voltage 2.4 - - V IOH = -1.0 mA

VOL Output low voltage - - 0.4 V IOL = 2.1 mA

ISB1 Standby supply current - 4 7 mA CE = VIH

ISB2 Standby supply current - 2.5 4 mA CE ≥ VCC - 0.2V,

0V ≤ VIN ≤ 0.2 V ,

or VIN ≥ VCC - 0.2V

ICC Operati ng supply curre nt - 55 75 mA Min. cycle, duty = 100%,

CE = VIL, II/O = 0m A

VPFD Power-fail-detect voltage 4.55 4.62 4.75 V bq4011

4.30 4.37 4.50 V bq4011Y

VSO Supply s witch-ov er voltage - 3 - V

Note: Ty p i ca l va lu es ind i c at e ope ra t io n at TA = 25°C, VCC = 5V.

Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CI/O Input/output capacitance - - 10 pF Output vol tage = 0V

CIN Input capacitance - - 10 pF Input voltage = 0V

Note: These parameters are sampled and not 100% tested.

Aug. 1993 C

bq4011/bq4011Y

AC Test Conditions

Parameter Test Conditions

Input pulse le vels 0V to 3.0V

Input rise and fal l times 5 n s

Input and output timing reference levels 1.5 V (unless otherwise specified)

Output load (including scope and jig) See Figures 1 and 2

Figure 1. Output Load A Figure 2. Output Load B

Read Cycle (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)

Symbol Parameter

-70/-70N -100 -150/-150N -200

Unit Conditions

Min. Max. Min. Max. Min. Max. Min. Max.

tRC Read cycle time 70 - 100 - 150 - 200 - ns

tAA Address access time - 70 - 100 - 150 - 200 ns Output load A

tACE Chip enable access time - 7 0 - 100 - 150 - 200 ns Ou tput load A

tOE Output enable to

output valid - 35 - 50 - 70 - 90 ns Output load A

tCLZ Chip enable to output

in low Z 5 - 5 - 10 - 10 - ns Output load B

tOLZ Output enable to

output in low Z 5 - 5 - 5 - 5 - ns Output load B

tCHZ Chip disable to output

in high Z 025040060070 nsOutput load B

OHZ Output disable to

output in high Z 025035050070nsOutput load B

OH Output hold from

address chang e 10 - 10 - 10 - 10 - ns Output load A

Aug. 1993 C

bq4011/bq4011Y

Aug. 1993 C

Read Cycle No. 2 (CE Access) 1,3,4

Read Cycle No. 1 (Address Access) 1,2

Notes: 1. WE is held hi gh for a read cycle.

2. Device is continuously selected: CE = OE = VIL.

3. Address is valid prior to or coincident with CE tran sition low.

4. OE = VIL.

5. Device is continuously selected: CE = VIL.

Read Cycle No. 3 (OE Acces s) 1,5

bq4011/bq4011Y

Write Cycle (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)

Symbol Parameter

-70/-70N -100 -150/-150N -200

Units Conditions/Notes

Min. Max. Min. Max. Min. Max. Min. Max.

tWC Write cy cle time 70 - 100 - 150 - 200 - ns

tCW Chip enable to

end of write 55 - 90 - 100 - 150 - ns (1)

tAW Address valid to

end of write 55 - 80 - 90 - 150 - ns (1)

tAS Address setup

time 0-0-0-0-ns

Measured from

address valid to

beginning of write. (2)

tWP Write p ulse

width 55 - 75 - 90 - 130 - ns Measured from

beginning of write to

end of write. (1)

tWR1 Write recovery

time (wr ite

cycle 1) 5-5-5-5-ns

Mea sured from WE

going high to end of

write cycle. (3 )

tWR2 Write recovery

time (wr ite

cycle 2) 15 - 15 - 15 - 15 - ns Mea sured from CE

going high to end of

write cycle. (3)

tDW Data valid to end

of write 30 - 40 - 50 - 70 - ns Mea sured from first

low-to-high transition

of either CE or WE.

tDH1 Data hold time

(write cycle 1) 0-0-0-0-ns

Mea sured from WE

going high to end of

write cycle. (4)

tDH2 Data hold time

(write cycle 2) 0-0-0-0-ns

Mea sured from CE

going high to end of

write cycle. (4)

tWZ Write enabled to

output in high Z 025035050070ns

I/O pins are in output

state. (5)

tOW Output ac tive

from end of write 5-5-5-5-ns

I/O pins are in output

state. (5)

Notes: 1. A write ends at the earlier tr ans iti on of CE going high an d WE going high.

2. A wr ite oc curs during the overlap of a low C E and a low WE. A write begins at the later transition

of CE goi ng low and WE going low.

3. Either tWR1 or tWR2 must be met.

4. Either tDH1 or tDH2 must be met.

5. If CE goes low simultaneo usly wi th WE goin g low or after WE going low, the outputs remain in

high-impedance state.

Aug. 1993 C

bq4011/bq4011Y

Aug. 1993 C

Write Cycle No. 1 (WE-Controlled) 1,2,3

Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5

Notes: 1. CE or WE must be high during address transition.

2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the

outputs must not be applied.

3. If OE is high, the I/O pins remain in a state of high impedance.

4. Either tWR1 or tWR2 must be met.

5. Either tDH1 or tDH2 must be met.

bq4011/bq4011Y

Power-Down/Power-Up Cycle (TA = TOPR)

Symbol Parameter Minimum Typical Maximum Unit Conditions

tPF VCC slew, 4.75 to 4.25 V 300 - - µs

tFS VCC slew, 4.25 to VSO 10 - - µs

tPU VCC sl ew, V SO to VPFD (max.) 0 - - µs

tCER Chip enable recovery time 40 80 120 ms Time during which SRAM is

writ e-protected after VCC

passes VPFD on power - up .

tDR Data-retention time in

absence of VCC 10 - - years TA = 25°C. (2)

tDR-N Data-retention ti me in

absence of VCC 6--years

= 25°C (2); industrial

temperature range (-N) only.

tWPT Write-protect time 40 100 150 µsDelay after VCC slews down

past VPFD before SRAM is

write-protected.

Notes: 1 . T y pica l va lu es ind i c at e ope ra t io n a t TA = 25°C, VCC = 5V.

2. Battery is disconnected from circuit until af ter VCC is applied for the first time. tDR is the

accumulated time in absence of power beginning when power is first applied to the device.

Caution: Negative undershoots below the absolute maximum r ating of -0.3V in battery-ba ckup mode

may affect data integrity.

Power-Down/Power-Up Ti min g

Aug. 1993 C

bq4011/bq4011Y

Aug. 1993 C

Change No. Page No. Description

1 2, 3, 4, 6, 8, 9 Added industrial temperature range for bq4011YMA- 150N.

2 1, 4, 6, 9 Added 70 ns speed grade for bq4011Y-70 and added industrial

temperatu re range for bq4011YMA- 70N.

Notes: Change 1 = Sept 1992 B changes from Sept. 1990 A.

Change 2 = Aug. 1993 C changes from Sept. 1991 B.

Data Sh eet Revision History

28-P in MA (A-t yp e modul e)

28-Pi n MA (A-Type Module)

Dimension Minimum Maximum

A 0.365 0.375

A1 0.015 -

B 0.017 0.023

C 0.008 0.013

D 1.470 1.500

E 0.710 0.740

e 0.590 0.630

G 0.090 0.110

L 0.120 0.150

S 0.075 0.110

All dimensions are in inches.

bq4011/bq4011Y

Aug. 1993 C

Ordering Information

bq4011 MA -

Speed Option s:

70 = 70 ns

100 = 100 n s

150 = 150 n s

200 = 200 n s

Package Option:

MA = A-type module

Supply Tolerance:

no mark = 5% negative supply tolerance

Y = 10% negative supply tolerance

Device:

bq4011 32K x 8 NVSR AM

Temperature:

bl ank = Co mmercial (0 to +70°C)

N = Industrial (-40 to +85°C)*

*Note: Only 10% supply (“Y”) version is available in industrial

temperature range; c ontact factory for s peed gr ade avai l-

ability.

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.