CLC-EDRCS-PCASM EDRCS Evaluation Board User's Guide 0 0 Overview Required Evaluation Items n EDRCS Board The Enhanced Diversity Receiver Chipset (EDRCS) is an IF sampling receiver optimized for GSM/EDGE systems. It provides the extreme dynamic range required for EDGE through a novel AGC-based architecture. The chipset consists of two CLC5526 Digital Variable Gain Amplifiers (DVGAs), two CLC5957 Analog-to-Digital Converters (ADCs), and one CLC5903 Dual Digital Tuner/AGC. (CLC-EDRCS-PCASM) n +5V/1A power supply n Signal generator n DRCS Control Panel software n PC running Windows(R) 95/98/NT/ 2000 The EDRCS Evaluation Board (CLC-EDRCS-PCASM) supports complete evaluation of the Enhanced Diversity Receiver Chipset (EDRCS). Configuration of the Digital Tuner/AGC is controlled by a COP8 micro-controller. Several useful configurations can be directly loaded by the COP8 or specialized configurations can be created and loaded with the provided DRCS Control Panel software (drcscp.exe). A Data Capture Board (CLC-CAPT-PCASM) and accompanying software (capture.exe) are available for use with the EDRCS Evaluation Board. The Capture Board enables the user to capture and transfer data from the EDRCS Evaluation Board into a file on a PC. Matlab(R) script files are provided to assist in data analysis. Figure 1 shows a functional block diagram of the EDRCS. The DVGA controls the ADC's input level to expand the dynamic range. The ADC sub-samples the input and feeds the digitized IF to the CLC5903. The CLC5903 mixes the IF with a digital oscillator, removes the DVGA gain steps, and filters the result. A final output of quadrature baseband signals is provided in both serial and parallel formats. CLC5957 n Matlab(R) software or other data analysis software n One PC serial port Suggested Evaluation Items n Data Capture Board (CLC-CAPT-PCASM) n Data Capture Board software n Second PC serial port Reference Documents n CLC5957 data sheet n CLC5526 data sheet n CLC5903 data sheet n Data Capture Board User's Guide n Evaluation Board Interoperability User's Guide CLC5903 (one channel of two) CLC5526 IF Input `Q' Channel Filter Complex Output F S + 2FS + ... Figure 1 AGC Compensation DVGA Filter to remove broadband DVGA noise at sampling Input Clock intervals. 150MHz is the default tuning frequency. The undersampling process looks like mixing with multiples of the input clock. CLC-EDRCS-PCASM EDRCS Evaluation Board User's Guide October 2001 `I' SINE AGC Compensation Channel Filter COSINE NCO AGC Power Detector Integrator & Control Table Enhanced Diversity Receiver Chipset Single Channel Functional Block Diagram (c)2001 National Semiconductor Corporation Rev. 1.1.5 October 11, 2001 Table of Contents: Section Overview . . . . . . . . . . Required Evaluation Items . . . . . . Suggested Evaluation Items . . . . . Reference Documents . . . . . . . Table of Contents: . . . . . . . . Key Concepts . . . . . . . . . Definition of Terms . . . . . . Sub-Sampling . . . . . . . . Processing Gain . . . . . . . General Description . . . . . . . EDRCS Evaluation Board I/Os . . . . Power . . . . . . . . . . Clock Input . . . . . . . . IF Signal Inputs . . . . . . . CLC5903 Serial Outputs . . . . . CLC5903 Parallel Output . . . . . CLC5903 Debug Output . . . . . COP8 RS-232 Serial Interface . . . EDRCS Block Interfaces . . . . . . DVGA to ADC Interface (LC Noise Filter) ADC to CLC5903 Interface . . . . Clocking the EDRCS . . . . . . Quick Start . . . . . . . . . . Common Questions . . . . . . . DRCS Control Panel Software. . . . . Channels Page . . . . . . . . AGC Page . . . . . . . . . Output Page . . . . . . . . Filter Data Pages . . . . . . . Serial Communications . . . . . Control Panel Software Questions . . Default Configuration and SW2 Settings . . Data Capture Board Settings . . . . . In-Depth Operation . . . . . . . DDC Large-Signal Nonlinearity Exercise . . Connector Pinouts . . . . . . . . Operation with a 13MHz Reference . . . Schematics . . . . . . . . . . Reference Design . . . . . . . . PC Board Layout . . . . . . . . Appendix . . . . . . . . . . DVGA . . . . . . . . . . ADC . . . . . . . . . . DDC . . . . . . . . . . AGC . . . . . . . . . . Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 2 2 2 2 3 3 4 4 4 4 4 5 5 5 5 5 6 6 8 9 13 14 14 14 14 15 15 15 16 16 18 20 20 20 20 27 31 31 31 31 33 Fundamental - Desired input signal shown on an FFT plot. Tone - A signal shown on the FFT plot. The fundamental will usually be the tone with the largest amplitude on the FFT plot. dBc - dB relative to carrier (or fundamental) level. dBFS - dB relative to the ADC or EDRCS Full-Scale output level. Pinput - Magnitude of the largest signal found in the FFT. Measured in dBFS since it is relative to the full scale output value. The EDRCS and ADC FFT routines include variables to specify the full scale value appropriately. SFDR - Spurious Free Dynamic Range. The difference between the fundamental amplitude and the next largest signal on the FFT (excluding DC). Includes all distortion terms. Typically in dBc. Integrated Noise Floor - The sum of the FFT bins excluding DC, the fundamental, and the first 50 harmonics. Measured in dBFS. The excluded information is replaced by the average noise floor level. SNR - Signal to Noise Ratio. The sum of the FFT bins excluding DC, the fundamental, and the first 50 harmonics. Typically in dBc. Add back the number of dB below full scale (Pinput) to get the noise floor or SNR in dBFS. ENOB - Effective number of bits. (Noise floor - 1.76) / 6.02. Each bit represents 6.02dB in the analog domain. This is of interest since a perfect 12 bit ADC would provide a 74dB noise floor. Real ADC performance falls short of this ideal and ENOB is a measure of the real performance. SINAD - Signal-to-noise + Distortion. The sum of the FFT bins excluding only DC and the fundamental. This metric approximates the root sum of squares of both SNR a n d S F D R . Fo r e x a m p le , if SN R = 5 2 . 6 3 d B c a n d SFDR=57.4dBc then SINAD will be about 52.6dBc dominated by the SNR. THD - The sum of all harmonic energy relative to full scale. Any non-harmonic spurs will be excluded. Sub-Sampling Definition of Terms The process of sub-sampling can be thought of as mixing the input signal with the sampling frequency and its harmonics. This means that many signals can be mixed down to DC and their original frequency can no longer be determined. For example, if the sample frequency (F S ) is 52MHz then inputs at 6MHz, 52-6=46, 52+6=58, 98, 110, 150, 162,... would all mix down to 6MHz. The IF SAW filter will only allow a single frequency to be sampled by the ADC so the original input or carrier frequency is known. Full Scale - The maximum digital output level (+/-211 or +2047/-2048 for 12-bit ADCs). Full scale for the CLC5903 can be set for 8, 16, 24, or 32 bits. The EDRCS Board defaults to 24-bit outputs. This value is often related back to the corresponding analog input voltage (2Vpp differential for the CLC5957). Sub-sampling cannot be used if the original input frequency must be determined at the ADC output without an IF filter. This is because the Nyquist criteria is violated. Sub-sampling still proves useful if there is no need to determine the carrier frequency at the ADC output. This is true for the EDRCS since the receiver only needs to Key Concepts Rev. 1.1.5 October 11, 2001 2 (c)2001 National Semiconductor Corporation recover the information on the carrier and not the carrier itself. Nyquist is not violated for the required information bandwidth of 200kHz for GSM/EDGE systems. Channel Filter Each sampling image folds back to < FS/2. FS/2 Information Bandwidth Figure 2 FS 52 162 150 110 98 58 6 46 Output Noise 3FS 156 2FS 104 Figure 3 ADC noise performance is typically limited by thermal noise. When an ADC is specified the noise bandwidth is normally defined as the Nyquist bandwidth. This leads to an integrated noisefloor measurement of -65dB relative to full-scale (dBFS) in a 26MHz bandwidth for the CLC5957 at 52MSPS. When the CLC5957 output is filtered by the CLC5903 a much narrower bandwidth is provided at the output. This filtering process provides noise processing gain (PG) as a function of the bandwidth reduction. For the EDRCS Evaluation Board the sample rate (F S ) is 52MSPS and the output bandwidth defaults to roughly 200kHz (100kHz) so the processing gain should be: BW OUT PG = 10 x log -----------------FS 2 200kHz PG = 10 x log ------------------26MHz PG = - 21.1 dB EQ. 1 as shown in Figure 3. DVGA Processing Gain BW OUT PG = 10 x log -----------------FS Processing Gain Transformer ADC PG = 10 x log 200kHz ------------------52MHz PG = - 24.1 dB EQ. 2 The ADC output noise in a 200kHz bandwidth (after filtering by the CLC5903) will then become: -65dBFS + (-24.1dB) = -79.1dBFS As seen in Figure 4, the EDRCS Board accepts analog IF inputs on a pair of SMA connectors and processes these into baseband digital waveforms. There are several analog components that condition the signal prior to sampling with a pair of ADCs. The most important of these is the DVGA, the gain control element of an AGC loop. The sampled signals are applied to the CLC5903 which performs a final mix to baseband, digitally filters the waveforms, and decimates to a lower output sample rate. An automatic gain control (AGC) processor in the CLC5903 12 } AOUT (serial) BOUT (serial) SCK SFS RDY ParOut CKA Input SMA Connectors 3 3 Transformer DDC/AGC J1 Digital Baseband Outputs 12 DVGA EQ. 3 General Description 150MHz AIN2 FS The CLC5903 filters provide an additional 3dB of processing gain because they remove the alias image and noise near FS. The processing gain equations then become: Sub-Sampling AIN1 ADC Noise FS/2 Freq MHz I/Q Phase reversal will occur for the dashed lines. The CLC5903 removes the alias image that would normally appear here. The noise is also removed. ADC CKB 150MHz Clock Figure 4 52MHz Oscillator Transformer COP8 Controller J9 RS-232 Serial I/O CLC-EDRCS-PCASM Block Diagram (c)2001 National Semiconductor Corporation 3 Rev. 1.1.5 October 11, 2001 directs the DVGAs to extend the dynamic range of the analog signal paths. decreases the degradation of the ADC's SNR will also decrease. SNR degradation due to clock jitter only happens when the input signal is near full-scale. This large input signal will typically mask any SNR degradation that may occur. This would not be the case if more than one carrier was digitized. Note The operation of the AGC will be transparent at the EDRCS output since the CLC5903 includes circuitry to digitally compensate for the DVGA gain steps. IF Signal Inputs The EDRCS Board is factory configured for an IF of 150MHz, a sampling frequency (FCK) of 52MSPS, and an overall decimation of 192. This yields an output sample rate of 270.8KSPS which is suitable for GSM/EDGE systems. The CLC5903 features a high degree of programmability. Key parameter s su ch as m ixer f requ ency, decimation ratio, filter shape, AGC operation, etc. can be configured by the user. EDRCS Evaluation Board I/Os Power The AIN1 and AIN2 SMA connectors accept IF signals up to +20dBm and below -100dBm. Always start with a signal at or below 0dBm, reset the EDRCS Board, then increase the signal if desired. This allows the AGC loop to control the DVGA properly as it will in a receiver. When measuring very small signals consider using an external attenuator in addition to the level control in the signal generator. Some signal generators do not perform well at very low output levels. For optimal performance a low jitter low phase noise signal source must be used (i.e. HP8644B or R&S SME-03). CLC5903 Serial Outputs The EDRCS Board requires +5V and ground which are supplied through J1. The Data Capture Board includes a terminal block for power connections which feed the EDRCS Board. A +5V/1A power supply is sufficient for the EDRCS Board with the Data Capture Board. The terminal block may include a -5V position (VEE) but it is not required for the EDRCS. The default setup of the EDRCS Board is 3$&.(' , 08;B02'( , 6)6B02'( , and )250$7 . These settings provide a 24-bit serial output word, a frame sync output pulse once for each I/Q pair, and the outputs for channel A and B are muxed onto the single output pin $287 as shown in Figure 5. Note Clock Input The EDRCS Board includes a 52MHz crystal oscillator module so that an external clock source is not required. If a different sample rate is desired a +16dBm sinewave or a TTL level squarewave may be applied to the &/. input SMA. The crystal oscillator module should be removed from its socket when an external clock is used. For optimal performance a low jitter low phase noise clock must be provided (i.e. HP8644B or R&S SME-03). This is the format expected by the Data Capture Board. The serial outputs and control signals are available at the DIN connector J1. This connector mates with the Data Capture Board. These signals are also accessible on the DSP header for simple connection to a DSP. The CLC5957 converts the differential input clock to a TTL clock suitable for driving the CLC5903 &. input. In some cases it may be desirable to remove the second SFS pulse so that channel A and B can be identified. Setting 6)6B02'( will mask the second SFS pulse. At high input levels the CLC5957 ADC's SNR is limited by clock jitter. In an EDRCS-based receiver the effects of clock jitter can be reduced by operating the AGC at a lower threshold. As the input signal level to the ADC The default serial output configuration is compatible with the TI TMS320C54X serial input. To interface to the `C54X, set the DSP serial port in continuous mode (FSM bit set to 0) with frame ignore enabled (FIG bit set to 1). In 96 clocks 5'< 6&. 6)6 $287 Figure 5 0 23 ... 1 0 0 23 ... 1 lsb msb lsb msb I chan A Q chan A 0 23 ... 1 msb lsb I chan B 23 ... 1 0 msb lsb Q chan B EDRCS Default Serial Port Format Rev. 1.1.5 October 11, 2001 4 (c)2001 National Semiconductor Corporation Each channel is identical. For each channel the I & Q paths are identical. The debug tap is always aligned into the MSB of the 20-bit debug port output. NCO NCO Cos A COS SIN NCO Sin A Mixer AI I Input Mux Figure 6 Q F1 Out AI F1 In AI AGC Shifter CIC & Scale GAIN FIR F1 FIR F1 CLC5903 Debug Port Access Taps this mode the 24-bit words may be read as 3 groups of 8 bits. The overall input stream of four 24-bit words is read as twelve 8-bit words for later reassembly by the DSP. Additional serial port modes are discussed in the CLC5903 datasheet. in evaluation the CLC5903 may also be completely reconfigured via an RS-232 serial port. The DRCS Control Panel software running on a PC sends commands to the COP8 serial port. The COP8 interprets these commands and programs the CLC5903 registers as required. CLC5903 Parallel Output EDRCS Block Interfaces The CLC5903 parallel output port is available on J1. It is a 16-bit port which can be mapped into the address space of a DSP. Each output component (AI, AQ, BI, & BQ) is allocated 2 registers of 16 bits. In 8-bit or 16-bit mode only a single register for each component needs to be read. To access the data place the proper address on the three 3287B6(/ lines and enable the outputs with 3287B(1. The 5'< signal can be used as an interrupt to indicate new data is ready. Complete details are provided in the CLC5903 datasheet. To facilitate testing of the parallel outputs SW1 can be used to force the state of 3287B6(/ and 3287B(1. Note All EDRCS Board SW1 positions must be `OFF' if the Data Capture Board is used for parallel data capture. CLC5903 Debug Output In some cases it may be desirable to look at signals internal to the CLC5903. The CLC5903 debug port is tied to an internal 20-bit bus which can tap into the internal nodes shown in Figure 6. When in debug mode the DSP serial port pins are reconfigured and the serial port is no longer functional. 6&. is used to clock out the debug data at the proper rate. Additional information on the debug port is provided in the CLC5903 datasheet. The debug port can be used to observe the ADC outputs prior to processing by the CLC5903. This can be done by selecting the mixer output tap for the I component and setting the NCO frequency to zero. This setup is included in the default COP8 options. COP8 RS-232 Serial Interface The CLC5903 can be set to several default configurations by the COP8 micro-controller. To support more flexibility (c)2001 National Semiconductor Corporation 5 DVGA to ADC Interface (LC Noise Filter) While the IF SAW filter allows only the desired signal to be sampled, the DVGA introduces broad-band noise at the ADC input. A simple noise filter between the DVGA and ADC removes this noise. Failure to attenuate noise from the DVGA appearing at the ADC sampling image frequencies will degrade the system performance. Figure 7 shows the response of the noise filter with respect to the sampling images. The nominal component values for the filter provide a center frequency of 150MHz, a 3dB bandwidth of 18MHz, and an insertion loss of 0.7dB. Assuming an ADC sample rate of 52MSPS, the filter provides about 4dB of attenuation at the closest image frequency which is at 162MHz (Figure 7). More attenuation is possible by increasing the Q of the filter, but this would make the center frequency tolerance more critical and increase the group delay through the filter (the stability of the AGC loop is reduced by large group delays). More attenuation will also be achieved if the IF is moved further away from 156MHz. To change the IF frequency of the EDRCS Board, the noise filter components must be changed. The equations below pertain to Figure 8 and provide a means of computing the new values: 1 c = ---------------L1 CT EQ. 4 1 BW = ------------RT C T EQ. 5 RT C G LC = 1 + ------- ------T QL L1 EQ. 6 CT = C 93 2 + C 99 + 1.5pF EQ. 7 Rev. 1.1.5 October 11, 2001 In these equations, C 93 = C 94 , RT = 600 || 1K = 375 , G LC is the filter gain at c , and Q L is the quality factor of the inductor at c . DVGA Output ADC Input and Stray PCB Capacitance C93 600 L1 C99 1.5p 1K Noise filter components for AIN1. In addition to setting the center frequency of the filter, capacitors C 93 and C94 absorb the transient current that is sourced out of the ADC coincident with the sampling instant. It is recommended that C 93 and C 94 be no less than 20pF. It is easy to calculate a new set of filter components using a spreadsheet program set up as follows: 1 2 3 4 5 6 7 8 9 The frequency response of the noise filter can be checked at spot frequencies by observing either the CLC5903 Mixer AI or BI outputs in debug mode with the NCO set to 0 frequency and 0 phase. The tuning can be verified at the CLC5903 output by sweeping both the input frequency and the CLC5903 tuning so that they track. The test signal must be input after the IF SAW to use this method. ADC to CLC5903 Interface C94 Figure 8 available the center frequency should be checked to verify the effects of PCB parasitics. T h e C L C 5 9 5 7 A D C o u t p u t s a r e c u r r e n t l i m i t ed (DATA~2.5mA, DAV~5mA) to prevent crosstalk back to the analog input. For this reason it is important to minimize the parasitic capacitance on the data outputs and the DAV signal. Excessive capacitance will degrade the ADC's SNR performance and may cause errors in the output data. A target for capacitive loading should be 5-7pF. To meet this target all power and ground planes should be removed below the ADC output pins, traces, and CLC5903 input pins. The area where the power and ground planes are removed should be the point where analog and digital planes are split. The included PCB layout on page 27 shows how this can be done. Clocking the EDRCS A C93, C94 C99 Parasitic B 0.00000000002 0.000000000001 0.0000000000015 Ct =B1/2+B2+B3 L1 0.000000033 Fcenter =1/(2*3.14*(B7*B5)^0.5) The CLC5957 and CLC5903 datasheets contain all the timing parameters required to verify these conditions. Now, using the datasheet specifications, consider each of the above constraints. When providing a clock signal for the EDRCS several constraints must be observed: Start by selecting an inductor with a relatively high Q (30-40). Next, iteratively try available capacitor values for C 93 and C 94 . Use C99 to fine-tune the result. This example uses 20pF and 1pF capacitors with a 33nH inductor for a center frequency of 247.9MHz. Once the final PCB is 1. The CLC5957 ENCODE specifications must be met, 2. The CLC5903 CK specifications must be met, and 3. The CLC5903 data input setup and hold times must be met. CLC5957 ENCODE Requirements: The CLC5957 ENCODE specifications require that the ENCODE signal always be high (tP) for at least 7.1ns and low (tM) for at least 7.1ns. The maximum time for tP and Baseband Filter Translated To Sampling Images Baseband Filter The desired signal at 150MHz appears as a 6MHz signal at the ADC output. The other sampling images at 162MHz, 202MHz, 214MHz, ... will also appear as 6MHz signals at the ADC output. The LC noise filter prevents extra noise from these sampling images from appearing at the ADC output. 4dB LC Noise Filter Sampling Image IF Frequency 150 Figure 7 4X Sampling Frequency 3X Sampling Frequency 6MHz 156 202 162 208 214 Frequency (MHz) Illustration of the need for noise filter attenuation at the sampling images. Rev. 1.1.5 October 11, 2001 6 (c)2001 National Semiconductor Corporation tP tM (1& tDAV1 '$9 tS1 '$7$ tH1 tDAV2 '$9 tCKL '$7$ tS2 tH2 tDELTA Figure 9 EDRCS ADC to CLC5903 Clock Timing at 52MHz t M is limited by the minimum conversion rate. This requires that 1/(tP + tM) never be less than 10MHz. With a clock rate of 52MHz (as used in the EDRCS for GSM/EDGE systems) the period is 19.23ns. In this case, if tP is reduced to 7.1ns then tM will be 19.23ns - 7.1ns or 12.13ns. This corresponds to an acceptable duty cycle variation of 37%/63%. t HD = t DNV - t PDB = 7 - 3.2 = 3.8ns EQ. 9 These margins (4.23ns, 2.8ns) are duty cycle independent. Inverter `A' is IDT74ALVC1G04 CLC5903 AIN ADC ENC ENC CLC5903 CK Requirements: The CLC5903 is specified to operate with a clock up to 78MHz with up to 40%/60% duty cycle variation. OSC ENC ENC All capacitors are 0.01uF. CLC5903 Input Setup and Hold Requirements: The CLC5903 includes an internal OR gate to combine the input clocks from two different CLC5957s (&.$ and &.%). Each data input has its own register making the input setup and hold times independent. The possible clock variation (tDELTA=tDAV2-tDAV1) from &.$ to &.% of 2.4ns due to the CLC5957 variation is shown in Figure 9. The (1& duty cycle can vary from 40% to 60% for (1& less than 72MHz without violating the minimum t CKL value of 3.1ns. CKA CKB A BIN ADC Figure 10 Single-Ended Clock Schematic A summary of the CLC5903 and CLC5957 datasheet timing parameters is provided in Table 1 for convenience. Parameter Timinga Symbol Pulse width high, CLC5957 (1&2'( tP 9.615ns Ignoring the DAV Signals Pulse width low, CLC5957 (1&2'( tM 9.615ns When a square wave clock is available to drive ENCODE this same signal may be inverted to drive the CLC5903 &.$ input. When this is done, the duty cycle requirements are those set by the CLC5903. The CLC5903 data input setup and hold times will be independent of clock duty cycle since all timing is now relative to the falling edge of ENCODE. Figure 10 shows a single-ended clock circuit and Figure 11 shows the timing diagram for this approach. Rising (1&2'( to rising '$9, CLC5957 tDAV1 8.5ns Rising (1&2'( to rising '$9, CLC5957 tDAV2 10.9ns '$7$ setup to rising '$9, CLC5957 tS1, tS2 7.215ns '$7$ hold after rising '$9, CLC5957 tH1, tH2 8.015ns Falling (1&2'( to '$7$ invalid, CLC5957 tDNV 7.0ns Falling (1&2'( to '$7$ valid, CLC5957 tDGV 13.0ns Minimum time low for &.=&.$|&.% tCKL 3.1ns $_%,1 setup to rising &., CLC5903 tSU 3.0ns $_%,1 hold after rising &., CLC5903 tHD 1.0ns For the IDT74ALVC1G04 inverter, tPDA is the minimum propagation delay of 1.0ns and tPDB is the maximum value of 3.2ns. In this case, the setup and hold times are: t SU = ( t P + t M ) - t DGV + t PDA = 19.23 - 13 + 1 = 7.23ns (c)2001 National Semiconductor Corporation EQ. 8 Table 1 ADC to CLC5903 Timing Summary a. Clock is 52MHz, values are min/max from CLC5957 and CLC5903 datasheets. Datasheet values take precedence. 7 Rev. 1.1.5 October 11, 2001 (1& tPDA tPDB ,19B(1& tDNV tHD tSU '$7$ tDGV Figure 11 Inverted ENCODE Clock Timing at 52MHz Quick Start Initial performance measurements of the EDRCS Evaluation Board can be obtained very quickly with the Data Capture Board and associated Matlab scripts. The equipment required to verify the EDRCS performance includes: 1. EDRCS Evaluation (CLC-EDRCS-PCASM), 2. Data Capture Board (CLC-CAPT-PCASM), 3. +5V/1A power supply, 4. Signal generator (150MHz sinewave, 0dBm), 5. PC with Windows 95, 98, NT4, or 2000 and Matlab, 6. DRCS Control Panel and Capture software. 7. Connect the Capture Board J9 (serial port) to the PC serial port with the supplied cable, 8. Turn on the +5V supply, 9. Start the Capture software. The Capture Software Panel shown in Figure 12 will be displayed, Board Figure 12 Capture Software Panel 10. Click the right mouse button over the Capture software panel (do not click over the `Start' or `?' buttons), select `Configure I/O' (shown in Figure 13), then select your COM port. Note Existing installations of the DRCS Control Panel Software (drcscp.exe) should be upgraded to version 2.0.10.1 or later to add CLC5903 support. To make an FFT plot of the EDRCS output: 1. Install the Data Capture software from the included CDROM (this also installs the DRCS Control Panel software), Note Remove the spare mating connector shipped with the eval board if attached. Figure 13 Capture I/O Dialog 2. Connect +5V and ground to J3 (the orange terminal block) on the Capture Board, 3. Verify that a 52MHz oscillator module is installed at Y2 (next to the &/. SMA connector), 4. Set all the DIP switches `OFF" on both the EDRCS Board and the Capture Board, 5. On the Capture Board place the WCLK jumper in the `PIN120' position and the VCCD jumper in the `+5' position, 6. Connect a 0dBm 150MHz sinewave input signal to the $,1 SMA connector, Rev. 1.1.5 October 11, 2001 8 To proceed the Capture Board must have power, a sample clock, and be connected to the proper COM port. LED1 on the Capture Board should be on. LED6 should be on about half as bright as LED1. 11. Click the right mouse button over the Capture software panel, select `Configure Capture', then select the options shown in the `Capture Configuration Dialog' (Figure 14). 12. Now click `Start' to capture a 32k sample record. The data will be saved in `c:\temp\data.dat', 13. Start Matlab and add `c:\nsc\mfiles' to the path, (c)2001 National Semiconductor Corporation repeated execution. Type `3+4' then hit enter to see Matlab display `ans=7'. Use the menu to create a new script file (m-file): `file->new->m-file'. Type `3+4' on line 1. Save this file as `my_test.m' in the default location. Now type `my_test' to see `ans=7'. Now that my_test.m exists, simply type `edit my_test' to load it in the editor. To repeat a command hit the up-arrow until the desired command is displayed then hit enter. When the DRCS & Capture software are installed all the m-files are placed in `c:\nsc\mfiles' by default. This location should be added to the Matlab path. Use the path browser: `file->set path'. Browse to `c:\nsc\mfiles' then `path->add to path' and exit the path browser. Now Matlab will be able to locate all the provided scripts. The command `whos' will list all the variables and their sizes. `Clear' will clear all the variables. Figure 14 Capture Configuration Dialog, Serial Port To create a new plot type `figure(1)' then plot the data to the figure with `plot(data)'. Type `zoom on, grid on' to enable zoom and draw a grid. Click and hold the left mouse button to draw a zoom box. Double-click the right mouse button to zoom full. 14. Type `analysis_menu' in the Matlab command window, 15. Click `DRCS Serial' on the menu to plot an FFT (or run `drcs_ser_fft.m' from the Matlab command line). The resulting FFT should be similar to Figure 15, showing a single tone at about 50kHz. The measured Pinput should be about -20dB relative to full-scale (dBFS) with 0dBm at the SMA input connector. Matlab includes a comprehensive set of help files. Type `help' to get a list of available help files. 2. Since the 52MHz crystal oscillator is not locked to the signal generator, the tone in the FFT may not be exactly 50kHz. A second signal generator locked to the first can be used to clock the EDRCS Board and remove the frequency error. Set the clock signal generator to 52MHz at +16dBm. Be sure to remove the crystal oscillator module from its socket. 32768 Point FFT Analysis -20 -40 Pinput = -19.3dBFS SFDR = 68.3dBc Integrated Noisefloor = -80.1dBFS MAGNITUDE (dBFS) -60 -80 Phase Noise 3. -120 -140 -160 -180 -200 4 6 8 FREQUENCY 10 12 4 x 10 Figure 15 IF Input = 150MHz at 0dBm Common Questions 1. What are the basic operating instructions for Matlab? The Matlab command window opens when Matlab is started. All Matlab commands can be directly typed into the command window or saved in a script file for (c)2001 National Semiconductor Corporation 9 The measured results are much worse than expected. Why? Observing the FFT plots in Figure 15 and Figure 16 (close-up) the tone at 50kHz may show some spreading near the noise floor. This is typically caused by a signal generator with poor phase noise performance. The phase noise will be translated into jitter which impacts the ADC sampling performance. These phase noise skirts can be so large that the measured data on the FFT plot is incorrect. An alternate FFT routine is provided to remove the effects of the phase noise by excluding the region near the fundamental tone. Click `Alt DRCS Serial' (or run `drcs_ser_fft_excl.m') to observe the change in both SFDR and the Integrated Noisefloor from Figure 15 to Figure 17. Editing the Matlab script `drcs_ser_fft_excl.m' allows the exclusion region to be set to the desired value. It is 2kHz by default. -100 2 The tone in the FFT is not exactly 50kHz. Why? Figure 18 shows an example of an input signal with extremely poor phase noise performance. 4. Will the EDRCS work with such a poor clock signal? Yes, this problem will not prevent the EDRCS from easily recovering an EDGE signal. For full rate EDGE Rev. 1.1.5 October 11, 2001 32768 Point FFT Analysis 32768 Point FFT Analysis -20 -20 -30 -40 -60 -50 MAGNITUDE (dBFS) MAGNITUDE (dBFS) -40 Very Bad Phase Noise: Pinput = -18.6dBFS SFDR = 36.8dBc Integrated Noisefloor = -46.5dBFS 68dBc SFDR -60 The signal generator phase noise limits the system performance. Use the alternate FFT routine to exclude the excess phase noise for accurate measurements. -70 -80 -80 -100 -120 -140 -90 -160 -100 -180 -110 4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 FREQUENCY 5.0 2 Figure 16 IF Input = 150MHz at 0dBm, Close-up Alternate FFT Routine Results: Pinput = -19.3dBFS SFDR = 84.5dBc Integrated Noisefloor = -90.0dBFS 12 4 x 10 Low Level Results: Pinput = -98.9dBFS SFDR = 34.8dBc Integrated Noisefloor = -121.0dBFS -120 MAGNITUDE (dBFS) MAGNITUDE (dBFS) 84.5dBc SFDR 10 32768 Point FFT Analysis -100 -60 8 Figure 18 IF Input = 150MHz at 0dBm 32768 Point FFT Analysis -40 6 FREQUENCY -20 -80 4 4 x 10 -100 -120 -140 -140 -160 -180 -160 -180 -200 -200 2 4 6 8 FREQUENCY 10 12 2 Figure 17 IF Input = 150MHz at 0dBm, Alternate FFT What happens when the filter coefficients are changed? The noisefloor in the FFT plots reflects the digital filter response. Changing the filter coefficients will change the shape of the noisefloor. Verify this by capturing a new data record as follows: Rev. 1.1.5 October 11, 2001 6 8 10 12 4 x 10 Figure 19 IF Input = 150MHz at -80dBm, Alternate FFT the 23dB C/I requirement is still met with margin. At lower signal levels jitter (from phase noise) does not significantly affect the ADC's performance. Take a look at the same signal at -80dBm (Figure 19) instead of 0dBm (Figure 18). 5. 4 FREQUENCY 4 x 10 10 1. Connect the EDRCS Board and Capture Board as described in the Quick Start section on page 8, 2. Turn on the power and apply 150MHz at -80dBm to the AIN1 connector, 3. Start Matlab and the Capture software, 4. Configure the Capture software as in Figure 14, 5. On the EDRCS Board turn SW2-4 & SW2-8 `ON', 6. Press the EDRCS RESET button (LEDs should alternate), 7. Capture new data and plot an FFT. (c)2001 National Semiconductor Corporation power of two. These new coefficients are optimized for GSM/EDGE systems. 32768 Point FFT Analysis -100 Low Level Results, GSM Filter: Pinput = -99.0dBFS SFDR = 39.3dBc Integrated Noisefloor = -123.0dBFS MAGNITUDE (dBFS) -120 -140 9. What if SW2-4 and SW2-8 are not set the same? SW2-4 sets the decimation and SW2-8 selects the filter coefficients. Both must be either `OFF' for the STD coefficients or `ON' for the GSM coefficients. If they are not the same the tone in the FFT plot may show up at the wrong frequency or the rolloff from the filter will not be observed. -160 10. Why does the FFT plot look like Figure 21? In the Capture software, make sure that `Capture 1st Bit' is checked. This option controls the deserialization of the EDRCS output. For some combinations of output and decimation this setting may change. The DRCS Control Panel software will tell you how to set this option on the `Output' tab (see page 14). -180 -200 -220 2 4 6 8 FREQUENCY 10 32768 Point FFT Analysis 12 4 x 10 Wrong Capture Settings: Pinput = -4.7dBFS SFDR = 8.7dBc Integrated Noisefloor = -3.0dBFS -10 Figure 20 IF Input = 150MHz at -80dBm, Alternate FFT -20 6. How are the two sets of filter coefficients different? The STD coefficients are optimized for a narrow transition-band (about 50kHz) with a flat pass-band and stop-band response. The stop-band rejection is about -80dBFS . The -3dBFS point is at 119kHz placing the filter bandwidth at 88% of the output sample rate (119kHz * 2)/270.833kHz. The GSM coefficients are optimized to meet the GSM blocking test requirements. These filters sacrifice the narrow transition-band response of the STD filters for an ultimate stop-band rejection of -105dBFS beyond 800kHz. The -3dBFS point is at 87kHz placing the filter bandwidth at 64% of the output sample rate. The CLC5903 can meet the GSM-900 channel filter requirements totally in the digital domain with these filter coefficients. 7. Which filter coefficients should be used for GSM/ EDGE systems? Since there is a SAW filter in front of the ADC either set of coefficients may be used. Using the STD set may make it easier to recover the signal since it provides a little wider bandwidth. 8. Why are the F1 coefficients included with the DRCS Control Panel software and the COP8 configuration file different than those in the CLC5903 datasheet? These coefficients have been uniformly scaled to create +4dB of gain relative to those in the datasheet. This compensates for the error in the SCALE and CIC filter combination when the CIC decimation is not a (c)2001 National Semiconductor Corporation 11 -30 MAGNITUDE (dBFS) Notice in Figure 20 that the integrated noisefloor improved by 2dB over Figure 19. This is because the slightly reduced bandwidth increased the processing gain (see the processing gain discussion on page 3). -40 -50 -60 -70 -80 -90 2 4 6 8 10 FREQUENCY 12 4 x 10 Figure 21 IF Input = 150MHz at 0dBm, Bad Alignment 11. Why is the default tuning at 150.05MHz? An input signal at 150.0MHz can be easily generated by driving a 150MHz bandpass filter with a 50MHz crystal oscillator. Only the third harmonic is passed by the filter providing a low-jitter test signal. Tuning to 150.05MHz places the 150MHz signal at 50kHz in the EDRCS output. Adding a variable attenuator allows a wide range of measurements to be made without an expensive synthesized signal generator. 12. Can the ADC output be observed? Yes. The CLC5903 debug output allows the complex mixer outputs to be observed. When the NCO is set to 0Hz the ADC output will be present at the I output. The Q output will be zero unless a phase offset is introduced. 13. What if a scope is to be used to look at the ADC digital outputs? Rev. 1.1.5 October 11, 2001 Make a special scope probe by soldering a 1K ohm resistor to the center of a BNC connector. Add a short ground clip to the outer conductor. Now plug the BNC into a 50 ohm cable to the scope and set the scope to 50 ohm input mode. This method will provide accurate results since there is very little parasitic capacitance. 14. How can the AGC operation be verified? 0.8 7 DVGA Steps of -6dB 0.6 0.4 0.2 0 To verify the AGC operation both the ADC output and the CLC5903 output can be compared. The ADC output will reveal the 6dB steps caused by the DVGA. The CLC5903 output will be linear since the 6dB steps are precisely compensated in both amplitude and time. -0.2 -0.4 -0.6 7 DVGA Steps of +6dB -0.8 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 4 In normal operation the AGC keeps the ADC input in the optimal range throughout the TDMA burst. The AGC will adjust the DVGA at the beginning and end of each burst and perhaps during a fade. This is true for GSM since the modulation is of a constant amplitude. Observing an AM modulated carrier through the debug port allows the steps in the ADC output to be observed. Figure 22 shows the ADC output with an AM modulated input signal (3kHz modulation at 150MHz IF, -15dBFS threshold, 12dB deadband, 1.5us tc). x 10 Figure 23 AM Modulation, 150MHz IF, DDC Output 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 1 -0.3 7 DVGA Steps of -6dB 0.8 -0.4 0.6 -0.5 0.4 2000 3000 4000 5000 6000 7000 8000 0.2 Figure 24 EDGE Modulation, 150MHz IF, ADC Output, AGC Disabled (DVGA fixed at +6dB) 0 -0.2 -0.4 1 -0.6 DVGA -6dB Step 0.8 -0.8 -1 7 DVGA Steps of +6dB 0.6 1 1.5 2 2.5 4 x 10 0.4 0.2 Figure 22 AM Modulation, 150MHz IF, ADC Output 0 Changing only the modulation frequency (300Hz) and looking at the CLC5903 (DDC) output shows the reconstructed waveform (Figure 23). -0.2 -0.4 -0.6 When receiving an EDGE signal the AGC must properly reconstruct the AM content of the modulation. The precise time-alignment of the compensation circuitry enables EDGE data recovery with no loss in performance. In some cases the AGC operation will increase the noisefloor slightly but since this only happens at high signal levels it does not impact the receiver's performance. Figure 24 shows the ADC output with an EDGE modulated 150MHz IF input. The DVGA is set to a fixed Rev. 1.1.5 October 11, 2001 12 -0.8 DVGA +6dB Step -1 1.4 1.5 1.6 1.7 1.8 1.9 2 4 x 10 Figure 25 EDGE Modulation, 150MHz IF, ADC Output, AGC Enabled gain of +6dB. The same signal (skewed in time) with the AGC enabled is shown in Figure 25. A symbol-by-symbol comparison of these two signals at the (c)2001 National Semiconductor Corporation CLC5903 output (baseband I component) is shown in Figure 26. This figure demonstrates the high degree of you to view a summary of the register values that are down-loaded to the CLC5903. 0.1 Error 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 I Samples with and without AGC -0.08 -0.1 650 660 670 680 690 700 710 720 730 740 750 Figure 26 EDGE Modulation, Baseband I Component, AGC Fixed and AGC Enabled Compared Figure 27 Registers Page linearity achieved by the CLC5903/CLC5526 AGC circuitry. 15. How can the various evaluation boards be interconnected? Refer to the Evaluation Board Interoperability User's Guide at www.national.com under the Wireless Infrastructure Product Site for this information. 16. When the CLC5903 is in 16-bit output mode all of the serial output bits are zero. Is something broken? The theoretical noisefloor for a 16-bit digital word is about -98dBFS. The output noisefloor of the EDRCS Board is about -121dBFS for the default setup. A signal must be applied to bring the output above -98dBFS before the serial output will change. DRCS Control Panel Software The DRCS Control Panel (drcscp.exe) requires Windows 95/98/NT/2000 and a free serial port to operate. Run setup.exe from the CD ROM to copy the appropriate files to your hard drive and build the necessary directory structure. Run drcscp.exe to start the program. Note Existing installations of the DRCS Control Panel Software (drcscp.exe) should be upgraded to version 2.0.10.1 or later to add CLC5903 support. To configure the COM port, choose &RQILJXUH,2 from the )LOH menu. The DRCS Control Panel is a user interface which allows the CLC5903 configuration registers to be programmed from a PC. All register settings are controlled from the four tabs on the left. The 5HJLVWHUV page (Figure 27) allows (c)2001 National Semiconductor Corporation 13 Note The DRCS Control Panel software can only write to the CLC5903 registers. The software cannot read the CLC5903 register values. Except for the 5HJLVWHUV page, each page has a 6HQG3DJH or 6HQG button. When pressed, the register values associated with that page are down-loaded to the CLC5903. In addition, a 6HQG$OO'DWD command is available under the )LOH menu. Note The 6HQG buttons only send the data for their own pages. The configuration data entered into the various pages can be saved to a .dcp configuration file so they can be reloaded later. The file is ASCII and has one line for each byte that is written to the CLC5903. The first column is the address and the second is the data. Both are in hex format. This hex data can be copied and used in the final system to simplify the development process. The 6DYH &RQILJXUDWLRQ and /RDG&RQILJXUDWLRQ commands can be found under the )LOH menu. When you start the DRCS Control Panel, it will load the la s t u s ed . d c p f il e w it h i n t h e d a ta s u b d i r e c t o r y (c:\nsc\data). If you have not yet created one, it will look for default.dcp. If default.dcp is not found, it will use a set of hard-coded defaults for everything except FIR Filters F1 and F2. For the filters, the program will search for default.f1 and default.f2. If they are not found, zeros will be loaded for the coefficients. Rev. 1.1.5 October 11, 2001 The data entry fields are designed to allow values to be entered using pulldown menus or edit boxes in familiar engineering terms, rather than the integer values that are required by the CLC5903. The engineering values are converted to the appropriate integer values and appear on the 5HJLVWHUV page. For example, when -150.05 is entered into )UHT, &KDQQHO$, the 5HJLVWHUV page displays the value 491443374 for )5(4B$ (Figure 27). When the mouse is held over a data entry field, a balloon is displayed which describes the function. If a value is entered that is outside the valid range, a warning is displayed. The proper setting of the `1st Bit' option of the Capture software will be shown on the 2XWSXWpage (Figure 28). For the most part, the data entry fields are intuitive given an understanding of the CLC5903 data sheet. A few exceptions are noted below: Channels Page )UHT is the frequency of the NCO. You can either enter the IF frequency at the ADC input or the aliased frequency at the ADC output. To down-convert without a phase inversion, use the plot in Figure 2. The signals with dashed lines should be entered with a negative sign. For example, an IF frequency of 150.05MHz requires an entry of -150.05 for no phase inversion. An alternative is to recognize that 150.05MHz aliases to -5.95MHz when )&. is 52MHz and, for no phase inversion, enter +5.95. )&. refers to the sample rate of the EDRCS Board, which has a factory default of 52MHz. Figure 28 Output Page Coefficient Assignment Page Each of the two independent coefficient memories for F1 and F2 can be assigned to either or both channels. Control of the coefficient assignment crosspoint switch is shown on the &RHIILFLHQW$VVLJQPHQWpage (Figure 29). 6FDOH refers to the bit shift prior to the CIC filter (Figure 49). 6FDOH&DOFXODWHG is calculated by the program and is the value required of 6FDOH to maintain the gain of the DDC up to and including the CIC filter to unity or just below. It changes when &,&'HFLPDWLRQ changes. 6FDOH $GMXVW is a bit shift value added to 6FDOH prior to downloading to the CLC5903. You can enter either a positive or negative value with the restriction that 6FDOH$GMXVW + 6FDOH&DOFXODWHG fall within the range of 0 to +44 inclusive. A warning is issued for values entered outside this range. *DLQ refers to the bit shift after the CIC filter (Figure 49). AGC Page The popup menus for initial conditions and gains refer to the gain of the DVGA. The loop dynamics for the AGC are set in the lower left box. Press the Calculate button after entering values for 7KUHVKROG, 'HDGEDQG, and 7LPH & RQV WD QW a n d th e A G C lo o k u p t ab le v a l u e s a n d $*&B/223B*$,1 are computed. Adding the 1-tap or 4-tap comb sections to the power detector can improve carrier rejection for NCO frequencies near 3.25MHz when Fs = 52MHz. Output Page 6&.5DWH must be selected low enough to allow all serial bits to exit within one output sample period. If there is not enough time to transmit all the serial data an error message will be displayed. See the CLC5903 data sheet for further discussion. Rev. 1.1.5 October 11, 2001 14 Figure 29 Coefficient Assignment Page Filter Data Pages The coefficient values for each of the symmetric FIR filters can be manually entered or loaded from an ASCII text file using the /RDG button. The file must have a .f1 extension for ),5)LOWHU and a .f2 extension for ),5)LOWHU. The file format is one signed integer coefficient per line and the number of lines must equal the number of unique coefficients. Also, there must be no blank space before the values in the files. Open one of the default coefficient files (c:\nsc\data\default.f1) in a text editor to see the format. (c)2001 National Semiconductor Corporation Since the CLC5903 has two independent sets of coefficient memory, there are two Filter Data pages labeled Memory A and Memory B. Serial Communications There is no handshaking between the EDRCS Board and the PC. If the system is operating correctly, all the LEDs will light during transmission and only LED1 will remain lit at the completion of transmission. If the transmit sequence is upset, reset the EDRCS Board and re-send. Config Number SW2 (87654321) Channel A/B Tuning CIC/F1*F2 Decimationa Filter Set 7e 1XXX0111 +10.00MHz +7.50MHz 24/8 GSM 8 1XXX1000 -150.05MHz -150.05MHz 24/8 GSM 9 1XXX1001 +10.70MHz +10.70MHz 24/8 GSM 10 1XXX1010 -199.00MHz -199.00MHz 24/8 GSM 11 1XXX1011 -246.00MHz -246.00MHz 24/8 GSM 12f 1XXX1100 -150.05MHz -150.05MHz 12/8 GSM Control Panel Software Questions 1. Loading new filter coefficients did not change the response as expected. Why? If the new filter coefficients require a different decimation value it must also be sent to the EDRCS Board. 2. What happens to the default configuration loaded by the COP8 when new data is sent? When the DRCS Control Panel sends data to the EDRCS Board the new data replaces any existing data. Only the data for a single page is updated unless a 6HQG$OO'DWD command is issued. 3. Is there any non-volatile storage on the EDRCS Board? Only in the COP8 EPROM. No user-accessible non-volatile storage is available. Default Configuration and SW2 Settings Table 2 describes the tuning frequencies and filter sets selected by SW2 with a 52MHz clock. Additional SW2 settings (positions 8, 7, 6, & 5) are shown in Table 3. The Table 3 parameters operate independently from the Table 2 parameters except for SW2 position 8. SW2 (87654321) Channel A/B Tuning 0 0XXX0000 CIC/F1*F2 Decimationa Filter Set -150.05MHz -150.05MHz 48/4 STD 0XXX0001 +10.70MHz +10.70MHz 48/4 STD 2 0XXX0010 -199.00MHz -199.00MHz 48/4 STD 3 0XXX0011 -246.00MHz -246.00MHz 48/4 STD 4b 0XXX0100 -150.05MHz -150.05MHz 24/4 STD 5c 0XXX0101 0.00 0.00 N/A N/A 6d 0XXX0110 0.00 0.00 N/A N/A 1 Table 2 SW2 Default Configurations a. This column shows the CIC decimation and the F1 decimation * F2 decimation. All cases provide a total decimation of 192 for GSM/EDGE systems (270.833ksps output) except Config 4 & 12 which decimate by 96 (541.66ksps). b. 2x Oversampled Outputs (541.66ksps) c. Mixer AI Debug d. Mixer BI Debug e. (;3B,1+=1, $,1 drives both channels f. 2x Oversampled Outputs (541.66ksps) The complete COP8 programming tables are available in the file c:\nsc\data\drcs7config_013100.txt after the DRCS Control Panel software is installed. Function The CLC-EDRCS-PCASM is configured for 52MHz operation. A 52MHz crystal oscillator module is included so that only one signal generator is required for evaluation. Config Number Table 2 FIR Coefficientsa SW2 0 1 8 STD GSM AGC (Threshold/Deadband) 7 -12dBFS/ 12dB -15dBFS/ 9dB AGC Mode 6 Run Stop NCO Dither 5 On Off Dynamicsb Table 3 Additional SW2 settings a. SW2-4 and SW2-8 should always be in the same state. b. Both settings have a 1.5sec time constant. Note The default LC noise filter on the EDRCS Board has an 18MHz bandwidth centered at 150MHz. Some of the SW2 tuning options will require modification of the LC filter to prevent attenuation of the desired signal. SW2 Default Configurations (c)2001 National Semiconductor Corporation 15 Rev. 1.1.5 October 11, 2001 Table 4 gives the configuration register values for each of the AGC modes associated with SW2 position 6 as mentioned in Table 3. Capture Serial data Capture Parallel data To SRAM To FIFO Specifies the Serial Output pin on the CLC5903 to monitor SW2 Switch Position 6 Settings Register Name 0 (Run) 1 (Stop) $*&B+2/'B,& 0 0 $*&B5(6(7B(1D 0 0 $*&B)25&(E 1 0 (;3B,1+ 0 0 $*&B&2817F 2815 2815 $*&B,&B$% 32 32 Table 4 Register values corresponding to SW2 switch position 6. a. This function is not supported on the CLC5903. b. This function is not supported on the CLC5903. c. This function is not supported on the CLC5903. I/Q Options Any of these default configurations can be modified by using the DRCS Control Panel software. See the DRCS Control Panel Software section on page 13. Figure 30 Capture Software Quick Reference 2. Connect +5V to VCC and ground to GND of connector J3 (the orange terminal block) on the Data Capture Board. When the boards are connected together in the next step, these connections will power both boards. Note that VEE is not required because neither board needs a negative power supply. 3. Connect J1 of the EDRCS Board to J1 of the Data Capture Board. Be sure to remove the spare mating DIN connector if one is attached. 4. Connect a serial cable from the PC to J9 on the Data Capture Board. 5. If two serial ports are available on the PC, connect the other to J9 of the EDRCS Board. If not, the single port must be shared. 6. Make sure that all DIP switches on both boards are set to off. 7. Turn on the power supply. 8. Start the DRCS Control Panel and Data Capture Board software. 9. Configure the COM ports for the DRCS Control Panel and Data Capture Board software. The COM port setup for the DRCS Control Panel is located under )LOH, &RQILJXUH,2. The COM port setup for the Data Capture Board software is accessed by right-mouse-button clicking anywhere on the program window and selecting &RQILJXUH,2. Note that power must be applied to the Data Capture Board, the clock must be present, and the serial cable must be connected in order for the software to accept the COM port configuration. Data Capture Board Settings The Data Capture Board and companion software provide the ability to capture data from the EDRCS Board as well as a variety of analog-to-digital converter products. When evaluating the EDRCS Board, configure the Data Capture Board like this: * * * DIP switches all `OFF" `WCLK' jumper = `Pin120' `VCCD' jumper = `+5V' Figure 30 provides a quick reference for the Data Capture software configuration options. In-Depth Operation This procedure will verify proper operation of the EDRCS Board and Data Capture Board. Initial operation is covered in the Quick Start section on page 8. If a Data Capture Board is not available, an alternate method of saving the data to a file must be used. The default output format for the EDRCS Evaluation Board is shown in Figure 5. If the data is stored in a two's complement integer format the supplied Matlab scripts may still be used to process it. The sequence below requires an unmodulated sine wave source (i.e. HP8644B or R&S SME-03) to generate the input signal. The DRCS Control Panel software will not be used until the first tests are successfully completed. 1. If you have not already done so, install the DRCS Control Panel and Data Capture Board software. Rev. 1.1.5 October 11, 2001 16 Deserializer Control Deserialize the specified by DRCS selected channel Control Panel software (c)2001 National Semiconductor Corporation 10. Connect a -10dBm sinewave at 150.00MHz to the EDRCS Board $,1 input. The DVGA should servo to a gain of either +6dB ($*$,1=3) or +12dB ($*$,1=4) and the ADC should be operating at a level of -10dBFS or -6dBFS. Because (;3B,1+ is not asserted for this configuration, the DDC output (which will be observed below) should be at -28dBFS . This can be computed from the gain equations presented in the Appendix (page 31) and the register data provided in the 5HJLVWHUV page of the DRCS Control Panel. The first measurement will be to use the debug mode of the CLC5903 to probe the output of the ADC. 11. Set SW2 on the EDRCS Board to `00000101' (87654321) then press reset. This selects the Mixer AI debug output and sets the NCO to 0Hz. 12. Use the right mouse button to access the &RQILJXUH &DSWXUH screen of the Data Capture Board software and choose &DSWXUH'HEXJwithin the 0RGH box. Then choose 8SSHU%LWV within the %LWV box. Press 2. The screen should appear as in Figure 31. 13. Press 6WDUW on the front panel of the Data Capture software. When the completion bar reaches 100%, the captured data will be written to the file C:\TEMP\DATA.DAT. If the TEMP directory did not previously exist, the software will create it. You can also specify a different file name and directory by right-mouse-button-clicking on the Data Capture Board software window and choosing the &KDQJH'DWD)LOH command. Keep in mind that the Matlab scripts will look for the data in the default location. The values in DATA.DAT represent 24-bit 2's complement integers. When 0L[HU$, is selected, only the upper 15 bits are non-zero. These numbers can be converted to signed fractional values and plotted by running the Matlab script `plot_twos.m'. Verify that the waveform is sinusoidal. Verify that the amplitude is correct by plotting an FFT. Either select `DRCS Debug' from the `analysis_menu.m' script or run `drcs_par_fft.m'. The `Pinput' shown in the upper right should report either -10dBFS or -6dBFS and there should be a tone at 150MHz-(3*52MHz) = -6MHz. The next measurement will observe the output of the DDC. 14. Set all the EDRCS Board SW2 DIP switches to `OFF' and press reset. 15. Choose &DSWXUH within the 0RGH box of the &RQILJ XUH&DSWXUH screen of the Data Capture Board software. Then choose %LWV within the %LWV box and &DSWXUHVW%LW within the VW%LW box. Finally, choose &KDQQHO$ from the &KDQQHO box and press 2.. The screen should appear as in Figure 14 (see page 9). 16. Click 6WDUW on the front panel of the Data Capture Board software window. The values in the file again represent 24-bit 2's complement integers except now all 24 bits are non-zero. Use the MATLAB script `plot_twos.m' (Plot Twos from the analysis menu) to convert the data to signed fractional values and plot them. Note Regardless of the true width of the word being captured, the Data Capture Board will always write 24-bit, 2's complement numbers to DATA.DAT. The only exception to this is when probing $*&&,&$% in which case each number represents two appended 9 bit numbers. Verify with an FFT that the output is -28dBFS at frequency 150.00MHz-150.05MHz = -0.05MHz. Use the `DRCS Serial FFT' menu option or run `drcs_ser_fft.m' to plot the FFT. A slight frequency offset may exist due to variations in the frequency of the on-board 52MHz crystal oscillator. Note that the output sample rate is 52MHz / 192 = 270.8KHz. The FFT will show the CLC5903's filter bandwidth reflected in the shape of the noise floor. If the signal source causes excessive phase noise at the base of the fundamental tone in the FFT the measured data will be wrong. The routine `drcs_ser_fft_excl.m' (Alt DRCS Serial from the analysis menu) allows the data within 2kHz to be replaced by the average noise floor value. This will allow correct measurements to be made. The exclusion bandwidth can be set in the script. This script must be used to verify the proper noise processing gain. 17. Repeat steps 10 through 13 for input AIN2 replacing all occurrences of &KDQQHO$with &KDQQHO%. In step 11 set SW2 to `00000110'. Next the DRCS Control Panel software and the serial interface will be verified. Figure 31 Capture Configuration Dialog, Debug Port (c)2001 National Semiconductor Corporation 18. Press reset on the EDRCS Board. 17 Rev. 1.1.5 October 11, 2001 19. On the &KDQQHOV page of the DRCS Control Panel, enter 0 for )UHT within the &KDQQHO$ box to set the frequency of the channel A NCO to zero. Also check 'HEXJ(QDEOHG and select 0L[HU$, from the 3UREHDW pulldown menu within the &RPPRQ box. The screen should appear as in Figure 32. Click on the 6HQG3DJH button. Immediately following this, a data transfer indicator box will appear on the monitor and all the LEDs on the EDRCS Board will light momentarily. capturing more data, and performing an FFT should cause the output tone on the FFT to move the same amount. This completes the verification of the board operation. DDC Large-Signal Nonlinearity Exercise This exercise is intended to illustrate the two types of large-signal nonlinearity that can be encountered when the CLC5903 is incorrectly configured. Both can be observed at the input of filter F1. The same equipment is used as in the In-Depth Operation section on page 16. 1. Connect a -10dBm sinewave at 150.000MHz to the EDRCS Board $,1 input. 2. Load default.dcp by choosing /RDG &RQILJXUDWLRQ from the )LOH menu of the DRCS Control Panel. 3. On the &KDQQHOV page, enter -150.005 (5kHz offset) for )UHT within the &KDQQHO$ box and enter 6 for 6FDOH$GMXVW within the &RPPRQ box. Also check 'HEXJ(QDEOHG, select ),Q$, from the 3UREHDW pulldown menu, and set &KDQQHO*DLQs to 0. The screen should look like Figure 34. Click on the 6HQG3DJH button. Figure 32 EDRCS Channel Configuration, Debug Output Now repeat steps 12 and 13 and review the results as before. 20. On the &KDQQHOV page of the DRCS Control Panel, enter -150.05 for )UHT of &KDQQHO$, uncheck 'HEXJ (QDEOHG. The screen should appear as in Figure 33. Click on the 6HQG3DJH button. Figure 34 EDRCS Channel Configuration, CIC Rollover Figure 33 EDRCS Channel Configuration, Serial Output Repeat steps 15 and 16 and review the results as before. Changing the frequency with the DRCS Control Panel, Rev. 1.1.5 October 11, 2001 18 4. On the &RQILJXUH&DSWXUH screen of the Data Capture Board software, choose &DSWXUH'HEXJ within the 0RGH box and %LWV from the %LWV box (see Figure 31). Click on 2.. 5. Press 6WDUW on the front panel of the Data Capture Board software window. As before, the values in DATA.DAT represent 24-bit 2's complement integers and only the upper 18 bits are non-zero. Use the MATLAB script `plot_twos.m' (Plot Twos from the analysis menu) to convert the data to signed fractional values and plot them. Zoom in on the first 300 points to see something similar to Figure 35. This distortion is caused by overflow in the CIC filter due to 6&$/( being set too large. This overflow cannot be sensed and the only way to avoid it is by making sure that 6&$/( is set consistent with the chosen CIC decimation value so (c)2001 National Semiconductor Corporation ping as shown in Figure 37. This represents the type of nonlinearity at all stages of the DDC except for the CIC filter. 1 0.8 0.6 1 0.4 0.8 0.2 0.6 0 0.4 -0.2 0.2 -0.4 0 -0.6 -0.2 -0.8 -0.4 -1 -0.6 0 50 100 150 200 250 300 -0.8 -1 0 50 100 150 200 250 300 Figure 35 CIC Overflow Distortion that the CIC output is less than full scale. Figure 35 may not look exactly the same as yours due to the frequency error between the on-board clock oscillator and the input source. The important characteristic of the distortion is that the positive sinusoid peaks have been translated to negative values and the negative peaks to positive values. 6. Go back to the &KDQQHOV page of the DRCS Control Panel and change 6FDOH$GMXVW back to 0. Next, select G% from the *DLQ pulldown menu in the &KDQQHO$ box. The screen should look like Figure 36. Click on 6HQG3DJH. 7. Press 6WDUW on the front panel of the Data Capture Board software window. Figure 37 Datapath Saturation at the F1 Input Figure 36 DRCS Channel Configuration, Saturation Use `plot_twos.m' (Plot Twos from the analysis menu) to convert the data to signed fractional values and plot them. Zoom in on the first 300 points. You should see the clip(c)2001 National Semiconductor Corporation 19 Rev. 1.1.5 October 11, 2001 Connector Pinouts Table 5 describes the 64-pin DIN connector (J1) pinouts on the EDRCS Board. Power is supplied through J1. If the Data Capture Board is connected to J1, power should be connected to J3 (the orange terminal block) on the Data Capture Board. Pin J1 A J1 B pinout for J9, a female DB-9 used to connect the standard RS-232 serial cable from the PC. Pin JTAG DSP 1 TCK N/C 2 GND GND 3 TDO SCK 4 VCC GND 1 N/C N/C 5 TMS BFSR 2 GND GND 6 N/C GND 3 MSB_T MSB_F 7 TRST BDR 4 N/C D14_T 8 SCAN_EN GND 5 N/C D13_T 9 TDI GND GND 6 N/C D12_T 10 7 N/C D11_T 11 N/C GND 8 N/C D10_T 12 GND 9 N/C D9_T 13 N/C 10 N/C D8_T 14 GND 11 N/C D7_T 15 N/C 12 N/C D6_T 16 GND 13 N/C D5_T 14 N/C D4_T 15 N/C D3_T 16 N/C D2_T 17 N/C D1_T 18 N/C LSB_T 19 GND GND 20 N/C RDY 21 SFS SCK 22 BOUT AOUT 23 POUT_SEL2 N/C 24 POUT_SEL1 N/C 25 POUT_SEL0 RDY Table 6 JTAG and DSP header pinouts Operation with a 13MHz Reference The advantages of operating the EDRCS at 52MHz make it worthwhile to do so even in a 13MHz system. This can be done by either of these two methods: 1. Replace the system oscillator with a 52MHz unit and divide down to 13MHz. This is probably the lowest cost alternative since only one VCXO is required. Keep in mind that the phase noise of the 52MHz VCXO will also be divided down. 2. Phase-lock a 52MHz VCXO to the 13MHz clock. This approach requires additional components but has the least impact on existing circuitry. A circuit that can be used for this purpose is shown in Figure 42. 26 POUT_EN AGC_EN 27 GND GND 28 GND GND Schematics 29 N/C N/C 30 N/C N/C Figure 38, Figure 39, Figure 40, and Figure 41 are the CLC-EDRCS-PCASM schematics. 31 +5V (DIGITAL) +5V (DIGITAL) 32 +5V (ANALOG) +5V (ANALOG) Table 5 Reference Design Eurocard connector J1 pinout. Table 6 describes 10-pin JTAG header and 16-pin DSP header pinouts. The schematic in Figure 41 provides the Rev. 1.1.5 October 11, 2001 20 The schematic for a complete reference design is provided in Figure 43. This circuit is the same as the EDRCS Evaluation Board without the COP8 and its associated components. In this example the LC filter is tuned to 71MHz and must be re-tuned to the appropriate value. (c)2001 National Semiconductor Corporation Figure 38 ADC Input AIN1 (c)2001 National Semiconductor Corporation 21 Rev. 1.1.5 October 11, 2001 Figure 39 ADC Input AIN2 Rev. 1.1.5 October 11, 2001 22 (c)2001 National Semiconductor Corporation Figure 40 CLC5903 Dual Digital Tuner/AGC (c)2001 National Semiconductor Corporation 23 Rev. 1.1.5 October 11, 2001 Figure 41 COP8 Microprocessor Rev. 1.1.5 October 11, 2001 24 (c)2001 National Semiconductor Corporation Vectron Figure 42 Circuit for a 52MHz VCXO Locked to a 13MHz Reference (c)2001 National Semiconductor Corporation 25 Rev. 1.1.5 October 11, 2001 Figure 43 EDRCS Reference Design Rev. 1.1.5 October 11, 2001 26 (c)2001 National Semiconductor Corporation PC Board Layout Silk screen parts placement drawings are shown below. The complete board layout package can also be provided. Primary areas of concern are the analog inputs to the ADC and the ADC digital outputs. Care has been exercised to prevent ground loops and noise coupling on the circuit board at the inputs. Noise coupling is reduced by aligning the split between analog and digital planes across all layers. The ADC outputs have been kept as short as possible to minimize capacitive loading. The internal ground plane has been removed under these traces to reduce the para- sitic capacitance. Higher capacitance values will load the ADC output drivers causing additional noise on the internal analog signals. This will degrade the ADC performance. Analog and digital grounds have been star (common-point) connected to minimize crosstalk. The supplies have series inductors for each section to provide extra isolation. Figure 44, Figure 45, Figure 46, and Figure 47 show the EDRCS Board parts placement and PC board layers. PCB layout tips are annotated on the plots. Figure 44 EDRCS Board layout, Top, L1 + Silk Keep these traces to the minimum length possible. (c)2001 National Semiconductor Corporation 27 Rev. 1.1.5 October 11, 2001 AGND DGND Figure 45 EDRCS Board layout, GND, L2 Common-point ground where the analog and digital planes join. Line up split between analog and digital planes across all layers. Minimize parasitics at the LC filter since these are high-impedance nodes. Minimize capacitive loading on the ADC output by removing power and ground planes. Rev. 1.1.5 October 11, 2001 28 (c)2001 National Semiconductor Corporation Figure 46 EDRCS Board layout, Power, L3 Line up split between analog and digital planes across all layers. Minimize parasitics at the LC filter since these are high-impedance nodes. Minimize capacitive loading on the ADC output by removing power and ground planes. (c)2001 National Semiconductor Corporation 29 Rev. 1.1.5 October 11, 2001 Figure 47 EDRCS Board layout, Bottom, L4 Line up split between analog and digital planes across all layers. Minimize parasitics at the LC filter since these are high-impedance nodes. Minimize capacitive loading on the ADC output by removing power and ground planes. Rev. 1.1.5 October 11, 2001 30 (c)2001 National Semiconductor Corporation Appendix Input Circuit and Signal Levels The $,1 and $,1 IF inputs are transformer coupled into the DVGA inputs. The transformers convert the single-ended input signal to differential and match the 200 input of the DVGAs to the 50 input connectors. They have a voltage gain of 2: G XFMR = 2 (EQ. 10) In a production system, the transformer might be replaced by an IF SAW with differential output drive capability. With the DVGA set to maximum gain (+30dB), the total analog gain from the input connector to the ADC is 33.8dB and an input level of -23.8dBm will drive a full-scale input at the ADC. With the DVGA set to minimum gain (-12dB), the total analog gain is -8.3dB and a +18.3dBm input level is required to drive the ADC to full scale. Typically, the AGC reference level will be set such that the ADC will never see full scale and the lowest gain setting of the DVGA will not be used. The total gain of the EDRCS Board, including both the analog and digital parts is best described by the equation, G TOTAL = G XFMR G DVGA G LC G DDC , improves to 68dBFS (or, 55 nV Hz at 52MSPS). This behavior is due to the fact that the large-signal, high-frequency SNR is dominated by clock jitter. GSM systems typically require no more than 9dB of SNR (C/I) which can be achieved at input levels of 59dB below full scale. EDGE systems typically require 23dB SNR for full rate operation. This requirement can be met with an input signal at -45dBFS, still low enough to minimize the effects of clock jitter. The ADC acts as though it were a 68dB device for these systems (Figure 48). The digital filters following the ADC provide processing gain that improve further upon this by 24dB (factory default configuration, 200kHz output BW). Assuming that a single sampling image interferes at a level of -4dB (Figure 7), the total noise voltage density at the ADC input is, 2 2 55 + 69 ( 1 + 10 - 4 10 ) = 98nV Hz . (EQ. 13) When this is referred through the 33.8dB maximum gain to the input connector, this yields a 13dB noise figure for the EDRCS Board. SNR vs. Input Amplitude 80 (EQ. 11) Extrapolates to 68dB where the first term has already been introduced and the others will be in subsequent sections of this manual. 70 60 The DVGA is a 350MHz amplifier that has a digitally-controlled voltage gain range from -12 to +30dB in 6dB steps. It has a 3rd-order output intercept point of 24dB at 150MHz and an output noise spectral density of SNR (dBc) DVGA AGAIN , 20 (EQ. 12) 10 -50 where AGAIN is the 3-bit data word into the DVGA digital input of channel A. Refer to the CLC5526 data sheet for further details. The DVGA, in conjunction with the DDC/AGC, forms an automatic leveling loop that compresses the dynamic range of the input IF signal prior to sampling by the ADC. By doing so, it extends the dynamic range of the ADC by as much as 42dB. The loop dynamics and threshold of the AGC are set by programming the control registers within the CLC5903. It is also possible to inhibit the loop and force specific DVGA gain values. ADC The ADC is a 12 bit, wideband converter capable of inputs as high as 300MHz at sample rates of 70MSPS. The SNR for an input 3dB below the full scale input of 2VPP differential is 62dBFS at an IF frequency in the range of 150MHz. For levels much below this, however, the SNR (c)2001 National Semiconductor Corporation 31 40 30 69 nV Hz . At 150MHz, the data sheet plots place the maximum gain at about 28.5dB or, G DVGA = ( 0.21 ) 2 50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) Figure 48 CLC5957 SNR Extrapolates to 68dBFS DDC The ADC outputs feed into the two channel DDC/AGC. This part consists of two down converter channels (DDC) and automatic gain control (AGC) loops. The DDC performs the final mix to baseband and baseband filtering (see Figure 49). The NCO can tune across the full Nyquist band with 32 bit precision. With phase dither enabled, the spurious performance is -101dBc or better and SNR is 84dBFS. The frequency and phase of the two channels are completely independent. In addition, the phase dither of the two are uncorrelated. Rev. 1.1.5 October 11, 2001 + 1 , B3 ; ( EXP (from AGC) ( /$ & 6 )5(4B$ 21 I TO OUTPUT CIRCUIT SAT 21 F2 FILTER DECIMATE BY 2 OR 4 21 SAT & ROUND 21 F1 FILTER DECIMATE BY 2 SHIFT UP SAT & ROUND 22 CIC FILTER DECIMATE BY 8 TO 2K 15 17 22 SHIFT UP ROUND 15 FLOAT TO FIXED CONVERTER EXPONENT 14 B < % B & ( ' ) ( 2 & B ) EXP 3 MUXA & ( ' ) ( 2 & B ) $ B 1 , $ * Q 17 SIN COS NCO 3+$6(B$ Figure 49 CLC5903 Digital Down Converter, Channel A 0 A G ve C rT O hi per s R at an es ge assistance from the analog filter. Further, the blocker performance of ETSI GSM 05.05 paragraph 5.1 can be met with only minor assistance from the analog filter. DDC Output O Output Power The baseband filtering is performed by a cascade of three decimating FIR filters. The overall decimation ratio can be programmed from 8 to 16,384. The two final filters feature 21 and 63 channel-independent user-programmable taps, respectively. Two independent sets of filter coefficients can be selected via crossbar switch. A set of tap coefficients are published in the CLC5903 data sheet which provide adequate filtering to meet the GSM blocker and interferer requirements. The frequency response for these filters at a sample rate of 52MSPS is shown in Figure 50. 0 -10 ADC Output -20 -30 Magnitude (dB) GSM blocker and interferer requirements -40 -50 Input Power -60 Figure 51 ADC and DDC Output Level vs. Input Level -70 -80 -90 -100 -110 0 100 200 300 400 500 600 700 800 900 1000 Frequency (kHz) Figure 50 Frequency Response of GSM Filter Set Although the ADC combined with the processing gain of the digital filters provides 92dB of instantaneous SNR, this is not enough to meet the requirements of the GSM900 specification without some analog filtering to attenuate the blocker. Nonetheless, the digital filters can be used to relax the requirements on the analog filter. In particular, the digital filters can meet the reference interference level of ETSI GSM 05.05 paragraph 6.3 without any Rev. 1.1.5 October 11, 2001 32 The FLOAT TO FIXED CONVERTER within the DDC will match any change in gain by the DVGA with a compensating digital gain change. It does this by treating the complement of the DVGA control word as an exponent to the ADC output. The overall effect of this is to make the EDRCS Board appear as a fixed gain channel with extremely large dynamic range as shown in Figure 51. This mode can also be inhibited by asserting (;3B,1+. An expression for the gain through the DDC channel A is, 4 1 G DDC = --- ( '(& + 1 ) 2 2 2 , (EQ. 14) [ 6&$/( - 44 - AGAIN ( 1 - (;3B,1+ ) ] *$,1 G F1 GF2 (c)2001 National Semiconductor Corporation AGC_TABLE AGC_LOOP_GAIN FUNCTION PROGRAMMED INTO RAM 8 12 AGAIN 3 12 MUX 5 SHIFT DOWN 9 32X8 RAM POUT FIXED TO FLOAT CONVERTER 9 POST CIC COMB FILTER 16 2 STAGE DECIMATE BY 8 CIC FILTER 10 SHIFT DOWN AIN[13:4] (from MUXA) ABSOLUTE VALUE EXP AGC_IC_A AGC_HOLD_IC LOG -REF Figure 52 CLC-EDRCS-PCASM AGC circuit, Channel A 21 AGC Power Detection Filter: Amplitude Response h1 ( i ) G F1 = 10 i--------------------=1 -, 16 CIC CIC + 1-tap Comb CIC + 4-tap Comb 0 (EQ. 15) AGC_COMB_ORD=2 2 -10 AGC_COMB_ORD=0 -20 63 AGC_COMB_ORD=1 h2 ( i ) i--------------------=1 -. 16 (EQ. 16) 2 Magnitude/dB G F2 = -30 -40 -50 -60 The numerators of G F1 and G F2 equal the sums of the impulse response coefficients of F1 and F2, respectively. For the STD and GSM sets, G F1 and G F2 are nearly equal to unity. Observe that the AGAIN term in (EQ. 14) is cancelled by the corresponding term appearing in (EQ. 12) so that the entire gain of the EDRCS Board is independent of -70 -80 -90 -100 0 5 10 15 20 25 30 Frequency/MHz 35 40 45 50 1 the DVGA setting when (;3B,1+ . The --- appearing Figure 53 Power detector filter response, 52MHz in (EQ. 14) is the result of the 6dB conversion loss in the mixer. by altering the slope of the transfer function stored within the lookup table. When the DVGA gain is changed, there is a delay before the FLOAT TO FIXED CONVERTER is changed to minimize the effect of the gain steps on the output signal. In the CLC5903 this delay is programmable to allow the use of ADCs with more than three-clock pipeline delays. In the course of measuring ADC power, the absolute value block within the envelope detector also generates a second harmonic of the aliased IF frequency. For example, an IF of 150MHz aliases to -6MHz at the ADC output when the sample rate is 52MHz. The absolute value block produces from this a dc term and a second harmonic at -12MHz, the latter of which is rejected by the low pass filter. If the alias frequency is too low, though, its second harmonic will fall within the passband of the filter and a clean power detection will not occur. This problem can be avoided by choosing the IF and sample rates such that the alias frequency magnitude is greater than FCK/16. 2 AGC The AGC loop for channel A is shown in Figure 52. Each channel has its own loop. The ADC output power is measured with an envelope detector and used to adjust the DVGA gain. Envelope detection is performed by an absolute value circuit followed by a programmable lowpass filter whose response is shown in Figure 53. The filtered signal is used to address a lookup table which generates an error signal based on the programmed threshold, deadband, and loop time constant targets. This error is integrated to produce the 3 bit control signal for the DVGA. Integrator gain is programmable via the shifter preceding it to allow loop time constants that can be varied by factors of 2. Fractional control of time constant can be achieved (c)2001 National Semiconductor Corporation 33 The user interface software makes programming of the AGC very easy. The user need only specify the loop time constant, reference, and deadband. The lookup table values and shifter values can then be computed. A Matlab script which will calculate the AGC values is also available upon request. As shown in Figure 54, deadband in excess of 6dB shows up as hysteresis. Hysteresis will Rev. 1.1.5 October 11, 2001 Deadband 6dB DVGA Output Power EDRCS Evaluation Board User's Guide CLC-EDRCS-PCASM eliminate excessive DVGA gain changes caused by the input signal level dwelling at a transition point. Reference Hysteresis=Deadband-6dB 6dB DVGA Input Power Figure 54 Relationship between deadband and hysteresis The AGC can either be allowed to free-run or set to a fixed gain. In free-run mode, the loop is closed continuously and the DVGA gain setting is constantly updated in response to the signal level applied to the board. This mode is suitable for most applications. The default configuration of the EDRCS Board and user software allows the AGC to free-run. By using the configuration registers, it is possible to write the initial gain condition of the loop into the integrator and hold a fixed AGC gain value. This technique can be used to aid in system verification and debugging. Consult the CLC5903 data sheet for further details. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. N National Semiconductor Corporation National Semiconductor Europe Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com Fax: +49 (0) 180-530 85 86 E-mail: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 (c)2001 National Semiconductor Corporation 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com 34 National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Rev. 1.1.5 October 11, 2001