CLC-EDRCS-PCASM - National Semiconductor

CLC-EDRCS-PCASM

EDRCS Evaluation Board User’s Guide

October 2001

CLC-EDRCS-PCASM

EDRCS Evaluation Board User’s Guide

Overview

The Enhanced Diversity Receiver Chipset (EDRCS) is an IF

sampling receiver optimized for GSM/EDGE systems. It provides

the extreme dynamic range required for EDGE through a novel

AGC-based architecture. The chipset consists of two CLC5526

Digital Variable Gain Amplifiers (DVGAs), two CLC5957

Analog-to-Digital Converters (ADCs), and one CLC5903 D ual

Digital Tuner/AGC.

The EDRCS Evaluation Board (CLC-EDRCS-PCASM) supports

complete evaluation of the Enhanced Diversity Receiver Chipset

(EDRCS). Configuration of the Digital T uner/AGC is controlled by

a COP8 micro-controller. Several useful configurations can be

directly loaded by the COP8 or specialized configurations can be

created and load ed with the provided DR CS Contro l Panel software

(drcscp.exe).

A Data Capture Board (CLC-CAPT-PCASM) and accompanying

software (capture.exe) are available for use with the EDRCS

Evaluation Board. The Capture Board enables the user to capture

and transfer data from the EDR CS Evaluation Boar d into a file on a

PC. Matlab® script files are provided to assist in data analysis.

Figure 1 shows a functional block diagram of the EDRCS. The

DVGA controls the ADC’s input level to expand the dynamic

range. The ADC sub-samples the input and feeds the digitized IF to

the CLC5903. The CLC5903 mixes the IF with a digital oscilla tor,

removes the DVGA gain steps, an d filters the result. A final o utput

of quadrature baseband signals is provided in both serial and

parallel formats.

Figure 1 Enhanced Diversity Receiver Chipset Single Channel Functional Block Diagram

IF Input

Input Clock

DVGA

FS2FS…++

Filter to remove

broadband DVGA

noise at sampling

intervals. 150MHz

is the default tuning

frequency. The undersampling

process looks like

m ix in g w ith m u lt ip l es

of the input clock.

NCO

SINE COSINE

‘Q’

‘I’

Power

Detector

Channel

Filter

AGC

Compensation

AGC

Compensation Channel

Filter

Integrator &

Control T able

AGC

Complex

Output

CLC590 3 (one c hannel of two)CLC5957

CLC5526

Required Evaluation Items

EDRCS Board

(CLC-EDRCS-PCASM)

+5V/1A power suppl y

Signal generator

DRCS Control Panel software

PC running Windows® 95/98/NT/

2000

Matlab® software or other data

analysis software

One PC serial port

Suggested Evaluation Items

Data Capture Board

(CLC-CAPT-PCASM)

Data Capture Board software

Second PC serial port

Reference Documents

CLC5957 data she et

CLC5526 data she et

CLC5903 data sheet

Data Capture Board User’s Guide

Evaluation Board Interoperability

User’s Guide

Table of Contents:

Section Page

Overview . . . . . . . . . . . . 1

Required Evaluation Items. . . . . . . . 1

Suggested Evaluation Items . . . . . . . 1

Reference Documents . . . . . . . . . 1

Table of Contents: . . . . . . . . . . 2

Key Concepts . . . . . . . . . . . 2

Definition of Terms . . . . . . . . 2

Sub-Sampling . . . . . . . . . . 2

Processing Gain . . . . . . . . . 3

General Description . . . . . . . . . 3

EDRCS Evaluation Board I/Os . . . . . . 4

Power . . . . . . . . . . . . 4

Clock Input . . . . . . . . . . 4

IF Signal Inputs . . . . . . . . . 4

CLC5903 Serial Outputs . . . . . . . 4

CLC5903 Parallel Output . . . . . . . 5

CLC5903 Debug Output . . . . . . . 5

COP8 RS-232 Serial Interface . . . . . 5

EDRCS Block Interfaces . . . . . . . . 5

DVGA to ADC Interface (LC Noise Filter) . . 5

ADC to CLC5903 Interface . . . . . . 6

Clocking the EDRCS . . . . . . . . 6

Quick Start . . . . . . . . . . . . 8

Common Questions . . . . . . . . . 9

DRCS Control Panel Software. . . . . . . 13

Channels Page. . . . . . . . . . 14

AGC Page . . . . . . . . . . . 14

Output Page . . . . . . . . . . 14

Filter Data Pages . . . . . . . . . 14

Serial Communications . . . . . . . 15

Control Panel Software Questions . . . . 15

Default Configuration and SW2 Settings . . . . 15

Data Capture Board Settings . . . . . . . 16

In-Depth Operation . . . . . . . . . 16

DDC Large-Signal Nonlinearity Exercise . . . . 18

Connector Pinouts . . . . . . . . . . 20

Operation with a 13MHz Reference . . . . . 20

Schematics . . . . . . . . . . . . 20

Reference Design . . . . . . . . . . 20

PC Board Layout . . . . . . . . . . 27

Appendix . . . . . . . . . . . . 31

DVGA. . . . . . . . . . . . 31

ADC . . . . . . . . . . . . 31

DDC . . . . . . . . . . . . 31

AGC . . . . . . . . . . . . 33

Key Concepts

Definition of Terms

Full Scale - The maximum digital output level (+/-211 or

+2047/-2048 for 12-bit ADCs). Full scale for the

CLC5903 can be set for 8, 16, 24, or 32 bits. The EDRCS

Board defaults to 24-bit outputs. This value is often related

back to the corresponding analog input voltage (2Vpp dif-

ferential for the CLC5957).

Fundamental - Desired input signal shown on an FFT

plot.

Tone - A signal shown on the FFT plot. The fundamental

will usually be the tone with the largest amplitude on the

FFT plot.

dBc - dB relative to carrier (or fundamental) level.

dBFS - dB relative to the ADC or EDRCS Full-Scale out-

put level.

Pinput - M a gnitude of th e largest signal found in the FFT.

Measured in dBFS since it is relative to the full scale out-

put value. The EDRCS and ADC FFT routines include

variables to specify the full scale value appropriately.

SFDR - Spurious Free Dynamic Range. The difference

between the fundamental a mplitude and the next largest

signal on the FFT (excluding DC). In cludes all distortion

terms. Typically in dBc.

Integrated Noise Floor - The sum of the FFT bins

excluding DC, the fundamental, and the first 50 harmon-

ics. Measured in dBFS. The excluded information is

replaced by the average noise floor level.

SNR - Signal to Noise Ratio. The sum of the FFT bins

excluding DC, the fundamental, and the first 50 harmon-

ics. Typically in dBc. Add back the number of dB below

full scale (Pinput) to g e t the noise floor or SNR in dBFS.

ENOB - Effective nu mber of bits. (N oise floor - 1.76) /

6.02. Each bit represents 6.02dB in the analog domain.

This is of interest since a perfect 12 bit ADC would pro-

vide a 74d B noi se f loor. Real ADC performance falls sh ort

of this ideal and ENOB is a measure of the real perfor-

mance.

SINAD - Signal-to-noise + Distortion. The sum of the

FFT bins excluding on ly DC and the fundam ental. This

metric approximates the root sum of squares of both SNR

and SFDR. For example, if SNR=52.63dBc and

SFDR=57.4dBc then SINAD will be about 52.6dBc domi-

nate d by the SN R.

THD - The sum of all harmonic energy relative to full

scale. Any non-harmonic spurs will be excluded.

Sub-Sampling

The process of sub-sampling can be thought of as mixing

the input signal with the sam pling frequency and its h ar-

monics. This means that many signals can be mixed down

to DC and their original frequency can no longer be deter-

mined. For example, if the sample frequency (FS) is

52MHz then inputs at 6MHz, 52-6=46, 52+6=58, 98, 110,

150, 162 ,... would all mix down to 6MHz. The IF SAW fil-

ter will on ly allow a si ng l e frequency to be samp le d by the

ADC so the original input or carrier frequency is known.

Sub-sampling cannot be used if the original input fre-

quency must be determined at the ADC output without an

IF filter. This is because the Nyquist criteria is violated.

Sub-sampling still proves useful if there is no need to

determine the carrier frequency at the ADC output. This is

true for the EDRCS since the receiver only needs to

recover the information on the carrier and not the carrier

itself. Nyquist is not violated for the required information

bandwidth of 200kHz for GSM/EDGE systems.

Processing Gain

ADC noise performance is typically limited by thermal

noise. When an ADC is specified the noise bandwidth is

normally defined as the Nyquist bandwidth. This leads to

an integrated noisefloor measurement of -65dB relative to

full-scale (dBFS) in a 26MHz bandwidth for th e CLC595 7

at 52MSPS. When the CLC5957 o utput is filtered by the

CLC5903 a much narrower bandwidth is provided at the

output. This filtering process provides noise processing

gain (PG) as a function of the bandwidth reduction. For

the EDRCS Evaluation Board the sam ple rate (F S) is

52MSPS and the output bandwidth d efaults to roughly

200kHz (±100kHz) so the processing gain should be:

EQ. 1

as shown in Figure 3.

The CLC5903 filters provide an additio nal 3dB of pro-

cessing gain because they remove the alias image and

noise near FS. The processi ng gain eq uations t hen become:

EQ. 2

The ADC output noise in a 200kHz bandwidth (after filter-

ing by the CLC590 3) will then become:

-65dBFS + (-24.1dB) = -79.1dBFS EQ. 3

General Description

As seen i n Figure 4, the E DRCS Board accept s analog IF

inputs on a pair of SMA connectors and processes these

into baseband digital waveforms. There are several analog

componen ts that conditio n the signal prio r to sampling

with a pair of ADCs. The most important of these is the

DVGA, the ga in control element of an AGC loop. The

sampled signals are applied to the CLC5903 which per-

forms a final mix to b aseband, digitally filters the wave-

forms, and decimates to a lower output sample rate. An

automatic gain control (AGC) processor in the CLC5903

Figure 2 Sub-Sampling

FS/2 FS

Each sampling image folds back to < FS/2.

2FS3FS

52 104 156

Freq

MHz

110

150

162

I/Q Phase reversal will occur

Information

Bandwidth for the dashed lines.

PG 10 BWOUT

FS2

⁄

-------------------log

PG 10 200kHz

26MHz

-------------------log

PG 21.1–dB

Figure 3 Processing Gain

FS/2 FS

ADC Noise

Channel Filter

Output Noise

The CL C5903 re move s

the alias image that

would no rmally ap pear

here. The noise is also

removed.

PG 10 BWOUT

-------------------log

PG 10 200kHz

52MHz

-------------------log

PG 24.1–dB

Figure 4 CLC-EDRCS-PCASM Block Diagram

DDC/AGC

AIN1

AIN2

AOUT (serial)

BOUT (serial)

SCK

SFS

ParOut

RDY

}

150MHz

COP8 µController

RS-232

Serial I/O

DVGA

150MHz

DVGA

Trans-

former

Trans-

former

ADC

52MHz

Oscillator Trans-

former

CKA

Clock

Input SMA

Connectors Digital Baseband

Outputs

CKB

directs the DVGAs to extend the dynamic range of the

analog signal paths.

Note

The operation of the AGC will be transparent

at the EDRCS output since the CLC5903

includes circuitry to digitally compensate for

the DVGA gain steps.

The EDRCS Board is factory configured for an IF of

150MHz, a sampling frequency (FCK) of 52MSPS, and an

overall decimation of 192. This yields an output sample

rate of 270.8KSPS which is suitable for GSM/EDGE sys-

tems. The CL C59 03 fea tu res a hig h degr ee of pro gram ma-

bility. Key parameters such as mixer frequency,

decimation ratio, filter shape, AGC operation, etc. can be

configured by the user.

EDRCS Evaluation Board I/Os

Power

The ED RCS Board requ ires +5V and gro und which are

supplied through J1. The Data Capture Board includes a

terminal block for power connections which feed the

EDRCS Board. A +5V/1A power supply is sufficient for

the EDRCS B oard w ith the D ata Capture Boa rd. The ter -

minal bl ock may inclu de a -5 V pos i t ion (VEE) but i t is not

required for the EDRCS.

Clock Input

The EDRCS Board includes a 52MHz crystal oscillator

module so that an external clock source is not required. If

a different sample rate is desired a +16dBm sinewave or a

TTL leve l squarewave may be applied to the &/. input

SMA. The c rystal oscillator mo dule should be removed

from its socket when an extern al clock is used. For optimal

perfor mance a low jitter low phas e noise clock mu st be

provided (i.e. HP8644B or R&S SME-03).

The CLC5957 converts the differential input clock to a

TTL clock suitable for driving the CLC5903 &. input.

At high input levels the CLC5957 ADC’s SNR is limited

by clock jitter. In an EDRC S-based receiver the effects of

clock jitter can be reduced by operating the AGC at a

lower threshold. As the input signal level to the ADC

decreases the degradation of the ADC’s SNR will also

decrease.

SNR degrad atio n due t o clock jitt er onl y happ ens when t he

input signal is near full-scale. T his large input signal will

typically mask any SNR degradation that may occur. This

would not be the case if more than one carrier w as digi-

tized.

IF Signal Inputs

The AIN1 and AIN2 SMA conn ectors accept I F signals up

to +20dBm and below -100dBm. Always start with a sig-

nal at or below 0dBm, reset the EDRCS Board, then

increase the signal if desired. This allows the AGC loop to

control the DVGA properly as it will in a receiver. When

measuring very small signals consider using an externa l

attenuator in addition to the level control in the signal gen-

erator. Some signal generators do not perform well at very

low output levels. For optimal performance a low jitter

low phase noise signal source must be used (i.e. HP8644B

or R&S SME-03).

CLC5903 Serial Outputs

The default setup of the EDRCS Board is 3$&.(' ,

08;B02'( , 6)6B02'( , and )250$7 . These

settings provide a 24-bit ser ial output word, a frame sync

output pulse once for each I/Q pair, and the outputs for

channel A and B are mux ed onto the single output pin

$287 as shown in Figure 5.

Note

This is the format expected by the Data

Capture Boa r d.

The ser ial outputs an d control signals ar e availabl e at the

DIN connector J1. This connector mates with the Data

Capture Board. These signals are also accessible on the

DSP header for simple connection to a DSP.

In some c ases it m ay be desira ble to remo ve the sec ond

SFS pulse so t hat channel A and B can be ident ified. Set-

ting 6)6B02'(  will mask the second SFS pulse.

The default serial output configuration is compatible with

the TI TMS320C54X serial input. To interface to the

‘C54X, set the DSP ser ial port in continuous mode (FSM

bit set to 0) with frame ignore enabled (FIG bit set to 1). In

6&.

6)6

$287 023 ... 1 0 23 ... 1 023 ... 1 023 ... 1 0

I chan A Q chan A I chan B Q chan B

msb lsb

96 clocks

Figure 5 EDRCS Default Serial Port Format

msb lsb msb lsbmsb lsb

5'<

this mode the 24-bit words may be read as 3 groups of 8

bits. The overall input stream of four 24-bit words is read

as twelve 8-bit words for later reassembly by the DSP.

Additional serial port modes are discussed in the

CLC5903 datasheet.

CLC5903 Parallel Output

The CLC5903 paral le l output p ort i s availab le on J1. It is a

16-bit port which can be mapped into the address space of

a DSP. Each output com ponent (AI, AQ, BI, & BQ) is

allocated 2 registers of 16 bits. In 8-bit or 16-bit mode

only a single register for each co mpon ent n eeds to be r ead.

To access the data place the proper address on the three

3287B6(/ lines and ena ble the outputs with 3287B(1.

The 5'< signal can be used as an interrupt to indicate new

data is ready. Complete details are provided in the

CLC5903 datasheet.

To facilitate t esting of the parall el outputs SW1 can b e

used to force the state of 3287B6(/ and 3287B(1.

Note

All EDRC S Board SW1 positions m ust be

‘OFF’ if the Data Capture Board is used for

parallel data capt ure.

CLC5903 Debug Output

In some cases it may be desirable to look at signals inter -

nal to t he CLC59 03. The CLC5 903 debug por t is ti ed to an

internal 20-bit bus which can tap into the internal nodes

shown in Figure 6. When in debug mode the DSP serial

port pins are reconfigur ed an d the serial p ort is no longer

functional. 6&. is used to clock out the debug da ta at the

proper rate. Additional information on the debug port is

provided in the CLC5903 datasheet.

The debug port can be used to observe the ADC outputs

prior to processing by the CLC5903. This can be done by

selecting the mixer output tap for the I component and set-

ting the NCO frequenc y to zero. This setup is included in

the default COP 8 o ptions.

COP8 RS-232 Serial Interface

The CLC5903 can be set to several default configurations

by the COP8 micro-controller. To support more flexibility

in evaluation the CLC5903 may also be completely recon-

figured via an RS-232 serial port. The DRCS Control

Panel software running on a PC sends commands to the

COP8 seria l port. The COP 8 interprets the se commands

and programs the CLC5903 registers as required.

EDRCS Block Interfaces

DVGA to ADC Interface (LC Noise Filter)

While the IF SAW filter allows only the desired signal to

be sampled, the DVGA introduces broad-band noise at the

ADC input. A simple noise filter between the DVGA and

ADC removes this noise. Failu re to attenuate noise from

the DVGA appearing at the ADC sampling image frequen-

cies will degrad e the system perfor mance. Figure 7 shows

the response of the noise filter with respect to the sampling

images.

The nominal component values for the filter provide a cen-

ter fre quency of 150MH z, a 3dB bandw idth of 18MHz,

and an insertion loss of 0.7dB. Assuming an ADC sample

rate of 52MSPS, the filter provides about 4dB of attenua-

tion at the closest image frequency which is at 162MHz

(Figure 7). More attenuation is possible by increasing the

Q of the filter, but this would mak e the center frequency

tolerance more critical and increase the group delay

through the fi lter (the stabi lity of the AGC loop is reduced

by large group delays). More attenuation will also be

achieved if the IF is moved further away from 156MHz.

To change the IF frequency of the EDRCS Board, the

noise filter components must be changed. The equations

below pertain to Figure 8 and provide a means of comput-

ing the new values:

EQ. 4

EQ. 5

EQ. 6

EQ. 7

Figure 6 CLC5903 Debug Port Access Taps

COS SIN

NCO

Input

Mux I

Mixer AI

NCO Sin ANCO Cos A

F1 Out AI

AGC

Shifter CIC

& Scale FIR

F1 FIR

GAIN

F1 In AI

Each channel is identical. For each channel the I & Q

paths are ident ical.

The debug tap is always aligned into the MSB of the

20-bi t debug port output .

ωc1

L1CT

-----------------=

ωBW 1

RTCT

-------------=

GLC 1RT

-------CT

------⋅+=

CTC93 2⁄C99 1.5pF++=

In these equations, , ,

is the filter gain at , and is the quality factor of

the inductor at .

In addition to setting the center frequency of the filter,

capacitors and absorb the transient current that is

sourced out of the ADC coincident with the sampling

instant. It is recommended that and be no less

than 20pF.

It is easy to calculate a new s et of filter compo nents using

a spreadsheet program set up as follows:

Start by selecting an inductor with a relatively high Q

(30-40). Next, iteratively try available capacitor values for

and . Use to fine-tune the result. This exam -

ple uses 20pF and 1pF capacitors with a 33nH inductor for

a center frequen cy of 247.9MHz. On ce the final PCB is

available the center frequency should be checked to verify

the effects of PCB parasitics.

The frequency response of th e noise filter can be checked

at spot frequencies by observing either the CLC5903

Mixer AI or BI outputs in debug mode with the NCO set

to 0 freque ncy and 0 phase. T he tuning can be v erified at

the CLC59 03 out put by sweepi ng both t he input fr equen cy

and the CLC5903 tuning so that they track. The test signal

must be input after the IF SAW to u se th is method.

ADC to CLC5903 Interface

The CLC5957 ADC outputs are current limited

(DATA~2.5m A, DAV~5m A) to pr event cro sstalk ba ck to

the analog input. For this reason it is important to mini-

mize the parasitic capacitance on the data outputs and the

DAV signal. Excessive capacitance will degrade the

ADC’s SNR performance and may cause errors in the out-

put data. A target fo r capac itive loading shou ld be 5- 7pF.

To meet this target all power and ground planes should be

removed below the ADC output pins, traces, and

CLC5903 input pins. The area where the power and

ground planes are removed should be the point where ana-

log and digital planes are split. The included PCB layout

on page 27 shows how this can be done.

Clocking the EDRCS

When providing a clock signal for the EDRCS sever al

constraints must be observed:

1. The CLC5957 ENCODE specifications must be met,

2. The CLC5903 CK specifications must be met, and

3. The CLC5903 data input setup and hold times must

be met.

The CLC5957 and CLC5903 datasheets contain all the

timing parameters required to verify these conditions.

Now, using the datasheet specifications, consider each of

the above constraints.

CLC5957 ENCODE Requirements:

The CLC5957 ENCODE specifications require that the

ENCODE signal always be high (tP) for at least 7.1ns and

low (tM) for at least 7 .1ns. The m aximum time fo r tP and

4dB

150 156 162 Frequency (MHz)

Sampling

Image

IF Frequency

3X Sampling

Frequency

Baseband

Filter

Baseband Filter

Translated To

Sampling Images

LC Noi se

Filter

Figure 7 Illustration of the need for nois e fi lter attenuation at the samplin g images.

202 208 214

4X Sampling

Frequency

The desired signal at 150MHz appears as a 6MHz

signal a t th e ADC outp ut. T he other samp l in g

images at 162MHz, 202MHz, 214MHz, ... will

also appear as 6MHz signals at the ADC output.

The LC noise filter pre ve nts extra noise from these

sampling images from appearing at the ADC out put .

6MHz

C93 C94

=RT600 || 1K = 375 Ω=

GLC ωcQL

ωc

Figure 8 Noise filter components for AIN1.

C93

C94

1.5p 1K

600 C99

DVGA Output ADC Input and Stray PCB Capacitance

C93 C94

C93, C94 0.00000000002

C99 0.000000000001

Parasitic 0.0000000000015

Ct =B1/2+B2+B3

L1 0.000000033

Fcenter =1/(2*3.14*(B7*B5)^0.5)

C93 C94 C99

tM is limited by the minimum conversion rate. This

requires that 1/(tP + tM) never be less than 10MHz.

With a clock r ate of 52MH z (as used in the EDRC S for

GSM/EDGE systems) the period is 19.23ns. In this case, if

tP is reduced to 7.1ns the n tM will be 19.23ns - 7.1ns or

12.13ns. This correspond s to an acceptable duty cycle

varia t ion of 37%/63%.

CLC5903 CK Requirements:

The CLC5903 is specified to operate with a clock up to

78MHz with up to 40%/60% duty cycle variation.

CLC5903 Input Setup and Hold Requirements:

The CLC5903 includes an intern al OR gate to combine the

input clocks from two different CLC5957s (&.$ and

&.%). Each data input has its own register making the

input setup and hold times independent. The possible

clock variation (tDELTA=tDAV2-tDAV1) from &.$ to &.%

of 2.4ns due to the CLC5957 variation is shown in Figure

9. The (1& duty cycle can vary fr om 4 0% to 60 % for (1&

less than 72MHz withou t violating the m inimum tCKL

value of 3.1ns.

Ignoring the DAV Signals

When a square wave clock is available to drive ENCODE

this same signa l may be inverted to drive the CL C5903

&.$ input. When this is done, the duty cycle requirements

are those set by the CLC5903. The CLC5903 data input

setup and hold times will be independent of clock duty

cycle since all ti ming is no w relative to the falling edge o f

ENCODE. Figure 10 shows a single-ended clock circuit

and Figure 11 shows the timing diagram for this approach.

For the I DT74ALVC1G04 inverter, tPDA is the minimum

propagat i on del ay of 1.0ns an d tPDB is the maximum value

of 3.2ns. In this case, the setup and hold times are:

EQ. 8

EQ. 9

These margins (4.23ns, 2.8ns) are duty cycle independent.

A summary of the CLC5903 and CLC5957 datasheet tim-

ing parameters is provided in Table 1 for convenience.

'$7$

'$9

'$7$

Figure 9 EDRCS ADC to CLC5903 Clock Timing at 52MHz

'$9

(1&

tH2

tS2

tH1

tS1

tDAV1

tDAV2

tDELTA

tCKL

tSU tPtM

+()tDGV

–tPDA

19.23 13–1+

7.23ns

Parameter Symbol Timinga

a. Clock is 52MHz, values are min/max from CLC5957 and

CLC5903 datasheets. Datasheet va lues take pre cedenc e.

Pulse width high, CLC5957

(1&2'(

tP9.615ns

Pulse width low, CL C5957

(1&2'(

tM9.615ns

Rising

(1&2'(

to rising

'$9

, CLC5957 tDAV1 8.5ns

Rising

(1&2'(

to rising

'$9

, CLC5957 tDAV2 10.9ns

'$7$

setup to rising

'$9

, CLC59 57 tS1, tS2 7.215ns

'$7$

hold afte r risi ng

'$9

, CLC5 957 tH1, tH2 8.015ns

Falling

(1&2'(

'$7$

invalid, CL C5957 tDNV 7.0ns

Fall ing

(1&2'(

'$7$

valid, CL C5957 tDGV 13.0ns

Minimum time low for

&.$

&.%

tCKL 3.1ns

$_%,1

setup to rising

, CLC5903 tSU 3.0ns

$_%,1

hold afte r ri sing

, CLC5903 tHD 1.0ns

Table 1 ADC to CLC5903 Timing Summary

tHD tDNV tPDB

–

73.2–3.8ns

CKA

AIN

BIN

CLC5903

OSC

ADC

ENC ENC

Figure 10 Single-Ended Clock Schematic

All ca pa citors

are 0.01uF.

Inverter ‘A’ is

IDT74ALVC1G04

ACKB

Quick Start

Initial pe rformance meas urements of t he EDR CS Evalua-

tion Board can be obtaine d very quickly with the Data

Capture Board and associated Matlab scripts. The equip-

ment required to verify the EDRCS performance includes:

1. EDRCS Evaluation Board

(CLC-EDRCS-PCASM),

2. Data Capture Board (CLC-CAPT-PCASM),

3. +5V/1A power supply,

4. Signal generato r (150MHz si new ave, 0dBm),

5. PC with Windows 95, 98, NT4, or 2000 and Mat-

lab,

6. DRCS Cont rol Panel and Capt ure software.

Note

Existing installations of the DRCS Control

Panel Software (drcscp.exe) should be

upgraded to version 2 . 0.10.1 or later to add

CLC5903 support.

To make an FFT plot of the EDRCS output:

1. Install the Data Capture software from the included

CDROM (this also installs the DRCS Control Panel

software),

Note

Remove the spare mating connector shipped

with the eval board if attached.

2. Connect +5V and ground to J3 (the orange terminal

block) on the Ca pture Boar d,

3. Verify that a 52MHz oscillator module is installed

at Y2 (next to the &/. SMA connector),

4. Set all the DIP switches ‘OFF” on both the EDRCS

Board and the Capture Board,

5. On the Capture Board place the WCLK jumper in

the ‘PIN120’ position and the VCCD jumper in the

‘+5’ position,

6. Connec t a 0dBm 150M Hz sinewave input signal to

the $,1 SMA connector,

7. Connect the Capture Board J9 (serial port) to the

PC serial port with the supplied cable,

8. Turn on the +5V supply,

9. Start the Capture software. The Capture Software

Panel shown in Figure 12 will be displayed,

10. Click the right mouse button over the Capture soft-

ware panel (do not click over the ‘Start’ or ‘?’ but-

tons), sel ect ‘C onfigure I/ O’ (shown in F igure 1 3),

then select your COM port.

To proceed the Capture Board must have power, a sample

clock, and b e con nected to the pro per COM p ort. LED1 o n

the Capture Bo ard s hou ld be on. LED6 sho uld be on about

half as bright as LED1.

11. Click the right mouse button over the Capture soft-

ware panel, select ‘Configure Capture ’, then select

the options shown in the ‘Capture Configuration

Dialog’ (Figure 14).

12. Now click ‘Start’ to capture a 32k sample record.

The data will be saved in ‘c:\temp\data.dat’,

13. Start Matlab and add ‘c:\nsc\mfiles’ to the path,

tDGV

tDNV

tHD

tSU

tPDA

(1&

,19B(1&

'$7$

Figure 11 Inverted ENCODE Clock Ti ming at 52MHz

tPDB

Figure 12 Capture Software Panel

Figure 13 Capture I/O Dialog

14. Type ‘analys is_menu’ in the Matlab command win-

dow,

15. C lick ‘DRCS Serial’ on the menu to plot an FFT (or

run ‘drcs_ser_fft.m’ from the Matlab command

line).

The resulting FFT should be similar to Figure 15, showing

a single tone at about 50kHz. The measured Pinput should

be about -20dB relative to full-scale (dBFS) wi th 0dBm at

the SMA input connector.

Common Questions

1. What are the basic operating instructions for Matlab?

The Matlab command window opens when M atlab is

started. All Matlab commands can be directly typed

into the command window or saved in a script file for

repeated execution. Type ‘3+4’ then hit enter to see

Matlab display ‘ans=7’. Use the menu to create a new

script fil e (m-file): ‘ file->new->m- file’. Type ‘3+4’

on line 1. Save this file as ‘ my_test.m’ in the default

location. Now type ‘my_test’ to see ‘ans=7’. Now that

my_test.m exis ts, simp ly type ‘edit my_ test’ to load it

in the editor. To repeat a command hit the up-arrow

until the desired command is displayed then hit enter.

When the D RCS & C apture softw are are ins talled al l

the m-files are placed in ‘c:\nsc\mfiles’ by default.

This location should be add e d to the Matlab p a th. Use

the path browser: ‘file->set path’. Browse to

‘c:\nsc\mfiles’ then ‘path->add to path’ and exit the

path browser. Now Matlab will be able to locate all

the provided scripts.

The command ‘whos’ will list all the variables and

their sizes. ‘Clear’ will clear all the variables.

To create a new plot type ‘figure(1)’ then plot the data

to the figure with ‘plot(data)’. Type ‘zoom on, grid

on’ to enable zoom and draw a grid. Click and hold

the left mouse button to draw a zoom box. Dou-

ble-click the right mouse button to zoom full.

Matlab includes a comprehensive set of help files.

Type ‘help’ to get a list of available he lp files.

2. The tone in the FFT is not exactly 50kHz. Why?

Since the 52MHz crystal oscillator is not locked to the

signal generator, the tone in the FFT may not be

exactly 50kHz. A second signal generator locked to

the first can be used to clock the EDRCS Board and

remove the frequency error. Set the c lock signal gen-

erator to 52MHz at +16dBm. Be sure to remove the

crystal oscillator module from its socket.

3. The measured results are much worse than expected.

Why?

Observing the FFT plots in Figure 15 and Figure 16

(close-up) the tone at 50kHz may show some spread-

ing near the noise floor. This is typically caused b y a

signal generator with poor phase noise performance.

The phase noise will be translated into jitter which

impacts the ADC sampling performance. These phase

noise skirts can be so large that the measured data on

the FF T plot i s incorre ct. An alter nate FF T routine is

provided to remove the effects of the phase noise by

excluding the region near the fundamental tone. Click

‘Alt DRCS S erial’ (or ru n ‘drcs_ser_fft_excl.m’) to

observ e the change in both SFDR and th e Integrated

Noisefloor from Figure 15 to Figure 17. Editing the

Matlab sc ript ‘drcs_ser_fft_excl.m’ al lows t he exclu-

sion region to be set to the desired value. It is ±2kHz

by default.

Figure 18 shows an example of an input signal with

extremely poor phase noise performance.

4. Will the E DRCS work wi th such a poor clo ck signal?

Yes, this problem will not prevent the EDRCS from

easily recovering an E DGE signal. For full rate EDGE

Figure 14 Capture Configuration Dialog, Serial Port

2 4 6 8 10 12 x 104

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

FREQUENCY

MAGNITUDE (dBFS)

32768 Point FFT Analysis

Pinput = -19.3dBFS

SFDR = 68.3dBc

Integrated Noisefloor

= -80.1dBFS

Figure 15 IF Input = 150MHz at 0dBm

Phase Noise

the 23dB C/I requirement is still met with margin. At

lower signal levels jitter (from phase noise) does not

significantly affect the ADC’s performance. Take a

look at the same signal at (Figure 19) instead

of 0dBm (Fig ure 18).

5. What happens when the filter coefficients are

changed?

The noisefloor in the FF T pl ots reflects th e digi tal fil-

ter response. Changing the filter coefficients will

change the shape of the noisefloor. Verify this by cap-

turing a new data record as follows:

1. Connect the EDRCS Board and Capture Board as

described in the Quick Start section on page 8,

2. T ur n o n th e power and apply 15 0MHz at -80d Bm t o

the AIN1 connector,

3. Start Matlab and the Capture software,

4. Configure the Capture software as in Figure 14,

5. On the EDRCS Board turn SW2-4 & SW2-8 ‘ON’,

6. Press the EDRCS RESET button (LEDs should al-

ternate),

7. Capture ne w data and plot an FFT.

4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 5.0

x 104

−110

−100

−90

−80

−70

−60

−50

−40

−30

−20

FREQUENCY

MAGNITUDE (dBFS)

32768 Point FFT Analysis

The signal generator phase noise

limits the system performance. Use

the alternate FFT routine to exclude

the excess phase noise for accurate

measurements.

Figure 16 IF Input = 150MHz at 0dBm, Close-up

68dBc SFDR

2 4 6 8 10 12 x 104

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

FREQUENCY

MAGNITUDE (dBFS)

32768 Point FFT Analysis

Alternate FFT Routine Results:

Figure 17 IF Input = 150MHz at 0dBm, Alternate FFT

Pinput = -19.3dBFS

SFDR = 84.5dBc

Integrated Noisefloor

= -90.0dBFS

84.5dBc SFDR

-80dBm

2 4 6 8 10 12 x 104

−180

−160

−140

−120

−100

−80

−60

−40

−20

FREQUENCY

MAGNITUDE (dBFS)

32768 Point FFT Analysis

Very Bad Phase Noise:

Figure 18 IF Input = 150MHz at 0dBm

Pinput = -18.6dBFS

SFDR = 36.8dBc

Integrated Noisefloor

= -46.5dBFS

2 4 6 8 10 12 x 104

−200

−180

−160

−140

−120

−100

FREQUENCY

MAGNITUDE (dBFS)

32768 Point FFT Analysis

Low Level Results:

Figure 19 IF Input = 150MHz at -80dBm, Alternate FFT

Pinput = -98.9dBFS

SFDR = 34.8dBc

Integrated Noisefloor

= -121.0dBFS

Notice in Figure 20 that the integrated noisefloor

improved by 2dB over Figure 19. This is because the

slightly reduced bandwidth increased the processing

gain ( see the processing gain discussion on page 3).

6. How are the two sets of filter coefficients different?

The STD coefficients are optimized for a narrow tran-

sition-band (about 50kHz) with a flat pass-band and

stop-band resp onse. Th e stop-b and rejection is about

. The -3dBFS point is at 119kHz placing the

filter bandwidth at 88% of the output sample rate

(119kHz * 2)/270.833kHz.

The GSM coef ficients are op timized to meet th e GSM

blocking test requirements. These f ilters sacrifice the

narrow transition-band res ponse o f the STD filters for

an ultimate stop- band rejection of -10 5dBFS beyond

800kHz. The -3dBFS poi nt is at 87kHz placing the fil-

ter band width at 64 % of the ou tput sampl e rate. The

CLC5903 can meet the GSM-900 channel filter

requirements totally in the digital domain with these

filter coefficients.

7. Which filter coefficients should be used for GSM/

EDGE systems?

Since there is a SAW filter in front of the A DC either

set of coefficients may be used. Using the STD set

may make it easie r to recover the signal since it pro-

vides a little wider bandwidth .

8. Why are the F1 coefficients included with the DRCS

Control Panel software and the COP8 configuration

file different than those in the CLC 5903 datasheet?

These coefficients have been uniformly scaled to cre-

ate +4dB o f gain relative to t hose in t he da tasheet.

This compensates for the error in the SCALE and CIC

filter combination wh en the CIC decimation is not a

power of two. These new coefficients are optimized

for GSM/EDGE systems.

9. What if SW 2-4 and SW2-8 are not set the same?

SW2-4 sets the decimation and SW2-8 selects the fil-

ter coefficient s. Both must be e ither ‘O FF’ for the

STD coefficients or ‘ON’ for the GSM coefficients. If

they are not the same the tone in the FFT plot may

show up at the wrong frequency or the rolloff from

the filter will not be observed.

10. Why does the FFT plot look like Figure 21?

In the Capture software, make sure that ‘Capture 1st

Bit’ is checked. This option controls th e deserializa-

tion of the EDRCS output. For some combinations of

output and decimation this setting may change. The

DRCS Control Panel software will tell you how to set

this option on the ‘Output’ tab (see page 14 ).

11. Why is the default tuning at 150.05MHz?

An input signal at 150.0MHz can be easily generated

by driving a 150MHz bandpass filter with a 50MHz

crystal oscillator. Only the third harmonic is passed by

the filter providing a low-jitter test signal. Tuning to

150.05MHz places the 150MHz signal at 50kHz in

the EDRCS output. Adding a variable attenuator

allows a wide range of measurements to be made

without an expensive synthesized signal generator.

12. Can the ADC output be observed?

Yes. The CLC5903 debug output allows the complex

mixer outpu ts to be observed. When the NCO is set to

0Hz the ADC output will be pr esent at the I output.

The Q output will be zero unless a phase offset is

introduced.

13. What if a scope is to be u sed to look at the ADC dig i-

tal outputs?

2 4 6 8 10 12 x 104

−220

−200

−180

−160

−140

−120

−100

FREQUENCY

MAGNITUDE (dBFS)

32768 Point FFT Analysis

Low Level Results, GSM Filter:

Figure 20 IF Input = 150MHz at -80dBm, Alternate FFT

Pinput = -99.0dBFS

SFDR = 39.3dBc

Integrated Noisefloor

= -123.0dBFS

-80dBFS

2 4 6 8 10 12 x 104

−90

−80

−70

−60

−50

−40

−30

−20

−10

FREQUENCY

MAGNITUDE (dBFS)

32768 Point FFT Analysis

Wron g Capt u re Settin gs:

Figure 21 IF Input = 150MHz at 0dBm, Bad Alignment

Pinput = -4.7dBFS

SFDR = 8.7dBc

Integrated Noisefloor

= -3.0dBFS

Make a special sco pe probe by soldering a 1K ohm

resistor to the center of a BNC connector. Add a short

ground cli p to t he outer conduct or. Now plug the B NC

into a 50 ohm cable to the scope and set the scope to

50 ohm inpu t mode. This method will provide accu-

rate results since there is v ery little parasitic capaci-

tance.

14. How can the AGC operation be verified?

To verify the AGC operation both the ADC output

and the CLC5903 output can be compared. The ADC

output will reveal the 6dB steps caused by the DVGA.

The CLC5903 output will be linear since the 6dB

steps are precisely compensated in both amplitude

and time.

In normal operation the AGC keeps the ADC input in

the optima l range throughout th e TDMA burst. T he

AGC will adjust the DVGA at the beginning and end

of each burst and perhaps during a fade. This is true

for GSM since the modulation is of a constant ampli-

tude.

Observing an AM modulated carrier through the

debug port allows the step s in the ADC outpu t to be

observed. Figure 22 shows the ADC output with an

AM modulated input signal (3kHz modulation at

150MHz IF, -15dBFS threshold, 12dB deadband,

1.5us tc).

Changing on ly th e modul atio n frequency ( 300Hz) and

looking at the CLC5903 (DDC) output shows the

reconstructed waveform (Figure 23).

When receiving an EDGE signal the AGC must prop-

erly reconstruct the AM content of the modulation.

The precise time-alignment of the compensation cir-

cuitry enables EDGE data recov ery with no loss in

performance. In some cases the AGC operation will

increase the noisefloor slightly but since this only

happens a t high signal le vels it does not im pact the

receiver’s performance.

Figur e 2 4 s ho ws the ADC ou tput wit h an EDGE mo d-

ulated 150MHz IF input. The DVGA is set to a fixed

gain of +6dB. The same signal (skewed in time) with

the AGC enabled is shown in Figure 25. A sym-

bol-by-symbol comparison of these two signals at the

1 1.5 2 2.5

x 104

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

7 DVGA Steps of -6dB

7 DVGA Steps of +6dB

Figure 22 AM Modulation, 150MHz IF, ADC Output

1.3 1.4 1.5 1.6 1.7 1.8 1.9 2

x 10

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

7 DVGA Steps of -6dB

7 DVGA Steps of +6dB

Figure 23 AM Modulation, 150MHz IF, DDC Output

2000 3000 4000 5000 6000 7000 8000

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

Figure 24 EDGE Modulation, 150MHz IF, ADC Output,

AGC Disabled (DVGA fixed at +6dB)

1.4 1.5 1.6 1.7 1.8 1.9 2

x 10

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

DVGA +6dB Step

DVGA -6dB Step

Figure 25 EDGE Modulation, 150MHz IF, ADC Output,

AGC Enabled

CLC5903 output (baseband I component) is shown in

Figure 26. This figu re demon strates the high degree of

linearity achieved by the CL C5903/CLC5526 AGC

circuitry.

15. How can the various evaluation boards be intercon-

nected?

Refer to the Evaluation Board Interoperability User ’s

Guide at www.national.com under the Wireles s Infra-

structure Product Site for this information.

16. When the CLC 590 3 i s i n 16 -bit o ut put m ode al l o f the

serial output bits are zero. Is something broken?

The theoretical noisefloor for a 16-bit digital word is

about -98dBFS. The output noisefloor of the EDRCS

Board is abo u t -1 21 dBFS f or t he de fa ult s e tup. A sig -

nal must be applied to bring the output above

before the serial output will change.

DRCS Control Panel Software

The DRCS Control Panel (drcscp.exe) requires Windows

95/98/NT/2000 and a free serial port to operate. Run

setup.exe from the CD R OM to c opy the ap propriat e files

to your hard drive and build the necessary directory struc-

ture. Run drcscp.exe to start the program.

Note

Existing installations of the DRCS Control

Panel Software (drcscp.exe) should be

upgraded to version 2.0.10.1 or later to add

CLC5903 support.

To configure the COM port, choose &RQILJXUH,2 from the

)LOH menu.

The DRCS Co ntrol Panel is a user interface which allo ws

the CLC5903 con figuration registers to be programm ed

from a PC. All register settings are contro lled from the

four tabs on the left. The 5HJLVWHUV page (Figure 27) allows

you to view a summary of the register values that are

down-loaded to the CLC5903.

Note

The DRCS Control Panel software can only

write to the CLC5903 registers. The software

cannot read the CLC5903 register values.

Except for the 5HJLVWHUV page, each page has a 6HQG3DJH

or 6HQG button. When p ressed, the re gister values associ-

ated with that page are down-loaded to the CLC5903. In

addition, a 6HQG$OO'DWD command is available under the

)LOH menu.

Note

The 6HQG buttons only send the data for their

own pages .

The configuration data enter ed into the various pages can

be saved to a .dcp configuration file so they can be

reloaded later. The file is ASCII and has one li ne for each

byte that is written to the CLC5903. The first column is

the address and the second is the data. Both are in hex for-

mat. This hex data can be copied and used in the final sys-

tem to simplify the development process. The 6DYH

&RQILJXUDWLRQ and /RDG&RQILJXUDWLRQ co mmands can be

found under the )LOH menu.

When you start the DRC S Control Panel, it will load the

last used .dcp file within the data subdirectory

(c:\nsc\data) . If you have not yet created one, it will look

for default.dcp. If default.dcp is not found, it will use a set

of hard-coded defaults for everything except FIR Filters

F1 and F2. For the filters, the program will search for

default.f1 and default.f2. If they are not found, zeros will

be loaded for the coefficients.

Figure 26 EDGE Modulation, Baseband I Component,

AGC Fixed and AGC Enabled Compared

650 660 670 680 690 700 710 720 730 740 750

−0.1

−0.08

−0.06

−0.04

−0.02

0.02

0.04

0.06

0.08

0.1

Error

I Samples with

and without AGC

-98dBFS

Figure 27 Registers Page

The data entry fields are designed to allow values to be

entered using pulldown menus or edit boxes in familiar

engineering terms, rather than the integer values that are

required by the CLC5 903. The en gineerin g values are co n-

verted to the appropriate integer values and appe ar on the

5HJLVWHUV page. For example, when -150.05 is entered into

)UHT, &KDQQHO$, the 5HJLVWHUV page displays the value

491443374 for )5(4B$ (Figure 27). When the mous e is

held over a d ata entry fie ld, a balloon is displa yed which

describes the function. If a value is entered that is outside

the valid range, a warning is displayed.

For the most part, the data entry fields are intuitive given

an understanding of the CLC5903 data sheet. A few

exceptions are noted below:

Channels Page

)UHT is the frequency of the NCO. You can either enter the

IF frequency at the ADC input or the aliased frequency at

the ADC ou tput. To dow n-convert w ithout a phase inver -

sion, use the plot in Figure 2. The signals with dashed

lines should be entered with a negative sign. For example,

an IF frequency of 150.05MHz requires an entry of

for no phase inversion. An alternative is to recog-

nize that 150.05MHz aliases to -5.95MHz when )&. is

52MHz and, for no phase inversion, enter +5.95. )&.

refers to the sample rate of the EDRCS Board, which has a

fact ory default of 52 MHz.

6FDOH refers to the bit shift prior to th e CIC filter (Figure

49). 6FDOH&DOFXODWHG is calculated by the program and is

the value required of 6FDOH to mainta in th e gain of the

DDC up to and including the CIC filter to unity or just

below. It changes when &,&'HFLPDWLRQ changes. 6FDOH

$GMXVW is a bit shift value added to 6FDOH prior to down-

loading to the CLC5903. You can enter either a positive or

negative value with the restriction that 6FDOH$GMXVW +

6FDOH&DOFXODWHG fall within the range of 0 to +44 inclu-

sive. A warning is issued for values entere d outside this

range.

*DLQ refers to the bit shift after the CIC filter (Figure 49).

AGC Page

The popup menus for initial conditions and gains refe r to

the gain of the DVGA. The loop dynamics for the AGC

are set in the lower left box. Press the Calculate button

after ente ring values for 7KUHVKROG, 'HDGEDQG, and 7LPH

&RQVWDQW and the AGC lookup table values and

$*&B/223B*$,1 are computed. Adding the 1-tap or

4-tap comb sections to the power detector can improve

carrier rejection for NCO frequencies near 3.25MHz when

Fs = 52MHz.

Output Page

6&.5DWH must be selected low enough to allow all serial

bits to exit within o ne ou tput samp le period . If there is not

enough time to transmit all the serial data an error message

will be displayed. See the CLC5903 data sheet for further

discussion.

The proper setting of the ‘1st Bit’ option of the Capture

software will be shown on the 2XWSXWpage (Figure 28).

Coefficient Assignment Page

Each of the two independe nt coefficient memories for F1

and F2 can be assigned to either or both channels. Control

of the coefficient assignment crosspoint switch is shown

on the &RHIILFLHQW$VVLJQPHQWpage (Fig ure 29).

Filter Data Pages

The coefficient values for each of the symmetric FIR fil-

ters can be manually entered or loaded from an ASCII text

file using the /RDG button. The file must have a .f1 exten-

sion for ),5)LOWHU and a .f2 extension for ),5)LOWHU. The

file format is one signed integer coefficient per line and

the number of lines must equal the number of unique co ef-

ficients. Also, there must be no blank space befor e the val-

ues in the files. Open one of the default coefficient files

(c:\nsc\data\default.f1) in a text edito r to see the format.

-150.05

Figure 28 Output Page

Figure 29 Coefficient Assignment Page

Since the CLC5903 has two independent sets of coeffi-

cient memory, there are two Filter Data pages labeled

Memory A and Memory B.

Serial Communications

There is no handshaking between the EDRCS Board and

the PC. If the system is operating correctly, all the LEDs

will light during transmission and only LED1 will remain

lit at the completion of transmission. If the transmit

sequence is upset, reset the EDRCS Board and re-send.

Control Panel Software Questions

1. Loading new filter coefficients did not change the

response as expected. Why?

If the new filter coefficients require a different deci-

mation value it must also be sent to the EDRCS

Board.

2. What happens to the default configuration loaded by

the COP8 when new data is sent?

When the DRCS Control Panel sends data to the

EDRCS Board the new data replaces any existing

data. Only the data for a single page is updated unless

a 6HQG$OO'DWD command is issued.

3. Is there any non-volatile storage on the EDRCS

Board?

Only in the COP8 EPROM. No user-accessible

non-volatile storage is available.

Default Configuration and SW2 Settings

The CLC-EDRCS-PCASM is configured for 52MHz

operation. A 52MHz crystal oscillator module is included

so that only one signal gen erator is required fo r evaluation.

Table 2 describes the tuning frequencies and filter sets

selected by SW2 with a 52MHz clock. Additional SW2

settings (positions 8, 7, 6, & 5) are shown in Table 3. The

Table 3 parameter s operate i ndependen tly fro m the Table 2

parameters exce pt for SW 2 position 8.

The complete COP8 programming tables are available in

the file c:\nsc\data\drcs7config_013100.txt after the

DRCS Control Pan e l so ftw a re is installed.

Note

The default LC noise filter on the EDRCS

Board has an 18MHz bandwidth centered at

150MHz. S ome of t he SW2 t uning op tions will

require modification of the LC filter to

prevent attenuation of the desired signal.

Config

Number SW2

(87654321) Channel A/B

Tuning CIC/F1*F2

DecimationaFilter

Set

0 0XXX0000 -150.05MHz

-150.05MHz 48/4 STD

1 0XXX0001 +10.70MHz

+10.70MHz 48/4 STD

2 0XXX0010 -199.00MHz

-199.00MHz 48/4 STD

3 0XXX0011 -246.00MHz

-246.00MHz 48/4 STD

4b0XXX0100 -150.05MHz

-150.05MHz 24/4 STD

5c0XXX0101 0.00

0.00 N/A N/A

6d0XXX0110 0.00

0.00 N/A N/A

Table 2 SW2 Default Configurations

7e1XXX0111 +10.00MHz

+7.50MHz 24/8 GSM

8 1XXX1000 -150.05MHz

-150.05MHz 24/8 GSM

9 1XXX1001 +10.70MHz

+10.70MHz 24/8 GSM

10 1XXX1010 -199.00MHz

-199.00MHz 24/8 GSM

11 1XXX1011 -246.00MHz

-246.00MHz 24/8 GSM

12f1XXX1100 -150.05MHz

-150.05MHz 12/8 GSM

a. This col umn shows the CIC decima ti on and the F1 dec im a -

tion * F2 decimation. All cases provide a total decimation

of 192 for GSM/EDGE systems (270.833ksps output) ex-

cept Con fig 4 & 12 which dec i mate by 96 (541. 66ksps).

b. 2x Oversam pled Outputs (541.66ksps)

c. Mixer AI Debug

d. Mix er BI Debu g

(;3B,1+

=1,

$,1

drives both channels

f. 2x Oversamp le d Out puts (541.66ksps)

Function SW2 0 1

FIR Coefficientsa

a. SW2-4 and SW 2-8 should alwa ys be in the same state.

8STDGSM

AGC Dynamicsb

(Threshold/Deadband)

b. Both setti ngs ha ve a 1. 5µsec time constan t.

7-12dBFS/

12dB -15dBFS/

9dB

AGC Mode 6 Run Stop

NCO Dither 5 On Off

Table 3 Additional SW2 settings

Config

Number SW2

(87654321) Channel A/B

Tuning CIC/F1*F2

DecimationaFilter

Set

Table 2 SW2 Default Configurations

Table 4 gives the configuration regist er values for each of

the AGC modes associated with SW2 position 6 as men-

tioned in Table 3.

Any of thes e default configuration s can be modifie d by

using the D RCS Control Panel sof tware. See the DRCS

Control Panel Software section on page 13.

Data Capture Board Settings

The Data Capture Board and companion software provide

the ability to capt ure da ta from the EDR CS Board as well

as a variety of analog-to-digital converter products. When

evaluating the EDRCS Board, configure the Data Capture

Board like this:

• DIP switches all ‘OFF”

• ‘WCLK’ jumper = ‘Pin120’

• ‘VCCD’ jumper = ‘+5V’

Figure 30 provides a quick reference for the Data Capture

software conf ig urati o n opt ions .

In-Depth Operation

This procedure will verify proper operation of the EDRCS

Board and Da ta Capture Board. Initial operation is cov-

ered in the Quick Start section on page 8.

If a Data Capture Board is not available, an alternate

method of saving the data to a file must be used. The

default output format for the EDRCS Evaluation Board is

shown in F igure 5. If the data is s tored in a two’s comple-

ment integer format the supplied Matlab scripts may still

be used to process it.

The sequence below requires an unmodulated sine wave

source (i.e. HP864 4B or R& S SME-03) to generate the

input signal.

The DRCS Control Panel software will not be used until

the first tests are successfully completed.

1. If you have not already done so, install the DRCS

Control Panel and Data Capture Board software.

2. Connect +5V to VCC and ground to GND of con-

nector J3 (the ora nge terminal block) on the Data

Capture Board. When the b oards are c onnected to-

gether in the next step, these connections will pow-

er both boards. Note that VEE is not required

because ne ither board needs a negative power sup-

ply.

3. Connect J1 of the EDRCS Board to J1 of the Data

Capture Board. Be sure to remove the spare mating

DIN connector if one is attached.

4. Connect a serial cable from the PC to J9 on the Data

Capture Boar d.

5. If two serial ports are available on the PC, connect

the other to J9 of the EDRCS Boa rd . If not, the sin-

gle port must be shared.

6. Make sure that al l DIP s witches on both boards are

set to off.

7. Turn on the power supply.

8. Start the DRCS Control Panel and Data Capture

Board software.

9. Configure the COM ports for the DRCS Control

Panel and Data Capture Board software. The COM

port setup for the DRCS Control Panel is located

under )LOH, &RQILJXUH,2. The COM port setup for

the Data Capture Board software is accessed by

right-mouse-button clicking anywhere on the pro-

gram window and selecting &RQILJXUH,2. Note that

power must be applied to th e Data Capture Board,

the clock must be present, and the serial cable must

be connected in order for the software to accept the

COM port configurati on.

0 (Run) 1 (S top)

$*&B+2/'B,&

$*&B5(6(7B(1

a. This functio n is not supported on the CLC 5903.

$*&B)25&(

b. This function is not supported on the CLC5903.

(;3B,1+

$*&B&2817

c. This functio n is not supported on the CLC 5903.

2815 2815

$*&B,&B$%

32 32

Table 4 Register values corresponding to SW2 s witch

position 6.

Figure 30 Capture Software Quick Reference

Specifies the Serial

Output pin on the

CLC5903 to monitor

Capture Serial Capture Parallel

data data

I/Q Options

To FIFO

To SRAM

Deserialize the

selected channel

Deserializer Control

specified by DRCS

Control Panel software

10. Connect a -10dBm sinewave at 150.00MHz to the

EDRCS Board $,1 input.

The DVGA should servo to a gain of either +6dB

($*$,1=3) or +12dB ($*$,1=4) and the ADC should be

operating at a level of -10dBFS or -6dBFS. Because

(;3B,1+ is not asserted for this configuration, the DDC

output (which will be observed below) should be at

. This can be computed f rom the gain e quations

presented in the Appendix (pa ge 31) and the register data

prov id ed i n th e 5HJLVWHUV pag e of the DRC S Contr ol Panel .

The first measurement will be to use the debug mode of

the CLC5903 to pro be the outpu t of the ADC.

11. Set SW2 on the EDRCS Board to ‘00000101’

(87654321) then press reset. This selects the Mixer

AI debug output and sets the NCO to 0Hz.

12. Use the right mouse button to access the &RQILJXUH

&DSWXUH screen of the Data Capture Board software

and choose &DSWXUH'HEXJwithin the 0RGH box.

Then choose 8SSHU%LWV within the %LWV box.

Press 2. The screen should appear as in Figure 31.

13. Press 6WDUW on the front panel of the Data Capture

software . When the c ompletion bar rea ches 100%,

the captured data will be written to the file

C:\TEMP\DATA.DAT.

If the TEMP directory did not previously exist, the soft-

ware will create it. You can also specify a different file

name and directory by right-mouse-button-clicking on the

Data Captu re Board soft ware window an d choosing the

&KDQJH'DWD)LOH command. Keep in mind that the Mat lab

scripts will look for the data in the defau lt location.

The value s in DATA.DAT represent 24-bit 2’s complement

integers. Wh en 0L[HU$, is selected, only the upper 15 bits

are non-zero. These numbers can be converted to signed

fractional values and plotted by running the Matlab script

‘plot_twos.m’. Verify that the waveform is sinusoidal.

Veri fy that the amplitu de is correct by plotting an FFT.

Either select ‘ DRCS Debug’ from the ‘analysis_menu .m’

script or run ‘drcs_par_fft.m’. The ‘Pinput’ shown in the

upper right should report either -10dBFS or -6dBFS and

there should be a tone at 150MHz-(3*52MHz) = -6MHz.

The next measurement will observe the output of the

DDC.

14. Set all the EDRCS Board SW2 DIP switches to

‘OFF’ and press reset.

15. Choose &DSWXUH within the 0RGH box of the &RQILJ

XUH&DSWXUH s creen of t he Data Capt ure Board soft -

ware. Then choose %LWV within the %LWV box and

&DSWXUHVW%LW within the VW%LW box. Finally,

choose &KDQQHO$ from the &KDQQHO box and press

2.. The screen should appear as in Figure 14 (see

page 9).

16. Click 6WDUW on the front panel of the Data Capture

Board software window.

The values in th e file again represent 24-bit 2’s comple-

ment integers except now all 24 bits are non-zero. Use the

MATLAB script ‘plot_twos.m’ (Plot Twos from the analy-

sis m enu) to conve rt the da ta to s igned fractio nal valu es

and plot th em.

Note

Regardless of the true width of the word being

captured, the Data Capture Board will always

write 24-bit, 2’s complement numbers to

DATA.DAT. The only exception to this is

when probing $*&&,&$% in which case each

number represents two appended 9 bit

numbers.

Verify with an FFT that the output is -28dBFS at fre-

quency 150.00MHz-150.05MHz = -0.05MHz. Use the

‘DRCS Serial FFT’ menu op tio n or ru n ‘d rcs _ser_fft.m’ to

plot the FFT. A slight frequency offset may exist due to

variations in the frequency of the on-board 52MHz crystal

oscillator. Note that the output sample rate is 52MHz / 192

= 270.8KH z. The FFT w ill show the CLC5903’s filter

bandwidth reflected in the shape of the noise floor.

If the signal source causes excessive phase noise at the

base of the fun damental tone in the FFT the measur ed data

will be wrong. The routine ‘drcs_ser_fft_excl.m’ (Alt

DRCS Serial from the analysis menu) allows the data

within ±2kHz to be replaced by the average noise floor

value. This will allow correct measurements to be made.

The exclusion bandwidth can be set in the script. This

script m ust be us ed to verify the prope r noise pr ocessing

gain.

17. Repeat steps 10 through 13 for input AIN2 replac-

ing all occurrences of &KDQQHO$with &KDQQHO%. In

step 11 set SW2 to ‘00000110’.

Next the DRCS Control Panel software and the serial

interface will be verified.

18. Press reset on the EDRCS Board.

-28dBFS

Figure 31 Capture Configuration Dialog, Debug Port

19. On the &KDQQHOV page of the DRCS Control Panel,

enter 0 for )UHT within the &KDQQHO$ b ox to set th e

frequen cy of the channel A NCO to zero. Also

check 'HEXJ(QDEOHG and select 0L[HU$, from the

3UREHDW pulldown menu within the &RPPRQ box.

The screen should appear as in Figure 32. Click on

the 6HQG3DJH butto n. Imm edi at ely fol l owing th i s, a

data transfer indicator box will ap pear on the moni-

tor and all the LEDs on the EDRCS Board will light

momentarily.

Now repeat steps 12 and 13 and review the results as

before.

20. On the &KDQQHOV page of the DRCS Control Panel,

enter -15 0.0 5 fo r )UHT of &KDQQHO$, uncheck 'HEXJ

(QDEOHG. The screen should a ppear as in Figure 33.

Click o n the 6HQG3DJH button.

Repeat steps 15 and 16 and review the results as before.

Changing the frequency with the DRCS Control Panel,

capturing more data, and performing an FFT should cause

the output tone on the FFT to move the same amount.

This completes the verification of the board operation.

DDC Large-Signal Nonlinearity Exercise

This exercise is intended to illustrate the two types of

large-signal nonlinearity that can be encountered when the

CLC5903 is incorrectly configured. Both can be observed

at the input of filter F1. The same equipment is use d as in

the In-Depth Operation section on page 16.

1. Connect a -10dBm sinewave at 150.000MHz to the

EDRCS Board $,1 input.

2. Load default.dcp by choosing /RDG &RQILJXUDWLRQ

from the )LOH menu of the DRCS Control Panel.

3. On th e &KDQQHOV page, enter -150.005 (5kHz offset)

for )UHT wi thin the &KDQQHO$ box and enter 6 for

6FDOH$GMXVW withi n the &RPPRQ box. Also check

'HEXJ(QDEOHG, s elect ),Q$, from the 3UREHDW

pulldown menu, and set &KDQQHO*DLQs to 0. The

screen should look like Figure 34. Click on the

6HQG3DJH button.

4. On the &RQILJXUH&DSWXUH screen of the Data Cap-

ture Board software, choose &DSWXUH'HEXJ within

the 0RGH box a nd %LWV from the %LWV box (se e

Figure 31). Click on 2..

5. Press 6WDUW on the front panel of the Data Capture

Board software window.

As before, the values in DATA.DAT repres ent 24-bit 2’s

complement integers and only the upper 18 bits are

non-zero. Use the MATLAB script ‘plot_twos.m’ (Plot

Twos from the analysis menu) to convert the data to signed

fractional values and plot them. Zoom in on the first 300

points to see something similar to Figure 3 5. This distor-

tion is caus ed by overflow in the CIC filter du e to 6&$/(

being set too large. This overflow cannot be sensed and

the only wa y to av oid it is by making sure that 6&$/( is

set consistent with the chosen CIC decimatio n value so

Figure 32 EDRCS Channel Configuration, Debug Output

Figure 33 EDRCS Channel Configuration, Serial Output

Figure 34 EDRCS Channel Configuration, CIC Rollover

that the CIC output is less than full scale. Figure 35 m ay

not look exactly the same as yours due to the frequency

error between the on-board clock oscillator and the input

source. The important characteristic of the distortion is

that the positive sin usoid peaks hav e been translated to

negative values and the negative peaks to positive values.

6. Go back to the &KDQQHOV page of t he DR CS Control

Panel and change 6FDOH$GMXVW back to 0. Next, se-

lect G% from the *DLQ pulldown menu in the

&KDQQHO$ b ox. The screen should look like Figure

36. Click o n 6HQG3DJH.

7. Press 6WDUW on the front panel of the Data Capture

Board software window.

Use ‘plot_twos.m’ (Plot Twos from the ana lysis menu) to

convert the data to signed fractional values and plot them.

Zoom in on the first 300 points . You should see the clip-

ping as shown in Figure 37. This represents the type of

nonlinearity at all stages of the DDC except for the CIC

filter.

Figure 35 CIC Overflow Distortion

050 100 150 200 250 300

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

Figure 36 DRCS Channel Conf iguration, Saturation

Figure 37 Datapath Saturation at the F1 Input

050 100 150 200 250 300

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

Connector Pinouts

Table 5 describes the 64-pin DIN connector (J1) pinouts

on the EDRCS Board.

Power is supplied through J1. If the Data Capture Board is

connected to J1, pow er should be co nnected to J3 (the

orange terminal block) on the Data Capture Board.

Table 6 describes 10-pin JTAG header and 16-pin DSP

header pinouts. The schematic in Figure 41 provides the

pinout for J9, a female DB-9 used to connect the standard

RS-232 serial cable from the PC.

Operation with a 13MHz Reference

The advantages of operating the EDRCS at 52MHz make

it worthwhile to do so eve n in a 13MHz system. This can

be done by either of these two methods:

1. Replace the system oscillator with a 52MHz unit

and divide down to 13MHz. This is probably the

lowest cost altern ative since only one VC XO is re-

quired. Keep in mind that the phase noise of the

52MHz VCXO will also be divided down.

2. Phase-lock a 52MHz VCXO to the 13MHz clock.

This approach requires additional components but

has the least impact on existing circuitry. A circuit

that can be used for this purpose is shown in Figure

42.

Schematics

Figure 38, Figure 39, Figure 40, and Figure 41 are the

CLC-EDRCS-PCASM schematics.

Reference Design

The schematic for a complete reference design is provided

in Figure 43. This circuit is the same as the EDRCS Evalu-

ation Board without the COP8 and its associated compo-

nents. In this ex ample the LC filter is tu ned to 71MHz and

must be re-tuned to the appropriate value.

Pin J1 A J1 B

1N/C N/C

2 GND GND

3 MSB_T MSB_F

4 N/C D14_T

5 N/C D13_T

6 N/C D12_T

7 N/C D11_T

8 N/C D10_T

9N/C D9_T

10 N/C D8_T

11 N/C D7_T

12 N/C D6_T

13 N/C D5_T

14 N/C D4_T

15 N/C D3_T

16 N/C D2_T

17 N/C D1_T

18 N/C LSB_T

19 GND GND

20 N/C RDY

21 SFS SCK

22 BOUT AOUT

23 POUT_SEL2 N/C

24 POUT_SEL1 N/C

25 POUT_SEL0 RDY

26 POUT_EN AGC_EN

27 GND GND

28 GND GND

29 N/C N/C

30 N/C N/C

31 +5V (DIGITAL ) +5V (DIGITAL )

32 +5V (ANALOG) +5V (ANALOG)

Table 5 Eurocard connector J1 pinout.

Pin JTAG DSP

1 TCK N/C

2 GND GND

3 TDO SCK

4 VCC GND

5 TMS BFSR

6 N/C GND

7 TRST BDR

8 SCAN_EN GND

9 TDI GND

10 GND GND

11 N/C

12 GND

13 N/C

14 GND

15 N/C

16 GND

Table 6 JTAG and DSP header pinouts

Figure 38 ADC Input AIN1

Figure 39 ADC Input AIN2

Figure 40 CLC5903 Dual Digital Tuner/AGC

Figure 41 COP8 Microprocessor

Figure 42 Circuit for a 52MHz VCXO Locked to a 13MHz Reference

Vectron

Figure 43 EDRCS Reference Design

PC Board Layout

Silk screen parts placement drawings are shown below.

The complete board layout package can also be provided.

Primary areas of concern are the analog inputs to the ADC

and the ADC digital outputs.

Care has been exercis ed to prev ent gro und loops and no i se

coupling on the circuit board at the inputs. Noise coupling

is reduced by aligning the split between analog and digital

planes across all layers.

The ADC outputs have been kept as short as possible to

minimize ca pacitive loading. The interna l ground pla ne

has been removed under the se traces to reduce the para-

sitic capacitance. Higher capacitance values will load the

ADC output drivers causing additional noise on the inter-

nal analog signals. This will degrade the ADC perfor-

mance. Analog and digital grounds have been star

(common-point) connected to minimize crosstalk. The

supplies have series inductors for e ach section to pr ovide

extra isolation.

Figure 44, Figure 45, Figure 46, and Figure 47 show the

EDRCS Board parts placement and PC board layers. PCB

layout tips are annotated on the plots.

Figure 44 EDRCS Board layout, Top, L1 + Silk

Keep these traces

to the minimum

length possible.

Figure 45 EDRCS Board layout, GND, L2

AGND

DGND

Line up split between analog

and digital planes across all layers.

Minimize parasitics at

the LC filter since these

are high-impedan ce nodes .

Common-point ground

where the analog and

digital plan es join.

Minimize capacitive loading

on the ADC output by removing

power and ground planes.

Figure 46 EDRCS Board layout, Power, L3

Line up split between an al og

and digital planes across all layers.

Minimize parasitics at

the LC filter since these

are high-imped ance nodes .

Minimize capacitive loading

on the ADC output by removing

power and ground planes.

Figure 47 EDRCS Board layout, Bottom, L4

Line up split b etween analog

and digital planes across all layers.

Minimize parasitics at

the LC filter since these

are high-impedance nodes.

Minimize capacitive loading

on the ADC output by removing

power and ground planes.

Appendix

Input Circuit a nd Signal Levels

The $,1 and $,1 IF in puts are tra nsformer coup led

into the DVGA inputs. The transformers convert the sin-

gle-ended input signal to differential and match the 200

input of the DVGAs to the 50 input connectors. The y

have a voltage gain of 2:

(EQ. 10)

In a production system, the transformer might be replaced

by an IF SAW with differential output drive capability .

With the DVGA set to maximum gain (+30dB), the total

analog gain from the input connector to the ADC is

33.8dB and an input level of -23.8dBm will drive a

full-scale input at the ADC. With the DVGA set to mini-

mum gain (-12dB), the total analog gain is -8.3dB and a

+18.3dBm input level is required to drive the ADC to full

scale. Typically, the AGC reference level will be set such

that the ADC wi ll never see full sca le and the lowest gain

setting of the DVGA will not be used.

The total gain of the EDRCS Board, including both the

analog and digital part s is best des cribed by the e quation,

,(EQ. 11)

where the first term has already been introduced and the

others wil l be in su bsequent sections of this m anual.

DVGA

The DVGA is a 350MHz amplifier that has a digi-

tally-controlled voltage gain range from -12 to +30dB in

6dB steps. It has a 3rd-order output intercept po i nt of 24dB

at 150MHz and an output noise spectral density of

69 . At 150MHz, the data sheet plots place the

maximum gain at about 28.5dB or,

,(EQ. 12)

where is the 3-bit data word into the DVGA digi-

tal input of channel A. Refer to the CLC5526 data sheet

for further details.

The DVGA, in conjunction with the DDC/AGC, forms an

automatic leveling loop that compresses the dynamic

range of the input IF signal prior to sampling by the ADC.

By doing so, it extends the dynamic range of the ADC by

as much as 42dB. The loop dynamics and threshold of the

AGC are se t by programming the control registers with in

the CLC5903. It is also possible to inhibit the loop and

force specific DVGA gain values.

ADC

The ADC is a 12 bit, wideband converter capabl e of input s

as high as 300MHz at sample rates of 70MSPS. The SNR

for an input 3dB below the full scale input of 2V PP differ -

ential is 62dBFS at an IF frequency in the range of

150MHz. For levels much below this, however, the SNR

improves to 68dBFS (or, 55 at 52MSPS). This

behavior is due to the fact that the large-signal, high-fre-

quency SNR is dominated by clock jitter.

GSM systems typically require no more than 9dB of SNR

(C/I) which can be achieved at input levels of 59dB below

full scale. EDGE systems typically require 23dB SNR for

full rate operation. This requirement can be m et with an

input signal at -45dBFS, still low enough to minimize the

effects of clock jitter.

The ADC acts as though it were a 68dB device for these

systems (Figure 48). The digital filters following the ADC

provide processing gain that improve further upon this by

24dB (factory default configuration, 200kHz output BW).

Assuming that a single sampling imag e interferes at a level

of -4dB (Figure 7), the total noise voltage density at the

ADC input is,

.(EQ. 13)

When this is referred th rough the 33 .8dB maxim um gain

to the input connector, this yields a 13dB noise figure for

the EDRCS Board.

DDC

The ADC outputs feed into the two channel DDC/AGC.

This part consists of two down converter channels (DDC)

and automatic gain control (AG C) loops. The DDC per-

forms the final mix to baseband and baseband filtering

(see Figure 49).

The NCO can tune across the full Nyquist band with 32 bit

precision. With phase dither enabled, the spurious perfor-

mance is -101dBc or better and SNR is 84dBFS. The fre-

quency and phase of the two channels are completely

independent. In addition, the phase dither of the two are

uncorrelated.

Ω

GXFMR 2=

GTOTAL GXFMRGDVGAGLCGDDC

nV Hz⁄

GDVGA 0.21()2AGAIN

⋅=

AGAIN

nV Hz⁄

552692110

4–10

⁄

+()+98nV Hz⁄=

Figure 48 CLC5957 SNR Extrapolates to 68dBFS

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0

SNR (dBc)

Inpu t Ampli t ude (dB FS)

SNR vs. Input Amplitude

Extrapolates to 68dB

The baseband filtering is performed by a cascade of thr ee

decimating FIR filters. The overall decimation ratio can be

programmed from 8 to 16,384. The two final filters feature

21 and 63 channel- independ ent user-pro grammable taps,

respectively. Two independent sets of filter coefficients

can be selected via crossbar switch. A set of tap coeffi-

cients are published in the CLC5903 data sheet which pro-

vide adequate filtering to meet the GSM blocker and

interferer requirem ents. The f requency response for these

filters at a sample rate of 52MSPS is shown in Figure 50.

Although the AD C com bined with the pr ocessing ga in of

the digital filters provid es 92dB of instantaneous SNR,

this is not enough to meet the requirements of the

GSM900 specification without some analog filtering to

attenuate the blocker. Nonetheless, the digital filters can be

used to relax the requirements on the analog filter. In par-

ticular, the digital filte rs can meet the reference inte rfer-

ence level of ETSI GSM 05.05 paragraph 6.3 without any

assistance from the anal og filter. Further, the blocke r per-

formance of ETSI GSM 05.05 paragraph 5.1 can be met

with only minor assistance from the analog filter.

The FLOAT TO FIXED CONVE RTER within the DDC

will match any change in gain by the DVGA with a com-

pensating digital gain change. It does this by treating the

complement of the DVGA control word as an exponent to

the ADC output. The overall effect of this is to make the

EDRCS Board appear as a fixed gain channel with

extremely large dynamic range as shown in Figure 51.

This mode can also be inhibited by asserting (;3B,1+.

An expression for the gain through the DDC channel A is,

,(EQ. 14)

Figure 49 CLC5903 Digital Down Converter, Channel A

NCO

(

CIC FILTER

)5(4B$

3+$6(B$

SHIFT UP

)



(

)

F1 FILTER

)



(

)

F2 FILTER

DECIMATE BY

8 TO 2K

DECIMATE BY 2

DECIMATE BY

SHIFT UP

MUXA

2 OR 4

(



CONVERTER

TO FIXED

FLOAT

EXPONENT

EXP

(

;

EXP

OUTPUT

CIRCUIT

17 17

SAT & ROUND

SAT

SAT & ROUND

ROUND

SIN COS

(from AGC)

Figure 50 Frequency Response of GSM Filter Set

0100 200 300 400 500 600 700 800 900 1000

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Magnitude (dB)

GSM blocker and interferer

requirements

Frequency (kHz)

Figure 51 ADC and DDC Output Level vs. Input Level

Input Power

Output Power

DDC Output

ADC Output

AGC Operates

Over This Range

GDDC 1

---'(& 1+()

6&$/(

44–AGAIN 1

(;3

,1+

–

()⋅

–

[]

*$,1

GF1GF2

⋅

⋅⋅

,(EQ. 15)

.(EQ. 16)

The numerators of and equal the su ms of the

impulse response coefficients of F1 and F2, respectively.

For the STD and GSM sets, and are nearly equal

to unity. Observe that the term in (EQ. 14) is can -

celled by the corresponding term appearing in (EQ. 12) so

that the entire gain of the EDRCS Board is indepen dent of

the DVGA setting when (;3B,1+ . The appearing

in (EQ. 14) is the re sult of the 6dB conversion loss in the

mixer.

When the DVGA gain is changed, there is a delay before

the FLOAT TO FIXED CONVERTER is changed to mini-

mize the eff ect of the gain steps on the output signal. I n the

CLC5903 this delay is programmable to allow the use of

ADCs with more than three-clock pipeline delays.

AGC

The AGC loop for channel A is shown in Figure 52. Each

channel has its own loop. The ADC output power is mea-

sured with an envelope detector and used to adjust the

DVGA gain. Envelope detection is performed by an abso-

lute value circuit followed by a programmable lowpass fil-

ter whose response is shown in Figure 53. The filtered

signal i s used to address a lookup table whi ch generates an

error signal based on the programmed threshold, dead-

band, and loop time constant targets. This error is inte-

grated to produce the 3 bit control signal for the DVGA.

Integrator gain is programmable via the shifter preceding

it to allow loop time constants that can be varied by factors

of 2. Fractional control of time constan t can be achieved

by altering the slope of the transfer function stored within

the looku p tab le.

In the course of measuring ADC powe r, the absolute value

block withi n the enve lo pe det ector al so gene rate s a second

harmonic of the a liased IF frequency. For example, an IF

of 150MHz aliases to -6MHz at t he ADC output when the

sample rate is 52MHz. The absolute valu e block prod uces

from this a dc term and a second harmonic at -12MHz, the

latter of which is rejected by the low pass filter. If the alias

frequency is too low, though, its second harmonic wi ll fall

within the passband of the filter and a clean power detec-

tion will not occur . This problem can be avoided by choos-

ing the IF and sample rates such that the alias frequency

magnitude is greater than FCK/16.

The user interface software makes programming of the

AGC very ea sy. The user need only sp ecify the loop time

constant, reference, and deadband. The lookup table val-

ues and shifter values can then be computed. A Matlab

script which w ill calculate the AG C values is al so avail-

able upon request. As shown in Figure 54, deadband in

excess of 6dB shows up as hysteresis. Hysteresis will

GF1

h1i()

i1=

∑

216

----------------------=

GF2

h2i()

i1=

∑

216

----------------------=

GF1GF2

AGAIN

---

AGC_LOOP_GAIN

SHIFT DOWN

VALUE

ABSOLUTE

CONVERTER

TO FLOAT

FIXED

2 STA GE

32X8

SHIFT DOWN

16 5

MUX

812

AGC_HOLD_IC

-REF

LOG

FUNCTION PROGRAMMED

INTO RAM

AGC_IC_A

AIN[13:4] 9

DECIMATE BY 8

CIC FILTER

RAM

AGC_TABLE

AGAIN

Figure 52 CLC- ED RCS-PCASM AGC ci rcuit, Channel A

EXP

(from MUXA) 9

POST CIC

COMB FILTER

POUT

Figure 53 Power detector filter response, 52MHz

0 5 10 15 20 25 30 35 40 45 50

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

Frequency/MHz

Magnitude/dB

AGC Power Detection Filter: Amplitude Response

CIC

CIC + 1−tap Comb

CIC + 4−tap Comb

AGC_COMB_ORD=2

AGC_COMB_ORD=0

AGC_COMB_ORD=1

EDRCS Evaluation Board User’s Guide

CLC-EDRCS-PCASM

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT A UTHORIZED FOR USE AS CRITI CAL COMPONENTS IN LIFE SUPPO RT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF

NATIONAL SEMICONDUCTOR CORPORATIO N. As us ed herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surg ical implant into the body, or

(b) support or sustain life, and whose failure to perform

when properly used in accordance with instructions for use

provided in t he labeling, can be reasonably expected to re-

sult in a significant injury to the user.

2. A critical componen t is any co mpone nt of a life sup port de-

vice or system whose fai lure to perform can be reason ably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

National Semiconductor

Corporation National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

National Semiconductor

Japan Ltd.

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

www.national.com

Fax: +49 (0) 180-530 85 86

E-mail: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Francais Tel: +33 (0) 1 41 91 8790

Tel: 65-2544466

Fax: 65-2504466

Email: ap.support@nsc.com

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

eliminate excessive DVGA gain changes caused by

the input signal level dwellin g at a transition point.

The AGC c an either be allowed to fre e-run or se t to a

fixed gain. In free-run m ode , the loop is cl osed contin-

uously and the DVGA gain setting is constantly

updated in response to the signal level applied to the

board. This mode is suitable for most applications. The

default configur ation of the EDRCS Board and user

software allows the AGC to free-run.

By using the configuration registers, it is possible to

write the initial gain condition of the loop into the inte-

grator and hold a fixed AGC gain value. This tech-

nique can be used to aid in system verification and

debugging. Consult the CLC5903 data sheet for fur-

ther details.

Figure 54 Relationship between deadband and

hysteresis

DVGA Input Power

DVGA Output Power

Deadband

Hysteresis=Deadband-6dB

Reference

6dB