oO PRELIMINARY DATA SHEET unl N Z8E000 Totally Logical FEATURE-RICH Z8LUS OnE-TiME- PROGRAMMABLE MICROCONTROLLER FEATURES Part ROM RAM* Speed _ Each Bit Programmable as Push-Pull or Open- Number (Bytes) (Bytes) (MHz) Drain Z8E000 512 32 10 * General-Purpose Microcontroller Core Features All Instructions Execute in | us Instruction Cycle @ 10 MHz 512 x 8 On-Chip OTP EPROM Memory 32 x 8 General-Purpose Registers (SRAM) Four Vectored Hardware Interrupts with Fixed Priority Two Additional Software Interrupts Operating Speed: DC-10 MHz Six Addressing Modes: R, IR, X, D, RA, & IM Peripheral Features @ One 16-Bit Standard Timer 16-Bit Programmable Watch-Dog Timer (WDT) 13 Total Input/Output Pins One 8-Bit I/O Port (Port A) 1/O Bit Programmable One 5-Bit I/O Port (Port B) I/O Bit Programmable Includes Special Functionality: Stop-Mode Re- covery Input, Selectable Edge Interrupts Additional Features On-Chip Oscillator that Accepts XTAL, Ceramic Reso- nator, LC, or External Clock @ Programmable Options: EPROM Protect @ Power Reduction Modes: HALT Mode with Peripheral Units Active STOP Mode with all Functionality Shut Down CMOS/Technology Features @ Low-Power Consumption @ 3.5V to 5.5V Operating Range @ 0C to +70C 4.5V to 5.5V Operating Range @ 40C to +105C 18-Pin DIP, SOIC, and 20-Pin SSOP Packages. GENERAL DESCRIPTION ZiLOGs Z8E000 Microcontroller (MCU) is a One-Time Programmable (OTP) member of ZiLOGs single-chip Z8's MCU family. The Z8E000 allows easy software de- velopment, debug, and prototyping. For applications demanding powerful I/O capabilities, the Z8E000s dedicated input and output lines are grouped into two ports, and are configurable under software control. One 16-bit on-chip standard timer, offloads the system of administering real-time tasks such as counting/timing and I/O data communications. DS003600-Z8X1098Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG GENERAL DESCRIPTION (Continued) Power connections follow conventional descriptions be- Note: All signals with an overline, " are active Low. For ex- low: ample, B/W (WORD is active Low, only); B/W (BYTE is active Low, only). Connection Circuit Device Power Vec Vpp Ground GND Vss Vec GND XTAL RESET Lf Machine Timing lI & Inst. Control ALU | One 16-bit = , Std. Timer FLAG TCS OTP Prg. Memory Interrupt Control = if Register Pointer N Program an Counter RAM Register File P PortA Port B vO ! VO ! Figure 1. Functional Block Diagram 2 PRELIMINARY DS003600-Z8X1098Z8E000 ZiLOG Z8PLUS One-Time Programmable Microcontroller D7-0 AD9-0 MCU - AD9-0 ADDRESS J | MUX DATA ADDRESS AAD9-0 EPROM D7-0 MUX GENERATOR } AN] vo D/-0 } PoRT 4 ROM PROT OPTION BIT PGM + TEST 1 | MODE LOGIC a PGM ADCLR/Vpp ADCLK XTAL1 Figure 2. EPROM Programming Mode Block Diagram DS003600-Z8X1098 PRELIMINARYZ8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG PIN DESCRIPTION L/ PBi cj|1 18) PBO PB2 c I XTAL1 PB3 c rs XTAL2 PB4 rm Vss RESET | 18-PinDIPisoic Ly. PA7 1 PAO PA6 J pA PAS q ] pA? PAS G9 106 pa3 Figure 3. 18-Pin DIP/SOIC Pin Identification Table 1. 18-Pin DIP/SOIC Pin Assignments Standard Mode Pin # Symbol Function Direction 144 PB1-PB4 Port B, Pins 1,2,3,4 In/Output 5 RESET Reset Input 6-9 PA7PA4 Port A, Pins 7,6,5,4 In/Output 10-13 PA3-PAO Port A, Pins 3,2,1,0 In/Output 14 Vec Power Supply 15 Vss Ground 16 XTAL2 Crystal Oscillator Clock Output 17 XTAL1 Crystal Oscillator Clock Input 18 PBO Port B, Pin 0 In/Output 4 PRELIMINARY DS003600-Z8X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller _ PGM GND GND GND ADCLR/Vpp D7 D6 D5 D4 18 18-Pin DIP/SOIC 0 10 UUUUUUUOUD Figure 4. 18-Pin DIP/SOIC Pin Identification; ADCLK XTAL1 NC GND Vop DO D1 D2 D3 EPROM Programming Mode Table 2. 18-Pin DIP/SOIC Pin Assignments; EPROM Programmable Mode EPROM Programming Mode Pin # Symbol Function Direction 1 PGM Program Mode input 2-4 GND Ground 5 ADCLR/Vpp Clear Clock/Program Voltage Input 6-9 D7-D4 Data 7,6,5,4 In/Output 10-13 D3-D0 Data 3,2,1,0 In/Output 14 Vop Power Supply 15 GND Ground 16 NC No Connection 17 XTAL1 1 MHz Clock Input 18 ADCLK Address Clock Input DS003600-Z8X1098 PRELIMINARYZ8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG PIN DESCRIPTION (Continued) PB1 C1 20) PBO PB2 q mt XTALI PB3 XTAL2 PB4 cq Vss RESET = 20-Pin SSOP_Ss P Vcc NC o Onc PA7 G PAO PA6 PAI PAS G PA? PA4 qq 10 112 pa3 Figure 5. 20-Pin SSOP Pin Identification Table 3. 20-Pin SSOP Pin Assignments Standard Mode Pin # Symbol Function Direction 1-4 PB1-PB4 Port B, Pins 1,2,3,4 In/Output 5 RESET Reset Input 6 NC No Connection 7-10 PA7PA4 Port A, Pins 7,6,5,4 In/Output 11-14 PA3PA0O Port A, Pins 3,2,1,0 In/Output 15 NC No Connection 16 Vec Power Supply 17 Vss Ground 18 XTAL2 Crystal Oscillator Clock Output 19 XTAL1 Crystal Oscillator Clock Input 20 PBO Port B, Pin 0 In/Output 6 PRELIMINARY DS003600-28X1098Z8E000 ZiLOG Z8PLUS One-Time Programmable Microcontroller PGM 1 20 ADCLK GND OG - XTAL1 GND NC GND - GND ADCLR/Vpp 20-Pin SSOP I Vop NC I NC D7 1 DO D D1 D5 Oo - D2 D4 q 10 116 D3 Figure 6. 20-Pin SSOP Pin Identification; EPROM Programming Mode Table 4. 20-Pin SSOP Pin Assignments; EPROM Programming Mode EPROM Programming Mode Pin # Symbol Function Direction 1 PGM Program Mode Input 2-4 GND Ground 5 ADCLR/Vpp Clear Clock/Program Voltage Input 6 NC No Connection 7-10 D7-D4 Data 7,6,5,4 In/Output 11-14 D3-D0 Data 3,2,1,0 In/Output 15 NC No Connection 16 Vpp Power Supply 17 GND Ground 18 NC No Connection 19 XTAL1 1 MHz Clock Input 20 ADCLK Address Clock Input DS003600-28X1098 PRELIMINARYZ8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG ABSOLUTE MAXIMUM RATINGS Parameter Min Max Units Note Ambient Temperature under Bias -40 +105 Cc Storage Temperature -65 +150 Cc Voltage on any Pin with Respect to Vss -0.6 +7 Vv 1 Voltage on Vpp Pin with Respect to Vss 0.3 +7 Vv Voltage on RESET Pin with Respect to Vgs -0.6 Vopt1 Vv 2 Total Power Dissipation 880 mW Maximum Allowable Current out of Vss 80 mA Maximum Allowable Current into Vop 80 mA Maximum Allowable Current into an Input Pin -600 +600 mA 3 Maximum Allowable Current into an Open-Drain Pin -600 +600 mA 4 Maximum Allowable Output Current Sunk by Any I/O Pin 25 mA Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA Maximum Allowable Output Current Sunk by Port A 40 mA Maximum Allowable Output Current Sourced by Port A 40 mA Maximum Allowable Output Current Sunk by Port B 40 mA Maximum Allowable Output Current Sourced by Port B 40 mA Notes: 1. Applies to all pins except the RESET pin and where otherwise noted. 2. There is no input protection diode from pin to Vpp. 3. Excludes XTAL pins. 4. Device pin is not at an output Low state. Stresses greater than those listed under Absolute Maximum _ not exceed 880 mW for the package. Power dissipation is Ratings can cause permanent damage tothe device. Thisrat- calculated as follows: ing is a stress rating only. Functional operation of the device at any condition above those indicated in the operational Total Power Dissipation =Vpp x [Ipp (sum of lon)] sections of these specifications is not implied. Exposure to + sum of [(Vpp Vou) X lou absolute maximum rating conditions for an extended period can affect device reliability. Total power dissipation should + sum of (Vo, x lot) 8 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller STANDARD TEST CONDITIONS The characteristics listed below apply for standard test con- ditions as noted. All voltages are referenced to Ground. Pos- itive current flows into the referenced pin (Figure 7). From Output Under Test It 15 0pF Figure 7. Test Load Diagram CAPACITANCE Ta = 25C, Vec = GND = OV, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Min Max Input capacitance 0 12 pF Output capacitance 0 12 pF /O capacitance 0 12 pF DS003600-28X1098 PRELIMINARY 9Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG DC ELECTRICAL CHARACTERISTICS T, = 0C to +70C Typical Sym Parameter Voc" Min Max @ 25C? Units Conditions Notes Ven Clock Input High 3.5V 0.7Veg Vect0.3 1.3 V___ Driven by External Voltage Clock Generator 5.5V 0.7Vcco 3=Vect0.3 2.5 V___ Driven by External Clock Generator VeL Clock Input Low 3.5V Vgs-0.3 0.2Vec 0.7 V___ Driven by External Voltage Clock Generator 5.5V Vgs-0.3 0.2Vec 1.5 V___ Driven by External Clock Generator Vin Input High Voltage 3.5V 0.7Vec =Vect0.3 1.3 Vv 5.5V 0.7Vco = Vet 0.3 2.5 Vv Vit Input Low Voltage 3.5V Veg70-3 0.2V., 0.7 Vv 5.5V -V,.-0.3 0.2V., 1.5 Vv Von Output High Voltage 3.5V Voc 0-4 3.1 V lon =2.0mA 5.5V V0.4 48 Vi loy = 72-0 mA Vot1 Output Low Voltage 3.5V 0.6 0.2 Vv low =+4.0mA 5.5V 0.4 0.1 V1 = +4.0 mA Vot2 Output Low Voitage 3.5V 1.2 0.5 Vv low =+6 mA 5.5V 1.2 0.5 Vol, = +12 mA Veo Reset Input High 3.5V 0.5Vec Vec 1.1 Vv Voltage 55V. 05Vce Ver 2.2 V Var Reset Input Low 3.5V Vgs-0.3 0.2Vec 0.9 Vv Voltage 55V Vgg-0.3. 0.2Vog 1.4 Vv Mie Input Leakage 3.5V 1.0 2.0 0.064 WA V.=0V, Vo. 5.5V -1.0 2.0 0.064 WAV. =0V, Von lot Output Leakage 3.5V -1.0 2.0 0.114 WA V,=O0V,Vi, 5.5V -1.0 2.0 0.114 WA V.=0V.Ve. lir Reset Input Current 3.5V -10 -60 -30 MA 5.5V -20 -180 100 HA lee Supply Current 3.5V 2.5 2.0 mA @10MHz 3,4 5.5V 6.0 4.0 mA @ 10 MHz 3,4 leet Standby Current 3.5V 2.0 1.0 mA Halt Mode Vy = OV 3,4 Vec@1 0 MHz 5.5V 6.0 4.0 mA Halt Mode Vjy = OV 3,4 Vec@10 MHz 10 PRELIMINARY DS003600-Z28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller T,, = 0C to +70C Typical Sym ___ Parameter Voc" Min Max @ 25C? Units Conditions Notes loco Standby Current 3.5V 500 150 nA Stop Mode Vy = OV, 5 Vec 5.5V 500 250 nA Stop Mode Vix, = OV, 5 Vec Notes: 1. The Vec voltage specification of 3.5 V guarantees 3.5 V and the Vcc voltage specification of 5.5 V guarantees 5.0 V 0.5 V. 2. Typical values are measured at Voc = 3.3V and Vcc = 5.0V. 3. All outputs unloaded, I/O pins floating, and all inputs are at Vcc or Vs level. 4. CL1 = CL2 = 22 pF. 5. Same as note 3 except inputs at Vcc. DS003600-Z28X1098 PRELIMINARY 11Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG DC ELECTRICAL CHARACTERISTICS (Continued) Ta = 40C to +105C ' Typical Sym Parameter Veo Min Max @ 25C? Units Conditions Notes Vou Clock Input High 4.5V 0.7V V_+0.3 2.5 V_ Driven by External Clock cc cc Voltage Generator 5.5V 0.7 Voc Voc t0-3 2.5 V_ Driven by External Clock Generator Vor Clock Input Low 4.5V V..-0.3 0.2V 1.5 V__ Driven by External Clock Ss cc Voitage Generator 5.5V V0.3 0.2V 1.5 V__ Driven by External Clock Ss cc Generator Vin Input High Voitage 4.5V 0.7 Voc Voc t0-3 2.5 Vv 5.5V 0.7 Vig Voc t0.3 2.5 Vv V, Input Low Voltage 4.5V Vgg70-3 0.2Vi, 1.5 Vv 5.5V Vgg70:3 0.2V.. 1.5 Vv Von Output High Voltage 4.5V Voc70-4 4.8 Vv low =-2.0 mA 5.5V Voe70-4 48 Via, = 72:0 mA Vou Output Low Voltage 4.5V 0.4 0.1 Vv lo =+4.0mA 5.5V 0.4 0.1 Vly = +4.0 mA Voie Output Low Voltage 4.5V 1.2 0.5 V LoL =+12 mA, 5.5V 1.2 0.5 Vola = +12 mA, VrH Reset Input High 4.5V 0.5Vcc Vec 1.1 Vv Voltage 55V_0.5Vec Voc 2.2 V I Input Leakage 4.5V -1.0 2.0 <1.0 HA Vin = OV, Voc 5.5V -1.0 2.0 <1.0 HAV. = OV, Von lot Output Leakage 4.5V -1.0 2.0 <1.0 HA Vin = 0V, Voc 5.5V 1.0 2.0 <1.0 HAV = OV, Von lin Resetinput Current 4.5V -18 -180 112 mA 5.5V -18 -180 112 mA loc Supply Current 4.5V 7.0 4.0 mA @ 10 MHz 3,4 5.5V 7.0 4.0 mA @10 MHz 3,4 loca Standby Current 4.5V 2.0 1.0 mA HALT Mode V,, = OV, 3,4 Voc @ 10 MHz 5.5V 2.0 1.0 mA HALT Mode V,, = OV, 3,4 Voc @ 10 MHz 12 PRELIMINARY DS003600-Z8X1098Z8E000 ZiLOG Z8PLUS One-Time Programmable Microcontroller Ta = 40C to +105C 4 Typical Sym Parameter Voc Min Max @ 25C? Units Conditions Notes loco Standby Current 4.5V 700 250 nA STOP Mode Vin =0V, Voce 5 5.5V 700 250 nA STOP Mode Vin =0V, Voc 5 Notes: . The Vcc voltage specification of 4.5 V and 5.5 V guarantees 5.0 V 0.5 V. . Typical values are measured at Vcc = 3.3V and Voc = 5.0V. . All outputs unloaded, I/O pins floating, and all inputs are at Vcc or Vgg level. . CL1 = CL2 = 22 pF. . Same as note 3 except inputs at Vcc. ah whd = DS003600-Z28X1098 PRELIMINARY 13Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG AC ELECTRICAL CHARACTERISTICS IRQ, L ~<?- 5 | Figure 8. AC Electrical Timing Diagram Table 5. Additional Timings T= -40C to +105C @ 10 MHz No Symbol Parameter Vee" Min Max Units Notes 1 TpC Input Clock Period 3.5V 100 DC ns 2 5.5V 100 Dc ns 2 2 TrC, TIC Clock Input Rise and Fall Times 3.5V 15 ns 2 5.5V 15 ns 2 3 TwC Input Clock Width 3.5V 50 ns 2 5.5V 50 ns 2 4 TwiL Int. Request Input Low Time 3.5V 70 ns 2 5.5V 70 ns 2 5 TwlH Int. Request Input High Time 3.5V 5TpC 2 5.5V 5TpC 2 6 Twsm STOP Mode Recovery Width Spec. 3.5V 12 ns 5.5V 12 ns 7 Tost Oscillator Start-Up Time 3.5V 5TpC 5.5V 5TpC Notes: 1. The Vpp voltage specification of 3.5V guarantees 3.5V. The Vpp voltage specification of 5.5V guarantees 5.0V 0.5V. 2. Timing Reference uses 0.7 Vcc for a logic 1 and 0.2 Vc for a logic 0. 14 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller ZsPLUS CORE The Z8E000 is based on the ZiLOG Z8?"S Core Architec- ture. This core is capable of addressing up to 64K Bytes of program memory and 4KBytes of RAM. Register RAM is accessed as either 8- or 16-bit registers, using a combination of 4-, 8-, and 12-bit addressing modes. The architecture sup- ports up to 15 vectored interrupts from external and internal sources. The processor decodes 44 CISC instructions, using six addressing modes. See the Z8?!S Users Manual for more information. RESET This section describes the Z8E000 reset conditions, reset timing, and register initialization procedures. Reset is gen- erated by the Reset Pin, Watch-Dog Timer (WDT), and Stop-Mode Recovery (SMR). A system reset overrides all other operating conditions and puts the Z8E000 into a known state. To initialize the chips internal logic, the RESET input must be held Low for at least 30 XTAL clock cycles. The control registers and ports are reset to their default conditions after a reset from the RESET pin. The control registers and ports are not reset to their de- fault conditions after wakeup from Stop Mode or WDT tim- eout. During RESET, the program counter is loaded with 0020H. V/O ports and control registers are configured to their default reset state. Resetting the Z8E000 does not affect the con- tents of the general-purpose registers. RESET PIN OPERATION The Z8E000 hardware RESET pin initializes the control and peripheral registers, as indicated in Table 6. Specific reset values are indicated by | or 0, while bits whose states are unchanged are indicated by the letter U. RESET must first be held Low until the oscillator stabilizes. From than point, the pin then must be held for an additional 30 XTAL clock cycles to be sure that the internal reset is complete. The RESET pin has a Schmitt-Trigger input with atrip point. There is no High side protection diode. The user should place an external diode from RESET to Vcc. The internal pull-up resistor on the RESET pin is approximately 500 KQ, typical. Program execution starts 10 XTAL clock cycles after RE- SET has returned High. The initial instruction fetch is from location 0020H. Figure 9 indicates reset timing. After a reset, the first routine executed must be one that ini- tializes the TCTLHI control register to the required system configuration. This routine is then followed by initialization of the remaining control registers. Table 6. Control and Peripheral Register Reset Values Register Bits (HEX) Register Name 7 6 5 4 3 1 0 Comments FF Stack Pointer 0 0 U U U U U_ U Stack pointer is not affected by RESET FE Reserved FD Register Pointer U U U U O 0 0 O Register pointer is not affected by RESET FC Flags U U U U U U * * Only WDT & SMR flags are affected by RESET FB Interrupt Mask 0 0 0 0 0 0 0 O Allinterrupts masked by RESET FA Interrupt Request O 0 0 0 0 0 O O Allinterrupt requests cleared by RESET F9-FO Reserved EF-E0 Virtual Copy Virtual Copy of the Current Working Register Set DF-D8 Reserved D7 PortB Spec. Func. O 0 0 0 0 O O O Deactivates all port special functions after RESET D6 PortB Directional 0 0 0 0 0 0 O O Defines all bits as inputs in PortB after RESET Control D5 PortB Output U U U U U U U U Output register not affected by RESET DS003600-28X1098 PRELIMINARY 15Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG RESET PIN OPERATION (Continued) Table 6. Control and Peripheral Register Reset Values Register Bits (HEX) Register Name 7 6 5 4 3 2 1 =O Comments D4 PortB Input U U U U U U U_ U Current sample of the input pin following RESET D3 PortA Spec. Func. 0 0 0 0 0 0 0 O Deactivates all port special functions after RESET D2 _PortA Directional 0 0 0 0 0 0 0 O Defines all bits as inputs in PortA after RESET Control D1 PortA Output U U U U U U U_ U Output register not affected by RESET DO PortA Input U U U U U U U_ JU Current sample of the input pin following RESET CF Reserved CE Reserved CD Reserved CC Reserved CB T3VAL U UU U U UU U CA T2VAL U U UU U UU cg T3AR U U iU iU iU UU JU C8 T2AR U U Ui U Ui UU U C7 Reserved C6 Reserved C5 Reserved C4 Reserved C3 WDTHI 1 114 4 1 1 1 ~41 C2 WDTLO 1 114 47 14 1 1 C1 TCTLHI 1 #14 = #4 #4 ==1 = #0 OQ O WDT Enabled in HALT Mode, WDT timeout at maximum value, STOP Mode disabled Co TCTLLO 0 0 0 0 0 0 QO O Standard timer is disabled Note: *The SMR and WDT flags are set indicating the source of the RESET, as shown below: D1 DO Reset Source 0 RESET Pin 1 SMR Recovery 0 WDT Reset 1 Reserved -_ - Oo 16 PRELIMINARY DS003600-28X1098Z8E000 ZiLOG Z8PLUS One-Time Programmable Microcontroller First Machine Cycle ox LPL LLLP /L RESET oo iI Hold Low For 30 XTAL Periods (Minimum) tO XTAL CLOCK CYCLES a | | | lq First Instruction Fetch Figure 9. Reset Timing 100 KQ [ KQ [| | THF | Z8E000 Figure 10. Example of External Power-On Reset Circuit DS003600-Z28X1098 PRELIMINARY 17Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG RESET PIN OPERATION (Continued) TCTLHI D6,D5,D4 3 WDT TAP SELECT XTAL WDTRST _ 64 46-BITTIMER [2 WODTRST WATCH-DOG TIMER SMR (PBO) > SMR RECOVERY Figure 11. Z8E000 Reset Circuitry with WDT and SMR 18 PRELIMINARY DS003600-Z8X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller Z8E000 WATCH-DOG TIMER (WDT) The Watch-Dog Timer is a retriggerable one-shot 16-bit timer that resets the Z8E000 if it reaches its terminal count. The WDT is driven by the XTAL2 clock pin. To provide the longer timeout periods required in applications, the WDT is only updated every 64th clock cycle. When oper- ating in the RUN or HALT Modes, a WDT timeout reset is functionally equivalent to an interrupt vectoring the PC to 0020H and setting the WDT flag to a one state. Coming out of RESET, the WDT will be fully enabled with its timeout value set at the maximum value, unless otherwise pro- grammed during the first instruction. Subsequent execu- tions of the WDT instruction reinitialize the watch-dog tim- er registers (C2H and C3H) to their initial values as defined by bits D6, D5, and D4 of the TCTLHI register (Figure 12). The WDT cannot be disabled except on the first cycle after RESET, and if the device enters Stop mode. The WDT instruction should be executed often enough to provide some margin before allowing the WDT registers to get near 0. Because the WDT timeout periods are relatively long, a WDT reset will occur in the unlikely event that the WDT times out on exactly the same cycle that the WDT in- struction is executed. The WDT and SMR flags are the only flags that are affected by the external RESET pin. RESET clears both the WDT and SMR flags. A WDT timeout sets the WDT flag. The STOP instruction sets the SMR flag. This behavior enables software to determine whether a pin RESET occurred, whether a WDT timeout occurred, or whether a return from STOP Mode occurred. Reading the WDT flag does not reset it to zero. The user must clear the WDT flag via software. Failure to clear the WDT flag can result in undefined be- havior. DS003600-28X1098 PRELIMINARY 19Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG Z8E000 WATCH-DOG TIMER (WDT) (Continued) 0c1 TCTLHI D7 D6 D5 D4 D3 D2 D1 DO RESERVED (MUST BE 0) 0 = STOP MODE ENABLED 1 = STOP MODE DISABLED* D6 D5 D4 WDT TIMEOUT VALUE 0 DISABLED 1 65,536 TpC 0 131,072 TpC 1 262,144 TpC 0 524,288 TpC 1 0 1 1,048,576 TpC 2,097,152 TpC 4,194,304 TpC* (XTAL CLOCKS TO TIMEOUT) = 2 2 OOOO 1 = WDT ENABLED IN HALT MODE* 0 = WDT DISABLED IN HALT MODE * Designates Default Value after RESET Figure 12. Z8E000 TCTLHI Register for Control of WDT Table 7. Time-Out Period of the WDT Note: The WDT can only be disabled via software if the first instruction out of RESET performs this function. Logic within the Z8E000 will detect that it is in the process of Crystal Clocks Time-Out Using executing the first instruction after the part leaves RE- D6 D5 D4 _ to Timeout a10 MHz Crystal SET. During the execution of this instruction, the upper 0 0.60 OO Disabled Disabled five bits of the TCTLHI register can be written. After this 0 0 4 65,536 TpC 6.55 ms first instruction, hardware will not allow the upper five 0 7 0 131,072 TpC 43.11ms bits of this register to be written. 0 1 1 262,144 TpC 56.21 ms 1 0 0 524,288 TpC 52.43 ms The TCTLHI bits for control of the WDT are described be- 1 0 1 1,048,576 TpC 104.86 ms low: 1 1 0 2,097,152 TpC 209.72 ms 1 1 1 4,194,304 TpC 419.43 ms WDT Time Select (D6, D5, D4). Bits 6, 5, and 4 deter- Notes: mine the time-out period. Table 7 indicates the range of tim- TpC = XTAL clock cycle. eout values that can be obtained. The default values of D6, The default on reset is D6 = D5 = D4 = 1. D5, and D4 are all 1, thus setting the WDT to its maximum timeout period when coming out of RESET. 20 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller WDT During HALT (D7). This bit determines whether or not the WDT is active during HALT Mode. A 1 indicates active during HALT. A 0 prevents the WDT from reset- ting the part while halted.Coming out of reset, the WDT will be enabled during HALT Mode. STOP MODE (D3). Coming out of RESET, the Z8E000 will have the STOP Mode disabled. If an application re- quires use of STOP Mode, bit D3 must be cleared immedi- ately upon leaving RESET. If bit D3 is set, the STOP in- struction will execute as a NOP. If bit D3 is cleared, the STOP instruction will enter Stop Mode. Whenever the Z8E000 wakes up after having been in STOP Mode, the STOP Mode will be disabled once again. Bits 2, 1 and O. These bits are reserved and must be 0. POWER-DOWN MODES In addition to the standard RUN mode, the Z8E000 MCU supports two Power-Down modes to minimize device cur- rent consumption. The two modes supported are HALT and STOP. HALT MODE OPERATION The HALT Mode suspends instruction execution and tums offthe internal CPU clock. The on-chip oscillator circuit re- mains active, so the internal clock continues to run and is applied to the timers and interrupt logic. To enter the HALT Mode, the Z8E000 only requires a HALT instruction. It is NOT necessary to execute a NOP instruction immediately before the HALT instruction. 7F HALT : enter HALT Mode The HALT Mode can be exited by servicing an interrupt (ei- ther externally or internally). Upon completion of the in- terrupt service routine, the user program continues from the instruction after HALT. The HALT Mode can also be exited viaa RESET activation or a Watch-Dog Timer (WDT) timeout. In these cases, pro- gram execution will restart at the reset address 0020H. DS003600-28X1098 PRELIMINARY 21Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG STOP MODE OPERATION The STOP Mode provides the lowest possible device stand- by current. This instruction turns off the on-chip oscillator and internal system clock. To enter the STOP Mode, the Z8E000 only requires a STOP instruction. It is NOT necessary to execute a NOP instruc- tion immediately before the STOP instruction. 6F STOP ;enter STOP Mode The STOP Modeis exited by any one of the following resets: RESET pin or a STOP-Mode Recovery source. Upon reset generation, the processor will always restart the application program at address 0020H, thereby setting the STOP Mode Flag. Reading the STOP-Mode flag does not clear it. The user must clear the STOP-Mode flag with software. Note: Failure to clear the STOP-Mode flag can result in unde- fined behavior. The Z8E000 provides a dedicated STOP Mode Recovery (SMR) circuit. In this case, a low level applied to input pin PBO will trigger a SMR. To use this mode, pin PBO (I/O Port B, bit 0) must be configured as an input before the STOP Mode is entered. The low level on PBO must be held for a minimum pulse width Tywsyy, in addition to any oscil- lator startup time. Program execution starts at address 0020H after PBO is raised back to a high level. Notes: Use of the PBO input for the STOP mode recovery does not initialize the control registers. The STOP Mode current (Iccz) will be minimized when: * Vcc is at the low end of the devices operating range. * Output current sourcing is minimized. * All inputs (digital and analog) are at the Low or High rail voltages. CLOCK The Z8E000 MCU derives its timing from on-board clock circuitry connected to pins XTALI and XTAL2. The clock circuitry consists of an oscillator, a glitch filter, a divide- by-two shaping circuit, a divide-by-four shaping circuit, and a divide-by-eight shaping circuit. Figure 13 illustrates the clock circuitry. The oscillators input is XTAL] and its output is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock, or an external clock source. Filter (5 cycles per instruction) Machine i Clock xtaut [_} Glitch fae ee Clock WoT Clock Figure 13. Z8E000 Clock Circuit 22 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller OSCILLATOR OPERATION The Z8E000 MCU uses a Pierce oscillator with an internal feedback circuit (Figure 14). The advantages of this circuit are low cost, large output signal, low power level in the crys- tal, stability with respect to Vcc and temperature, and low impedances (not disturbed by stray effects). One draw back to the oscillator is the requirement for high gain in the amplifier to compensate for feedback path losses. The oscillator amplifies its own noise at start-up until it set- tles at the frequency that satisfies the gain/phase require- ments (A x B= 1, where A= V,/V; is the gain ofthe amplifier and B= V;/V, is the gain of the feedback element). The total phase shift around the loop is forced to zero (360 degrees). VIN must be in phase with itself. The amplifier/inverter thereby provides a | 80-degree phase shift, forcing the feed- back element to provide the other 180 degrees of phase shift. R, is a resistive component placed from output to input of the amplifier. The purpose of this feedback is to bias the am- plifier in its linear region and to provide the start-up tran- sition. Capacitor Cj, combined with the amplifier output resis- tance, provides a small phase shift. It will also provide some attenuation of overtones. Capacitor C), combined with the crystal resistance, pro- vides additional phase shift. C, and C, can affect the start-up time if they increase dra- matically in size. As C, and C) increase, the start-up time increases until the oscillator reaches a point where it does not start up any more. It is recommended for fast and reliable oscillator start-up (over the manufacturing process range) that the load capac- itors be sized as low as possible without resulting in over- tone operation. | | | | Vj Ri Vo | L WW | ~-- 4-4 XTAL1 Int XTAL2 iL = , = C, + Figure 14. Pierce Oscillator with Internal Feedback Circuit Layout Traces connecting crystal, caps, and the Z8E000 oscillator pins should be as short and wide as possible, to reduce par- asitic inductance and resistance. The components (caps, crystal, resistors) should be placed as close as possible to the oscillator pins of the Z8E000. The traces from the oscillator pins of the IC and the ground side of the lead caps should be guarded from all other traces (clock, Vcc, address/data lines, system ground) to reduce cross talk and noise injection. Guarding is usually accom- plished by keeping other traces and system ground trace planes away from the oscillator circuit, and by placing a Z8E000 device Vcg ground ring around the traces/compo- nents. The ground side of the oscillator lead caps should be connected to a single trace of the Z8E000 Veg (GND) pin. The ground side of these caps should not be shared with any other system ground trace or components except at the Z8E000 device Vg pin. The objective is to prevent differ- ential system ground noise injection into the oscillator (Fig- ure 15). Indications of an Unreliable Design There are two major indicators that are used in working de- signs to determine their reliability over full lot and temper- ature variations. They are: Start-up Time. If start-up time is excessive, or varies wide- ly from unit to unit, there is probably a gain problem. C, and C, require reduction ifthe amplifier gain is not adequate at frequency, or crystal Rs are too large. Output Level. The signal at the amplifier output should swing from ground to Vcc to indicate adequate gain in the amplifier. As the oscillator starts up, the signal amplitude grows until clipping occurs. At this point, the loop gain is effectively reduced to unity, and constant oscillation is achieved. A signal of less than 2.5 volts peak-to-peak is an indication that low gain can be a problem. Either C, or Cy should be made smaller or a low-resistance crystal should be used. Circuit Board Design Rules The following circuit board design rules are suggested: = To prevent induced noise, the crystal and load capacitors should be physically located as close to the Z8E000 as possible. @ Signal lines should not run parallel to the clock oscillator inputs. In particular, the crystal input circuitry and the in- ternal system clock output should be separated as much as possible. DS003600-28X1098 PRELIMINARY 23Z8E000 Z8PLUS One-Time Programmable Microcontroller OSCILLATOR OPERATION (Continued) Vcc power lines should be separated from the clock os- cillator input circuitry. _ xTaL1 [17] iI _l Cc Z8E000 Ca XTAL2 [16] | C2 Vss 1s} ______ Clock Generator Circuit Signals A B | 11 (Parallel Traces 1 | Must Be Avoided) II -- TM Signal C XTAL1 4 [__] z8e000 Mey to an I XTAL2 [16] 74 if tt ZiLOG Resistance between XTALI or XTAL2 and the other pins should be greater than 10 MQ. Z8E000 Board Design Example (Top View) Figure 15. Circuit Board Design Rules Crystals and Resonators Crystals and ceramic resonators (Figure 16) should have the following characteristics to ensure proper oscillator opera- tion: Crystal Cut AT (crystal only) Mode Parallel, Fundamental Mode Crystal Capacitance </pF Load Capacitance 10pF < CL < 220 pF, 15 typical Resistance 100 ohms max Depending on operation frequency, the oscillator can re- quire the addition of capacitors C, and C, (shown in Figure 17 and Figure 18). The capacitance values are dependent on the manufacturers crystal specifications. 24 PRELIMINARY DS003600-Z8X1098ZiLOG Vss Z8E000 XTAL2 es XTAL1 Figure 16. Crystal/Ceramic Resonator Oscillator XTAL1 | - Z8E000 Vss | XTAL2 Ll Figure 17. LC Clock In most cases, the Rp is zero ohms (0), and Ry is infinite. The set value is determined and specified by the crystal/ce- ramic resonator manufacturer. Rp can be increased to de- Z8E000 Z8PLUS One-Time Programmable Microcontroiler crease the amount of drive from the oscillator output to the crystal. Rp can also be used as an adjustment to avoid clip- ping of the oscillator signal to reduce noise. Rp can be used to improve the start-up of the crystal/ceramic resonator. The Z8E000 oscillator already has an internal shunt resistor in parallel to the crystal/ceramic resonator. >O| XTAL1 Z8E000 ss NIC XTAL2 Figure 18. External Clock Figure 16, Figure 17, and Figure 18 recommend that the load capacitor ground trace connect directly to the Veg (GND) pin of the Z8E000, thereby ensuring that no system noise is injected into the Z8E000 clock. This trace should not be shared with any other components except at the Veg pin of the Z8E000. Note: A parallel resonant crystal or resonator data sheet will specify a load capacitor value that is the series combina- tion of C, and C3, including all parasitics (PCB and hold- er). DS003600-28X1098 PRELIMINARY 25Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG LC OSCILLATOR The Z8E000 oscillator can use a LC network to generate a XTAL clock (Figure 18). The frequency stays stable over Vcc and temperature. The oscillation frequency is determined by the equation: 1 Frequency = = ________ 2n (LCz) "2 where L is the total inductance including parasitics and Cy is the total series capacitance including the parasitics. Simple series capacitance is calculated using the following equation: 41 Cy = 1/C, + 1/C> If C, = Co W/Cry =2 C, C, =2 Cy A sample calculation of capacitance C, and C> for 5.83- MHz frequency and inductance value of 27 uH is illustrated as follows: 5.83(10%)= | 2m [2.7 (10) Cy] 1/2 Cy = 27.6 pf Thus C, = 55.2 pf and C, = 55.2 pf. TIMERS Two 8-bit timers (T2 and T3), are provided but can only op- erate in cascade to function as a 16-bit standard timer (Fig- ure 19). ENABLE TCTLLO (D5) oy ad osc 18 16-bit DOWN COUNTER p> IRQS (123) i i T3VAL T3AR 16-bit Standard Timer T2AR T2VAL GG a Internal Data Bus Figure 19. Timer Block Diagram 26 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller oco TCTLLO D7 D6 D5 D4 D3 D2 D1 DO RESERVED (MUST BE 0) RESERVED (MUST BE 0) 1 = 723 16-BIT TIMER ENABLED WITH AUTO-RELOAD ACTIVE 0 = T2 AND T3 TIMERS DISABLED RESERVED (MUST BE 0) Note: Timer T23 is a standard 16-bit timer formed by cascading 8-bit timers t3(msb) and t2(Isb). Figure 20. TCTLLO Register Each 8-bit timer is equipped with a pair of readable and writ- able registers, which are both readable and writable. One of the registers is defined to contain the auto-initialization value for the timer, while the second register contains the current value for the timer. When a timer is enabled, the tim- er will decrement whatever value is currently held in its count register. From that point, the timer continues decre- menting until it reaches 0, at which time an interrupt will be generated and the contents of the auto-initialization reg- ister are optionally copied into the count value register. If auto-initialization is not enabled, the timer will stop count- ing upon reaching 0, and control logic will clear the appro- priate control register bit to disable the timer. This operation is referred to as a single-shot. If auto-initialization is en- abled, the timer will continue counting from the initializa- tion value. Software should not attempt to use registers that are defined as having timer functionality for any other pur- pose. Software is allowed to write to any register at any time, but care should be taken if timer registers are updated while the timer is enabled. If software updates the count value while the timer is in operation, the timer will continue counting based upon the software-updated value. Strange behavior can result ifthe software update occurred at exactly the point that the timer was reaching 0 to trigger an interrupt and/or reload. Similarly, if software updates the initialization value reg- ister while the timer is active, the next time that the timer reaches 0, it will be initialized using the updated value. Again, strange behavior could result ifthe initialization val- ue register is being written while the timer is in the process of being initialized. Whether initialization is done with the new or old value is a function of the exact timing of the write operation. In all cases, the Z8E000 will prioritize the soft- ware write above that of a decrementer writeback. Howev- DS003600-28X1098 PRELIMINARY 27Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG TIMERS (Continued) er, when hardware clears a control register bit for a timer that is configured for single-shot operation, the clearing of the control bit will override a software write. Reading either register can be done at any time, and will have no effect on the functionality of the timer. When defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. In this case, a single interrupt will be generated, and the in- terrupt will correspond to the even 8-bit timer. For example, timers T2 and T3 are cascaded to form a single 16-bit timer, so the interrupt for the combined timer will be defined to be that of timer T2 rather than T3 (Figure 20). When a timer pair is specified to act as a single 16-bit timer, the even timer registers in the pair (timer T2) will be defined to hold the timers least significant byte. Conversely, the odd timer in the pair (timer T3) will hold the timers most significant byte. In parallel with the posting of the interrupt request, the in- terrupting timers count value will be initialized by copying the contents of the auto-initialization value register to the count value register. Note: Any time that a timer pair is defined to act as a single 16- bit timer, the auto-reload function will be performed au- tomatically. All 16-bit timers will continue counting while their interrupt requests are active, and will operate in a free-running manner. If interrupts are disabled for a long period of time, it is pos- sible for the timer to decrement to 0 again before its initial interrupt has been responded to. This condition is termed a degenerate case, and hardware is not required to detect it. When the timer control register is written, all timers that are enabled by the write will begin counting using the value that is held in their count register. In this case, an auto-initial- ization is not performed. All timers can receive an internal clock source only. Each timer that is enabled will be updated every 8th XTAL clock cycle. 28 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller RESET CONDITIONS After a hardware RESET, the timers are disabled. See Table 5 for timer control, value, and auto-initialization register status after RESET. (0 PORTS The Z8E000 has 13 lines dedicated to input and output. These lines are grouped into two ports known as Port A and Port B. Port A is an 8-bit port that is bit-programmable as either inputs or outputs. Port B can be programmed to pro- vide standard input/output or the following special func- tions: SMR input and external interrupt inputs. All ports have push-pull CMOS outputs. In addition, the outputs of Port A, on a bit-wise basis, can be configured for open-drain operation. As such, the register values for / at a given bit position only affect the bit in question. Each port is defined by a set of four control registers. See Figure 21. Directional Control and Special Function Registers Each port on the Z8E000 has an associated and dedicated Directional Control Register that determines on a bit-wise basis whether a given port bit will operate as an input or as an output. Each port on the Z8E000 has a Special Function Register that, in conjunction with the directional control register, im- plements on a bit-wise basis, and supports special function- ality that can be defined for each particular port bit. Input and Output Value Registers Each port has an Output Value Register and an Input Value Register. For port bits configured as an input by means of the Directional Control Register, the Input Value Register for that bit position will contain the current synchronized input value. REGISTER ADDRESS !DENTIFIER Port B SPECIAL FUNCTION 0D7H PTBSFR Port B DIRECTIONAL CONTROL} OD6H PTBDIR Port B OUTPUT VALUE OD5H PTBOUT Port B INPUT VALUE 0D4H ~C~PTIN Port A SPECIAL FUNCTION OD3H PTASFR Port A DIRECTIONAL CONTROL] 0D2H PTADIR Port A OUTPUT VALUE OD1H PTAOUT Port A INPUT VALUE ODOH PTAIN Figure 21. Z8E000 I/O Ports Registers For port bits configured as an output by means of the Di- rectional Control Register, the value held in the correspond- ing bit of the Output Value Register is driven directly onto the output pin. The opposite register bit for a given pin (the output register bit for an input pin and the input register bit for an output pin) will hold their previous value. They will not be changed by hardware nor will they have any effect on the hardware. DS003600-Z8X1098 PRELIMINARY 29Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG READ/WRITE OPERATIONS The control for each port is done on a bit-wise basis. All bits are capable of operating as inputs or outputs, depending upon the setting of the ports directional control register. If configured as an input, each bit is provided a Schmitt-trig- ger. The output of the Schmitt-trigger is latched twice to per- form a synchronization function, while the output of the synchronizer is fed to the port input register, which can be read by software. A write to a port input register has the effect of updating the contents of the input register, but subsequent reads will not necessarily return the same value that was written. If the bit in question is defined as an input, the input register for that bit position will contain the current synchronized input value. Thus, writes to that bit position will be overwritten on the next clock cycle with the newly sampled input data. However, if the particular port bit is programmed as an out- put, the input register for that bit will retain the software- updated value. The port bits that are programmed as outputs do not sample the value being driven out. Any bit in either port can be defined as an output by setting the appropriate bit in the directional control register. If such is the case, the value held in the appropriate bit of the port output register is driven directly onto the output pin. Note: The above result does not necessarily reflect the actual output value. If an external error is holding an output pin either High or Low against the output driver, the soft- ware read will return the required value, not the actual state caused by the contention. When a bit is defined as an output, the Schmitt-trigger on the input will be dis- abled to save power. Updates to the output register will take effect based upon the timing of the internal instruction pipeline; however, this timing is referenced to the rising edge of the clock. The out- put register can be read at any time, and will return the cur- rent output value that is held. No restrictions are placed on the timing of reads and/or writes to any of the port registers with respect to the others, but care should be taken when updating the directional control and special function regis- ters. When updating a directional control register, the special function register should first be disabled. If this precaution is not taken, spurious events could take place as a result of the change in port I/O status. This precaution is especially important when defining changes in Port B, as the spurious event referred to above could be one or more interrupts. Clearing of the SFR register should be the first step in con- figuring the port, and setting the SFR register should be the final step in the port configuration process. To ensure de- terministic behavior, the SFR register should not be written until the pins are being driven appropriately and all initial- ization has been completed. 30 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller PORTA Port A isa general-purpose port (Figure 23). Each of its lines can be independently programmed as input or output via the Port A Directional Control Register (PTADIR at 0D2H) as seen in Figure 22. A bit set toa 1 in PTADIR configures the corresponding bit in Port A as an output, while a bit cleared to 0 configures the corresponding bit in Port A as an input. The input buffers are Schmitt-triggered. Bits programmed as outputs can be individually programmed as either push- pull or open drain by setting the corresponding bit in the Special Function Register (PTASFR, Figure 27.) PTASFR.DbitN N =0...7 PTADIR.bitN N=0...7 PTAIN.bitN N =0...7 Register OD2H PTADIR Register [D7 |D6|D5]D4]D3]D2]D1] Do] | 1 = Output 0 = Input Figure 22. Port A Directional Control Register PAO-PA7 PIN Figure 23. Port A Configuration with Open-Drain Capability and Schmitt-Trigger DS003600-28X1098 PRELIMINARY 31Z8E000 Z8PLUS One-Time Programmable Microcontroller PORT A REGISTER DEFINITIONS Register ODOH PTAIN D7 D6 D5 D4 D3 D2 D1 DO Register OD1H Figure 24. Port A Input Value Register PTAOUT D7 D6 D5 D4 D3 D2 D1 DO ZiLOG PORT A BIT N CURRENT INPUT VALUE {only updated for pins in input mode) PORT A BIT N CURRENT OUTPUT VALUE Figure 25. Port A Output Value Register 32 PRELIMINARY DS003600-28X1098Z8E000 ZiLOG Z8PLUS One-Time Programmable Microcontroller Register 0D2H PTADIR D7 D6 D5 D4 D3 D2 D1 DO 1 = BIT N SET AS AN OUTPUT 0 = BIT N SET AS AN INPUT Figure 26. Port A Directional Control Register Register OD3H PTASFR D7 D6 D5 D4 D3 D2 D1 DO 1 = BIT NIN OPEN-DRAIN MODE 0 = BIT N IN PUSH-PULL MODE Figure 27. Port A Special Function Register DS003600-Z8X1098 PRELIMINARY 33Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG PORT B Port B Description Table 8. Port B Special Functions Port B is a 5-bit, bidirectional, CMOS-compatible I/O port. Input Special Output Special These five I/O lines can be configured under software con- Port Pin Function Function trol to be an input or output, independently. Input buffers PBO Stop Mode R N are Schmitt-triggered. See Figure 29 through Figure 33 for oP ecovery one . ; Input diagrams of all five Port B pins. PB4 None None In addition to standard input/output capability on all five PB2 IRQ3 None pins of Port B, each pin provides special functionality as in- PB3 None None dicated in Table 8: PB4 IRQ1/IRQ4 None Special functionality is invoked via the Port B Special Func- tion Register. See Figure 28 for the arrangement and control conventions for this register. Register OD7H PTBSER D7 D6 D5 D4 D3 D2 D1 DO ENABLE PBO AS SMR INPUT NO SPECIAL FUNCTIONALITY RESERVED (MUST BE 0) 1 0 ENABLE PB2 AS IRQ3 INPUT NO SPECIAL FUNCTIONALITY RESERVED (MUST BE 0) PB4 Interrupts Enabled PB4 Interrupts Disabled RESERVED (MUST BE 0) Figure 28. Port B Special Function Register 34 PRELIMINARY DS003600-28X1098Z8E000 ZiLOG Z8PLUS One-Time Programmable Microcontroller PORT BPIN 0 CONFIGURATION PTBDIR.bitO PTBIN.bitO SMR RESET PTBSFR.bitO SMR Flag PTBDIR.bitO PTBOUT.bit0 Figure 29. Port B Pin 0 Diagram DS003600-28X1098 PRELIMINARY 35Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG PORT BPIN 1 CONFIGURATION PTBDIR.bit1 PTBIN.bit1 IT PTBDIR bit1 ~~ | ono PBI _e__| PIN PTBOUT.bit1 o ) et Figure 30. Port B Pin 1 Diagram 36 PRELIMINARY DS003600-Z8X1098Z8E000 ZiLOG Z8PLUS One-Time Programmable Microcontroller PORT BPIN 2 CONFIGURATION PTBDIR.bit2 PTBIN.bit2 | IRQ3 a EDGE DETECT LOGIC id PTBSFR bit? PTBDIR.bit2 PB2 PIN PTBOUT.bit2 e ) ot Figure 31. Port B Pin 2 Diagram DS003600-28X1098 PRELIMINARY 37Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG PORT BPINS 3 AND 4 CONFIGURATION PTBDIR.bit4 be, PTBIN.bit4 NX oe EDGE DETECT LOGIC S/S fF PTBSFR.bit4 PTBDIR.bit3 D5, PTBIN.bit3 QI] PTBDIR.bit3 Don PB3 b PIN PTBOUT.bit3 | ) eh 17 PTBDIR.bit4 d PB4 PIN PTBOUT.bit4 ) OF Figure 32. Port B Pins 3 and 4 Diagram 38 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller PORT B CONTROL REGISTER DEFINITIONS PORT B BIT N CURRENT INPUT VALUE (only updated for pins in input mode) RESERVED (MUST BE 0) PORT B BIT N CURRENT OUTPUT VALUE RESERVED (MUST BE 0) Register 0D4H PTBIN D7 D6 D5 D4 D3 D2 D1 DO Figure 33. Port B Input Value Register Register OD5H PTBOUT D7 D6 D5 D4 D3 D2 D1 DO Figure 34. Port B Output Value Register Register OD6H PTBDIR D7 D6 D5 D4 D3 D2 D1 DO 1 = BIT N SET AS OUTPUT 0=BITN SET AS INPUT RESERVED (MUST BE 0) Figure 35. Port B Directional Control Register DS003600-Z28X1098 PRELIMINARY 39Z8E000 Z8PLUS One-Time Programmable Microcontroller PORT B CONTROL REGISTER DEFINITIONS (Continued) Register 0D7H PTBSFR D7 D6 D5 D4 D3 D2 D1 DO ZiLOG 1 = ENABLE PBO AS SMR INPUT 0 = NO SPECIAL FUNCTIONALITY RESERVED (MUST BE 0) 1 = ENABLE PB2 AS IRQ3 INPUT 0 =NO SPECIAL FUNCTIONALITY RESERVED (MUST BE 0) 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled RESERVED (MUST BE 0) Figure 36. Port B Special Function Register 40 PRELIMINARY DS003600-28X1098ZiLOG (0 PORT RESET CONDITIONS Full Reset Port A and Port B output value registers are not affected by RESET. On RESET, the Port A and Port B directional control reg- isters will be cleared to all zeros, which will define all pins in both ports as inputs. On RESET, the directional control registers redefine all pins as inputs, and the Port A and Port B input value registers Z8E000 Z8PLUS One-Time Programmable Microcontroller will overwrite the previously held data with the current sam- ple of the input pins. On RESET, the Port A and Port B special function registers will be cleared to all zeros, which will deactivate all port special functions. Note: The SMR and WDT timeout events are NOT full device resets. None of the port control registers is affected by ei- ther of these events. INPUT PROTECTION All I/O pins on the Z8E000 have diode input protection. There is a diode from the I/O pad to Vcc and to Vos. See Figure 37. PIN Vss Figure 37. /O Pin Diode Input Protection However, on the Z8E000, the RESET pin has only the input protection diode from the pad to Vg. See Figure 38. Vss Figure 38. RESET Pin Input Protection The High-side input protection diode was removed on this pin to allow the application of high voltage during the OTP programming mode. For better noise immunity in applications that are exposed to system EMI, a clamping diode to Vcec from this pin is required to prevent entering the OTP programming mode, or to prevent high voltage from damaging this pin. DS003600-28X1098 PRELIMINARY 41Z8E000 Z8PLUS One-Time Programmable Microcontroller ZiLOG PACKAGE INFORMATION ; , sympa. |_MILLIMETER INCH Oooo ooo MIN MAX MIN MAX j Al os! | 081 020 032 q Et a2 325 | 3.43 128 135 | B 038 | 053 | O15 021 Uo UU CU to Us ty Co 6 1 BL 14 165 | 045 | 065 E oe3 | o38 | ooo | 15 D 22.35 [23.37 | sae | 920 E 7.62 | 813 300 320 C EL 622 | 648 | 245 | 255 a | 254 TYP 100 TYP ea eA 787 | ae9 | 310 350 L 318 | 3.81 125 150 al use | 165 | 060 065 S aso | 165 | 035 | .065 4 1 5 fc Qi C Ae 4 CONTROLLING DIMENSIONS + INCH | L Al -o4 s 3] B Figure 39. 18-Pin DIP Package Diagram D ~ c MILLIMETER INCH SYMBOL T | 9 ' MIN MAX MIN | MAX oF : H H Fj cms J A | 240 | 2.65 | 0.094 0.104 7 eet ee Al 0.10 0.30 | 0.004 | 0.012 i az 2.24 244 | 0.088 | 0.096 | | | 8 0.36 0.46 0.014 0.018 la : c 0.23 0.30 | 0.009 | 0.012 H \ | D 11.40 11.75 | 0.449 | 0.463 i 7.40 7.60 0.291 | 0.299 ' @ 1.27 TYP 0.050 TYP TT H 10.00 | 10.65 | 0.394 | 0.419 Hl I H H H H H H \ h 0.30 0.50 | 0.012 | 0.020 10 18 DETAIL A 7 L 0.60 1.00 | 0.024 0,039 Qi 0.97 1.07 | 0.038 | 0,042 a i t f a2 TE tA d T ft CONTROLLING DIMENSIONS : MM re LEADS ARE COPLANAR WITHIN .004 INCH. at | ig) -h- B ~ SEATING PLANE 0-8. DETAIL A Figure 40. 18-Pin SOIC Package Diagram 42 PRELIMINARY DS003600-2Z8X1098ZiLOG i ABRRARAAAR O SU BUHED EHH 10 Qi Z8E000 Z8PLUS One-Time Programmable Microcontroller DETAIL A Pte dhe ~ 4 i 2 CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH. A pt SEATING PLANE 4 A Te DETAIL A oeob SYMBOL MILLIMETER INCH MIN NOM MAX MIN NOM MAX A 1.73 1.85 1.98 0.068 0.073 0.078 At 0.05 0.13 0.21 0.002 0.005 0.008 A2 1.68 1.73 1.83 0.066 0.068 0.072 8 0.25 0.30 0.38 0.010 0.012 0.015 c 0.13 0.15 0.22 0.005 0,006 0.009 D 7.07 7.20 7.33 0.278 0.283 0.289 E 5.20 5.30 5.38 0.205 0.209 0.212 a 0.65 TYP 0.0256 TYP H 7.65 7,80 7,90 0.301 0.307 0.311 L 0.56 0.75 0.94 0.022 0.030 0.037 Qt 0.74 0.78 0.82 0.029 0.031 0.032 Figure 41. 20-Pin SSOP Package Diagram DS003600-Z8X1098 PRELIMINARY 43Z8E000 Z8PLUS One-Time Programmable Microcontroller ORDERING INFORMATION Standard Temperature 18-Pin DIP 18-Pin SOIC 20-Pin SSOP Z8E00010PSC Z8E00010SSC Z8E00010HSC Extended Temperature 18-Pin DIP 18-Pin SOIC 20-Pin SSOP Z8E00010PEC Z8E00010SEC Z8E00010HEC For fast results, contact your local ZiLOG sales office for assistance in ordering the part(s) required. Codes Preferred Package P = Plastic DIP Longer Lead Time S$ = SOIC H = SSOP Preferred Temperature S=0C to +70C E =-40C to +105C Speed 10 = 10 MHz Environmental C = Plastic Standard Example: Z 8E000 10 PSC is a Z86E000, 10 MHz, DIP, 0 to +70C, Plastic Standard Flow L_ Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix ZiLOG 44 PRELIMINARY DS003600-28X1098ZiLOG Z8E000 Z8PLUS One-Time Programmable Microcontroller Pre-Characterization Product: The product represented by this data sheet is newly introduced and ZiLOG has not completed the full characterization of the product. The data sheet states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects of the data sheet may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. 1998 by ZiLOG, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of ZiLOG, Inc. The information in this doc- ument is subject to change without notice. Devices sold by ZiLOG, Inc. are covered by warranty and patent indemnification provisions appearing in ZiLOG, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATU- TORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTEL- LECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FIT- NESS FOR ANY PURPOSE. ZiLOG, Inc. shall not be responsible for any errors that may appear in this document. ZiLOG, Inc. makes no commitment to update or keep current the information contained in this document. ZiLOGs products are not authorized for use as critical components in life support devices or systems unless a specific written agree- ment pertaining to such intended use is executed between the cus- tomer and ZiLOG prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. ZiLOG, Inc. 910 East Hamilton Avenue, Suite 110 Campbell, CA 95008 Telephone: (408) 558-8500 FAX: (408) 558-8300 Internet: http://www.ZiLOG.com DS003600-Z28X1098 PRELIMINARY 45