Dual 8-/10-/12-/14-/16-Bit
250 MSPS Digital-to-Analog Converters
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
High dynamic range, dual DACs
Low noise and intermodulation distortion
Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF
Innovative switching output stage permits useable outputs
beyond Nyquist frequency
LVCMOS inputs with dual-port or optional interleaved
single-port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, Pb-free, 72-Lead LFCSP
APPLICATIONS
Wireless infrastructure:
WCDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications:
LMDS/MMDS, point-to-point
Instrumentation:
RF signal generators, arbitrary waveform generators
GENERAL DESCRIPTION
The AD9741/AD9743/AD9745/AD9746/AD9747 are pin-
compatible, high dynamic range, dual digital-to-analog
converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions
and sample rates of up to 250 MSPS. The devices include
specific features for direct conversion transmit applications,
including gain and offset compensation, and they interface
seamlessly with analog quadrature modulators, such as the
ADL5370.
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. In addition, some pin-programmable
features are offered for those applications without a controller.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enables
high quality synthesis of wideband signals.
2. Proprietary switching output for enhanced dynamic
performance.
3. Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
FUNCTIONAL BLOCK DIAGRAM
16-BIT
DAC1
16-BIT
DAC2
INTERFACE LOGIC
GAIN
DAC
GAIN
DAC
OFFSET
DAC
OFFSET
DAC
INTERNAL
REFERENCE
AND
BIAS
REFIO
FSADJ
SERIAL
PERIPHERAL
INTERFACE
SDO
SDIO
SCLK
CSB
10
CMOS
INTERFACE
CLKP
CLKN
PID<15:0>
P2D<15:0>
IOUT1P
IOUT1N
IOUT2P
IOUT2N
AUX1P
AUX1N
AUX2P
AUX2N
06569-001
Figure 1.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Digital and Timing Specifications.............................................. 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Serial Peripheral Interface ......................................................... 18
General Operation of the Serial Interface ............................... 18
Instruction Byte.......................................................................... 18
MSB/LSB Transfers .................................................................... 19
Serial Interface Port Pin Descriptions..................................... 19
SPI Register Map ............................................................................ 20
SPI Register Descriptions .............................................................. 21
Digital Inputs and Outputs ........................................................... 22
Input Data Timing ..................................................................... 22
Dual-Port Mode Timing ........................................................... 22
Single-Port Mode Timing ......................................................... 22
SPI Port, Reset, and Pin Mode.................................................. 22
Driving the DAC Clock Input .................................................. 23
Full-Scale Current Generation ................................................. 23
DAC Transfer Function ............................................................. 24
Analog Modes of Operation ..................................................... 24
Auxiliary DACS .......................................................................... 25
Power Dissipation....................................................................... 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
5/07—Revision 0: Initial Version
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 3 of 28
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 1. AD9741, AD9743, and AD9745
AD9741 AD9743 AD9745
Parameter Min Typ Max Min Typ Max Min Typ Max
Unit
RESOLUTION 8 10 12 Bits
ACCURACY
Differential Nonlinearity (DNL) ±0.03 ±0.05 ±0.13 LSB
Integral Nonlinearity (INL) ±0.05 ±0.10 ±0.25 LSB
MAIN DAC OUTPUTS
Offset Error ±0.001 ±0.001 ±0.001 %FSR
Offset Error Temperature Coefficient 1.0 1.0 1.0 ppm/°C
Gain Error ±2.0 ±2.0 ±2.0 %FSR
Gain Error Temperature Coefficient 100 100 100 ppm/°C
Gain Matching (DAC1 to DAC2) ±1.0 ±1.0 ±1.0 %FSR
Full-Scale Output Current 8.6 31.7 8.6 31.7 8.6 31.7 mA
Output Compliance Voltage −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V
Output Resistance 10 10 10 MΩ
AUXILIARY DAC OUTPUTS
Resolution 10 10 10 Bits
Full-Scale Output Current −2.0 +2.0 −2.0 +2.0 −2.0 +2.0 mA
Output Compliance Voltage Range—Sink Current 0.8 1.6 0.8 1.6 0.8 1.6 V
Output Compliance Voltage Range—Source Current 0 1.6 0 1.6 0 1.6 V
Output Resistance 1 1 1 MΩ
Monotonicity 10 10 10 Bits
REFERENCE INPUT/OUTPUT
Output Voltage 1.2 1.2 1.2 V
Output Voltage Temperature Coefficient 10 10 10 ppm/°C
External Input Voltage Range 1.15 1.3 1.15 1.3 1.15 1.3 V
Input or Output Resistance 5 5 5 kΩ
POWER SUPPLY VOLTAGES
AVDD33, DVDD33 3.13 3.47 3.13 3.47 3.13 3.47 V
CVDD18, DVDD18 1.70 1.90 1.70 1.90 1.70 1.90 V
POWER SUPPLY CURRENTS
IAVDD33 56 60 56 60 56 60 mA
IDVDD33 10 14 10 14 11 15 mA
ICVDD18 18 22 18 22 18 22 mA
IDVDD18 28 32 29 33 30 34 mA
POWER DISSIPATION
fDAC = 250 MSPS, fOUT = 20 MHz 300 345 300 345 305 350 mW
DAC Outputs Disabled 115 115 120 mW
Full Device Power-Down 3 3 3 mW
OPERATING TEMPERATURE −40 +85 −40 +85 −40 +85 °C
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 4 of 28
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted. The AD9745 is repeated in Table 2 so the user can compare it with all other parts.
Table 2. AD9745, AD9746, and AD9747
AD9745 AD9746 AD9747
Parameter Min Typ Max Min Typ Max Min Typ Max
Unit
RESOLUTION 12 14 16 Bits
ACCURACY
Differential Nonlinearity (DNL) ±0.13 ±0.5 ±2.0 LSB
Integral Nonlinearity (INL) ±0.25 ±1.0 ±4.0 LSB
MAIN DAC OUTPUTS
Offset Error ±0.001 ±0.001 ±0.001 %FSR
Offset Error Temperature Coefficient 0.1 0.1 0.1 ppm/°C
Gain Error ±2.0 ±2.0 ±2.0 %FSR
Gain Error Temperature Coefficient 100 100 100 ppm/°C
Gain Matching (DAC1 to DAC2) ±1.0 ±1.0 ±1.0 %FSR
Full-Scale Output Current 8.6 31.7 8.6 31.7 8.6 31.7 mA
Output Compliance Voltage −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V
Output Resistance 10 10 10 MΩ
AUXILIARY DAC OUTPUTS
Resolution 10 10 10 Bits
Full-Scale Output Current −2.0 +2.0 −2.0 +2.0 −2.0 +2.0 mA
Output Compliance Voltage Range—Sink Current 0.8 1.6 0.8 1.6 0.8 1.6 V
Output Compliance Voltage Range—Source Current 0 1.6 0 1.6 0 1.6 V
Output Resistance 1 1 1 MΩ
Monotonicity 10 10 10 Bits
REFERENCE INPUT/OUTPUT
Output Voltage 1.2 1.2 1.2 V
Output Voltage Temperature Coefficient 10 10 10 ppm/°C
External Input Voltage Range 1.15 1.3 1.15 1.3 1.15 1.3 V
Input or Output Resistance 5 5 5 kΩ
POWER SUPPLY VOLTAGES
AVDD33, DVDD33 3.13 3.47 3.13 3.47 3.13 3.47 V
CVDD18, DVDD18 1.70 1.90 1.70 1.90 1.70 1.90 V
POWER SUPPLY CURRENTS
IAVDD33 56 60 56 60 56 60 mA
IDVDD33 11 15 12 16 12 16 mA
ICVDD18 18 22 18 22 18 22 mA
IDVDD18 30 34 31 35 32 36 mA
POWER DISSIPATION
fDAC = 250 MSPS, fOUT = 20 MHz 305 350 310 355 310 355 mW
DAC Outputs Disabled 120 125 125 mW
Full Device Power-Down 3 3 3 mW
OPERATING TEMPERATURE −40 +85 −40 +85 −40 +85 °C
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 5 of 28
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 3. AD9741, AD9743, and AD9745
AD9741 AD9743 AD9745
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 250 MSPS, fOUT = 20 MHz 70 80 82 dBc
fDAC = 250 MSPS, fOUT = 70 MHz 70 70 70 dBc
fDAC = 250 MSPS, fOUT = 180 MHz1 64 64 66 dBc
INTERMODULATION DISTORTION (IMD)
fDAC = 250 MSPS, fOUT = 20 MHz 80 80 86 dBc
fDAC = 250 MSPS, fOUT = 70 MHz 80 80 80 dBc
fDAC = 250 MSPS, fOUT = 180 MHz1 72 72 74 dBc
CROSSTALK
fDAC = 250 MSPS, fOUT = 20 MHz 80 80 80 dBc
fDAC = 250 MSPS, fOUT = 70 MHz 80 80 80 dBc
fDAC = 250 MSPS, fOUT = 180 MHz1 80 80 80 dBc
ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE
CARRIER WCDMA
fDAC = 245.76 MSPS, fOUT = 15.36 MHz 54 66 76 dBc
fDAC = 245.76 MSPS, fOUT = 61.44 MHz 54 66 76 dBc
fDAC = 245.76 MSPS, fOUT = 184.32 MHz1 54 64 72 dBc
NOISE SPECTRAL DENSITY (NSD)
fDAC = 245.76 MSPS, fOUT = 15.36 MHz −132 −144 −155 dBm/Hz
fDAC = 245.76 MSPS, fOUT = 61.44 MHz −132 −144 −155 dBm/Hz
fDAC = 245.76 MSPS, fOUT = 184.32 MHz1 −135 −147 −155 dBm/Hz
1 Mix Mode.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 6 of 28
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted. The AD9745 is repeated in Table 4 so the user can compare it with all other parts.
Table 4. AD9745, AD9746, and AD9747
AD9745 AD9746 AD9747
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 250 MSPS, fOUT = 20 MHz 82 82 82 dBc
fDAC = 250 MSPS, fOUT = 70 MHz 70 70 70 dBc
fDAC = 250 MSPS, fOUT = 180 MHz1 66 66 66 dBc
INTERMODULATION DISTORTION (IMD)
fDAC = 250 MSPS, fOUT = 20 MHz 86 86 86 dBc
fDAC = 250 MSPS, fOUT = 70 MHz 80 80 80 dBc
fDAC = 250 MSPS, fOUT = 180 MHz1 74 74 74 dBc
CROSSTALK
fDAC = 250 MSPS, fOUT = 20 MHz 80 80 80 dBc
fDAC = 250 MSPS, fOUT = 70 MHz 80 80 80 dBc
fDAC = 250 MSPS, fOUT = 180 MHz1 80 80 80 dBc
ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE
CARRIER WCDMA
fDAC = 245.76 MSPS, fOUT = 15.36 MHz 76 78 82 dBc
fDAC = 245.76 MSPS, fOUT = 61.44 MHz 76 78 80 dBc
fDAC = 245.76 MSPS, fOUT = 184.32 MHz1 72 74 74 dBc
NOISE SPECTRAL DENSITY (NSD)
fDAC = 245.76 MSPS, fOUT = 15.36 MHz −155 −163 −165 dBm/Hz
fDAC = 245.76 MSPS, fOUT = 61.44 MHz −155 −160 −162 dBm/Hz
fDAC = 245.76 MSPS, fOUT = 184.32 MHz1 −155 −158 −160 dBm/Hz
1 Mix Mode.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 7 of 28
DIGITAL AND TIMING SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 5. AD9741/AD9743/AD9745/AD9746/AD9747
Parameter Min Typ Max Unit
DAC CLOCK INPUTS (CLKP, CLKN)
Differential Peak-to-Peak Voltage 400 800 1600 mV
Single-Ended Peak-to-Peak Voltage 800 mV
Common-Mode Voltage 300 400 500 mV
Input Current 1 μA
Input Frequency 250 MHz
DATA CLOCK OUTPUT (DCO)
Output Voltage High 2.4 V
Output Voltage Low 0.4 V
Output Current 10 mA
DAC Clock to Data Clock Output Delay (tDCO) 2.0 2.2 2.8 ns
DATA PORT INPUTS
Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current 1 μA
Data to DAC Clock Setup Time (tDBS Dual-Port Mode) 400 ps
Data to DAC Clock Hold Time (tDBH Dual-Port Mode) 1200 ps
DAC Clock to Analog Output Data Latency (Dual-Port Mode) 7 Cycles
Data or IQSEL Input to DAC Clock Setup Time (tDBS Single-Port Mode) 400 ps
Data or IQSEL Input to DAC Clock Hold Time (tDBH Single-Port Mode) 1200 ps
DAC Clock to Analog Output Data Latency (Single-Port Mode) 8 Cycles
SERIAL PERIPHERAL INTERFACE
SCLK Frequency (fSCLK) 40 MHz
SCLK Pulse Width High (tPWH) 10 ns
SCLK Pulse Width Low (tPWL) 10 ns
CSB to SCLK Setup Time (tS) 1 ns
CSB to SCLK Hold Time (tH) 0 ns
SDIO to SCLK Setup Time (tDS) 1 ns
SDIO to SCLK Hold Time (tDH) 0 ns
SCLK to SDIO/SDO Data Valid Time (tDV) 1 ns
RESET Pulse Width High 10 ns
WAKE-UP TIME AND OUTPUT LATENCY
From DAC Outputs Disabled 200 μs
From Full Device Power-Down 1200 μs
DAC Clock to Analog Output Latency (Dual-Port Mode) 7 Cycles
DAC Clock to Analog Output Latency (Single-Port Mode) 8 Cycles
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
With
Respect to Rating
AVDD33, DVDD33 AVSS DVSS
CVSS
−0.3 V to +3.6 V
DVDD18, CVDD18 AVSS DVSS
CVSS
−0.3 V to +1.98 V
AVSS DVSS CVSS −0.3 V to +0.3 V
DVSS AVSS CVSS −0.3 V to +0.3 V
CVSS AVSS DVSS −0.3 V to +0.3 V
REFIO AVSS −0.3 V to AVDD33 + 0.3 V
IOUT1P, IOUT1N, IOUT2P,
IOUT2P, AUX1P, AUX1N,
AUX2P, AUX2N
AVSS −1.0 V to AVDD33 + 0.3 V
P1D15 to P1D0,
P2D15 to P2D0
DVSS −0.3 V to DVDD33 + 0.3 V
CLKP, CLKN CVSS −0.3 V to CVDD18 + 0.3 V
RESET, CSB, SCLK, SDIO, SDO DVSS –0.3 V to DVDD33 + 0.3 V
Junction Temperature 125°C
Storage Temperature −65°C to +150°C
THERMAL RESISTANCE
Thermal resistance tested using JEDEC standard 4-layer
thermal test board with no airflow.
Table 7.
Package Type θJA Unit
CP-72-1 (Exposed Pad Soldered to PCB) 25 °C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
P1D7
P1D6
P1D5
P1D4
P1D3
P1D2
P1D1
P1D0
17NC
18NC
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
NC
NC
NC
NC
NC
NC
DCO
NC
DVDD33
DVSS
IQSEL
NC
P2D7
P2D6
P2D5
P2D4
35P2D3
36P2D2
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FSADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
NC
NC
NC
NC
NC
NC
NC
P2D0
P2D1
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
NC = NO CONNECT
06569-006
PIN 1
INDICATOR
AD9741
(TOP VIEW)
Figure 2. AD9741 Pin Configuration
Table 8. AD 9741 Pin Function Descriptions
Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Common (0 V).
3 CLKP Differential DAC Clock Input.
4 CLKN Complementary Differential DAC Clock Input.
7, 28, 48 DVSS Digital Supply Common (0 V).
8, 47 DVDD18 Digital Core Supply Voltage (1.8 V).
9 to 16 P1D<7:0> Port 1 Data Bit Inputs.
17 to 24, 26, 30, 39 to 46 NC No Connect.
25 DCO Data Clock Output. Use to clock data source.
27 DVDD33 Digital I/O Supply Voltage (3.3 V).
29 IQSEL I/Q Framing Signal for Single-Port Mode Operation.
31 to 38 P2D<7:0> Port 2 Data Bit Inputs.
49 SDO Serial Peripheral Interface Data Output.
50 SDIO Serial Peripheral Interface Data Input and Optional Data Output.
51 SCLK Serial Peripheral Interface Clock Input.
52 CSB Serial Peripheral Interface Chip Select Input. Active low.
53 RESET Hardware Reset. Active high.
54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS.
55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS.
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V).
59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1.
60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0.
62 AUX2P Auxiliary DAC2 Default Current Output Pin.
63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI.
65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI.
66 AUX1P Auxiliary DAC1 Default Current Output Pin.
68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0.
69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1.
EPAD AVSS
Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical
stability and must be electrically tied to low impedance GND plane for low noise performance.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 10 of 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
P1D9
P1D8
P1D7
P1D6
P1D5
P1D4
P1D3
P1D2
17P1D1
18P1D0
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
NC
NC
NC
NC
NC
NC
DCO
NC
DVDD33
DVSS
IQSEL
NC
P2D9
P2D8
P2D7
P2D6
35P2D5
36P2D4
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FSADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
NC
NC
NC
NC
NC
P2D0
P2D1
P2D2
P2D3
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
NC = NO CONNECT
06569-005
PIN 1
INDICATOR
AD9743
(TOP VIEW)
Figure 3. AD9743 Pin Configuration
Table 9. AD 9743 Pin Function Descriptions
Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Common (0 V).
3 CLKP Differential DAC Clock Input.
4 CLKN Complementary Differential DAC Clock Input.
7, 28, 48 DVSS Digital Supply Common (0 V).
8, 47 DVDD18 Digital Core Supply Voltage (1.8 V).
9 to 18 P1D<9:0> Port 1 Data Bit Inputs.
19 to 24, 26, 30, 41 to 46 NC No Connect.
25 DCO Data Clock Output. Use to clock data source.
27 DVDD33 Digital I/O Supply Voltage (3.3 V).
29 IQSEL I/Q Framing Signal for Single-Port Mode Operation.
31 to 40 P2D<9:0> Port 2 Data Bit Inputs.
49 SDO Serial Peripheral Interface Data Output.
50 SDIO Serial Peripheral Interface Data Input and Optional Data Output.
51 SCLK Serial Peripheral Interface Clock Input.
52 CSB Serial Peripheral Interface Chip Select Input. Active low.
53 RESET Hardware Reset. Active high.
54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS.
55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS.
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V).
59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1.
60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0.
62 AUX2P Auxiliary DAC2 Default Current Output Pin.
63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI.
65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI.
66 AUX1P Auxiliary DAC1 Default Current Output Pin.
68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0.
69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1.
EPAD AVSS
Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical
stability and must be electrically tied to low impedance GND plane for low noise performance.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 11 of 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
P1D11
P1D10
P1D9
P1D8
P1D7
P1D6
P1D5
P1D4
17P1D3
18P1D2
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P1D1
P1D0
NC
NC
NC
NC
DCO
NC
DVDD33
DVSS
IQSEL
NC
P2D11
P2D10
P2D9
P2D8
35P2D7
36P2D6
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FSADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
NC
NC
NC
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
NC = NO CONNECT
06569-004
PIN 1
INDICATOR
AD9745
(TOP VIEW)
Figure 4. AD9745 Pin Configuration
Table 10. AD9745 Pin Function Descriptions
Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Common (0 V).
3 CLKP Differential DAC Clock Input.
4 CLKN Complementary Differential DAC Clock Input.
7, 28, 48 DVSS Digital Supply Common (0 V).
8, 47 DVDD18 Digital Core Supply Voltage (1.8 V).
9 to 20 P1D<11:0> Port 1 Data Bit Inputs.
21 to 24, 26, 30, 43 to 46 NC No Connect.
25 DCO Data Clock Output. Use to clock data source.
27 DVDD33 Digital I/O Supply Voltage (3.3 V).
29 IQSEL I/Q Framing Signal for Single-Port Mode Operation.
31 to 42 P2D<11:0> Port 2 Data Bit Inputs.
49 SDO Serial Peripheral Interface Data Output.
50 SDIO Serial Peripheral Interface Data Input and Optional Data Output.
51 SCLK Serial Peripheral Interface Clock Input.
52 CSB Serial Peripheral Interface Chip Select Input. Active low.
53 RESET Hardware Reset. Active high.
54 FSADJ Full-Scale Current Output Adjust. Connect 10 kΩ resistor to AVSS.
55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS.
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V).
59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1.
60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0.
62 AUX2P Auxiliary DAC2 Default Current Output Pin.
63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI.
65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI.
66 AUX1P Auxiliary DAC1 Default Current Output Pin.
68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0.
69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1.
EPAD AVSS
Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical
stability and must be electrically tied to low impedance GND plane for low noise performance.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 12 of 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
P1D13
P1D12
P1D11
P1D10
P1D9
P1D8
P1D7
P1D6
17P1D5
18P1D4
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P1D3
P1D2
P1D1
P1D0
NC
NC
DCO
NC
DVDD33
DVSS
IQSEL
NC
P2D13
P2D12
P2D11
P2D10
35P2D9
36P2D8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FSADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
NC
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
P2D7
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
NC = NO CONNECT
06569-003
PIN 1
INDICATOR
AD9746
(TOP VIEW)
Figure 5. AD9746 Pin Configuration
Table 11. AD9746 Pin Function Descriptions
Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Common (0 V).
3 CLKP Differential DAC Clock Input.
4 CLKN Complementary Differential DAC Clock Input.
7, 28, 48 DVSS Digital Supply Common (0 V).
8, 47 DVDD18 Digital Core Supply Voltage (1.8 V).
9 to 22 P1D<13:0> Port 1 Data Bit Inputs.
23, 24, 26, 30, 45, 46 NC No Connect.
25 DCO Data Clock Output. Use to clock data source.
27 DVDD33 Digital I/O Supply Voltage (3.3 V).
29 IQSEL I/Q Framing Signal for Single-Port Mode Operation.
31 to 44 P2D<13:0> Port 2 Data Bit Inputs.
49 SDO Serial Peripheral Interface Data Output.
50 SDIO Serial Peripheral Interface Data Input and Optional Data Output.
51 SCLK Serial Peripheral Interface Clock Input.
52 CSB Serial Peripheral Interface Chip Select Input. Active low.
53 RESET Hardware Reset. Active high.
54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS.
55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS.
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V).
59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1.
60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0.
62 AUX2P Auxiliary DAC2 Default Current Output Pin.
63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI.
65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI.
66 AUX1P Auxiliary DAC1 Default Current Output Pin.
68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0.
69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1.
EPAD AVSS
Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability
and must be electrically tied to low impedance GND plane for low noise performance.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 13 of 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
P1D15
P1D14
P1D13
P1D12
P1D11
P1D10
P1D9
P1D8
17P1D7
18P1D6
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P1D5
P1D4
P1D3
P1D2
P1D1
P1D0
DCO
NC
DVDD33
DVSS
IQSEL
NC
P2D15
P2D14
P2D13
P2D12
35P2D11
36P2D10
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FSADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
P2D7
P2D8
P2D9
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
NC = NO CONNECT
06569-002
PIN 1
INDICATOR
AD9747
(TOP VIEW)
Figure 6. AD9747 Pin Configuration
Table 12. AD9747 Pin Function Descriptions
Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Common (0 V).
3 CLKP Differential DAC Clock Input.
4 CLKN Complementary Differential DAC Clock Input.
7, 28, 48 DVSS Digital Supply Common (0 V).
8, 47 DVDD18 Digital Core Supply Voltage (1.8 V).
9 to 24 P1D<15:0> Port 1 Data Bit Inputs.
25 DCO Data Clock Output. Use to clock data source.
26, 30 NC No Connect.
27 DVDD33 Digital I/O Supply Voltage (3.3 V).
29 IQSEL I/Q Framing Signal for Single-Port Mode Operation.
31 to 46 P2D<15:0> Port 2 Data Bit Inputs.
49 SDO Serial Peripheral Interface Data Output.
50 SDIO Serial Peripheral Interface Data Input and Optional Data Output.
51 SCLK Serial Peripheral Interface Clock Input.
52 CSB Serial Peripheral Interface Chip Select Input. Active low.
53 RESET Hardware Reset. Active high.
54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS.
55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS.
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V).
59 IOUT2P DAC2 Current Output. Sources full-scale current when input data bits are all 1.
60 IOUT2N Complementary DAC2 Current Output. Sources full-scale current when data bits are all 0.
62 AUX2P Auxiliary DAC2 Default Current Output Pin.
63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI.
65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI.
66 AUX1P Auxiliary DAC1 Default Current Output Pin.
68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0.
69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1.
EPAD AVSS Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical
stability and must be electrically tied to low impedance GND plane for low noise performance.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 14 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
40
50
60
70
80
90
100
0 20406080100120
250MSPS
125MSPS
06569-007
f
OUT
(MHz)
SFDR (dBc)
Figure 7. AD9747 SFDR vs. fOUT, Normal Mode
150 175 200 225
40
50
60
70
80
90
100
125 250
06569-008
f
OUT
(MHz)
SFDR (dBc)
Figure 8. AD9747 SFDR vs. fOUT, Mix Mode, 250 MSPS
60
65
70
75
80
85
90
50 100 150 200
0 250
06569-009
f
OUT (MHz)
ACLR (dBc)
NORMAL MODE
MIX MODE
Figure 9. AD9747 ACLR vs. fOUT, Single Carrier WCDMA, 245.76 MSPS
40
50
60
70
80
90
100
0 20406080100120
250MSPS
06569-010
f
OUT (MHz)
IMD (dBc)
125MSPS
Figure 10. AD9747 IMD vs. fOUT, Normal Mode
150 175 200 225
40
50
60
70
80
90
100
125 250
06569-011
f
OUT
(MHz)
IMD (dBc)
Figure 11. AD9747 IMD vs. fOUT, Mix Mode, 250 MSPS
–168
–166
–164
–162
–160
–158
–156
–154
–
152
50 100 150 200
02
06569-012
f
OUT
(MHz)
NSD (dBm/Hz)
50
NORMAL MODE
MIX MODE
Figure 12. AD9747 NSD vs. fOUT, Single Carrier WCDMA, 245.76 MSPS
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 15 of 28
30mAFS
40
50
60
70
80
90
100
0 20 40 60 80 100 120
06569-036
f
OUT
(MHz)
SFDR (dBc)
10mAFS
20mAFS
Figure 13. AD9747 SFDR vs. Analog Output, 250 MSPS
–3dBFS
40
50
60
70
80
90
100
0 20 40 60 80 100 120
06569-037
f
IN
(MHz)
SFDR (dBc)
–6dBFS
0dBFS
Figure 14. AD9747 SFDR vs. Digital Input, 250 MSPS
60
65
70
75
80
85
90
10 20 30 40 50 60 70 80 90 100 110
RANGE OF POSSIBLE SFDR
PERFORMANCE IS DEPENDENT ON
INPUT DATA TIMING RELATIVE TO
THE DAC CLOCK. SEE INPUT DATA
TIMING SECTION.
06569-038
f
OUT
(MHz)
SFDR (dBc)
Figure 15. AD9747 SFDR vs. fOUT Over Input Data Timing
10mAFS
20mAFS
30mAFS
40
50
60
70
80
90
100
0 20406080100120
06569-039
f
OUT
(MHz)
IMD (dBc)
Figure 16. AD9747 IMD vs. Analog Output, 250 MSPS
0dBFS
–3dBFS
40
50
60
70
80
90
100
0 20406080100120
06569-040
f
IN
(MHz)
IMD (dBc)
–6dBFS
Figure 17. AD9747 IMD vs. Digital Input, 250 MSPS
f
OUT
(MHz)
60
65
70
75
80
85
90
20 30 40 50 60 70 80 90 100 11010
06569-041
IMD (dBc)
RANGE OF IMD PERFORMANCE IS
ESSENTIALLY INDEPENDENT OF
INPUT DATA TIMING RELATIVE TO
THE DAC CLOCK. SEE INPUT DATA
TIMING SECTION.
Figure 18. AD9747 IMD vs. fOUT Over Input Data Timing
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 16 of 28
–5
–4
–3
–2
–1
0
1
25 75 125 175 22550 100 150 2000 250
06569-042
f
OUT
(MHz)
A
OUT
(dBm)
NORMAL MODE
MIX MODE
–165
–160
–155
–150
–145
–140
–135
–
130
AD9747AD9746AD9745AD9743AD9741
06569-044
NSD (dBm/Hz)
Figure 19. Nominal Power in the Fundamental, IFS = 20 mA Figure 21. NSD vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS, fCARRIER
fCARRIER = 61.44 MHz
50
55
60
65
70
75
80
85
AD9747AD9746AD9745AD9743AD9741
06569-043
ACLR (dBc)
Figure 20. ACLR vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS,
fCARRIER = 61.44 MHz
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 17 of 28
TERMINOLOGY
Integral Nonlinearity (INL)
The maximum deviation of the actual analog output from the
ideal output, as determined by a straight line drawn from zero
scale to full scale.
Differential Nonlinearity (DNL)
A measure of the maximum deviation in analog output associated
with any single value change in the digital input code relative to
an ideal LSB.
Monotonicity
A DAC is monotonic if the analog output increases or remains
constant in response to an increase in the digital input.
Offset Error
The deviation of the output current from the ideal zero-scale
current. For differential outputs, 0 mA is expected at IOUTP when
all inputs are low, and 0 mA is expected at IOUTN when all inputs
are high.
Gain Error
The deviation of the output current from the ideal full-scale
current. Actual full-scale output current is determined by
subtracting the output (when all inputs are low) from the
output (when all inputs are high).
Output Compliance Range
The range of allowable voltage seen by the analog output of a
current output DAC. Operation beyond the compliance limits
may cause output stage saturation and/or a breakdown resulting
in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change in a
parameter from ambient temperature (25°C) to either TMIN
or TMAX and is typically reported as ppm/°C.
Spurious-Free Dynamic Range (SFDR)
The difference in decibels between the peak amplitude of a test
tone and the peak amplitude of the largest spurious signal over
the specified bandwidth.
Intermodulation Distortion (IMD)
The difference in decibels between the maximum peak ampli-
tude of two test tones and the maximum peak amplitude of
the distortion products created from the sum or difference of
integer multiples of the test tones.
Adjacent Channel Leakage Ratio (ACLR)
The ratio between the measured power of a wideband signal
within a channel relative to the measured power in an empty
adjacent channel.
Noise Spectral Density (NSD)
The measured noise power over a 1 Hz bandwidth seen at the
analog output.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 18 of 28
THEORY OF OPERATION
The AD9741/AD9743/AD9745/AD9746/AD9747 combine
many features to make them very attractive for wired and
wireless communications systems. The dual DAC architecture
facilitates easy interfacing to common quadrature modulators
when designing single sideband transmitters. In addition, the
speed and performance of the devices allow wider bandwidths
and more carriers to be synthesized than in previously available
products.
All features and options are software programmable through
the SPI port.
SERIAL PERIPHERAL INTERFACE
AD9747
SPI
PORT
SDO
SDIO
SCLK
CSB
0
6569-013
Figure 22. SPI Port
The SPI port is a flexible, synchronous serial communications
port allowing easy interfacing to many industry-standard
microcontrollers and microprocessors. The port is compatible
with most synchronous transfer formats including both the
Motorola SPI and Intel® SSR protocols.
The interface allows read and write access to all registers that
configure the AD9741/AD9743/AD9745/AD9746/AD9747.
Single or multiple byte transfers are supported as well as MSB-
first or LSB-first transfer formats. Serial data input/output can
be accomplished through a single bidirectional pin (SDIO) or
through two unidirectional pins (SDIO/SDO).
The serial port configuration is controlled by Register 0x00,
Bits<7:6>. It is important to note that any change made to the
serial port configuration occurs immediately upon writing to
the last bit of this byte. Therefore, it is possible with a multibyte
transfer to write to this register and change the configuration in
the middle of a communication cycle. Care must be taken to
compensate for the new configuration within the remaining
bytes of the current communication cycle.
Use of a single-byte transfer when changing the serial port
configuration is recommended to prevent unexpected device
behavior.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to any communication cycle with the
AD9741/AD9743/AD9745/AD9746/AD9747: Phase 1 and
Phase 2. Phase 1 is the instruction cycle, which writes an
instruction byte into the device. This byte provides the serial
port controller with information regarding Phase 2 of the
communication cycle: the data transfer cycle.
The Phase 1 instruction byte defines whether the upcoming
data transfer is read or write, the number of bytes in the data
transfer, and a reference register address for the first byte of the
data transfer. A logic high on the CSB pin followed by a logic
low resets the SPI port to its initial state and defines the start
of the instruction cycle. From this point, the next eight rising
SCLK edges define the eight bits of the instruction byte for the
current communication cycle.
The remaining SCLK edges are for Phase 2 of the communication
cycle, which is the data transfer between the serial port control-
ler and the system controller. Phase 2 can be a transfer of 1, 2, 3,
or 4 data bytes as determined by the instruction byte. Using
multibyte transfers is usually preferred although single-byte
data transfers are useful to reduce CPU overhead or when only
a single register access is required.
All serial port data is transferred to and from the device in syn-
chronization with the SCLK pin. Input data is always latched
on the rising edge of SCLK whereas output data is always valid
after the falling edge of SCLK. Register contents change imme-
diately upon writing to the last bit of each transfer byte.
When synchronization is lost, the device has the ability to
asynchronously terminate an I/O operation whenever the CSB
pin is taken to logic high. Any unwritten register content data is
lost if the I/O operation is aborted. Taking CSB low then resets the
serial port controller and restarts the communication cycle.
INSTRUCTION BYTE
The instruction byte contains the information shown in the
following bit map.
MSB LSB
B7 B6 B5 B4 B3 B2 B1 B0
R/W N1 N0 A4 A3 A2 A1 A0
Bit 7, R/W, determines whether a read or a write data transfer
occurs after the instruction byte write. Logic high indicates a
read operation. Logic 0 indicates a write operation.
Bits<6:5>, N1 and N0, determine the number of bytes to be
transferred during the data transfer cycle. The bits decode as
shown in Table 13.
Table 13. Byte Transfer Count
N1 N0 Description
0 0 Transfer one byte
0 1 Transfer two bytes
1 0 Transfer three bytes
1 1 Transfer four bytes
Bits<4:0>, A4, A3, A2, A1, and A0, determine which register is
accessed during the data transfer of the communications cycle.
For multibyte transfers, this address is a starting or ending
address depending on the current data transfer mode. For MSB-
first format, the specified address is an ending address or the
most significant address in the current cycle. Remaining
register addresses for multiple byte data transfers are generated
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 19 of 28
internally by the serial port controller by decrementing from
the specified address. For LSB-first format, the specified address
is a beginning address or the least significant address in the
current cycle. Remaining register addresses for multiple byte
data transfers are generated internally by the serial port
controller by incrementing from the specified address.
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register 0x00, Bit 6.
The default is Logic 0, which is MSB-first format.
When using MSB-first format (LSBFIRST = 0), the instruction
and data bit must be written from MSB to LSB. Multibyte data
transfers in MSB-first format start with an instruction byte that
includes the register address of the most significant data byte.
Subsequent data bytes are loaded into sequentially lower
address locations. In MSB-first mode, the serial port internal
address generator decrements for each byte of the multibyte
data transfer.
When using LSB-first format (LSBFIRST = 1), the instruction
and data bit must be written from LSB to MSB. Multibyte data
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant data byte.
Subsequent data bytes are loaded into sequentially higher
address locations. In LSB-first mode, the serial port internal
address generator increments for each byte of the multibyte
data transfer.
Use of a single-byte transfer when changing the serial port data
format is recommended to prevent unexpected device behavior.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Chip Select Bar (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communication lines. CSB must stay low during the entire
communication cycle. Incomplete data transfers are aborted
anytime the CSB pin goes high. SDO and SDIO pins go to a
high impedance state when this input is high.
Serial Clock (SCLK)
The serial clock pin is used to synchronize data to and from the
device and to run the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is registered on
the rising edge of SCLK. All data is driven out on the falling
edge of SCLK.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However,
SDIO can also function as a bidirectional data output line.
The configuration of this pin is controlled by Register 0x00,
Bit 7. The default is Logic 0, which configures the SDIO pin
as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. The configuration of this
pin is controlled by Register 0x00, Bit 7. If this bit is set to a
Logic 1, the SDO pin does not output data and is set to a high
impedance state.
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
06569-014
Figure 23. Serial Register Interface—MSB First
A0 A1 A2 A3 A4 N0 N1 R/W D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
0
6569-015
Figure 24. Serial Register Interface Timing—LSB First
INSTRUCTION BIT 6INSTRUCTION BIT 7
CSB
SCLK
SDIO
t
S
t
DS
t
DH
t
PWH
t
PWL
f
SCLK–1
06569-016
Figure 25. Timing Diagram for SPI Register Write
DATA BIT N – 1DATA BIT N
CSB
SCLK
SDIO
SDO
tDV
06569-017
Figure 26. Timing Diagram for SPI Register Read
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 20 of 28
SPI REGISTER MAP
Reading any register returns previously written values for all defined register bits, unless otherwise noted. Change serial port configu-
ration or execute software reset in single byte instruction only to avoid unexpected device behavior.
Table 14.
Register Name Address Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPI Control 0x00 0x00 SDIODIR LSBFIRST SWRESET
Data Control 0x02 0x00 DATTYPE ONEPORT INVDCO
Power Down 0x03 0x00 PD_DCO PD_AUX2 PD_AUX1 PD_BIAS PC_CLK PD_DAC2 PD_DAC1
DAC Mode Select 0x0A 0x00 DAC1MOD<1:0> DAC2MOD<1:0>
DAC1 Gain LSB 0x0B 0xF9 DAC1FSC<7:0>
DAC1 Gain MSB 0x0C 0x01 DAC1FSC<9:8>
AUX DAC1 LSB 0x0D 0x00 AUXDAC1<7:0>
AUX DAC1 MSB 0x0E 0x00 AUX1PIN AUX1DIR AUXDAC1<9:8>
DAC2 Gain LSB 0x0F 0xF9 DAC2FSC<7:0>
DAC2 Gain MSB 0x10 0x01 DAC2FSC<9:8>
AUX DAC2 LSB 0x11 0x00 AUXDAC2<7:0>
AUX DAC2 MSB 0x12 0x00 AUX2PIN AUX2DIR AUXDAC2<9:8>
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 21 of 28
SPI REGISTER DESCRIPTIONS
Table 15.
Register Address Bit Name Description
7 SDIODIR 0, operate SPI in 4-wire mode, SDIO pin operates as an input only
1, operate SPI in 3-wire mode, SDIO pin operates as a bidirectional I/O line
6 LSBFIRST 0, LSBFIRST off, SPI serial data mode is MSB to LSB
1, LSBFIRST on, SPI serial data mode is LSB to MSB
5 SWRESET 0, resume normal operation following software RESET
SPI Control 0x00
1, software RESET; loads default values to all registers (except Register 0x00)
7 DATTYPE 0, DAC input data is twos complement binary format
1, DAC input data is unsigned binary format
6 ONEPORT 0, normal two port input mode
1, optional single port input mode, interleaved data received on Port 1 only
Data Control 0x02
4 INVDCO 1, inverts data clock output signal
7 PD_DCO 1, power down data clock output
5 PD_AUX2 1, power down AUX2 DAC
4 PD_AUX1 1, power down AUX1 DAC
3 PD_BIAS 1, power down reference voltage bias circuit
2 PD_CLK 1, power down DAC clock input circuit
1 PD_DAC2 1, power down DAC2 analog output
Power Down 0x03
0 PD_DAC1 1, power down DAC1 analog output
3:2 DAC1MOD<1:0> 00, selects normal mode, DAC1
01, selects mix mode, DAC1
10, selects return-to-zero mode, DAC1
1:0 DAC2MOD<1:0> 00, selects normal mode, DAC2
01, selects mix mode, DAC2
DAC Mode Select 0x0A
10, selects return-to-zero mode, DAC2
0x0B 7:0 DAC1FSC<7:0> DAC1 full-scale 10-bit adjustment word
1:0 DAC1FSC<9:8> 0x03FF, sets full-scale current to the maximum value of 31.66 mA
0x01F9, sets full-scale current to the nominal value of 20.0 mA
DAC1 Gain
0x0C
0x0000, sets full-scale current to the minimum value of 8.64 mA
0x0D 7:0 AUXDAC1<7:0> Auxiliary DAC1 10-bit output current adjustment word
1:0 AUXDAC1<9:8> 0x03FF, sets output current magnitude to 2.0 mA
0x0200, sets output current magnitude to 1.0 mA
0x0000, sets output current magnitude to 0.0 mA
7 AUX1PIN 0, AUX1P output pin is active
1, AUX1N output pin is active
6 AUX1DIR 0, configures AUX1 DAC output to source current
AUX DAC1
0x0E
1, configures AUX1 DAC output to sink current
0x0F 7:0 DAC2FSC<7:0> DAC2 full-scale 10-bit adjustment word
1:0 DAC2FSC<9:8> 0x03FF, sets full-scale current to the maximum value of 31.66 mA
0x01F9, sets full-scale current to the nominal value of 20.0 mA
DAC2 Gain
0x10
0x0000, sets full-scale current to the minimum value of 8.64 mA
0x11 7:0 AUXDAC2<7:0> Auxiliary DAC2 10-bit output current adjustment word
0x12 1:0 AUXDAC2<9:8> 0x03FF, sets output current magnitude to 2.0 mA
0x0200, sets output current to 1.0 mA
0x0000, sets output current to 0.0 mA
7 AUX2PIN 0, AUX2P output pin is active
1, AUX2N output pin is active
6 AUX2DIR 0, configures AUX2 DAC output to source current
AUX DAC2
1, configures AUX2 DAC output to sink current
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 22 of 28
DIGITAL INPUTS AND OUTPUTS
The AD9741/AD9743/AD9745/AD9746/AD9747 can operate
in two data input modes: dual-port mode and single-port mode.
For the default dual-port mode (ONEPORT = 0), each DAC
receives data from a dedicated input port. In single-port mode
(ONEPORT = 1), however, both DACs receive data from Port 1.
In single-port mode, DAC1 and DAC2 data is interleaved and
the IQSEL input is used to steer data to the correct DAC.
In single-port mode, when the IQSEL input is high, Port 1
data is delivered to DAC1 and when IQSEL is low, Port 1 data
is delivered to DAC2. The IQSEL input should always coincide
and be time-aligned with the other data bus signals. In single-
port mode, minimum setup and hold times apply to the IQSEL
input as well as to the input data signals. In dual-port mode, the
IQSEL input is ignored.
In dual-port mode, the data must be delivered at the sample rate
(up to 250 MSPS). In single-port mode, data must be delivered
at twice the sample rate. Because the data inputs function only
up to 250 MSPS, it is only practical to operate the DAC clock at
up to 125 MHz in single-port mode.
In both dual-port and single-port modes, a data clock output
(DCO) signal is available as a fixed time base with which to
stimulate data from an FPGA. This output signal always
operates at the sample rate. It may be inverted by asserting
the INVDCO bit.
INPUT DATA TIMING
With most DACs, signal-to-noise ratio (SNR) is a function of
the relationship between the position of the clock edges and the
point in time at which the input data changes. The AD9741/
AD9743/AD9745/AD9746/AD9747 are rising edge triggered
and thus exhibit greater SNR sensitivity when the data tran-
sition is close to this edge.
The specified minimum setup and hold times define a window
of time, within each data period, where the data is sampled
correctly. Generally, users should position data to arrive
relative to the DAC clock and well beyond the minimum
setup and minimum hold times. This becomes increasingly
more important at increasingly higher sample rates.
DUAL-PORT MODE TIMING
The timing diagram for the dual-port mode is shown in
Figure 27.
CLKP/CLKN
DCO
P1D<15:0>
P2D<15:0>
t
DCO
t
DBH
t
DBS
06569-018
I1 I2 I3 I4
Q1 Q2 Q3 Q4
Figure 27. Data Interface Timing, Dual-Port Mode
In Figure 27, data samples for DAC1 are labeled Ix and data
samples for DAC2 are labeled Qx. Note that the differential
DAC clock input is shown in a logical sense (CLKP/CLKN).
The data clock output is labeled DCO.
Setup and hold times are referenced to the positive transition of
the DAC clock. Data should arrive at the input pins such that
the minimum setup and hold times are met. Note that the data
clock output has a fixed time delay from the DAC clock and
may be a more convenient signal to use to confirm timing.
SINGLE-PORT MODE TIMING
The single-port mode timing diagram is shown in Figure 28.
06569-019
CLKP/CLKN
DCO
P1D<15:0>
IQSEL
t
DBS
t
DBH
t
DCO
I1 Q1 I2 Q2
Figure 28. Data Interface Timing, Single-Port Mode
In single-port mode, data for both DACs is received on the
Port 1 input bus. Ix and Qx data samples are interleaved and
arrive twice as fast as in dual-port mode. Accompanying the
data is the IQSEL input signal, which steers incoming data to its
respective DAC. When IQSEL is high, data is steered to DAC1
and when IQSEL is low, data is steered to DAC2. IQSEL should
coincide as well as be time-aligned with incoming data.
SPI PORT, RESET, AND PIN MODE
In general, when the AD9741/AD9743/AD9745/AD9746/
AD9747 are powered up, an active high pulse applied to the
RESET pin should follow. This insures the default state of all
control register bits. In addition, once the RESET pin goes low,
the SPI port can be activated, so CSB should be held high.
For applications without a controller, the AD9741/AD9743/
AD9745/AD9746/AD9747 also support pin mode operation,
which allows some functional options to be pin, selected with-
out the use of the SPI port. Pin mode is enabled anytime the
RESET pin is held high. In pin mode, the four SPI port pins
take on secondary functions, as shown in Table 16.
Table 16. SPI Pin Functions (Pin Mode)
Pin Name Pin Mode Description
SCLK ONEPORT (Register 0x02, Bit 6), bit value (1/0)
equals pin state (high/low)
SDIO DATTYPE (Register 0x02, Bit 7), bit value (1/0)
equals pin state (high/low)
CSB Enable Mix Mode, if CSB is high, Register 0x0A
is set to 0x05 putting both DAC1 and DAC2 into
mix mode
SDO Enable full power-down, if SDO is high, Register
0x03 is set to 0xFF
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 23 of 28
In pin mode, all register bits are reset to their default values
with the exception of those that are controlled by the SPI pins.
Note also that the RESET pin should be allowed to float and
must be pulled low. Connect an external 10 kΩ resistor to
DVSS. This avoids unexpected behavior in noisy environments.
DRIVING THE DAC CLOCK INPUT
The DAC clock input requires a low jitter drive signal. It is a
PMOS differential pair powered from the CVDD18 supply.
Each pin can safely swing up to 800 mV p-p at a common-
mode voltage of about 400 mV. Though these levels are not
directly LVDS-compatible, CLKP and CLKN can be driven by
an ac-coupled, dc-offset LVDS signal, as shown in Figure 29.
LVDS_P_IN CLKP
50Ω
50Ω
0.1µ
F
0.1µF
LVDS_N_IN CLKN
V
CM
= 400mV
06569-021
Figure 29. LVDS DAC Clock Drive Circuit
Using a CMOS or TTL clock is also acceptable for lower sample
rates. It can be routed through an LVDS translator and then
ac-coupled as described previously, or alternatively, it can be
transformer-coupled and clamped, as shown in Figure 30.
50Ω
50Ω
T
TL OR CMOS
CLK INPUT CLKP
CLKN
V
CM
= 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1µ
F
06569-022
Figure 30. TTL or CMOS DAC Clock Drive Circuit
If a sine wave signal is available, it can be transformer-coupled
directly to the DAC clock inputs, as shown in Figure 31.
50Ω
SINE WAVE
INPUT CLKP
CLKN
V
CM
= 400mV
06569-034
Figure 31. Sine Wave DAC Clock Drive Circuit
The 400 mV common-mode bias voltage can be derived from
the CVDD18 supply through a simple divider network, as
shown in Figure 32.
0.1µF 1nF
V
CM
= 400mV
CVDD18
CVSS
1kΩ
2
87Ω
06569-023
Figure 32. DAC Clock VCM Circuit
It is important to use CVDD18 and CVSS for any clock bias
circuit as noise that is coupled onto the clock from another
power supply is multiplied by the DAC input signal and
degrades performance.
FULL-SCALE CURRENT GENERATION
The full-scale currents on DAC1 and DAC2 are functions of
the current drawn through an external resistor connected to
the FSADJ pin (Pin 54). The required value for this resistor is
10 kΩ. An internal amplifier sets the current through the
resistor to force a voltage equal to the band gap voltage of 1.2 V.
This develops a reference current in the resistor of 120 μA.
CURRENT
SCALING
1.2V BANDGAP DAC1 GAIN
DAC2 GAIN
AD9747
DAC1
DAC2
DAC FULL SCALE
REFERENCE CURRENT
REFIO
FSADJ
0
.1µ
F
10kΩ
06569-024
Figure 33. Reference Circuitry
REFIO (Pin 55) should be bypassed to ground with a 0.1 μF
capacitor. The band gap voltage is present on this pin and can
be buffered for use in external circuitry. The typical output
impedance is near 5 kΩ. If desired, an external reference can
be connected to REFIO to overdrive the internal reference.
Internal current mirrors provide a means for adjusting the
DAC full-scale currents. The gain for DAC1 and DAC2 can be
adjusted independently by writing to the DAC1FSC<9:0> and
DAC2FSC<9:0> register bits. The default value of 0x01F9 for
the DAC gain registers gives an IFS of 20 mA, where IFS equals
⎟
⎠
⎞
⎜
⎝
⎛⎟
⎠
⎞
⎜
⎝
⎛×+×= FSCDACIFS n
16
3
72
10,000
V 1.2
The full-scale output current range is 8.6 mA to 31.7 mA for
register values 0x000 to 0x3FF.
06569-025
35
30
25
20
15
10
5
I
FS
(mA)
0 256 512 768 1024
DAC GAIN CODE
Figure 34. IFS vs. DAC Gain Code
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 24 of 28
DAC TRANSFER FUNCTION
Each DAC output of the AD9741/AD9743/AD9745/AD9746/
AD9747 drives complementary current outputs IOUTP and IOUTN.
IOUTP provides a near full-scale current output (IFS) when all bits
are high. For example,
DAC CODE = 2N − 1
where:
N = 8-/10-/12-/14-/16-bits (for AD9741/AD9743/AD9745/
AD9746/AD9747 respectively), and IOUTN provides no current.
The current output appearing at IOUTP and IOUTN is a function of
both the input code and IFS and can be expressed as
IOUTP = (DAC DATA/2N) × IFS (1)
IOUTN = ((2N − 1) − DAC DATA)/2N × IFS (2)
where DAC DATA = 0 to 2N − 1 (decimal representation).
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTP and IOUTN
should be connected to matching resistive loads (RLOAD) that are
tied to analog common (AVSS). The single-ended voltage
output appearing at the IOUTP and IOUTN pins is
VOUTP = IOUTP × RLOAD (3)
VOUTN = IOUTN × RLOAD (4)
Note that to achieve the maximum output compliance of 1 V at
the nominal 20 mA output current, RLOAD must be set to 50 Ω.
Also note that the full-scale value of VOUTP and VOUTN should
not exceed the specified output compliance range to maintain
specified distortion and linearity performance.
There are two distinct advantages to operating the AD9741/
AD9743/AD9745/AD9746/AD9747 differentially. First, differ-
ential operation helps cancel common-mode error sources
associated with IOUTP and IOUTN, such as noise, distortion, and
dc offsets. Second, the differential code dependent current
and subsequent output voltage (VDIFF) is twice the value of the
single-ended voltage output (VOUTP or VOUTN), providing 2×
signal power to the load.
VDIFF = (IOUTP – IOUTN) × RLOAD (5)
ANALOG MODES OF OPERATION
The AD9741/AD9743/AD9745/AD9746/AD9747 utilize a
proprietary quad-switch architecture that lowers the distortion
of the DAC output by eliminating a code dependent glitch that
occurs with conventional dual-switch architectures. But whereas
this architecture eliminates the code dependent glitches, it creates
a constant glitch at a rate of 2 × fDAC. For communications
systems and other applications requiring good frequency
domain performance, this is seldom problematic.
The quad-switch architecture also supports two additional
modes of operation; mix mode and return-to-zero (RZ) mode.
The waveforms of these two modes are shown in Figure 35. In
mix mode, the output is inverted every other half clock cycle.
This effectively chops the DAC output at the sample rate. This
chopping has the effect of frequency shifting the sinc roll-off
from dc to fDAC. Additionally, there is a second subtle effect on
the output spectrum. The shifted spectrum is shaped by a second
sinc function with a first null at 2 × fDAC. The reason for this
shaping is that the data is not continuously varying at twice the
clock rate, but is simply repeated.
In RZ mode, the output is set to midscale on every other half
clock cycle. The output is similar to the DAC output in normal
mode except that the output pulses are half the width and half
the area. Because the output pulses have half the width, the
sinc function is scaled in frequency by 2 and has a first null at
2 × fDAC. Because the area of the pulses is half that of the pulses
in normal mode, the output power is half the normal mode
output power.
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
10
INPUT DATA
DAC CLK
4-SWITCH
DAC OUT PUT
(f
S
MIX MODE)
4-SWITCH
DAC OUT PUT
(RETURN TO
ZERO MODE)
0
6569-026
t
t
Figure 35. Mix Mode and RZ Mode DAC Waveforms
The functions that shape the output spectrums for normal mode,
mix mode, and RZ mode, are shown in Figure 36. Switching
between the modes reshapes the sinc roll off inherent at the
DAC output. This ability to change modes in the AD9741/
AD9743/AD9745/D9746/AD9747 makes the parts suitable for
direct IF applications. The user can place a carrier anywhere in
the first three Nyquist zones depending on the operating mode
selected. The performance and maximum amplitude in all three
zones are impacted by this sinc roll off depending on where the
carrier is placed, as shown in Figure 36.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 25 of 28
0
–10
–20
–30
–40
T(f) (dB)
0.5 1.5 2
F
S
NORMAL
RZ
MIX
06569-027
Figure 36. Transfer Function for Each Analog Operating Mode
AUXILIARY DACS
Two auxiliary DACs are provided on the AD9741/AD9743/
AD9745/AD9746/AD9747. A functional diagram is shown
in Figure 37. The auxiliary DACs are current output devices
with two output pins, AUXP and AUXN. The active pin can
be programmed to either source or sink current. When either
sinking or sourcing, the full-scale current magnitude is 2 mA.
The available compliance range at the auxiliary DAC outputs
depends on whether the output is configured to a sink or source
current. When sourcing current, the compliance voltage is 0 V
to 1.6 V, but when sinking current, the output compliance
voltage reduces to 0.8 V to 1.6 V. Either output can be used, but
only one output of the auxiliary DAC (P or N) is active at any
time. The inactive pin is always in a high impedance state
(>100 kΩ).
06569-035
VBIAS
AUXP
AUXN
SINK
OR
SOURCE
POSITIVE
OR
NEGATIVE
0m
A
TO
2mA
0mA
TO
2mA
Figure 37. Auxiliary DAC Functional Diagram
In a single side band transmitter application, the combination of
the input referred dc offset voltage of the quadrature modulator
and the DAC output offset voltage can result in local oscillator
(LO) feedthrough at the modulator output, which degrades
system performance. The auxiliary DACs can be used to remove
the dc offset and the resulting LO feedthrough. The circuit
configuration for using the auxiliary DACs for performing
dc offset correction depends on the details of the DAC and
modulator interface. An example of a dc-coupled configuration
with low-pass filtering is outlined in the Power Dissipation
section.
AD9747
AUX
DAC1 OR
DAC2
AD9747
DAC1 OR
DAC2
25Ω TO 50Ω
QUAD MOD
I OR Q INPUTS
QUADRATURE
MODULATOR V+
25Ω TO 50Ω
06569-029
OPTIONAL
PASSIVE
FILTERING
Figure 38. DAC DC Coupled to Quadrature Modulator with Passive DC Shift
POWER DISSIPATION
Figure 39 shows the power dissipation and current draw of the
AD9741/AD9743/AD9745/AD9746/AD9747. It shows that the
devices have a quiescent power dissipation of about 190 mW.
Most of this comes from the AVDD33 supply. Total power
dissipation increases about 50% as the clock rate is increased
to the maximum clock rate of 250 MHz.
350
310
270
230
190
150
P
TOTAL
(mW)
0 50 100 150 200 250
f
DAC
(MHz)
06569-030
25 75 125 175 225
f
OUT
= DC
f
OUT
= NYQUIST
Figure 39. AD9747 Power Dissipation vs. fDAC
15
12
9
6
3
0
I
DVDD33
(mA)
0 50 100 150 200 250
f
DAC
(MHz)
06569-031
25 75 125 175 225
AD9747
AD9741
Figure 40. DVDD33 Current vs. fDAC
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 26 of 28
30
24
18
12
6
0
I
DVDD18
(mA)
0 50 100 150 200 250
f
DAC
(MHz)
06569-032
25 75 125 175 225
AD9747
AD9741
Figure 43 shows the power consumption for each power supply
domain as well as the total power consumption. Individual bars
within each group display the power in full active mode (blue)
vs. power for five increasing levels of power-down.
06569-045
P
DISS
(mW)
0
50
100
150
200
250
300
350
AVDD33 DVDD18 CVDD18 DVDD33 TOT PWR
FULL ACTIVE
DCO OFF
AUX OFF
DAC OFF
CLK OFF
BIAS OFF
Figure 41. DVDD18 Current vs. fDAC
15
13
11
9
7
5
I
CVDD18
(mA)
0 50 100 150 200 250
f
DAC
(MHz)
06569-033
25 75 125 175 225
Figure 43. Power Dissipation vs. Power-Down Mode
The overall power consumption is dominated by AVDD33 and
significant power savings can be achieved simply by disabling
the DAC outputs. Also, disabling the DAC outputs is a signifi-
cant way to conserve power and still maintain a fast wake-up
time. Full power-down disables all circuitry for minimum
power consumption. Note, however, that even in full power-
down, there is a small power draw (25 mW) due to incoming
data activity. To lower power consumption to near zero, all
incoming data activity must be halted.
Figure 42. CVDD18 Current vs. fDAC
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 27 of 28
OUTLINE DIMENSIONS
COMP LI ANT TO JEDEC STANDARDS M O-220-VNND-4
111507-A
0.20 REF
0.80 M A X
0.65 TYP
1.00
0.85
0.80 0.05 MA X
0.02 NOM
1
18
54
37 19
36
72
55
0.50
0.40
0.30
8.50 RE F
4.70
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
TOP VIEW
9.75
BSC SQ
10.00
BSC SQ
PIN 1
INDI
ATOR
SEATING
PLANE
12° MAX
0.60
0.42
0.24
0.60
0.42
0.24
0.30
0.23
0.18
0.50
BSC
PIN 1
INDICATOR
COPLANARITY
0.08
EXPOSED P AD M UST BE
SOLDERED T O PCB AND
CO NN ECT ED T O AVSS .
Figure 44. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm, Very Thin Quad
(CP-72-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9741BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9741BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9743BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9743BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9745BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9745BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9746BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9746BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9747BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9747BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9741-EBZ1 Evaluation Board
AD9743-EBZ1 Evaluation Board
AD9745-EBZ1 Evaluation Board
AD9746-EBZ1 Evaluation Board
AD9747-EBZ1 Evaluation Board
1 Z = RoHS Compliant Part.
AD9741/AD9743/AD9745/AD9746/AD9747
Rev. 0 | Page 28 of 28
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06569-0-5/07(0)