© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 3
1Publication Order Number:
CAT24AA01/D
CAT24AA01, CAT24AA02
1-Kb and 2-Kb I2C CMOS
Serial EEPROM
Description
The CAT24AA01/24AA02 are 1−Kb and 2−Kb CMOS Serial
EEPROM devices internally organized as 128x8/256x8 bits.
They feature a 16−byte page write buffer and support both the
Standard (100 kHz) and the Fast (400 kHz) I2C protocols.
In contrast to the CAT24C01/24C02, the CAT24AA01/24AA02
have no external address pins, and are therefore suitable in
applications that require a single CAT24AA01/02 on the I2C bus.
Features
•Supports Standard and Fast I2C Protocol
•1.7 V to 5.5 V Supply Voltage Range
•16−Byte Page Write Buffer
•Hardware Write Protection for Entire Memory
•Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
•Low Power CMOS Technology
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•Industrial Temperature Range
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
SDA
SCL
WP
CAT24AA02
CAT24AA01
VCC
VSS
Figure 1. Functional Symbol
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PIN CONFIGURATIONS
SDA
SCL
WP
VCC
VSS
NC
NC
NC 1
(Top View)
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SOIC−8
W SUFFIX
CASE 751BD
TSOT−23
TB SUFFIX
CASE 419AE
2
3
4
8
7
6
5
VCC
WP
SDA
VSS
SCL 1
(Top View)
2
3
5
4
SOIC
TSOT−23
PIN FUNCTION
Pin Name
SDA
Function
Serial Data/Address
SCL Clock Input
WP Write Protect
VCC Power Supply
VSS Ground
NC No Connect
CAT24AA01, CAT24AA02
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2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature −65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. REABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program/Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode @ 25°C
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz 0.5 mA
ICCW Write Current Write 1 mA
ISB Standby Current All I/O Pins at GND or VCC 1mA
ILI/O Pin Leakage Pin at GND or VCC 1mA
VIL Input Low Voltage −0.5 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 2) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN (Note 2) Input Capacitance (other pins) VIN = 0 V 6 pF
IWP (Note 4) WP Input Current VIN < VIH 100 mA
VIN > VIH 1
4. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
CAT24AA01, CAT24AA02
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3
Table 5. A.C. CHARACTERISTICS (Note 5) (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol Parameter
Standard Fast
Units
Min Max Min Max
FSCL Clock Frequency 100 400 kHz
tHD:STA START Condition Hold Time 4 0.6 ms
tLOW Low Period of SCL Clock 4.7 1.3 ms
tHIGH High Period of SCL Clock 4 0.6 ms
tSU:STA START Condition Setup Time 4.7 0.6 ms
tHD:DAT Data In Hold Time 0 0 ns
tSU:DAT Data In Setup Time 250 100 ns
tRSDA and SCL Rise Time 1000 300 ns
tF (Note 6) SDA and SCL Fall Time 300 300 ns
tSU:STO STOP Condition Setup Time 4 0.6 ms
tBUF Bus Free Time Between STOP and START 4.7 1.3 ms
tAA SCL Low to Data Out Valid 3.5 0.9 ms
tDH Data Out Hold Time 100 100 ns
Ti (Note 6) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
tSU:WP WP Setup Time 0 0 ms
tHD:WP WP Hold Time 2.5 2.5 ms
tWR Write Cycle Time 5 5 ms
tPU (Notes 6, 7) Power−up to Ready Mode 1 1 ms
5. Test conditions according to “A.C. Test Conditions” table.
6. Tested initially and after a design or process change that affects this parameter.
7. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times ≤ 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
CAT24AA01, CAT24AA02
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Power−On Reset (POR)
Each CAT24AA01/02 incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
below the POR trigger level.
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and delivered on the negative
edge of SCL.
WP: When the Write Protect input pin is forced HIGH by an
external source, all write operations are inhibited. When the
pin is not driven by an external source, it is pulled LOW
internally.
Functional Description
The CAT24AA01/02 supports the Inter−Integrated
Circuit (I2C) Bus protocol. The protocol relies on the use of
a Master device, which provides the clock and directs bus
traffic, and Slave devices which execute requests. The
CAT24AA01/02 operates as a Slave device. Both Master
and Slave can transmit or receive, but only the Master can
assign those roles.
I2C BUS PROTOCOL
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
Master provides the clock to the SCL line, and the Master
and Slaves drive the SDA line. A ‘0’ is transmitted by
pulling a line LOW and a ‘1’ by releasing it HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). A START is generated by a
HIGH to LOW transition, while a STOP is generated by a
LOW to HIGH transition. The START acts like a wake−up
call. Absent a START, no Slave will respond to the Master.
The STOP completes all commands.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address
(Figure 3). The four most significant bits of the Slave
address are 1010 (Ah).
For the CAT24AA01/02 the next three bits must be 000.
The last bit, R/W, instructs the Slave to either provide (1)
or accept (0) data, i.e. it signals a Read (1) or a Write (0)
request.
Acknowledge
During the 9th clock cycle following every byte sent onto
the bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
Figure 2. Start/Stop Timing
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 3. Slave Address Bits
1010000R/W
CAT24AA01, CAT24AA02
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5
Figure 4. Acknowledge Timing
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 5. Bus Timing
SCL
SDA IN
SDA OUT
tBUF
tSU:STO
tSU:DAT
tR
tAA tDH
tLOW
tHIGH
tLOW
tSU:STA
tHD:STA
tHD:DAT
tF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends an address
byte and a data byte and concludes the session by creating
a STOP condition on the bus. The Slave responds with ACK
after every byte sent by the Master (Figure 5). The STOP
starts the internal Write cycle, and while this operation is in
progress (tWR), the SDA output is tri−stated and the Slave
does not acknowledge the Master (Figure 6).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 7). Up to 16 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 8). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24AA01/02 is shipped erased, i.e., all bytes are FFh.
CAT24AA01, CAT24AA02
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6
Figure 6. Byte Write Sequence
ADDRESS
BYTE
DATA
BYTE
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
a7÷a0d7÷d0
Figure 7. Write Cycle Timing
tWR
STOP
CONDITION START
CONDITION ADDRESS
ACK8th Bit
Byte n
SCL
SDA
Figure 8. Page Write Sequence
A
C
K
A
C
K
A
C
K
S
T
O
P
S
A
C
K
A
C
K
S
T
A
R
T
P
SLAVE
ADDRESS
n = 1
xv15
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
Figure 9. WP Timing
189
18
ADDRESS
BYTE
DATA
BYTE
SCL
SDA
WP
tSU:WP
tHD:WP
a7a0d7d0
CAT24AA01, CAT24AA02
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7
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends an address
byte to the Slave. Rather than completing the Byte Write
sequence by sending data, the Master then creates a START
condition and broadcasts a Slave address with the R/W bit
set to ‘1’. The Slave responds with ACK after every byte sent
by the Master and then sends out data residing at the selected
address. After receiving the data, the Master responds with
NoACK and then terminates the session by creating a STOP
condition on the bus (Figure 11).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory. For the CAT24AA01, the internal address
counter will not wrap around at the end of the 128 byte
memory space.
Figure 10. Immediate Read Sequence and Timing
SCL
SDA 8th Bit
STOPNO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
K
DATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
Figure 11. Selective Read Sequence
SLAVE
S
A
C
K
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
S
A
C
K
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
DATA
BYTE
ADDRESS
BYTEADDRESS
BUS ACTIVITY:
MASTER
SLAVE
Figure 12. Sequential Read Sequence
A
C
K
A
C
K
A
C
K
S
T
O
P
N
O
A
C
K
A
C
K
P
SLAVE
ADDRESS
DATA
BYTE
n
DATA
BYTE
n+1
DATE
BYTA
n+2
DATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
CAT24AA01, CAT24AA02
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8
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
CAT24AA01, CAT24AA02
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9
PACKAGE DIMENSIONS
TSOT−23, 5 LEAD
CASE 419AE−01
ISSUE O
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
L1
LL2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-193.
SYMBOL
θ
MIN NOM MAX
q
A
A1
A2
b
c
D
E
E1
e
L
0º 8º
L1
L2
0.01
0.80
0.30
0.12
0.30
0.05
0.87
0.15
2.90 BSC
2.80 BSC
1.60 BSC
0.95 TYP
0.40
0.60 REF
0.25 BSC
1.00
0.10
0.90
0.45
0.20
0.50
CAT24AA01, CAT24AA02
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10
Example of Ordering Information
Prefix Device # Suffix
Company ID
CAT 24AA02 TD
Product Number
24AA01
I− GT3
Package
I = Industrial (−40°C to +85°C)
Temperature Range
TD: TSOT−23 5−Lead
W: SOIC 8−Lead
Lead Finish
G: NiPdAu
Blank: Matte−Tin
T: Tape & Reel
3: 3,000 Units / Reel
10: 10,000 / Reel
24AA02
Tape & Reel (Note 12)
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard lead finish is NiPdAu.
10.The device used in the above example is a CAT24AA02TDI−GT3 (TSOT−23 5−Lead, Industrial Temperature, NiPdAu, Tape & Reel,
3,000/Reel).
11. For additional package and temperature options, please contact your nearest ON Semiconductor sales office.
12.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
CAT25320/D
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
PUBLICATION ORDERING INFORMATION
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USA/Canada
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Email: orderlit@onsemi.com
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