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IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEPT. 2009
2000 Integrated Device Technology, Inc. DSC-4771/3c
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 500ps (max.)
• Very low duty cycle distortion < 600ps (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: -32mA IOH, +48mA IOL
• Two independent output banks with 3-state control
• 1:5 fanout per bank
• "Heartbeat" monitor output
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• Available in the following packages:
– Commercial: QSOP, SOIC, SSOP
– Military: CERDIP, LCC
NOTE: EOL for non-green parts to occur on 5/13/10 per
PDN U-09-01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT49FCT805BT/CT
FAST CMOS
BUFFER/CLOCK DRIVER
DESCRIPTION:
This buffer/clock driver is built using advanced dual metal CMOS
technology. The FCT805T is a non-inverting clock driver consisting of two
banks of drivers. Each bank drives five output buffers from a standard TTL
compatible input. This part has extremely low output skew, pulse skew, and
package skew. The device has a “heart-beat” monitor for diagnostics and
PLL driving. The monitor output is identical to all other outputs and complies
with the output specifications in this document.
The FCT805T is designed for fast, clean edge rates to provide accurate
clock distribution in high speed systems.
INA
INB
OEB
OEA
OA1-OA5
OB1-OB5
MON
5
5
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
QSOP/ SOIC/ SSOP/ CERDIP
TOP VIEW LCC
TOP VIEW
1
2
3
4
5
6
7
8
9 101112 13
14
15
16
17
18
19
20
OA3
OA4
OA5
GND
GND
(1)
OB3
OB4
OB5
OB2
GND
OEA
INA
INB
OEB
MON
OA2
OA1
VCC
VCC
OB1
INDEX
VCC
OA1
OA2
GND
(1)
INA
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
201
OA3
OA4
OA5
OEA
VCC
OB1
GND
MON
INB
OB2
OB3
OB4
OB5
OEB
GND
NOTE:
1. Pin 8 is internally connected to GND. To insure compatibility with all products, pin
8 should be connected to GND at the board level.
PIN DESCRIPTION
Pin Names Description
OEA, OEB3-State Output Enable Inputs (Active LOW)
INA, INBClock Inputs
OAx, OBx Clock Outputs
MON Monitor Output
FUNCTION TABLE (1)
Inputs Outputs
OEA, OEBINA, INBOAx, OBx MON
LLLL
LHHH
HLZL
HHZH
NOTE:
1. H = HIGH
L = LOW
Z = High-Impedance
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 5.5 8 pF
NOTE:
1. This parameter is measured at characterization but not tested.
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IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, Military: TA = -55°C to +125°C, VCC = 5V ± 10%
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
IIH Input HIGH Current(5) VCC = Max. VI = 2.7V — — ±1µA
IIL Input LOW Current(5) VCC = Max. VI = 0.5V — — ±1µA
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1µA
IOZL (3-State Output Pins) VO = 0.5V — — ±1
IIInput HIGH Current VCC = Max., VI = VCC (Max.) — — ±1µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND(3) –60 –120 –255 mA
VCC = Min. IOH = –12mA MIL 2.4 3.3 — V
VOH Output HIGH Voltage VIN = VIH or VIL IOH = –15mA COM'L
IOH = –24mA MIL 2 3 — V
IOH = –32mA COM'L(4)
VOL Output LOW Voltage VCC = Min. IOL = 32mA MIL — 0.3 0.55 V
VIN = VIH or VIL IOL = 48mA COM'L
IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V — — ±1µA
VHInput Hysteresis for all inputs — — 150 — mV
ICCL Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA
ICCH
ICCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition should not exceed one second.
5. The test limit for this parameter is ±5µA at TA = -55°C.
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply Current VCC = Max. — 1 2 mA
TTL Inputs HIGH VIN = 3.4V(3)
ICCD Dynamic Power Supply Current(4) VCC = Max. VIN = VCC — 60 100 µA/MHz
Outputs Open VIN = GND
OEA = OEB = GND
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 1.5 3
Outputs Open VIN = GND
fO = 25MHz
50% Duty Cycle VIN = 3.4V — 1.8 4
OEA = OEB = VCC VIN = GND
Mon. Output Toggling
VCC = Max. VIN = VCC — 33 55.5(5) mA
Outputs Open VIN = GND
fO = 50MHz
50% Duty Cycle VIN = 3.4V — 33.5 57.5(5)
OEA = OEB = GND VIN = GND
Eleven Outputs Toggling
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IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES:
1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested.
2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation delay limits do not imply
skew.
3. See Test Circuits and Waveforms.
4. Minimum limits are guaranteed but not tested on Propagation Delays.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY(1,2)
FCT805BT FCT805CT
Symbol Parameter Conditions(3) Min.(4) Max.Min.(4) Max.Unit
tPLH Propagation Delay CL = 50pF 1.5 5.7 1.5 5.2 ns
tPHL INA to OAx, INB to OBx RL = 500Ω
tROutput Rise Time — 2 — 2 ns
tFOutput Fall Time — 1.5 — 1.5 ns
tSK(O) Output skew: skew between outputs of all banks of — 0.9 — 0.7 ns
same package (inputs tied together)
tSK(P) Pulse skew: skew between opposite transitions — 0.9 — 0.8 ns
of same output (|tPHL -– tPLH|)
tSK(PP) Part-to-part skew: skew between outputs of different — 1.5 — 1.2 ns
packages at same power supply voltage,
temperature, package type and speed grade
tPZL Output Enable Time 1.5 6.5 1.5 6 ns
tPZH OEA to OAx, OEB to OBx
tPLZ Output Disable Time 1.5 6.5 1.5 6 ns
tPHZ OEA to OAx, OEB to OBx
NOTES:
1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested.
2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation delay limits do not imply
skew.
3. See Test Circuits and Waveforms.
4. Minimum limits are guaranteed but not tested on Propagation Delays.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - COMMERCIAL(1,2)
FCT805BT FCT805CT
Symbol Parameter Conditions(3) Min.(4) Max.Min.(4) Max.Unit
tPLH Propagation Delay CL = 50pF 1.5 5 1.5 4.5 ns
tPHL INA to OAx, INB to OBx RL = 500Ω
tROutput Rise Time — 1.5 — 1.5 ns
tFOutput Fall Time — 1.5 — 1.5 ns
tSK(O) Output skew: skew between outputs of all banks of — 0.7 — 0.5 ns
same package (inputs tied together)
tSK(P) Pulse skew: skew between opposite transitions — 0.7 — 0.6 ns
of same output (|tPHL -– tPLH|)
tSK(PP) Part-to-part skew: skew between outputs of different — 1.2 — 1 ns
packages at same power supply voltage,
temperature, package type and speed grade
tPZL Output Enable Time 1.5 6 1.5 5 ns
tPZH OEA to OAx, OEB to OBx
tPLZ Output Disable Time 1.5 6 1.5 5 ns
tPHZ OEA to OAx, OEB to OBx
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
7V
VCC
Pulse
Generator D.U.T.
500
500
RT
VIN VOUT
50pF
CL
0V
VOH
tPLH tPHL
VOL
tR
3V
1.5V
tF
2.0V
0.8V
1.5V
OUTPUT
INPUT
CONTROL
INPUT
tPLZ 0V
OUTPUT
NORMALLY
LOW
tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VOL
VOH
0.3V
0.3V
1.5V
1.5V
tPZL
3.5V 3.5V
3V
1.5V
0V
VOH
tPLH tPHL
VOL
3V
1.5V
1.5V
OUTPUT
INPUT
tSK(p) = tPHL - tPLH
0V
VOH
tPLH1
VOL
1.5V
OUTPUT 1
3V
1.5V
INPUT
VOH
tSK(o)
VOL
1.5V
tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1
OUTPUT 2
tPLH1
tSK(o)
tPLH2 tPHL2
0V
VOH
tPLH1
VOL
1.5VPACKAGE 1
OUTPUT
3V
1.5V
INPUT
VOH
tSK(pp)
VOL
1.5V
tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL1
tSK(pp)
tPLH2 tPHL2
PACKAGE 2
OUTPUT
Package Delay
TEST CIRCUITS AND WAVEFORMS
Pulse Skew - tSK(P)
Test Circuits for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Switch
Disable LOW Closed
Enable LOW
Disable HIGH G ND
Enable HIGH
SWITCH POSITION
Enable and Disable Times
Output Skew
Part-to-Part Skew - tSK(PP)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
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IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT XXXX
Device Type
XX
Package
X
Process
Fast CMOS Buffer/Clock Driver
805BT
805CT
SO
SOG
Q
QG
PY
PYG
Commercial Options
Small Outline IC
SOIC - Green
Quarter-size Small Outline Package
QSOP - Green
Shrink Small Outline Package
SSOP - Green
D
L
Military Options
CERDIP
Leadless Chip Carrier
Blank
B
Commercial (0°C to +70°C)
MIL-STD-883, Class B (– 55°C to +125°C)
ORDERING INFORMATION
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
