TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 Dual-Synchronous, Step-Down Controller with Out-of-AudioTM Operation and 100-mA LDOs for Notebook System Power Check for Samples: TPS51125 FEATURES APPLICATIONS * * * * * * * * 1 2 * * * * * * * * Wide Input Voltage Range: 5.5 V to 28 V Output Voltage Range: 2 V to 5.5 V Built-in 100-mA 5-V/3.3-V LDO with Switches Built-in 1% 2-V Reference Output With/Without Out-of-AudioTM Mode Selectable Light Load and PWM only Operation Internal 1.6-ms Voltage Servo Softstart Adaptive On-Time Control Architecture with Four Selectable Frequency Setting 4500 ppm/C RDS(on) Current Sensing Built-In Output Discharge Power Good Output Built-in OVP/UVP/OCP Thermal Shutdown (Non-latch) QFN, 24-Pin (RGE) 13 kW Notebook Computers I/O Supplies System Power Supplies DESCRIPTION The TPS51125 is a cost effective, dual-synchronous buck controller targeted for notebook system power supply solutions. It provides 5-V and 3.3-V LDOs and requires few external components. The 270-kHz VCLK output can be used to drive an external charge pump, generating gate drive voltage for the load switches without reducing the main converter's efficiency. The TPS51125 supports high efficiency, fast transient response and provides a combined power-good signal. Out-of-AudioTM mode light-load operation enables low acoustic noise at much higher efficiency than conventional forced PWM operation. Adaptive on-time D-CAPTM control provides convenient and efficient operation. The part operates with supply input voltages ranging from 5.5 V to 28 V and supports output voltages from 2 V to 5.5 V. The TPS51125 is available in a 24-pin QFN package and is specified from -40C to 85C ambient temperature range. 20 kW 20 kW VIN 30 kW VIN 220 nF 3.3 m F VO2 5.1 W 3.3 V 3 2 VREF VFB1 7 VO2 8 VREG3 9 VBST2 100 kW 3.3 m F 5.1 W VO1 DRVH1 21 PowerPAD 5V LL1 20 EN0 SKIPSEL GND VIN VREG5 330 m F DRVL1 19 13 14 15 16 17 18 12 DRVL2 VREG5 0.1 m F VBST1 22 TPS51125RGE 11 LL2 5.5 V to 28 V VO1 24 PGOOD 23 10 DRVH2 330 m F EN0 1 ENTRIP1 4 VIN 10 m F x 2 VCLK 0.1 m F 5 VFB2 10 m F 6 TONSEL 10 m F x 2 130 kW ENTRIP2 130 kW VREG5 100 nF VREF VIN 33 m F 100 nF 15 V VO1 620 kW 100 nF 100 nF 1m F UDG-09019 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Out-of-Audio, D-CAP are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2012, Texas Instruments Incorporated TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com ORDERING INFORMATION ORDERABLE DEVICE NUMBER TA PACKAGE -40C to 85C Plastic Quad Flat Pack (QFN) TPS51125RGET TPS51125RGER OUTPUT SUPPLY PINS 24 MINIMUM QUANTITY Tape-and-Reel 250 Tape-and-Reel 3000 ECO PLAN Green (RoHS and no Sb/Br) ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE PARAMETER Input voltage range (1) MIN MAX VBST1, VBST2 -0.3 36 VIN -0.3 30 LL1, LL2 -2.0 30 LL1, LL2, pulse width < 20 ns -5.0 30 VBST1, VBST2 Output voltage range (1) (2) -0.3 6 EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2, TONSEL, SKIPSEL -0.3 6 DRVH1, DRVH2 -1.0 36 -0.3 6 -0.3 6 DRVH1, DRVH2 (2) PGOOD, VCLK, VREG3, VREG5, VREF, DRVL1, DRVL2 Human Body Model QSS 009-105 (JESD22-A114A) Electrostatic discharge Charged Device Model QSS 009-147 (JESD22-C101B.01) kV 1.5 -40 125 Storage temperature, Tstg -55 150 (2) V 2 Junction temperature range, TJ (1) UNIT C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltage values are with respect to the corresponding LLx terminal. DISSIPATION RATINGS 2-oz. trace and copper pad with solder. (1) PACKAGE TA < 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 85C POWER RATING 24 pin RGE (1) 1.85 W 18.5 mW/C 0.74 W Enhanced thermal conductance by 3x3 thermal vias beneath thermal pad. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER Supply voltage Input voltage range Output voltage range VIN 5.5 TYP MAX -0.1 34 VBST1, VBST2 (wrt LLx) -0.1 5.5 EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2, TONSEL, SKIPSEL -0.1 5.5 DRVH1, DRVH2 -0.8 34 DRVH1, DRVH2 (wrt LLx) -0.1 5.5 LL1, LL2 -1.8 28 VREF, VREG3, VREG5 -0.1 5.5 PGOOD, VCLK, DRVL1, DRVL2 -0.1 5.5 -40 85 Submit Documentation Feedback UNIT 28 VBST1, VBST2 Operating free-air temperature 2 MIN V C Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IVIN1 VIN supply current1 VIN current, T A = 25C, no load, VO1 = 0 V, VO2 = 0 V, EN0=open, ENTRIPx = 5 V, VFB1 = VFB2 = 2.05 V IVIN2 VIN supply current2 VIN current, TA = 25C, no load, VO1 = 5 V, VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V, VFB1 = VFB2 = 2.05 V IVO1 VO1 current IVO2 0.55 1 mA 4 6.5 A VO1 current, TA = 25C, no load, VO1 = 5 V, VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V, VFB1 = VFB2 = 2.05 V 0.8 1.5 mA VO2 current VO2 current, TA = 25C, no load, VO1 = 5 V, VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V, VFB1 = VFB2 = 2.05 V 12 100 IVINSTBY VIN standby current VIN current, TA = 25C, no load, EN0 = 1.2 V, ENTRIPx = 0 V 95 250 IVINSDN VIN shutdown current VIN current, TA = 25C, no load, EN0 = ENTRIPx = 0 V 10 25 A VREF OUTPUT VVREF VREF output voltage IVREF = 0 A 1.98 2.00 2.02 -5 A < IVREF < 100 A 1.97 2.00 2.03 4.8 5 5.2 VO1 = 0 V, IVREG5 < 100 mA, 6.5 V < VIN < 28 V 4.75 5 5.25 VO1 = 0 V, IVREG5 < 50 mA, 5.5 V < VIN < 28 V 4. 75 5 5.25 VO1 = 0 V, VREG5 = 4.5 V 100 175 250 Turns on 4.55 4.7 4.85 Hysteresis 0.15 0.25 0.3 1 3 V VREG5 OUTPUT VO1 = 0 V, IVREG5 < 100 mA, TA = 25C VVREG5 VREG5 output voltage IVREG5 VREG5 output current VTH5VSW Switch over threshold R5VSW 5 V SW RON VO1 = 5 V, IVREG5 = 100 mA V mA V VREG3 OUTPUT VO2 = 0 V, IVREG3 < 100 mA, TA= 25C VVREG3 IVREG3 VREG3 output voltage VREG3 output current VTH3VSW Switch over threshold R3VSW 3 V SW RON 3.2 3.33 3.46 VO2 = 0 V, IVREG3 < 100 mA, 6.5 V < VIN < 28 V 3.13 3.33 3.5 VO2 = 0 V, IVREG3 < 50 mA, 5.5 V < VIN < 28 V 3.13 3.33 3.5 VO2 = 0 V, VREG3 = 3 V 100 175 250 Turns on 3.05 3.15 3.25 0.1 0.2 0.25 1.5 4 Hysteresis VO2 = 3.3 V, IVREG3 = 100 mA V mA V INTERNAL REFERENCE VOLTAGE VIREF VVFB Internal reference voltage VFB regulation voltage IVREF = 0 A, beginning of ON state 1.95 1.98 2.01 FB voltage, IVREF = 0 A, skip mode 1.98 2.01 2.04 2.00 2.035 2.07 FB voltage, IVREF = 0 A, OOA mode (1) FB voltage, IVREF = 0 A, continuous conduction IVFB (1) VFB input current VFBx = 2.0 V, TA= 25C (1) V 2.00 -20 20 nA Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 3 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT VOUT DISCHARGE IDischg VOUT discharge current ENTRIPx = 0 V, VOx = 0.5 V 10 60 mA OUTPUT DRIVERS RDRVH DRVH resistance RDRVL DRVL resistance tD Dead time Source, VBSTx - DRVHx = 100 mV 4 8 1.5 4 4 8 Sink, VDRVLx = 100 mV 1.5 4 DRVHx-off to DRVLx-on 10 DRVLx-off to DRVHx-on 30 Sink, VDRVHx - LLx = 100 mV Source, VVREG5 - DRVLx = 100 mV ns CLOCK OUTPUT VCLKH High level voltage IVCLK = -10 mA, VO1 = 5 V, TA = 25 C VCLKL Low level voltage IVCLK = 10 mA, VO1 = 5 V, TA = 25 C fCLK Clock frequency TA = 25 C 4.84 4.92 0.06 0.12 175 270 325 0.7 V kHz INTERNAL BST DIODE VFBST Forward voltage VVREG5-VBSTx, IF = 10 mA, TA = 25 C 0.8 0.9 V IVBSTLK VBST leakage current VBSTx = 34 V, LLx = 28 V, TA = 25 C 0.1 1 A DUTY AND FREQUENCY CONTROL tON11 CH1 on time 1 VIN = 12 V, VO1 = 5 V, 200 kHz setting 2080 tON12 CH1 on time 2 VIN = 12 V, VO1 = 5 V, 245 kHz setting 1700 tON13 CH1 on time 3 VIN = 12 V, VO1 = 5 V, 300 kHz setting 1390 tON14 CH1 on time 4 VIN = 12 V, VO1 = 5 V, 365 kHz setting 1140 tON21 CH2 on time 1 VIN = 12 V, VO2 = 3.3 V, 250 kHz setting 1100 tON22 CH2 on time 2 VIN = 12 V, VO2 = 3.3 V, 305 kHz setting 900 tON23 CH2 on time 3 VIN = 12 V, VO2 = 3.3 V, 375 kHz setting 730 tON24 CH2 on time 4 VIN = 12 V, VO2 = 3.3 V, 460 kHz setting 600 tON(min) Minimum on time TA = 25 C 80 tOFF(min) Minimum off time TA = 25 C 300 Internal SS time Internal soft start 1.1 1.6 2.1 PG in from lower 92.50% 95% 97.50% PG in from higher 102.50 % 105% 107.50 % PG hysteresis 2.50% 5% 7.50% ns SOFT START tSS ms POWERGOOD VTHPG PG threshold IPGMAX PG sink current PGOOD = 0.5 V tPGDEL PG delay Delay for PG in 4 Submit Documentation Feedback 5 12 350 510 mA 670 s Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT LOGIC THRESHOLD AND SETTING CONDITIONS Shutdown VEN0 EN0 setting voltage IEN0 EN0 current VEN ENTRIP1, ENTRIP2 threshold 0.4 Enable, VCLK = off 0.8 Enable, VCLK = on 2.4 1.6 VEN0 = 0.2 V 2 3.5 5 VEN0 = 1.5 V 1 1.75 2.5 Shutdown 350 400 450 Hysteresis 10 30 60 200 kHz/250 kHz VTONSEL TONSEL setting voltage SKIPSEL setting voltage A mV 1.5 245 kHz/305 kHz 1.9 2.1 300 kHz/375 kHz 2.7 3.6 365 kHz/460 kHz 4.7 V PWM only VSKIPSEL V 1.5 Auto skip 1.9 OOA auto skip 2.7 VENTRIPx = 920 mV, TA= 25C 9.4 2.1 PROTECTION: CURRENT SENSE IENTRIP ENTRIPx source current TCIENTRIP ENTRIPx current temperature On the basis of 25C (2) coefficient VOCLoff OCP comparator offset ((VENTRIPx-GND/9)-24 mV -VGND-LLx) voltage, VENTRIPx-GND = 920 mV VOCL(max) Maximum OCL setting VENTRIPx = 5 V VZC Zero cross detection comparator offset VGND-LLx voltage VENTRIP Current limit threshold VENTRIPx-GND voltage, 10 4500 (2) ppm/C -8 0 8 185 205 225 -5 0 5 0.515 A 10.6 2 mV V PROTECTION: UNDERVOLTAGE AND OVERVOLTAGE VOVP OVP trip threshold tOVPDEL OVP prop delay OVP detect 110% 115% 120% VUVP Output UVP trip threshold tUVPDEL Output UVP prop delay 20 32 40 s tUVPEN Output UVP enable delay 1.4 2 2.6 ms 4.1 4.2 4.3 0.43 0.48 s 2 UVP detect 55% Hysteresis 60% 65% 10% UVLO VUVVREG5 VREG5 UVLO threshold VUVVREG3 VREG3 UVLO threshold Wake up Hysteresis Shutdown 0.38 (2) V VO2-1 THERMAL SHUTDOWN TSDN (2) Thermal shutdown threshold Shutdown temperature Hysteresis (2) (2) 150 10 C Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 5 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com DEVICE INFORMATION Table 1. TERMINAL FUNCTIONS TABLE TERMINAL NAME NO. I/O DESCRIPTION VIN 16 I High voltage power supply input for 5-V/3.3-V LDO. GND 15 - Ground. VREG3 8 O 3.3-V power supply output. Connect 10-F ceramic capacitor to Power GND near the device. A 1-F ceramic capacitor is acceptable when not loaded. VREG5 17 O 5-V power supply output. Connect 33-F ceramic capacitor to Power GND near the device. VREF 3 O 2-V reference voltage output. Connect 220-nF to 1-F ceramic capacitor to Signal GND near the device. Master enable input. Open : LDOs on, and ready to turn on VCLK and switcher channels. EN0 13 ENTRIP1 1 I/O 620 k to GND : enable both LDOs, VCLK off and ready to turn on switcher channels. Power consumption is almost the same as the case of VCLK = ON. GND : disable all circuit ENTRIP2 6 VO1 24 VO2 7 VFB1 2 VFB2 5 PGOOD 23 I/O Channel 1 and Channel 2 enable and OCL trip setting pins.Connect resistor from this pin to GND to set threshold for synchronous RDS(on) sense. Short to ground to shutdown a switcher channel. I/O Output connection to SMPS. These terminals work as fixed voltage inputs and output discharge inputs. VO1 and VO2 also work as 5 V and 3.3 V switch over return power input respectively. I O SMPS feedback inputs. Connect with feedback resistor divider. Power Good window comparator output for channel 1 and 2. (Logical AND) Selection pin for operation mode: SKIPSEL 14 I OOA auto skip : Connect to VREG3 or VREG5 Auto skip : Connect to VREF PWM only : Connect to GND On-time adjustment pin. 365 kHz/460 kHz setting : connect to VREG5 TONSEL 4 I 300 kHz/375 kHz setting : connect to VREG3 245 kHz/305 kHz setting : connect to VREF 200 kHz/250 kHz setting : connect to GND DRVL1 19 DRVL2 12 VBST1 22 VBST2 9 DRVH1 21 DRVH2 10 LL1 20 LL2 11 VCLK 18 6 O I O I O Low-side N-channel MOSFET driver outputs. GND referenced drivers. Supply input for high-side N-channel MOSFET driver (boost terminal). High-side N-channel MOSFET driver outputs. LL referenced drivers. Switch node connections for high-side drivers, current limit and control circuitry. 270-kHz clock output for 15-V charge pump. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 VO1 PGOOD VBST1 DRVH1 LL1 DRVL1 RGE PACKAGE (TOP VIEW) 24 23 22 21 20 19 ENTRIP1 1 18 VCLK VFB1 2 17 VREG5 VREF 3 16 VIN TPS51125RGE ENTRIP2 6 13 EN0 7 8 9 10 11 12 DRVL2 14 SKIPSEL LL2 5 DRVH2 VFB2 VBST2 15 GND VREG3 4 VO2 TONSEL Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 7 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com Functional Block Diagram 8 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 Switcher Controller Block Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 9 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS VIN SUPPLY CURRENT1 vs JUNCTION TEMPERATURE VIN SUPPLY CURRENT1 vs INPUT VOLTAGE 800 800 IVIN1 - VIN Supply Current1 - mA IVIN1 - VIN Supply Current1 - mA 700 700 600 500 400 300 200 100 600 500 400 300 200 100 0 -50 0 50 100 0 150 5 TJ - Junction Temperature - C 10 15 20 25 V IN - Input Voltage - V Figure 1. Figure 2. VIN SUPPLY CURRENT2 vs INPUT VOLTAGE 9 9 8 8 IVIN2 - VIN Supply Current2 - mA IVIN2 - VIN Supply Current2 - mA VIN SUPPLY CURRENT2 vs JUNCTION TEMPERATURE 7 6 5 4 3 2 7 6 5 4 3 2 1 1 0 0 -50 0 50 100 150 5 Figure 3. 10 10 15 20 25 V IN - Input Voltage - V T J - Junction Temperature - C Figure 4. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) VIN STANDBY CURRENT vs INPUT VOLTAGE VIN STANDBY CURRENT vs JUNCTION TEMPERATURE 250 IVINSTBY - VIN Standby Current - nA IVINSTBY - VIN Standby Current - mA 250 200 150 100 50 0 200 150 100 50 0 50 0 50 100 5 150 10 TJ - Junction Temperature - C Figure 5. 20 25 Figure 6. VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE VIN SHUTDOWN CURRENT vs INPUT VOLTAGE 25 IVINSDN - VIN Shutdown Current - mA 25 IVINSDN - VIN Shutdown Current - mA 15 V IN - Input Voltage - V 20 15 10 5 20 15 10 5 0 0 -50 0 50 100 150 5 10 15 20 25 V IN - Input Voltage - V T J - Junction Temperature - C Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 11 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) CURRENT SENSE CURRENT vs JUNCTION TEMPERATURE VCLK FREQUENCY vs JUNCTION TEMPERATURE 325 13 300 f CLK - VCLK Frequency - kHz IENTRIP - Current Sense Current - mA 14 12 11 10 9 8 275 250 225 200 7 175 -50 6 -50 0 50 100 150 0 50 100 T J - Junction Temperature - C T J - Junction Temperature - C Figure 9. Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE SWITCHING FREQUENCY vs INPUT VOLTAGE 500 500 TONSEL = 2V f SW - Swithching Frequency - kHz fSW - Swithching Frequency - kHz TONSEL = GND 400 300 CH2 200 CH1 100 0 400 CH2 300 CH1 200 100 0 6 8 10 12 14 16 18 20 22 24 26 6 8 V IN - Input Voltage - V 10 12 14 16 18 20 22 24 26 V IN - Input Voltage - V Figure 11. 12 150 Figure 12. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs INPUT VOLTAGE SWITCHING FREQUENCY vs INPUT VOLTAGE 500 500 CH2 400 f SW - Swithching Frequency - kHz f SW - Swithching Frequency - kHz TONSEL = 3.3V 300 CH1 200 100 0 CH2 TONSEL = 5V 400 CH1 300 200 100 0 6 8 10 12 14 16 18 20 22 24 26 6 8 10 V IN - Input Voltage - V 12 14 16 Figure 13. 20 22 24 26 Figure 14. SWITCHING FREQUENCY vs OUTPUT CURRENT SWITCHING FREQUENCY vs OUTPUT CURRENT 500 500 TONSEL = GND TONSEL = 2V f SW - Swithching Frequency - kHz f SW - Swithching Frequency - kHz 18 V IN - Input Voltage - V 400 300 CH2 PWM Only 200 CH1 PWM Only 100 CH2 Auto-skip CH2 OOA CH1 OOA 400 CH2 PWM Only 300 200 CH1 PWM Only CH2 Auto-skip 100 CH2 OOA CH1 OOA CH1 Auto-skip 0 0.001 0.01 0.1 1 CH1 Auto-skip 10 0 0.001 IOUT - Output Current - A 0.01 0.1 1 10 IOUT - Output Current - A Figure 15. Figure 16. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 13 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs OUTPUT CURRENT SWITCHING FREQUENCY vs OUTPUT CURRENT 500 500 400 TONSEL = 5V f SW - Swithching Frequency - kHz f SW - Swithching Frequency - kHz TONSEL = 3.3V CH2 PWM Only 300 CH1 PWM Only 200 CH2 Auto-skip 100 CH2 OOA CH2 PWM Only 400 CH1 PWM Only 300 200 CH2 Auto-skip CH2 OOA 100 CH1 OOA CH1 OOA CH1 Auto-skip CH1 Auto-skip 0 0.001 0.01 0.1 1 0 0.001 10 IOUT - Output Current - A 0.01 0.1 Figure 17. 10 Figure 18. OVP/UVP THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VREG5 OUTPUT VOLTAGE vs OUTPUT CURRENT 150 5.05 140 130 V VREG5 - VREG5 Output Voltage - V V OVP/VUVP - OVP/UVP Threshold - % 1 IOUT - Output Current - A 120 110 100 90 80 70 60 50 40 -50 0 TJ 50 100 - Junction Temperature - C 5.00 4.95 150 4.90 0 20 40 60 80 100 IVREG5 - VREG5 Output Current - m A Figure 19. 14 Figure 20. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) VREG3 OUTPUT VOLTAGE vs OUTPUT CURRENT VREF OUTPUT VOLTAGE vs OUTPUT CURRENT 3.35 2.015 V VREF - VREF Output Voltage - V V VREG3 - VREG3 Output Voltage - V 2.020 3.3 3.25 2.010 2.005 2.000 1.995 1.990 1.985 3.2 1.980 0 20 40 60 80 100 0 IVREG3 - VREG3 Output Current - m A 20 Figure 21. 100 3.360 OOA OOA 5.050 V OUT2 - 3.3-V Output Voltage - V V OUT1 - 5-V Output Voltage - V 80 3.3-V OUTPUT VOLTAGE vs OUTPUT CURRENT 5.075 5.000 60 Figure 22. 5-V OUTPUT VOLTAGE vs OUTPUT CURRENT 5.025 40 IVREF - VREF Output Current - mA Auto-skip PWM Only 4.975 4.950 0.001 0.01 0.1 1 10 3.330 Auto-skip 3.300 PWM Only 3.270 3.240 0.001 IOUT1 - 5-V Output Current - A 0.01 0.1 1 10 IOUT2 - 3.3-V Output Current - A Figure 23. Figure 24. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 15 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 5-V OUTPUT VOLTAGE vs INPUT VOLTAGE 3.3-V OUTPUT VOLTAGE vs INPUT VOLTAGE 3.360 5.050 V OUT2 - 3.3-V Output Voltage - V V OUT1 - 5-V Output Voltage - V 5.075 IO = 0A 5.025 5.000 IO = 6A 4.975 4.950 3.330 IO = 0A 3.300 IO = 6A 3.270 3.240 6 8 10 12 14 16 18 20 22 24 26 6 8 10 V IN - Input Voltage - V Figure 25. 100 Auto-skip VIN=8V h - Efficiency - % h - Efficiency - % 18 20 22 24 26 Auto-skip 80 60 VIN=12V VIN=20V 40 OOA VIN=8V 60 VIN=12V 40 20 VIN=20V OOA PWM Only PWM Only 0 0.001 0.01 0.1 1 10 0 0.001 0.01 0.1 5-V Switcher ON 1 10 IOUT2 - 3.3-V Output Current - A IOUT1 - 5-V Output Current - A Figure 27. 16 16 3.3-V EFFICIENCY vs OUTPUT CURRENT 80 20 14 Figure 26. 5-V EFFICIENCY vs OUTPUT CURRENT 100 12 V IN - Input Voltage - V Figure 28. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) 5-V Load Transient Response 3.3-V Load Transient Response VOUT2 (100mV/div) VOUT1 (100mV/div) IIND (5A/div) IIND (5A/div) IOUT2 (5A/div) IOUT1 (5A/div) Figure 29. Figure 30. 5-V Startup Waveforms 3.3-V Startup Waveforms ENTRIP2 (2V/div) ENTRIP1 (2V/div) VOUT1 (2V/div) VOUT2 (2V/div) PGOOD (5V/div) PGOOD (5V/div) Figure 31. Figure 32. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 17 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 5-V Switchover Waveforms 3.3-V Switchover Waveforms VREG5 (200mV/div) VREG3 (200mV/div) VOUT2 (200mV/div) VOUT1 (200mV/div) Figure 33. Figure 34. 5-V Soft-stop Waveforms 3.3-V Soft-stop Waveforms ENTRIP1 (5V/div) ENTRIP2 (5V/div) VOUT1 (2V/div) VOUT2 (2V/div) PGOOD (5V/div) PGOOD (5V/div) DRVL2 (5V/div) DRVL1 (5V/div) Figure 35. 18 Figure 36. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 APPLICATION INFORMATION PWM Operations The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAPTM mode. D-CAPTM mode does not require external compensation circuit and is suitable for low external component count configuration when used with appropriate amount of ESR at the output capacitor(s). At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes `ON' state. This MOSFET is turned off, or becomes `OFF' state, after internal one shot timer expires. This one shot is determined by VIN and VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control. The MOSFET is turned on again when the feedback point voltage, VFB, decreased to match with internal 2-V reference. The inductor current information is also monitored and should be below the over current threshold to initiate this new cycle. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or the "rectifying" MOSFET is turned on at the beginning of each `OFF' state to keep the conduction loss minimum.The rectifying MOSFET is turned off before the top MOSFET turns on at next switching cycle or when inductor current information detects zero level. In the auto-skip mode or the OOA skip mode, this enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current. Adaptive On-Time Control and PWM Frequency TPS51125 does not have a dedicated oscillator on board. However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time, one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio will be kept as VOUT/VIN technically with the same cycle time. The frequencies are set by TONSEL terminal connection as Table 2. Table 2. TONSEL Connection and Switching Frequency TONSEL CONNECTION SWITCHING FREQUENCY CH1 CH2 GND 200 kHz 250 kHz VREF 245 kHz 305 kHz VREG3 300 kHz 375 kHz VREG5 365 kHz 460 kHz Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 19 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com Loop Compensation From small-signal loop analysis, a buck converter using D-CAPTM mode can be simplified as below. VIN R1 DRVH PWM VFB + + R2 Control logic & Driver Lx Ic IL DRVL Io 2V ESR Vc Voltage Divider RL Switching Modulator Co Output Capacitor Figure 37. Simplifying the Modulator The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM comparator determines the timing to turn on high-side MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle substantially constant. For the loop stability, the 0dB frequency, f0, defined below need to be lower than 1/4 of the switching frequency. f0 = f 1 SW 2p ESR CO 4 (1) TM As f0 is determined solely by the output capacitor's characteristics, loop stability of D-CAP mode is determined by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100 F and ESR in range of 10 m. These will make f0 in the order of 100 kHz or less and the loop will be stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode. Ramp Signal The TPS51125 adds a ramp signal to the 2-V reference in order to improve its jitter performance. As described in the previous section, the feedback voltage is compared with the reference information to keep the output voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle is improved. Therefore the operation becomes less jitter and stable. The ramp signal is controlled to start with 20mV at the beginning of ON-cycle and to become 0 mV at the end of OFF-cycle in steady state. By using this scheme, the TPS51125 improve jitter performance without sacrificing the reference accuracy. 20 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 Light Load Condition in Auto-Skip Operation The TPS51125 automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of VOUT ripple. Detail operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its `valley' touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next `ON' cycle. The ON time is kept the same as that in the heavy load condition. In reverse, when the output current increase from light load to heavy load, switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the threshold between continuous and discontinuous conduction mode) can be calculated as follows; IOUT(LL) = 1 2Lf (VIN - VOUT ) VOUT VIN (2) where f is the PWM switching frequency. Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it decreases almost proportional to the output current from the IOUT(LL) given above. For example, it will be 60 kHz at IOUT(LL)/5 if the frequency setting is 300 kHz. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 21 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com Out-of-AudioTM Light-Load Operation Out-of-AudioTM (OOA) light-load mode is a unique control feature that keeps the switching frequency above acoustic audible frequencies toward virtually no load condition while maintaining best of the art high conversion efficiency. When the Out-of-AudioTM operation is selected, OOA control circuit monitors the states of both MOSFET and force to change into the `ON' state if both of MOSFETs are off for more than 32 s. This means that the top MOSFET is turned on even if the output voltage is higher than the target value so that the output capacitor is tends to be overcharged. The OOA control circuit detects the over-voltage condition and begins to modulate the on time to keep the output voltage regulated. As a result, the output voltage becomes 0.5% higher than normal light-load operation. Enable and Soft Start EN0 is the control pin of VREG5, VREG3 and VREF regulators. Bring this node down to GND disables those three regulators and minimize the shutdown supply current to 10 A. Pulling this node up to 3.3 V or 5 V will turn the three regulators on to standby mode. The two switch mode power supplies (channel-1, channel-2) become ready to enable at this standby mode. The TPS51125 has an internal, 1.6 ms, voltage servo softstart for each channel. When the ENTRIPx pin becomes higher than the enable threshold voltage, which is typically 430 mV, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start up. As TPS51125 shares one DAC with both channels, if ENTRIPx pin becomes higher than the enable threshold voltage while another channel is starting up, soft start is postponed until another channel soft start has completed. If both of ENTRIP1 and ENTRIP2 become higher than the enable threshold voltage at a same time (within 60 s), both channels start up at same time. Table 3. Enabling State EN0 ENTRIP1 ENTRIP2 VREF VREG5 VREG3 CH1 CH2 VCLK GND Don't Care Don't Care Off Off Off Off Off Off R to GND Off Off On On On Off Off Off R to GND On Off On On On On Off Off R to GND Off On On On On Off On Off R to GND On On On On On On On Off Open Off Off On On On Off Off Off Open On Off On On On On Off On Open Off On On On On Off On Off Open On On On On On On On On VREG5/VREG3 Linear Regulators There are two sets of 100-mA standby linear regulators which outputs 5 V and 3.3 V, respectively. The VREG5 serves as the main power supply for the analog circuitry of the device and provides the current for gate drivers. The VREG3 is intended mainly for auxiliary 3.3-V supply for the notebook system during standby mode. Add a ceramic capacitor with a value of at least 33 F and place it close to the VREG5 pin, and add at most 10 F to the VREG3 pin. Total capacitance connected to the VREG3 pin should not exceed 10 F. 22 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 VREG5 Switch Over When the VO1 voltage becomes higher than 4.7 V AND channel-1 internal powergood flag is generated, internal 5-V LDO regulator is shut off and the VREG5 output is connected to VO1 by internal switch over MOSFET. The 510-s powergood delay helps a switch over without glitch. VREG3 Switch Over When the VO2 voltage becomes higher than 3.15 V AND channel-2 internal powergood flag is generated, internal 3.3-V LDO regulator is shut off and the VREG3 output is connected to VO2 by internal switch over MOSFET. The 510-s powergood delay helps a switch over without glitch. Powergood The TPS51125 has one powergood output that indicates 'high' when both switcher outputs are within the targets (AND gated). The powergood function is activated with 2-ms internal delay after ENTRIPx goes high. If the output voltage becomes within +/-5% of the target value, internal comparators detect power good state and the powergood signal becomes high after 510-s internal delay. Therefore PGOOD goes high around 2.5 ms after ENTRIPx goes high. If the output voltage goes outside of +/-10% of the target value, the powergood signal becomes low after 2-s internal delay. The powergood output is an open drain output and is needed to be pulled up outside. Also note that, in the case of Auto-skip or Out-of-AudioTM mode, if the output voltage goes +10% above the target value and the power-good signal flags low, then the loop attempts to correct the output by turning on the low-side driver (forced PWM mode). After the feedback voltage returns to be within +5% of the target value and the power-good signal goes high, the controller returns back to auto-skip mode or Out-of-AudioTM mode. Output Discharge Control When ENTRIPx is low, the TPS51125 discharges outputs using internal MOSFET which is connected to VOx and GND. The current capability of these MOSFETs is limited to discharge slowly. Low-Side Driver The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is represented by its internal resistance, which are 4 for VREG5 to DRVLx and 1.5 for DRVLx to GND. A dead time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input capacitor connected between VREG5 and GND. The average drive current is equal to the gate charge at Vgs = 5 V times switching frequency. This gate drive current as well as the highside gate drive current times 5 V makes the driving power which need to be dissipated from TPS51125 package. High-Side Driver The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by the gate charge at Vgs = 5 V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance, which are 4 for VBSTx to DRVHx and 1.5 for DRVHx to LLx. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 23 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com VCLK for Charge Pump 270-kHz clock signal can be used for charge pump circuit to generate approximately 15-V dc voltage. The clock signal becomes available when EN0 becomes higher than 2.4 V or open state. Example of control circuit is shown in Figure 38. Note that the clock driver uses VO1 as its power supply. Regardless of enable or disable of VCLK, power consumption of the TPS51125 is almost the same. Therefore even if VCLK is not used, one can let EN0 pin open or supply logic `high', as shown in Figure 38, and let VCLK pin open. This approach further reduces the external part count. 3.3V TPS51125 TPS51125 EN0 EN0 Control Input 13 13 GND GND Control Input 15 15 (b) Control by Logic (a) Control by MOSFET switch Figure 38. Control Example of EN0 Master Enable VCLK 18 100nF 100nF VO1 (5V) D0 D1 100nF PGND D2 100nF PGND 15V/10mA D4 1uF PGND Figure 39. 15-V / 10-mA Charge Pump Configuration 24 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 Current Protection TPS51125 has cycle-by-cycle over current limiting control. The inductor current is monitored during the `OFF' state and the controller keeps the `OFF' state during the inductor current is larger than the over current trip level. In order to provide both good accuracy and cost effective solution, TPS51125 supports temperature compensated MOSFET RDS(on) sensing. ENTRIPx pin should be connected to GND through the trip voltage setting resistor, RTRIP. ENTRIPx terminal sources ITRIP current, which is 10 A typically at room temperature, and the trip level is set to the OCL trip voltage VTRIP as below. Note that the VTRIP is limited up to about 205 mV internally. VTRIP (mV ) = RTRIP (kW ) ITRIP (mA ) 9 - 24 (mV ) (3) External leakage current to ENTRIPx pin should be minimized to obtain accurate OCL trip voltage. The inductor current is monitored by the voltage between GND pin and LLx pin so that LLx pin should be connected to the drain terminal of the bottom MOSFET properly. Itrip has 4500 ppm/C temperature slope to compensate the temperature dependency of the RDS(on). GND is used as the positive current sensing node so that GND should be connected to the proper current sensing device, i.e. the source terminal of the bottom MOSFET. As the comparison is done during the `OFF' state, VTRIP sets valley level of the inductor current. Thus, the load current at over current threshold, IOCP, can be calculated in Equation 4. IOCP = (VIN - VOUT ) VOUT VTRIP I V 1 + RIPPLE = TRIP + RDS(on ) 2 RDS(on ) 2 L f VIN (4) In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. Eventually, it ends up with crossing the under voltage protection threshold and shutdown both channels. Over/Under Voltage Protection TPS51125 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON. Also, TPS51125 monitors VOx voltage directly and if it becomes greater than 5.75 V the TPS51125 turns off the top MOSFET driver. When the feedback voltage becomes lower than 60% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 s, TPS51125 latches OFF both top and bottom MOSFETs drivers, and shut off both drivers of another channel. This function is enabled after 2 ms following ENTRIPx has become high. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 25 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com UVLO Protection TPS51125 has VREG5 under voltage lock out protection (UVLO). When the VREG5 voltage is lower than UVLO threshold voltage both switch mode power supplies are shut off. This is non-latch protection. When the VREG3 voltage is lower than (VO2 - 1 V), both switch mode power supplies are also shut off. Thermal Shutdown TPS51125 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150C), TPS51125 is shut off including LDOs. This is non-latch protection. External Parts Selection The external components selection is much simple in D-CAPTM Mode. 1. Determine Output Voltage The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 37. R1 is connected between VFBx pin and the output, and R2 is connected betwen the VFBx pin and GND. Recommended R2 value is from 10 k to 20 k. Determine R1 using equation as below. R1 = (VOUT - 2.0 ) R2 2.0 (5) 2. Choose the Inductor The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable operation. L= 1 IIND(ripple ) f (V IN(max ) - VOUT ) V OUT VIN(max ) = 3 IOUT(max ) f (V IN(max ) - VOUT VIN(max ) ) V OUT (6) The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as follows. IIND(peak ) = VTRIP RDS (on ) + 1 Lf (V IN(max ) - VOUT ) V OUT VIN(max ) (7) 3. Choose the Output Capacitor(s) Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet required ripple voltage. A quick approximation is as shown in Equation 8. ESR = VOUT 20 (mV ) (1 - D ) 2 (V ) IRIPPLE = 20 (mV ) L f 2 (V ) where * * D is the duty cycle the required output ripple slope is approximately 20 mV per tSW (switching period) in terms of VFB terminal voltage (8) 4. Choose the Low-Side MOSFET It is highly recommended that the low-side MOSFET should have an integrated Schottky barrier diode, or an external Schottky barrier diode in parallel to achieve stable operation. 26 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 Layout Considerations Certain points must be considered before starting a layout work using the TPS51125. * TPS51125 has only one GND pin and special care of GND trace design makes operation stable, especially when both channels operate. Group GND terminals of output voltage divider of both channels and the VREF capacitor as close as possible, connect them to an inner GND plane with PowerPad, overcurrent setting resistor, EN0 pull-down resistor and EN0 bypass capacitor as shown in the thin GND line of Figure 40. This trace is named Signal Ground (SGND). Group ground terminals of VIN capacitor(s), VOUT capacitor(s) and source of low-side MOSFETs as close as possible, and connect them to another inner GND plane with GND pin of the device, GND terminal of VREG3 and VREG5 capacitors and 15-V charge-pump circuit as shown in the bold GND line of Figure 40. This trace is named Power Ground (PGND). SGND should be connected to PGND at the middle point between ground terminal of VOUT capacitors. * Inductor, VOUT capacitor(s), VIN capacitor(s) and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Power components of each channel should be at the same distance from the TPS51125. Other small signal parts should be placed on another side (component side). Inner GND planes above should shield and isolate the small signal traces from noisy power lines. * PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible. * VREG5 requires capacitance of at least 33 F and VREG3 requires capacitance of at most 10 F. VREF requires a 220-nF ceramic bypass capacitor which should be placed close to the device and traces should be no longer than 10 mm. * Connect the overcurrent setting resistors from ENTRIPx to SGND and close to the device, right next to the device if possible. * The discharge path (VOx) should have a dedicated trace to the output capacitor; separate from the output voltage sensing trace. When LDO5 is switched over Vo1 trace should be 1.5 mm with no loops. When LDO3 is switched over and loaded Vo2 trace should also be 1.5 mm with no loops. There is no restriction for just monitoring Vox. Make the feedback current setting resistor (the resistor between VFBx to SGND) close to the device. Place on the component side and avoid vias between this resistor and the device. * Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65-mm (25 mils) or wider trace and via(s) of at least 0.5 mm (20 mils) diameter along this trace. * All sensitive analog traces and components such as VOx, VFBx, VREF, GND, EN0, ENTRIPx, PGOOD, TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx, DRVHx and VCLK nodes to avoid coupling. * Traces for VFB1 and VFB2 should be short and laid apart each other to avoid channel to channel interference. * In order to effectively remove heat from the package, prepare thermal land and solder to the package's thermal pad. Three by three or more vias with a 0.33-mm (13 mils) diameter connected from the thermal land to the internal ground plane should be used to help dissipation. This thermal land underneath the package should be connected to SGND, and should NOT be connected to PGND. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 27 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com SGND VIN VIN 220 nF VOUT2 5 3 2 VFB2 VREF VFB1 DRVL2 VOUT1 DRVL1 12 19 TPS51125 VREG5 PowerPAD GND VREG3 PGND PGND 17 15 33 mF 8 15 V OUT 10 mF VCLK Charge Pump SGND UDG-09020 Figure 40. Ground System 28 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 * CH1 Vout divider Driver and switch node traces are shown for CH1 only. TPS51125 Top Layer DRVH1* LL1* CVREF DRVL1* CVREG5 CH2 Vout divider Connection to GND island Connection to GND Connection of Vout Through hole Connection to GND island CVREG3 Inner Layer GND GND island Cout L HS-MOSFET Vout1 To CH1 Vout divider LS-MOSFET To VO1 Cin VIN GND To VO2 Cin Vout2 To CH2 Vout divider HS-MOSFET L Cout Bottom Layer LS-MOSFET Figure 41. PCB Layout Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 29 TPS51125 SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 www.ti.com Application Circuit SGND R1 13kW R2 20kW R4 30kW R3 20kW C6 0.22mF R5 130kW R6 130kW 3.3V/100mA SGND SGND VREF VIN 7 VO2 F 1 VIN 5.5 ~ 28V RI P1 2 EN T 3 VR E EL VF B2 C2 10mF 4 TO NS RI P2 EN T C1 10mF 5 VF B1 VIN 6 VO1 24 PGOOD 23 VBST1 22 R8 100kW C3 10mF 8 VREG3 PGND VREG5 PGND PGND Q1 IRF7821 L1 3.3mH C9 10mF C8 10mF 9 VBST2 C4 0.1mF R7 5.1W C7 0.1mF R9 5.1W TPS51125RGE (QFN24) 10 DRVH2 DRVH1 21 LL1 20 Q3 IRF7821 L2 3.3mH VO2 3.3V/8A VO1 5V/8A 11 LL2 C5 POSCAP 330mF PowerPAD Q2 FDS6690AS DRVL1 VR E VC LK 13 14 15 16 17 18 D G5 VIN PGND GN PGND SK IPS EL VO2_GND EN 0 12 DRVL2 C10 POSCAP 330mF Q4 FDS6690AS 19 VO1_GND PGND PGND SGND VREG5 EN0 5V/100mA S1 C11 33mF R10 620kW C15 100nF C13 100nF VO1 VREF D1 D3 15V/10mA D4 D2 SGND PGND PGND C12 100nF C14 100nF C16 1uF PGND Figure 42. 5-V/8-A, 3.3-V/8-A Application Circuit (245-kHz/305-kHz Setting) Table 4. List of Materials for 5-V/8-A, 3.3-V/8-A Application Circuit MANUFACTURER PART NUMBER C1, C2, C8, C9 SYMBOL 10 F, 25 V Taiyo Yuden TMK325BJ106MM C3 10 F, 6.3 V TDK C2012X5R0J106K C11 33 F, 6.3 V TDK C3216X5RBJ336M C5, C10 330 F, 6.3 V, 25 m Sanyo 6TPE330ML L1, L2 3.3 H, 15.6 A, 5.92 m TOKO FDA1055-3R3M Q1, Q3 30 V, 9.5 m IR IRF7821 Q2, Q4 (1) 30 V, 12 m Fairchild FDS6690AS (1) 30 SPECIFICATION Please use MOSFET with integrated Schottky barrier diode (SBD) for low side, or add SBD in parallel with normal MOSFET. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 TPS51125 www.ti.com SLUS786G - OCTOBER 2007 - REVISED JUNE 2012 REVISION HISTORY Changes from Revision E (May 2011) to Revision F * Page Added Input voltage range parameter, LL1, LL2, pulse width < 20 ns with a value of -5 V to 30 V. ................................... 2 Changes from Revision F (March 2012) to Revision G * Page Added electrostatic discharge ratings in ABSOLUTE MAXIMUM RATINGS table .............................................................. 2 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS51125 31 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 4.25 1.15 8.0 12.0 Q2 TPS51125RGER VQFN RGE 24 3000 330.0 12.4 TPS51125RGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.1 8.0 12.0 Q2 TPS51125RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS51125RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS51125RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS51125RGET VQFN RGE 24 250 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 4.25 B0 (mm) PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51125RGER VQFN RGE 24 3000 367.0 367.0 35.0 TPS51125RGER VQFN RGE 24 3000 370.0 355.0 55.0 TPS51125RGER VQFN RGE 24 3000 367.0 367.0 35.0 TPS51125RGET VQFN RGE 24 250 210.0 185.0 35.0 TPS51125RGET VQFN RGE 24 250 210.0 185.0 35.0 TPS51125RGET VQFN RGE 24 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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