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FAN54040 -- FAN54047 USB-OTG, 1.55 A, Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Features Fully Integrated, High-Efficiency Charger for Single-Cell Li-Ion and Li-Polymer Battery Packs Power Path Circuit Ensures Fast System Startup with a Dead Battery when VBUS is Connected 1.55 A Maximum Charge Current Float Voltage Accuracy: - 0.5% at 25C - 1% from 0 to 125C 5% Input and Charge Current Regulation Accuracy Temperature-Sense Input Prevents Auto-Charging for JEITA Compliance Thermal Regulation and Shutdown 4.2 V at 2.3 A Production Test Mode 5 V, 500 mA Boost Mode for USB OTG 28 V Absolute Maximum Input Voltage 6 V Maximum Input Operating Voltage 2 Programmable through High-Speed I C Interface (3.4 Mb/s) with Fast Mode Plus Compatibility - Input Current - Fast-Charge / Termination Current - Float Voltage - Termination Enable 3 MHz Synchronous Buck PWM Controller with Wide Duty Cycle Range Small Footprint 1 H External Inductor Safety Timer with Reset Control Dynamic Input Voltage Control Very Low Battery Current when Charger Inactive Description 2 The FAN5404X family includes I C controlled 1.55 A USBcompliant switch-mode chargers with power path operation and USB OTG boost operation. Integrated with the charger, the IC supports production test mode, which provides 4.2 V at up to 2.3 A to the system. To facilitate fast system startup, the IC includes a power path circuit, which disconnects the battery from the system rail, ensuring that the system can power up quickly following a VBUS connection. The power path circuit ensures that the system rail stays up when the charger is plugged in, even if the battery is dead or shorted. The charging parameters and operating modes are 2 programmable through an I C Interface that operates up to 3.4 Mbps. The charger and boost regulator circuits switch at 3 MHz to minimize the size of external passive components. The FAN5404X provides battery charging in three phases: conditioning, constant current, and constant voltage. The integrated circuit automatically restarts the charge cycle when the battery falls below a voltage threshold. If the input source is removed, the IC enters a high-impedance mode blocking battery current from leaking to the input. Charge 2 status is reported back to the host through the I C port. Dynamic input voltage control prevents a weak adapter's voltage from collapsing, ensuring charging capability from such adapters. The FAN5404X is available in a 25-bump, 0.4 mm pitch, WLCSP package. VBUS PGND PMID GATE CMID Cell Phones, Smart Phones, PDAs Tablet, Portable Media Players Gaming Device, Digital Cameras CSYS SYS Applications L1 SW CBUS POK_B ILIM FAN5404X External PMOS VBAT CBAT SDA NTC SCL REF DIS STAT SYSTEM LOAD Q5 RREF BATTERY CREF + T AGND All trademarks are the property of their respective owners. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 Figure 1. Typical Application www.fairchildsemi.com FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support February 2015 Part Number Temperature Range Package FAN54040UCX 001 (1) (1) FAN54045UCX Packing Method 000 FAN54041UCX FAN54042UCX PN Bits: IC_INFO[5:3] -40 to 85C 25-Bump, Wafer-Level Chip-Scale Package (WLCSP), 0.4 mm Pitch (1) FAN54046UCX 010 101 Tape and Reel 110 FAN54047UCX 110 Note: 1. Contact Fairchild Sales for availability. Table 1. Feature Comparison Summary Part Number Slave Address Automatic Charge Battery Absent Behavior E1 Pin FAN54040 1101011 Yes Off POK_B FAN54041 1101011 No Off POK_B FAN54042 1101011 Yes On POK_B FAN54045 1101011 No Off ILIM FAN54046 1101011 No On ILIM FAN54047 1101011 Yes On ILIM (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 2 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Ordering Information VBUS PMID Q3 CBUS PGND Q1 Q1B IBUS & VBUS CONTROL AGND CMID Q1A CHARGE PUMP L1 SW CSYS PWM MODULATOR Q2 SYS VBUS OVP POWER OK SYSTEM LOAD PGND GATE SDA External PMOS Q4 CC and CV Battery Charger POK_B ILIM Q4A Q4B I2C INTERFACE VBAT LOGIC AND CONTROL NTC SCL DIS Q5 CBAT TEMP SENSE STAT REF RREF BATTERY CREF + T PMID Q1A Q1B Greater than VBAT ON OFF Less than VBAT OFF ON SYS Q4A Q4B Greater than VBAT ON OFF Less than VBAT OFF ON Figure 2. IC and System Block Diagram Table 2. Recommended External Components Component Description Vendor Parameter Typ. Unit L1 1 H, 20%, 2.2 A, 2016 Taiyo Yuden MAKK2016T1R0M or Equivalent L 1.0 H DCR (Series R) 75 m CBAT, CSYS 10 F, 20%, 6.3 V, X5R, 0603 Murata: GRM188R60J106M TDK: C1608X5R0J106M C 10 F CMID 4.7 F, 10%, 6.3 V, X5R, 0603 Murata: GRM188R60J475K TDK: C1608X5R0J475K 4.7 F CBUS, 1.0 F, 10%, 25 V, X5R, 0603 Murata GRM188R61E105K TDK:C1608X5R1E105M C 1.0 F Q5 PMOS,12 V, 16 m, MLP2x2 Fairchild FDMA905P RDS(ON) 16 m CREF 1 F, 10%, 6.3 V, X5R, 0402 C 1.0 F (2) C Note: 2. 6.3 V rating is sufficient for CMID since PMID is protected from over-voltage surges on VBUS by Q3. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 3 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Block Diagram SDA PGND SW PMID VBUS A1 A2 A3 A4 A5 B2 B3 B4 B5 C2 C3 C4 C5 SYS VBAT NTC D3 D4 D5 E3 E4 A5 A4 A3 A2 A1 B5 B4 B3 B2 B1 C5 C4 C3 C2 C1 D5 D4 D3 D2 D1 E5 E4 E3 E2 E1 SCL B1 DIS GATE C1 STAT D1 D2 POK_B AGND E1 E2 REF E5 Figure 3. Top View Figure 4. Bottom View Pin Definitions Pin # Name Description A1 SDA I C Interface Serial Data. This pin should not be left floating. B1 SCL I C Interface Serial Clock. This pin should not be left floating. C1 DIS Disable. If this pin is held HIGH, Q1 and Q3 are turned off, creating a HIGH Z condition at VBUS and the PWM converter is disabled. D1 STAT E1 POK_B E1 ILIM A2 - D2 PGND Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom of CMID should be as short as possible. E2 AGND Analog Ground. All IC signals are referenced to this node. A3 - C3 SW Switching Node. Connect to output inductor. D3 - E3 SYS System Supply. Output voltage of the switching charger and input to the power path controller. Bypass SYS to PGND with a 10 F capacitor. A4 - C4 PMID Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense. Bypass with a minimum of a 4.7 F, 6.3 V capacitor to PGND. D4 - E4 VBAT Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 10 F capacitor to PGND. VBAT is a power path connection. A5 - B5 VBUS Charger Input Voltage and USB-OTG output voltage. Bypass with a 1 F capacitor to PGND. C5 GATE External MOSFET Gate. This pin controls the gate of an external P-channel MOSFET transistor used to augment the internal ideal diode. The source of the P-channel MOSFET should be connected to SYS and the drain should be connected to VBAT. D5 NTC Thermistor input. The IC compares this node with taps on a resistor divider from REF to inhibit autocharging when the battery temperature is outside of permitted fast-charge limits. E5 REF Reference Voltage. REF is a 1.8 V regulated output. 2 2 Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in progress; can be used to signal the host processor when a fault condition occurs. Power OK (FAN54040-2). Open-drain output that pulls LOW when VBUS is plugged in and the battery has risen above VLOWV. This signal is used to signal the host processor that it can begin to draw significant current. Input Current Limit (FAN54045-7). Controls input current limit in Auto-Charge Mode. When LOW, input current is limited to 100 mA maximum. When HIGH, input current is limited to 500 mA. In 32-Second Mode, the input current limit is set by the IBUSLIM bits. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 4 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VBUS VI VO dVBUS dt Parameter Voltage on VBUS Pin Min. Continuous -0.3 Pulsed, 100 ms Maximum Non-Repetitive -1.0 Max. Unit 28.0 V Voltage on PMID Voltage Pin -0.3 7.0 Voltage on SW, SYS, VBAT, STAT, DIS Pins -0.3 7.0 Voltage on Other Pins -0.3 6.5 Maximum VBUS Slope Above 5.5 V when Boost or Charger Active Electrostatic Discharge Protection Level ESD (4) IEC 61000-4-2 System ESD (3) 4 Human Body Model per JESD22-A114 2000 Charged Device Model per JESD22-C101 500 Air Gap USB Connector Pins (VBUS to GND) Contact 15 V V V/s V kV 8 TJ Junction Temperature -40 +150 C TSTG Storage Temperature -65 +150 C +260 C TL Lead Soldering Temperature, 10 Seconds Note: 3. Lesser of 6.5 V or VI + 0.3 V. 4. Guaranteed if CBUS 1 F and CMID 4. 7F. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VBUS VBAT(MAX) dVBUS dt Parameter Supply Voltage Min. Max. Unit 4 6 V 4.5 V Maximum Battery Voltage when Boost enabled Negative VBUS Slew Rate during VBUS Short Circuit, CMID < 4.7 F, see VBUS Short While Charging TA < 60C 4 TA > 60C 2 V/s TA Ambient Temperature -30 +85 C TJ Junction Temperature (see Thermal Regulation and Protection section) -30 +120 C Thermal Properties Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer 2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperature TA. For measured data, see Table 18. Symbol Parameter Typical Unit JA Junction-to-Ambient Thermal Resistance (see also Figure 18) 50 C/W JB Junction-to-PCB Thermal Resistance 20 C/W (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 5 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Absolute Maximum Ratings Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for TJ=25C. Symbol Parameter Conditions Min. Typ. Max. Unit Power Supplies IVBUS VBUS Current VBUS > VBUS(min), PWM Switching 10 mA VBUS > VBUS(min); VBAT > VOREG IBUSLIM=100 mA 2.5 mA 0C < TJ < 85C, HZ_MODE=1 VBAT < VLOWV, 32S Mode, IREG=0 280 A 10 A IBAT_HZ Battery Discharge Current in HighImpedance Mode DIS=1, or HZ_MODE=1, VBUS=0, 5 V or Floating, VBAT=4.2 V IBUS_HZ Battery Leakage Current to VBUS in High-Impedance Mode DIS=1, or HZ_MODE=1, VBUS Shorted to Ground, VBAT=4.2 V -5.0 3.5 4.4 V TA=25C -0.5 +0.5 % -1 +1 % 1550 mA 390 mA -5 +5 % Weak Battery Threshold Range 3.4 3.7 V Weak Battery Threshold Accuracy -5 +5 % <1 -0.2 A Charger Voltage Regulation Charge Voltage Range VOREG Charge Voltage Accuracy TJ=0 to 125C Charging Current Regulation IOCHRG Output Charge Current Range VLOWV < VBAT < VOREG Charge Current Accuracy IO_LEVEL=0 IO_LEVEL=0 550 IO_LEVEL=1 290 340 Weak Battery Detection VLOWV Weak Battery Deglitch Time Rising Voltage, 2 mV Overdrive 30 ms Logic Levels : DIS, SDA, SCL VIH High-Level Input Voltage VIL Low-Level Input Voltage IIN Input Bias Current 1.05 Input Tied to GND or VBUS V 0.01 0.4 V 1.00 A mA Charge Termination Detection Termination Current Range I(TERM) Termination Current Accuracy VBAT > VOREG - VRCH, VBUS > VSLP 50 400 ITERM Setting < 100 mA -15 +15 ITERM Setting > 200 mA -5 +5 Termination Current Deglitch Time 30 % ms Power Path (Q4) Control ILIN VTHSYS Power Path Max. Charge Current VBAT to SYS Threshold for Q4 and Gate Transition While Charging IO_LEVEL=1 290 340 390 mA IBUSLIM > 01, IOCHARGE < 02 IO_LEVEL=0 400 450 510 mA IBUSLIM > 01, IOCHARGE > 02 IO_LEVEL=0 650 725 800 mA (SYS-VBAT) Falling -6 -5 -3 mV (SYS-VBAT) Rising -1 +1 2 mV 4.116 4.200 4.284 V Production Test Mode VBAT(PTM) Production Test Output Voltage 1 mA < IBAT < 2 A, VBUS=5.5 V IBAT(PTM) Production Test Output Current 20% Duty with Max. Period 10 ms 2.3 A Continued on the following page... (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 6 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Electrical Specifications Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for TJ=25C. Symbol Parameter Conditions Min. Typ. Max. Unit Input Power Source Detection T1 T1 (0C) Temperature Threshold 71.9 73.9 75.9 T2 T1 (10C) Temperature Threshold 62.6 64.6 66.6 T3 T1 (45C) Temperature Threshold 31.9 32.9 34.9 T4 T1 (60C) Temperature Threshold 21.3 23.3 25.3 % of VREF Input Power Source Detection VIN(MIN)1 VBUS Input Voltage Rising To Initiate and Pass VBUS Validation 4.29 4.42 V VIN(MIN)2 Minimum VBUS during Charge During Charging 3.71 3.94 V tVBUS_VALID VBUS Validation Time 30 ms VBUS Control Loop VBUSLIM -3 VBUS Loop Setpoint Accuracy +3 % Input Current Limit IBUSLIM Charger Input Current Limit Threshold IBUSLIM Set to 100 mA 88 93 98 IBUSLIM Set to 500 mA 450 475 500 mA VREF Bias Generator VREF Bias Regulator Voltage VBUS > VIN(MIN) Short-Circuit Current Limit 1.8 V 2.5 mA Battery Recharge Threshold VRCH Recharge Threshold Below V(OREG) Deglitch Time VBAT Falling Below VRCH Threshold 100 120 150 130 mV ms STAT, POK_B Output VSTAT(OL) STAT Output Low ISTAT=10 mA ISTAT(OH) STAT High Leakage Current VSTAT=5 V 0.4 V 1 A Battery Detection IDETECT Battery Detection Current before (5) Charge Done (Sink Current) tDETECT Battery Detection Time Begins after Termination Detected and VBAT < VOREG -VRCH -0.8 mA 262 ms Sleep Comparator VSLP Sleep-Mode Entry Threshold, VBUS - VBAT 2.3 V < VBAT < VOREG, VBUS Falling 0 0.04 0.10 180 250 130 225 V Power Switches (see Figure 2) Q3 On Resistance (VBUS to PMID) RDS(ON) ISYNC IIN(LIMIT)=500 mA Q1 On Resistance (PMID to SW) Q2 On Resistance (SW to GND) 150 225 Q4 On Resistance (SYS to VBAT) VBAT=4.2 V 70 100 Synchronous to Non-Synchronous (6) Current Cut-Off Threshold Low-Side MOSFET (Q2) Cycle-byCycle Current Limit 140 m m mA Continued on the following page... (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 7 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Electrical Specifications (Continued) Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for TJ=25C. Symbol Parameter Conditions Min. Typ. Max. Unit 2.7 3.0 3.3 MHz 100 % Charger PWM Modulator fSW Oscillator Frequency DMAX Maximum Duty Cycle DMIN Minimum Duty Cycle 0 % Boost Mode Operation (OPA_MODE=1, HZ_MODE=0) VBOOST Boost Output Voltage at VBUS IBAT(BOOST) Boost Mode Quiescent Current ILIMPK(BST) Q2 Peak Current Limit UVLOBST 2.5 V < VBAT < 4.5 V, ILOAD from 0 to 200 mA 4.80 3.0 V < VBAT < 4.5 V, ILOAD from 0 to 500 mA 4.77 5.20 V PFM Mode, VBAT=3.6 V, ILOAD=0 1350 Minimum Battery Voltage for Boost Operation 5.07 5.07 5.20 250 350 A 1550 1950 mA While Boost Active 2.32 To Start Boost Regulator 2.48 Normal Operation 500 k VBUS Validation 100 2.70 V VBUS Load Resistance RVBUS VBUS to PGND Resistance Protection and Timers VBUSOVP ILIMPK(CHG) VSHORT ISHORT TSHUTDWN VBUS Over-Voltage Shutdown VBUS Rising Hysteresis VBUS Falling Q1 Cycle-by-Cycle Peak Current Limit Charge Mode Battery Short-Circuit Threshold VBAT Rising 6.09 1.95 Hysteresis 6.49 Thermal Shutdown Threshold VBAT < VSHORT (7) (7) (7) TCF Thermal Regulation Threshold tINT Detection Interval (8) V 100 mV 3 A 2.00 2.05 100 Linear Charging Current Hysteresis 6.29 Power Path 13 Linear 30 TJ Rising 145 TJ Falling 25 Charge Current Reduction Begins 120 V mV mA C C 2.1 s Charger Enabled 20.5 25.2 28.0 Charger Disabled 18.0 25.2 34.0 13.5 15.0 min 25 % t32S 32-Second Timer t15MIN 15-Minute Timer 15-Minute Mode (FAN54040, FAN54042, FAN54046, FAN54047) 12.0 tLF Low-Frequency Timer Accuracy Charger Inactive -25 s Notes: 5. Negative current is current flowing from the battery to VBUS (discharging the battery). 6. Q2 always turns on for 60 ns, then turns off if current is below ISYNC. 7. Guaranteed by design; not tested in production. 8. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 8 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Electrical Specifications (Continued) Guaranteed by design. Symbol fSCL tBUF tHD;STA tLOW Parameter SCL Clock Frequency BUS-free Time between STOP and START Conditions START or Repeated START Hold Time SCL LOW Period Conditions Min. tSU;STA tSU;DAT tHD;DAT tRCL SCL HIGH Period Repeated START Setup Time Data Setup Time Data Hold Time SCL Rise Time Max. Standard Mode 100 Fast Mode 400 Fast Mode Plus 1000 High-Speed Mode, CB < 100 pF 3400 High-Speed Mode, CB < 400 pF 1700 Unit kHz Standard Mode 4.7 Fast Mode 1.3 Fast Mode Plus 0.5 Standard Mode 4 s Fast Mode 600 ns Fast Mode Plus 260 ns High-Speed Mode 160 ns Standard Mode 4.7 s Fast Mode 1.3 s Fast Mode Plus 0.5 s High-Speed Mode, CB < 100 pF 160 ns High-Speed Mode, CB < 400 pF 320 ns s 4 s Fast Mode 600 ns Fast Mode Plus 260 ns High-Speed Mode, CB < 100 pF 60 ns High-Speed Mode, CB < 400 pF 120 ns Standard Mode 4.7 s Fast Mode 600 ns Fast Mode Plus 260 ns High-Speed Mode 160 ns Standard Mode 250 Fast Mode 100 Fast Mode Plus 50 High-Speed Mode 10 Standard Mode tHIGH Typ. ns Standard Mode 0 3.45 s Fast Mode 0 900 ns Fast Mode Plus 0 450 ns High-Speed Mode, CB < 100 pF 0 70 ns High-Speed Mode, CB < 400 pF 0 150 ns Standard Mode 20+0.1CB 1000 Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 ns Continued on the following page... (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 9 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support I2C Timing Specifications Guaranteed by design. Symbol tFCL tRCL1 tRDA tFDA tSU;STO CB Parameter SCL Fall Time Rise Time of SCL after a Repeated START Condition and after ACK Bit SDA Rise Time SDA Fall Time Stop Condition Setup Time Conditions Typ. Max. Standard Mode 20+0.1CB 300 Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB < 100 pF 10 40 High-Speed Mode, CB < 400 pF 20 80 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 Standard Mode 20+0.1CB 1000 Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 Standard Mode 20+0.1CB 300 Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 Unit ns ns ns ns High-Speed Mode, CB < 100 pF 10 80 High-Speed Mode, CB < 400 pF 20 160 Standard Mode 4 s Fast Mode 600 ns Fast Mode Plus 120 ns High-Speed Mode 160 Capacitive Load for SDA and SCL (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 Min. ns 400 pF www.fairchildsemi.com 10 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support I2C Timing Specifications (Continued) tF tSU;STA tBUF SDA tR TSU;DAT tHD;STO tHIGH SCL tLOW tHD;STA tHD;DAT tHD;STA REPEATED START START STOP START 2 Figure 5. I C Interface Timing for Fast and Slow Modes tFDA tRDA REPEATED START tSU;DAT STOP SDAH tSU;STA tRCL1 tFCL tRCL tSU;STO tHIGH SCLH tLOW tHD;STA REPEATED START tHD;DAT note A = MCS Current Source Pull-up = RP Resistor Pull-up Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. 2 Figure 6. I C Interface Timing for High-Speed Mode (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 11 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Timing Diagrams Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25C. 800 140 4.5 VBUS 5.0 VBUS 700 5.5 VBUS Battery Charge Current (mA) Battery Charge Current (mA) 130 120 110 100 90 600 500 400 4.5 VBUS 300 5.0 VBUS 5.5 VBUS 200 80 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 2.7 4.3 2.9 3.1 Figure 7. Battery Charge Current vs. VBUS with IBUSLIM=100 mA 3.5 3.7 3.9 4.1 4.3 Figure 8. Battery Charge Current vs. VBUS with IBUSLIM=500 mA 95 90 90 88 85 86 Efficiency (%) Efficiency (%) 3.3 Battery Voltage VBAT (V) Battery Voltage VBAT (V) 80 75 84 82 4.5VBUS, 3.9VBAT 4.5 VBUS 70 5.0VBUS, 3.54VBAT 80 5.0 VBUS 5.0VBUS, 4.2VBAT 5.5 VBUS 5.5VBUS, 3.9VBAT 65 78 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 550 Battery Voltage VBAT (V) 950 1150 1350 1550 Battery Charge Current I BAT (mA) Figure 10. Efficiency vs. Charging Current, IBUSLIM=No Limit Figure 9. Efficiency vs. VBUS, IBUSLIM=500 mA, ISYS=0 (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 750 www.fairchildsemi.com 12 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Charge Mode Typical Characteristics Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25C. Figure 11. Charger Startup at VBUS Plug-In, 100 mA IBUSLIM, 3.2 VBAT, 100 SYS Load Figure 12. Charger Startup at VBUS Plug-In, 500 mA IINBUSLIM, 3.2 VBAT, 100 SYS Load Figure 13. Charger Startup at VBUS Plug-In Using 300 mA Current Limited Source, 500 mA IBUSLIM, 3.2 VBAT, 50 SYS Load Figure 14. Charger Startup with HZ Bit Reset, 500 mA IBUSLIM, 950 mA ICHARGE, 50 SYS Load (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 13 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Charge Mode Typical Characteristics Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25C. Figure 15. Battery Removal / Insertion while Charging, TE=0, 3.9 VBAT, ICHRG=950 mA, IBUSLIM=No Limit, 50 SYS Load Figure 16. Battery Removal / Insertion when Charging, TE=1, 3.9 VBAT, ICHRG=950 mA, IBUSLIM=No Limit, 50 SYS Load Figure 17. No Battery at VBUS Power-Up, FAN54040, 100 SYS Load, 1 k VBAT Load Figure 18. No Battery at VBUS Power-Up, FAN54042, 100 SYS Load, 1 k VBAT Load (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 14 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Charge Mode Typical Characteristics 1,000 2.00 800 1.80 VREF Output Voltage (V) High-Z Mode Input Current (A) Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25C. 600 400 -30C 200 1.60 1.40 1.20 -30C +25C +25C +85C +85C 0 1.00 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 0 VBUS Input Voltage (V) 1 2 3 4 5 VREF Load Current (mA) Figure 19. HZ Mode VBUS Current vs. Temperature, 3.7 VBAT Figure 20. VREF vs. Load Current, Over-Temperature, 5.0 VBUS Figure 21. Charging vs. Temperature (NTC), +30C to -10C Figure 22 Charging vs. Temperature (NTC), +30C to +70C 3.7 VBAT, ICHRG=950 mA, No IBUSLIM, 100 SYS Load 3.7 VBAT, ICHRG=950 mA, No IBUSLIM, 100 SYS Load (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 15 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Charge Mode Typical Characteristics A 2.0 A GSM pulse applied at VBAT with 5 s rise / fall time. Simultaneous to GSM pulse, 50 additional load applied at SYS. Figure 23. 2.0 A GSM Pulse Response, IBUSLIM=500 mA Control, ICHRG=950 mA, 3.7 VBAT, OREG=4.2 V (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 Figure 24. 2.0 A GSM Pulse Response, IBUSLIM=500 mA, ICHRG=950 mA, 3.7 VBAT, OREG=4.2 V, 200 mA Source Current Limit www.fairchildsemi.com 16 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support GSM Typical Characteristics 100 100 95 95 90 90 Efficiency (%) Efficiency (%) Unless otherwise specified, using circuit of Figure 1, VBAT=3.6 V, TA=25C. 85 -10C, 3.6VBAT 80 2.7VBAT 80 85 +25C, 3.6VBAT 3.6VBAT +85C, 3.6VBAT 4.2VBAT 75 75 0 100 200 300 400 0 500 100 200 300 400 500 VBUS Load Current (mA) VBUS Load Current (mA) Figure 25. Efficiency vs. IBUS Over VBAT Figure 26. Efficiency vs. IBUS Over-Temperature, 3.6 VBAT 5.15 30 2.7VBAT 3.6VBAT 25 4.2VBAT 5.05 VBUS Ripple (mVpp) Output Voltage VBUS (V) 5.10 5.00 4.95 20 15 10 2.7VBAT 4.90 5 4.85 0 3.6VBAT 4.2VBAT 0 100 200 300 400 500 0 100 VBUS Load Current (mA) 200 300 400 500 VBUS Load Current (mA) Figure 27. Regulation vs. IBUS Over VBAT Figure 28. Output Ripple vs. IBUS Over VBAT 350 10 +25C 300 +85C HZ Mode Battery Current (A) OTG/Boost Quiescent Current (A) -30C 250 200 150 8 6 4 -30C 2 +25C +85C 100 0 2 2.5 3 3.5 4 4.5 5 2 Battery Voltage, VBAT (V) 3 3.5 4 4.5 5 Battery Voltage, VBAT (V) Figure 29. Quiescent Current (IQ) vs. VBAT OverTemperature (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 2.5 Figure 30. Battery Discharge Current vs. VBAT, HZ / Sleep Mode www.fairchildsemi.com 17 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Boost Mode Typical Characteristics Unless otherwise specified, using circuit of Figure 1, VBAT=3.6 V, TA=25C. Figure 31. OTG Startup, 50 Load, 3.6 VBAT External / Additional 10 f on VBUS Figure 32. OTG VBUS Overload Response Figure 33. Load Transient, 20-200-20 mA IBUS, tRISE/FALL=100 ns Figure 34. Line Transient, 50 Load, 3.9-3.33.9 VBAT, tRISE/FALL=10 s (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 18 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Boost Mode Typical Characteristics When charging batteries with a current-limited input source, such as USB, a switching charger's high efficiency over a wide range of output voltages minimizes charging time. Battery Charging Curve If the battery voltage is below VSHORT, a linear current source pre-charges the battery until VBAT reaches VSHORT. The PWM charging circuit is then started and the battery is charged with a constant current if sufficient input power is available. The current slew rate is limited to prevent overshoot. FAN5404X combines a highly integrated synchronous buck regulator for charging with a synchronous boost regulator, which can supply 5 V to USB On-The-Go (OTG) peripherals. The FAN5404X employs synchronous rectification for both the charger and boost regulators to maintain high efficiency over a wide range of battery voltages and charge states. The FAN5404X is designed to work with a current-limited input source at VBUS. During the current regulation phase of charging, IBUSLIM or the programmed charging current limits the amount of current available to charge the battery and power the system. The effect of IBUSLIM on ICHARGE can be seen in Figure 36. Charge Mode: Charges a single-cell Li-ion or Li-polymer battery. 2. Boost Mode: Provides 5 V power to USB-OTG with an integrated synchronous rectification boost regulator, using the battery as input. 3. 4. ICHARGE VBATMIN ITERM VSHORT ISHORT Production Test Mode This mode provides 4.2 V output on VBAT and supplies a load current of up to 2.3 A. ISHORT CONSTANT CONSTANT PRECHARGE CHARGE CURRENT (CC) VOLTAGE (CV) RECHARGE ICHARGE Current Charging Figure 35. Charge Curve, ICHARGE Not Limited by IINLIM In Charge Mode, FAN5404X employs six regulation loops: 1. Input Current: Limits the amount of current drawn from VBUS. This current is sensed internally and can be 2 programmed through the I C interface. VFLOAT ICHARGE 2. Charging Current: Limits the maximum charging current. This current is sensed using an internal sense MOSFET. IO_LEVEL 4. IBAT IO_LEVEL High-Impedance Mode: Both the boost and charging circuits are OFF in this mode. Current flow from VBUS to the battery or from the battery to VBUS is blocked in this mode. This mode consumes very little current from VBUS or the battery. Charge Mode 3. VBAT VFLOAT VBAT IB BATTERY VOLTAGE DECAY 1. BATTERY VOLTAGE DECAY The FAN5404X has four operating modes: AT VBATMIN VBUS Voltage: This loop is designed to prevent the input supply from being dragged below VBUSLIM (typically 4.5 V) when the input power source is current limited. An example of this would be a travel charger. This loop cuts back the current when VBUS approaches VBUSLIM, allowing the input source to run in current limit. VSHORT ITERM ISHORT ISHORT CONSTANT CONSTANT PRECHARGE CHARGE CURRENT (CC) VOLTAGE (CV) RECHARGE Input Current Limited Charging Charge Voltage: The regulator is restricted from exceeding this voltage. As the internal battery voltage rises, the battery's internal impedance works in conjunction with the charge voltage regulation to decrease the amount of current flowing to the battery. Battery charging is completed when the current through Q4 drops below the ITERM threshold. Figure 36. Charge Curve, IBUSLIM Limits ICHARGE 5. Power Path: When VBAT is below VBATMIN, Q4 operates as a linear current source and modulates its current to ensure that the voltage on SYS stays above 3.4 V. Assuming that VOREG is programmed to the cell's fully charged "float" voltage, the current that the battery accepts with the PWM regulator limiting its output (sensed at VBAT) to VOREG declines and the charger enters the voltage regulation phase of charging. When the current declines to the programmed ITERM value, the charge cycle is complete. Charge current termination can be disabled by resetting the TE bit (REG1[3]). 6. Temperature: If the IC's junction temperature reaches 120C, charge current is reduced until the IC's temperature is below 120C. The charger output or "float" voltage can be programmed by the OREG bits from 3.5 V to 4.44 V in 20 mV increments, as shown in Table 4. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 19 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Circuit Description / Overview Charge Current Limit (IOCHARGE) Table 3. Programmable Charging Parameters Table 5. IOCHARGE Current as Function of IOCHARGE Bits (REG4 [6:3]) Parameter Name Register Output Voltage Regulation VOREG REG2[7:2] Battery Charging Current Limit IOCHRG REG4[6:3] Input Current Limit IINLIM REG1[7:6] Charge Termination Limit ITERM REG4[2:0] Weak Battery Voltage VLOWV REG1[5:4] DEC BIN HEX IOCHARGE (mA) 0 0000 0 550 1 0001 1 650 2 0010 2 750 3 0011 3 850 4 0100 4 950 Table 4. OREG Bits (OREG[7:2]) vs. Charger VOUT (VOREG) Float Voltage 5 0101 5 1,050 Decimal Hex VOREG 6 0110 6 1,150 Decimal Hex VOREG 7 0111 7 1,250 0 00 3.50 24 18 3.98 8 1000 8 1,350 1 01 3.52 25 19 4.00 9 1001 9 1,450 2 02 3.54 26 1A 4.02 10-15 1010-1111 A-F 1,550 3 03 3.56 27 1B 4.04 4 04 3.58 28 1C 4.06 5 05 3.60 29 1D 4.08 6 06 3.62 30 1E 4.10 7 07 3.64 31 1F 4.12 8 08 3.66 32 20 4.14 9 09 3.68 33 21 4.16 The IC uses a current-mode PWM controller to regulate the output voltage and battery charge currents. The synchronous rectifier (Q2) has a negative current limit that turns off Q2 at 140 mA to prevent current flow from the battery. 10 0A 3.70 34 22 4.18 Termination Current Limit 11 0B 3.72 35 23 4.20 12 0C 3.74 36 24 4.22 Current charge termination is enabled when TE (REG1[3])=1. Typical termination current values are given in Table 6. 13 0D 3.76 37 25 4.24 14 0E 3.78 38 26 4.26 15 0F 3.80 39 27 4.28 16 10 3.82 40 28 4.30 17 11 3.84 41 29 4.32 18 12 3.86 42 2A 4.34 19 13 3.88 43 2B 4.36 20 14 3.90 44 2C 4.38 21 15 3.92 45 2D 4.40 22 16 3.94 46 2E 4.42 23 17 3.96 47 - 63 2F-3F 4.44 When the IO_LEVEL bit is set (default), the IOCHARGE bits are ignored and charge current is set to 340 mA. PWM Controller in Charge Mode Table 6. Termination Current as Function of ITERM Bits (REG4[2:0]) or PC_IT Bits (REG7[2:0] ITERM Bits or PC_IT Bits Termination Current (mA) 0 1 2 3 4 5 6 7 50 100 150 200 250 300 350 400 Note: 9. Default settings are denoted by bold typeface. Provided DIS, CE# and HZ_MODE are LOW, a new charge cycle begins when one of the following occurs: When the charge current falls below ITERM; PWM charging stops, but the STAT pin remains LOW. The STAT pin then goes HIGH and the STATUS bits change to CHARGE DONE (10), provided the battery and charger are still connected. 1. The battery voltage falls below VOREG - VRCH after charge termination has occurred. 2. Any I C write occurs causing the T32 s timer to run. A post-charging feature, "top-off" charging, is available to continue the battery charging to a lower charge current to maximize battery capacity. The PC_EN bit must be set to 1 before the battery charging current reaches the termination current ITERM for normal charging. The post-charging termination current is set by the PC_IT[2:0] bits, as shown in Table 6. If PC_EN is set to 1; right after the normal charging is ended as described above, post charging is started with PC_ON monitor bit set to 1. Once the current reaches the 2 Products that include the auto-charge feature also begin charging if: 3. VBUS Power-on-Reset (POR) occurs and the battery voltage is below the weak battery threshold (VLOWV). (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 20 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support The following charging parameters can be programmed by 2 the host through I C: During post-charging, the STAT pin is HIGH, indicating that the charge current is below the ITERM level. To exit postcharging, one of the following must occur: a V BUS POR, the POK_B cycled when VBAT <3.0 V, or the CE# or HZ_Mode bit cycled. The POK_B signal can be used to keep the system in a lowpower state, preventing excessive loading from the system while attempting to charge a depleted battery. Table 7. VBATMIN Thresholds to Exit Power Path Mode Safety Timer At the beginning of charging, the IC starts a 15-minute timer (t15MIN ). When this timer times out, charging is terminated. 2 Writing to any register through I C stops and resets the t15MIN timer, which in turn starts a 32-second timer (t32S). Setting the TMR_RST bit (REG0[7]) resets the t32S timer. If the t32S timer times out; charging is terminated, the registers are set to their default values, and charging resumes using the default values with the t15MIN timer running. VBATMIN (V) 100 500 800 No Limit 3.4 3.3 3.2 3.2 After VBAT reaches VBATMIN, Q4 closes and is used as a 2 current-sense element to limit ICHARGE per the I C register settings by limiting the PWM modulator's current (Full PWM Mode). During PWM Mode, if SYS drops more than 5 mV (VTHSYS) below VBAT, Q4 and Q5 are turned on (GATE is pulled LOW). Once SYS voltage becomes higher than VBAT, Q5 is turned off and Q4 again serves as the current-sense element to limit IOCHARGE. Normal charging is controlled by the host with the t32S timer running to ensure that the host is alive. Charging with the t15MIN timer running is used for charging unattended by the host. If the t15MIN timer expires, the IC turns off the charger and indicates a timer fault (110) on the FAULT bits (REG0[2:0]). This sequence prevents overcharge if the host fails to reset the t32S timer. VBUS POR / Non-Compliant Charger Rejection Q4 and Q5 are both turned on when the IC enters SLEEP Mode (VBUS < VBAT). 256 ms after VBUS is connected, the IC pulses the STAT pin and sets the VBUS_CON bit. Before starting to supply current, the IC applies a 110 load from VBUS to GND. VBUS must remain above VIN(MIN)1 and below VBUSOVP for tVBUS_VALID (32 ms) before the IC initiates charging or supplies power to SYS. The VBUS validation sequence always occurs before significant current is drawn from VBUS (for example, after a VBUS OVP fault or a VRCH recharge initiation). tVBUS_VALID ensures that unfiltered 50/60 Hz chargers and other non-compliant chargers are rejected. POK_B pulls LOW once VBAT reaches VLOWV, and remains LOW as long as the IC is in Full PWM Mode. The IC remains in Full PWM Mode as long as VBAT > 3.0 V, at which point, the IC enters Power Path Charging Mode. Startup with a Dead Battery At VBUS POR, a 2 k load is applied to VBAT for 256 ms to discharge any residual system capacitance in case the battery is absent or its discharge protection switch is open. USB-Friendly Boot Sequence If VBAT < VLOWV, all registers are reset to default values and the IC charges in T15Min Mode. If VBAT < VSHORT, the SAFETY register is reset to its default value and the Battery Detection test below is performed. At VBUS POR, when the battery voltage is above the weak battery threshold (VLOWV); the IC operates in accordance with 2 its I C register settings. If VBAT < VLOWV and t32s is not running, the IC sets all registers to their default values and begins to deliver power to SYS. Battery Detection If VBAT is below VSHORT when charging is enabled, the DBAT_B bit is reset and the IC (except FAN54045 and FAN54046) performs an addition battery detection test. After VBAT rises above VSHORT, PWM charging begins (when CE# = 0) with the float voltage (VOREG) temporarily set to 4 V. If the battery voltage exceeds 3.7 V within 32 ms of the beginning of PWM charging, the battery is absent. If battery absence is detected: 1. STAT pulses, with FAULT bits set to 111, and the NOBAT bit is set. 2. For FAN54040 only; the t15MIN timer is disabled until VBUS is removed, IDLE state is entered, and POK_B remains HIGH. 3. The IC bypasses the protection switch close test below, since no battery is present. FAN54040, FAN54042, and FAN54047 feature auto-charge, which allow these parts to deliver charge to the battery prior to receiving host commands. FAN54041 does not automatically initiate charging at V BUS POR. Instead, it waits in IDLE state for the host to initiate 2 charging through I C commands. While in IDLE state, Q4 and Q5 are on. This allows the system to run through a separate power path without requiring an additional disconnection MOSFET. Power Path Operation As long as VBAT < VBATMIN, Q4 operates as a linear current source, (Power Path Mode) with its current limited to 340 mA. The IC then regulates SYS to 3.54 V and attempts to charge the battery with as much current as possible with the available IBUSLIM input current, without allowing SYS to drop below 3.4 V. This ensures that system power always receives first priority from a limited input supply. During this (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 IBUSLIM (mA) The FAN54042 and FAN54047 continue to charge. If VBAT remained below 3.7 V during the initial 32 ms period, Power Path Mode charging continues to ensure that the www.fairchildsemi.com 21 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support time, POK_B is HIGH. If VBAT < VSHORT, Q4's current is further reduced to about 13 mA (ISHORT) when IBUSLIM is set to 100 or 500 mA. For all other input current limits, ISHORT current is approximately 30 mA. threshold for post-charging completion, PWM charging stops and PC_ON bit changes back to 0. 1. Once the host processor begins writing to the IC, charge parameters are set by the host, which must continually reset the t32S timer to continue charging using the programmed charging parameters. If VBAT is less than 3.4 V, VSYS is set to 4 V, and Power Path charging continues until VBAT has exceeded 3.4 V for at least 128 ms. Charging continues until: 2. VBAT has dropped below 3.2 V for at least 32 ms. Once this occurs, VSYS returns to the OREG register setting (default 3.54 V). 3. VBAT has again risen above VBATMIN for at least 4 ms. If t32S times out; the register defaults are loaded, the FAULT bits are set to 110, STAT is pulsed, and charging continues with default charge parameters in T15MIN Mode for the FAN54040, FAN54042, and FAN54047. POK_B (see Table 8) The POK_B pin and bit are intended to provide feedback to the baseband processor that the battery is strong enough to allow the device to fully function. Whenever the IC is operating in Power Path Mode, POK_B is HIGH. On exiting Power Path Mode, POK_B remains HIGH until VBAT > VLOWV. Reg1[5:4] sets the VLOWV threshold. After these three events, PWM Mode is entered and the IC sets the DBAT_B bit. If the host sets the DBAT_B bit (Reg2[1]), events 1 and 2 above are skipped and PWM Mode is entered once VBAT rises above VBATMIN. In a typical application, as soon as the host processor has cleared its UVLO threshold (typically 3.3 V), the host's low level software would set the IBUSLIM and IOCHARGE registers to charge the battery more rapidly above V BATMIN as soon as the host determines that more than 100 mA is available through VBUS (see Figure 37). The STAT pin pulses any time the POK_B pin changes. Table 8. Q4, Q5, POK_B, and GATE Operation vs. Charging Mode Q4 CC-CV Control VBUS VBAT VSYS Power Path Mode: Maintain VSYS > 3.4 V Valid < VBATMIN <3.4 Linear OFF HIGH HIGH Power Path Mode: Limit ICHARGE < 340 mA Valid < VBATMIN > 3.4 Linear OFF HIGH HIGH PWM Mode. Q4 Senses Current for ICHARGE Valid OFF <VBAT > VBATMIN and < VLOWV > VLOWV X Q4 Q5 GATE POK_B X ON OFF HIGH X ON ON LOW HIGH LOW HIGH Note: 10. POK_B remains LOW until Q4 returns to Power Path Mode. Q4 and Q5 are both ON if VSYS < VBAT and CE# = 0. If CE# = 1 and VSYS < VBAT, Q5 is OFF and Q4 blocks current flow from VBAT to SYS. Table 9. Q4, Q5 Operation as a Function of Relationship between VBUS and VBAT PWM Charger CE# VBUS VBAT Q4 Q5 GATE ON PWM Mode 0 Valid < VSYS, >VBATMIN ON OFF HIGH ON PWM Mode 0 Valid > VSYS, >VBATMIN ON ON LOW ON Disabled 1 Valid X OFF OFF HIGH ON Power Path Charging 0 Valid 2 V < VBAT < VBATMIN Linear OFF HIGH OFF 30 mA Linear Charging X Valid < 2 VBAT ON ON LOW OFF OFF X X X ON ON LOW (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 22 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support battery's discharge protection switch has closed before exiting Power Path Mode: FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support System Wake-up Load Low-level software Determine USB power available Battery Installed? NO HALT YES Set Safety Register Set IINLIM per USB power available, reset IO_LEVEL and set IOCHARGE bits NO Set TMR_RST bit every 10 sec. DEADBAT bit SET? NO 2 minutes elapsed? YES YES Set all charge parameters SET DEADBAT bit YES NO POK_B = 0? YES Load full functionality Figure 37. Recommended Host Software Sequence when Booting with Dead Battery (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 23 The host processor can disable temperature-driven control of charging parameters by writing 1 to the TEMP_DIS bit. Since TEMP_DIS is reset whenever the IC resets its registers, the temperature controls are enforced whenever the IC is auto-charging, since auto-charge is always preceeded by a reset of registers. The FAN5404X reduces the maximum charge current and termination voltage if an NTC measuring battery temperature (TBAT) indicates that it is outside the fast-charging limits (T2 1 to T3), as described in the JEITA specification . There are four temperature thresholds that change battery charger operation: T1, T2, T3, and T4, shown in Table 10. To disable the thermistor circuit, tie the NTC pin to GND. Before enabling the charger, the IC tests to see if NTC is shorted to GND. If NTC is shorted to GND, no thermistor readings occur and the NTC_OK and NTC1-NTC4 is reset. Table 10. Battery Temperature Thresholds For use with 10 k NTC, = 3380, and RREF = 10 k. Threshold Temperature % of VREF T1 0C 73.9 T2 10C 64.6 The IC first measures the NTC immediately prior to entering any PWM charging state, then measures the NTC once per second, updating the result in NTC1-NTC4 bits (Reg 12H[3:0]). T3 45C 32.9 Table 13. NTC1-NTC4 Decoding T4 60C 23.3 TBAT (C) Table 11. Charge Parameters vs. TBAT TBAT (C) ICHARGE Below T1 VFLOAT Charging to VBAT Disabled Between T1 and T2 IOCHARGE / 2 Between T2 and T3 IOCHARGE Between T3 and T4 IOCHARGE / 2 Above T4 (11) 4.0 V NTC4 NTC3 NTC2 NTC1 Above T4 1 1 1 1 Between T3 and T4 0 1 1 1 Between T2 and T3 0 0 1 1 Between T1 and T2 0 0 0 1 Below T1 0 0 0 0 VOREG (11) 4.0 V Charging to VBAT Disabled Note: 11. If IOCHARGE is programmed to less than 650 mA, the charge current is limited to 340 mA. Thermistors with other values can be used, with some shift in the corresponding temperature threshold, as shown in Table 12. Table 12. Thermistor Temperature Thresholds RREF = RTHRM at 25C Parameter Various Thermistors RTHRM(25C) 10 k 10 k 47 k 100 k 3380 3940 4050 4250 T1 0C 3C 6 8 T2 10C 12C 13 14 T3 45C 42C 41 40 T4 60C 55C 53 51 1 Japan Electronics and Information Technology Industries Association (JEITA) and Battery Association of Japan. "A Guide to the Safe Use of Secondary Lithium Ion Batteries in Notebook-type Personal Computers," April 28, 2007. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 24 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Battery Temperature (NTC) Monitor FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Flow Charts VBUS POR HZ or DISABLE Pin set? YES VBAT > VLOWV T32Sec Armed? NO YES NO NO YES Ready State HZ, or DISABLE Pin set? YES HZ State T32Sec Armed? NO YES Charge State Reset all registers Start T32SEC NO Figure 38. Charger VBUS POR Flow Chart Ready State PWM = OFF Q4, Q5 = ON VBAT > VLOWV? NO RUN T32Sec YES HZ_STATE YES HZ or DISABLE Pin set? NO NO T32Sec Armed? YES Charge State Figure 39. Ready State Flow Chart (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 25 CHARGE STATE FIRST TIME? YES NO YES Linear Charging Reset Safety reg YES VBAT < VSHORT VBAT < VSHORT Enable PWM YES NO Battery Present? YES NO NO Enable PWM YES CE# = 1 NO Timer Running? YES CE# = 1 Enunciate battery absent fault NO IDLE State NO ON VBAT < VBATMIN Protection switch closed? YES NO IDLE State Enable PowerPath charging NO Battery Removed Battery T15MIN T.O. or [T32S T.O. and FAN54041] ? NO Present? IOUT < ITERM and TE = 1 YES Reset charge parameters & Safety Regs Indicate Charge Complete YES PWM ON Q4 and Q5 OFF VBUS OK? EOC = 1 NO VBAT < VOREG-VRCH ? NO IDLE State NO YES YES Indicate timer fault behavior? OFF YES Enable PWM charging Battery absent Indicate VBUS Fault YES NO Disable PWM for 2 seconds YES CHARGE STATE Figure 40. Charge State Flow Chart (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 26 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support NO DIS PIN FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support HZ State PWM = OFF Q4, Q5 = ON Reset T15min if running HIGH LOW Stop T32Sec Run T32Sec NO HZ_MODE or DIS pin set? YES YES VBAT > VLOWV? NO Timer Armed? NO IDLE STATE YES Start timer and GOTO Charge State Figure 41. HZ State IDLE State T32Sec Armed? PWM = OFF Q4, Q5 = ON NO YES Charge State NO HZ or DISABLE Pin set? YES HZ STATE Figure 42. IDLE State (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 27 Start T15MIN Reset Registers YES T32SEC NO Expired? Start T32SEC Stop T15MIN T15MIN Active? YES YES NO I2C Write Received? T15MIN NO Timer Fault PWM = OFF Expired? NO Continue Charging YES Figure 43. Timer Flow Chart for FAN54040, FAN54042, FAN54047 Charge Start from Host control Reset T32SEC Charge T32SEC Expired? YES Timer Fault Stop PWM and Reset Registers NO NO YES TMR_RST Bit Set? Figure 44. Timer Flow Chart for FAN54041 Input Current Limiting For the FAN54041, no charging occurs automatically at VBUS POR, so the input current limit is established by the IBUSLIM bits. To minimize charging time without overloading VBUS current limitations, the IC's input current limit can be programmed by the IBUSLIM bits (REG1[7:6]). VBUS Control loop Table 14. Input Current Limit The IC includes a control loop that limits input current in case a current-limited source is supplying VBUS. IBUSLIM REG1[7:6] Input Current Limit 00 100 mA The control increases the charging current until either: 01 500 mA 10 800 mA 11 No Limit (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 IBUSLIM or IOCHARGE is reached VBUS=VBUSLIM. OR If VBUS collapses to VBUSLIM, the VBUS loop reduces its current to keep VBUS=VBUSLIM. When the VBUS control loop is limiting the charge current, the VLIM bit (REG5[3]) is set. www.fairchildsemi.com 28 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Charge Start Table 17. VSAFE (VOREG Limit) as Function of VSAFE Bits (REG6[3:0]) VBUSLIM (REG5[2:0]) VSAFE (REG6[3:0]) DEC BIN HEX VBUSLIM 0 000 0 4.213 1 001 1 DEC BIN HEX OREG Max. (REG2[7:2]) VOREG Max. 4.293 0 0000 0 100011 4.20 0001 1 100100 4.22 2 010 2 4.373 1 3 011 3 4.453 2 0010 2 100101 4.24 4 100 4 4.533 3 0011 3 100110 4.26 0100 4 100111 4.28 5 101 5 4.613 4 6 110 6 4.693 5 0101 5 101000 4.30 7 111 7 4.773 6 0110 6 101001 4.32 7 0111 7 101010 4.34 Safety Settings 8 1000 8 101011 4.36 The IC contains a SAFETY register (REG6) that prevents the values in OREG (REG2[7:2]) and IOCHARGE (REG4[7:4]) from exceeding the values of the VSAFE and ISAFE values. 9 1001 9 101100 4.38 10 1010 A 101101 4.40 11 1011 B 101110 4.42 12-15 1100-1111 C-F 101111-110010 4.44 After VBAT rises above VSHORT, the SAFETY register is loaded with its default value and may be written to only before writing to any other register. The same 8-bit value should be written to the Safety register twice to set the register value. After writing to any other register, the SAFETY register is locked until VBAT falls below VSHORT. Thermal Regulation and Protection When the IC's junction temperature reaches TCF (about 120C), the charger reduces its output current to 550 mA to prevent overheating. If the temperature increases beyond TSHUTDOWN; charging is suspended, the FAULT bits are set to 101, and STAT is pulsed HIGH. In Suspend Mode, all timers stop and the state of the IC's logic is preserved. Charging resumes at programmed current after the die cools to about 120C. The ISAFE (REG6[7:4]) and VSAFE (REG6[3:0]) registers establish values that limit the maximum values of I OCHARGE and VOREG used by the control logic. If the host attempts to write a value higher than VSAFE or ISAFE to OREG or IOCHARGE, respectively; the VSAFE, ISAFE value appears as the OREG, IOCHARGE register value, respectively. Additional JA data points, measured using the FAN54040 evaluation board, are given in Table 18 (measured with TA=25C). Note that as power dissipation increases, the effective JA decreases due to the larger difference between the die temperature and ambient. Table 16. Maximum IOCHARGE as Function of ISAFE Bits (REG6[7:4]) DEC BIN HEX IOCHARGE(MAX) (mA) 0 0000 0 550 1 0001 1 650 Power (W) JA 54C/W Table 18. Evaluation Board Measured JA 2 0010 2 750 0.504 3 0011 3 850 0.844 50C/W 4 0100 4 950 1.506 46C/W 5 0101 5 1,050 6 0110 6 1,150 7 0111 7 1,250 8 1000 8 1,350 9 1001 9 1,450 10-15 1010-1111 A-F 1,550 (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 29 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Table 15. VBUS Limit as Function of VBUSLIM Bits (REG5[2:0]) The IC can detect the presence, absence, or removal of a battery if the termination bit (TE) is set and CE# = 0. During normal charging, once VBAT is close to VOREG and the charge current falls below ITERM; the PWM charger continues to provide power to SYS and Q4 is turned off. It then turns on a discharge current, IDETECT, for tDETECT. If VBAT is still above VOREG - VRCH, the battery is present and the IC sets the STATUS bits to 10 (Charge Done). If VBAT is below VOREG - VRCH, the battery is absent and the IC: Sleep Mode When VBUS falls below VBAT + VSLP and VBUS is above VIN(MIN), the IC enters Sleep Mode to prevent the battery from draining into VBUS. During Sleep Mode, reverse current is disabled by body switching Q1. Input Supply Low-Voltage Detection The IC continuously monitors VBUS during charging. If VBUS falls below VIN(MIN), the IC: 1. Sets the charging parameters to their default values. 1. Terminates charging 2. 2. Pulses the STAT pin, sets the STATUS bits to 11, and sets the FAULT bits to 011. Sets the FAULT bits to 111 (Battery Absent) and sets the NOBAT bit. 3. If VBUS recovers above the VIN(MIN) rising threshold after time tINT (about two seconds), the charging process is repeated. This function prevents the USB power bus from collapsing or oscillating when the IC is connected to a suspended USB port or a low-current-capable OTG device. If EOC=0, the IC turns off the PWM for tINT, then resumes charging. If the battery is still absent, the battery absent fault is then re-enunciated every tINT. 4. If EOC = 1, the PWM remains on to provide power to SYS, but charge termination and the battery absent test are performed every tINT. Input Over-Voltage Detection Linear Charging When the VBUS exceeds VBUSOVP, the IC: If the battery voltage is below the short-circuit threshold (VSHORT); a linear current source, ISHORT, charges VBAT until VBAT > VSHORT. 1. Turns off Q3 2. Suspends charging 3. Sets the FAULT bits to 001, sets the STATUS bits to 11, and pulses the STAT pin. For IBUSLIM settings of 100 mA or 500 mA, the linear charging current is typically 13 mA. For higher IBUSLIM settings, the linear charging current is increased to 30 mA. When VBUS falls about 100 mV below VBUSOVP, the fault is cleared and charging resumes after VBUS is revalidated (see VBUS POR / Non-Compliant Charger Rejection). Charger Status / Fault Status VBUS Short While Charging Table 19. STAT Pin Function The STAT pin indicates the operating condition of the IC and provides a fault indicator for interrupt driven systems. If VBUS is shorted with a very low impedance while the IC is charging with IBUSLIMIT=100 mA, the IC may not meet datasheet specifications until power is removed. To trigger this condition, VBUS must be driven from 5 V to GND with a high slew rate. Achieving this slew rate requires a 0 short to the USB cable less than 10 cm from the connector. SYS Short During Discharge / Supplemental Mode Caution should be taken to ensure the SYS pin is not shorted when connected to a battery. This condition can induce high current flow through the BATFET (Q4) until the battery's own safety circuit trips. The resulting high current can damage the IC. Charge State STAT Pin 0 X OPEN X Normal Conditions OPEN 1 Charging LOW X Fault (Charging or Boost) 128 s Pulse, then OPEN The FAULT bits (R0[2:0]) indicate the type of fault in Charge Mode (see Table 28). Production Test Mode (PTM) Charge Mode Battery Detection & Protection PTM provides 4.2 V at up to 2.3 A to VBAT when VBUS = 5.5 V 5%. VBAT Over-Voltage Protection The OREG voltage regulation loop prevents VBAT from overshooting VOREG by more than 50 mV when the battery is removed. When the PWM charger runs with no battery, the TE bit is not set and a battery is inserted that is charged to a voltage higher than VOREG; PWM pulses stop. If no further pulses occur for 30 ms, the IC sets the FAULT bits to 100, sets the STATUS bits to 11, and pulses the STAT pin. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 EN_STAT The IC enters PTM when the PROD bit is set and the NOBAT bit is HIGH, indicating that the IC has detected battery absence. A battery absence detection test after VBUS POR is performed automatically for FAN54040, FAN54042, and FAN54047 only. A battery-absent detection test can be performed at any time by setting the TE bit, setting VOREG to at least 4.0 V, then resetting the CE# bit. If no battery is present; charge termination occurs, followed by a battery absent test, which sets the NOBAT bit. Battery-absence detection is completed within 500 ms from the time that CE# is set. www.fairchildsemi.com 30 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Battery Detection During Charging Charge Mode Input Supply Protection During PTM, high current pulses (load currents greater than 1.5 A) must be limited to 20% duty cycle with a minimum period of 10 ms. VBUS Output Resistance (m) 400 Charge Mode Control Bits 2 Setting either HZ_MODE through I C or DIS pin to HIGH disables the charger, puts the IC into High-Impedance Mode, and stops t32S. If VBAT < VLOWV while in High-Impedance Mode, t32S begins running and, when it overflows, all registers (except SAFETY) reset, which enables t15MIN charging on versions with the 15-minute timer if DIS=0. When t15MIN overflows, the IC enters High-Impedance Mode 2 (IDLE). A new charge cycle can only be initiated through I C or VBUS POR. Setting the RESET bit clears all registers. If HZ_MODE bit was set when the RESET bit is set, this bit is also cleared, but the t32S timer is not started and the IC remains in HighImpedance Mode. DIS Pin HZ_MODE ENABLE 0 0 DISABLE X 1 DISABLE 1 X 240 2.5 3.0 3.5 4.0 4.5 Battery Voltage, VBAT (V) Figure 45. Output Resistance (ROUT) VBUS as a function of ILOAD can be computed when the regulator is in PWM Mode (continuous conduction) as: VOUT 5.07 ROUT ILOAD EQ. 1 At VBAT=3.0 V and ILOAD=300 mA, VBUS drops to: VOUT 5.07 0.30 0.3 4.98V EQ. 2 At VBAT=3.6 V and ILOAD=500 mA, VBUS drops to: VOUT 5.07 0.24 0.5 4.95V EQ. 3 PFM Mode If VBUS > VREFBOOST (nominally 5.07 V) when the minimum off-time ends, the regulator enters PFM Mode. Boost pulses are inhibited until VBUS < VREFBOOST. The minimum on-time is increased to enable the output to pump up sufficiently with each PFM boost pulse. Therefore, the regulator behaves like a constant on-time regulator, with the bottom of its output voltage ripple at 5.07 V in PFM Mode. Boost Mode Boost Mode can be enabled if the IC is in 32-Second Mode by setting the OPA_MODE bit HIGH and clearing the HZ_MODE bit. Table 21. Enabling Boost OPA_MODE 280 2.0 Raising the DIS pin stops t32S from advancing, but does not reset it. If the DIS pin is raised during t15MIN charging, the t15MIN timer is reset. CE# determines whether charging to VBAT is enabled or not. HZ_MODE 320 200 Table 20. DIS Pin and HZ_MODE Bit Functionality Charging 360 BOOST Table 22. Boost PWM Operating States 0 1 Enabled Mode Description Invoked When 1 X Disabled LIN Linear Startup VBAT > VBUS X 0 Disabled SS Boost Soft-Start VBUS < VBST BST Boost Operating Mode VBAT > UVLOBST and SS Completed To remain in Boost Mode, the TMR_RST must be set by the host before the t32S timer times out. If t32S times out in Boost Mode; the IC resets all registers, pulses the STAT pin, sets the FAULT bits to 110, and resets the BOOST bit. VBUS POR or reading R0 clears the fault condition. Startup When the boost regulator is shut down, current flow is prevented from VBAT to VBUS, as well as reverse flow from VBUS to VBAT. Boost PWM Control The IC uses a minimum on-time and computed minimum offtime to regulate VBUS. The regulator achieves excellent transient response by employing current-mode modulation. This technique causes the regulator to exhibit a load line. During PWM Mode, the output voltage drops slightly as the input current rises. With a constant VBAT, this appears as a constant output resistance. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 31 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support The "droop" caused by the output resistance when a load is applied allows the regulator to respond smoothly to load transients with no undershoot from the load line. This can be seen in Figure 33 and Figure 45. In PTM, GATE is LOW, Q4 and Q5 are on, and all auxiliary control loops are disabled. Only the OREG loop is active, which controls VBAT to 4.2 V, regardless of the OREG register setting. Thermal shutdown remains active. Monitor Registers (Reg10H, Reg11H) When EN rises, if VBAT > UVLOBST; the regulator first attempts to bring PMID within 400 mV of VBAT using an internal 450 mA current source from VBAT (LIN State). If PMID has not achieved VBAT - 400 mV after 560 s, a FAULT state is initiated. Additional status monitoring bits enable the host processor to have more visibility into the status of the IC. The monitor bits are real-time status indicators and are not internally debounced or otherwise time qualified. The state of the MONITOR register bits listed in HighImpedance Mode is valid only when VBUS is valid. SS State I2C Interface When PMID > VBAT - 400 mV, the boost regulator begins switching with a reduced peak current limit of about 50% of its normal current limit. The output slews up until VBUS is within 5% of its setpoint; at which time, the regulation loop is closed and the current limit is set to 100%. The FAN5404X's serial interface is compatible with 2 Standard, Fast, Fast Plus, and High-Speed Mode I C bus specifications. The FAN5404X SCL line is an input and the SDA line is a bi-directional open-drain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first. If the output fails to achieve 95% of its setpoint (VBST) within 128 s, the current limit is increased to 100%. If the output fails to achieve 95% of its setpoint after this second 384 s period, a fault state is initiated. Slave Address BST State 2 Table 24. I C Slave Address Byte This is the normal operating mode of the regulator. The regulator uses a minimum tOFF-minimum tON modulation scheme. The minimum tOFF is proportional to VIN , which VOUT 7 6 5 4 3 2 1 0 1 1 0 1 0 1 1 R/ W keeps the regulator's switching frequency reasonably constant in CCM. tON(MIN) is proportional to VBAT and is a higher value if the inductor current reached 0 before tOFF(MIN) in the prior cycle. In hex notation, the slave address assumes a 0 LSB. The hex slave address is D6H for all parts in the family. Other slave addresses can be accommodated upon request. Contact a Fairchild Semiconductor representative. To ensure VBUS does not overshoot the regulation point, the boost switch remains off as long as VFB > VREF(BST). Bus Timing As shown in Figure 46, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the next SCL rising edge. Boost Faults If a BOOST fault occurs: 1. The STAT pin pulses. 2. OPA_MODE bit is reset. 3. The power stage is in High-Impedance Mode. 4. The FAULT bits (REG0[2:0]) are set per Table 23. Data change allowed SDA Restart After Boost Faults tH OPA_MODE is reset on boost faults. Boost Mode can only be re-enabled by setting the OPA_MODE bit. tSU SCL Table 23. Fault Bits During Boost Mode Fault Bit B2 B1 B0 Figure 46. Data Transfer Timing Fault Description 0 0 0 Normal (no fault) 0 0 1 VBUS > VBUSOVP 0 1 0 VBUS fails to achieve the voltage required to advance to the next state during soft-start or sustained (>50 s) current limit during the BST state. 0 1 1 VBAT < UVLOBST 1 0 0 NA: This code does not appear. 1 0 1 Thermal shutdown 1 1 0 Timer fault; all registers reset. 1 1 1 NA: This code does not appear. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a START condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 47 SDA tHD;STA Slave Address MS Bit SCL Figure 47. Start Bit www.fairchildsemi.com 32 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support LIN State Slave Releases SDA Master Drives Read and Write Transactions The figures below outline the sequences for data read and write. Bus control is signified by the shading of the packet, tHD;STO Master Drives Bus ACK(0) or NACK(1) defined as and All addresses and data are MSB first. Slave Drives Bus . Table 25. Bit Definitions for Figure 50 - Figure 53 SCL Symbol Definition Figure 48. Stop Bit S START, see Figure 47 During a read from the FAN5404X (Figure 51), the master issues a Repeated Start after sending the register address and before resending the slave address. The Repeated Start is a 1-to-0 transition on SDA while SCL is HIGH, as shown in Figure 49. A ACK. The slave drives SDA to 0 to acknowledge the preceding packet. A NACK. The slave sends a 1 to NACK the preceding packet. R Repeated START, see Figure 49 P STOP, see Figure 48 High-Speed (HS) Mode The protocols for High-Speed (HS), Low-Speed (LS), and Fast-Speed (FS) Modes are identical except the bus speed for HS Mode is 3.4 MHz. HS Mode is entered when the bus master sends the HS master code 00001XXX after a start condition. The master code is sent in Fast or Fast Plus Mode (less than 1 MHz clock); slaves do not ACK the transmission. Multi-Byte (Sequential) Read and Write Transactions Sequential Write (Figure 52) The Slave Address, Reg Addr address, and the first data byte are transmitted to the FAN5404x in the same way as in a byte write (Figure 50). However, instead of generating a Stop condition, the master transmits additional bytes that are written to consecutive sequential registers after the falling edge of the eighth bit. After the last byte written and its ACK bit received, the master issues a STOP bit. The IC contains an 8-bit counter that increments the address pointer after each byte is written. The master then generates a repeated start condition (Figure 49) that causes all slaves on the bus to switch to HS 2 Mode. The master then sends I C packets, as described above, using the HS Mode clock rate and timing. The bus remains in HS Mode until a stop bit (Figure 48) is sent by the master. While in HS Mode, packets are separated by repeated start conditions (Figure 49). Slave Releases SDA tSU;STA Sequential Read (Figure 53) tHD;STA ACK(0) or NACK(1) Sequential reads are initiated in the same way as a singlebyte read (Figure 51), except that once the slave transmits the first data byte, the master issues an acknowledge 2 instead of a STOP condition. This directs the slave's I C logic to transmit the next sequentially addressed 8-bit word. The FAN5404x contains an 8-bit counter that increments the address pointer after each byte is read, which allows the entire 2 memory contents to be read during one I C transaction. SLADDR MS Bit SCL Figure 49. Repeated Start Timing Figure 50. Single-Byte Write Transaction Figure 51. Single-Byte Read Transaction Figure 52. Multi-Byte (Sequential) Write Transaction Figure 53. Multi-Byte (Sequential) Read Transaction (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 33 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Transactions end with a STOP condition, which is SDA transitioning from 0 to 1 with SCL HIGH, as shown in Figure 48. The eight user-accessible IC registers are defined in Table 26. 2 Table 26. I C Register Address Register Address Bits Name REG# 7 6 5 4 3 2 1 0 CONTROL0 0H 0 0 0 0 0 0 0 0 CONTROL1 1H 0 0 0 0 0 0 0 1 OREG 2H 0 0 0 0 0 0 1 0 IC_INFO 3H 0 0 0 0 0 0 1 1 IBAT 4H 0 0 0 0 0 1 0 0 VBUS_CONTROL 5H 0 0 0 0 0 1 0 1 SAFETY 6H 0 0 0 0 0 1 1 0 POST_CHARGING 7H 0 0 0 0 0 1 1 1 MONITOR0 10H 0 0 0 1 0 0 0 0 MONITOR1 11H 0 0 0 1 0 0 0 1 NTC 12H 0 0 0 1 0 0 1 0 WD_CONTROL 13H 0 1 1 0 1 1 0 0 Table 27. Register Bit Definitions This table defines the operation of each register bit for all IC versions. Default values are in bold text. Bit Name Value Type Description CONTROL0 7 TMR_RST 6 EN_STAT Register Address: 00 0 W 0 R/W 1 00 5:4 STAT BOOST 2:0 FAULT Writing a 1 resets the t32S timer; writing a 0 has no effect. Reading this bit always returns 0 Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate faults Enables STAT pin to be LOW when IC is charging R Ready 01 PWM Enabled. Charging is occurring if CE# = 0. 10 Charge done 11 3 Default Value=0100 0000 0 Fault R 1 IC is not in Boost Mode IC is in Boost Mode R Table 28. Charger Mode Faults Fault Bit Fault Description 2 0 1 0 0 0 Normal (No Fault) 0 0 1 VBUS OVP 0 1 0 Sleep Mode 0 1 1 Poor Input Source 1 0 0 Battery OVP 1 0 1 Thermal Shutdown 1 1 0 Timer Fault 1 1 1 No Battery For Boost Mode faults, see Table 23 (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 34 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Register Descriptions Name Value Type CONTROL1 7:6 Register Address: 01 IBUSLIM 00 5:4 VLOWV 3 TE 2 CE# 1 HZ_MODE 0 Description OPA_MODE Input current limit; defaults to 00 (100 mA), see Table 14 R/W 3.4 V 01 3.5 V 10 3.6 V 11 3.7 V 0 R/W 1 0 Disable charge current termination Charging enabled. Default for FAN54040, FAN54042, FAN54047. Charging disabled. Default for FAN54041, FAN54045 , FAN54046. R/W 1 0 Weak battery voltage threshold Enable charge current termination R/W 1 0 Not High-Impedance Mode High-Impedance Mode R/W 1 Charge Mode Register Address: 02 OREG 0 1 R/W R/W Indicates that the IC detected a dead battery after VBUS_POR and that the charger has not yet completed the three steps to ensure that the battery's protection switch is closed if a battery is present, as described in the Dead Battery section on page 21. Writing a 0 to this bit is ignored. The IC sets this bit to 1 if any of the following are true: 1. Dead Battery (VBAT < VSHORT) was not detected at VBUS_POR. 2. The IC has completed the three steps to ensure that if the battery is present, the battery's protection switch has closed, as described in the Dead Battery section on page 21. If the host sets this bit while the IC is charging the battery and DBAT_B is LOW, the three steps are aborted and normal Power Path or PWM charging proceeds. 1 0 R/W EOC If no battery is detected when a full battery (end of charge) is reached, PWM stops, Q4 and Q5 remain on, and the charger automatically restarts after two seconds with TE and CE# bits unchanged. If no battery is detected when a full battery (end of charge) is reached, the PWM charger stays on, allowing the host processor to continue to run with no battery. 1 IC_INFO Register Address: 03 10 Default Value=0000 1000 (08H) Charger output "float" voltage; programmable from 3.5 to 4.44 V in 20 mV increments; defaults to 000010 (3.54 V), see Table 4. DBAT_B 0 See Table 21 Boost Mode OREG 7:2 Default Value=0011 0X00 R/W Default Value=100X XXXX 7:6 Vendor Code R Identifies Fairchild Semiconductor as the IC supplier 5:3 PN R Part number bits, see the Ordering Info on page 2 2:0 REV R IC Revision, revision 1.X, where X is the decimal of these three bits IBAT Register Address: 04 Default Value=1000 0001 (81H) Writing a 1 resets all registers, except the Safety register (Reg6), to their defaults: writing a 0 has no effect; read returns 1 7 RESET 1 W 6:3 IOCHARGE Table 5 R/W Programs the maximum charge current, see Table 5 2:0 ITERM Table 6 R/W Sets the current used for charging termination, see Table 6 (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 35 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Bit Name Value Type VBUS_CONTROL 7 Reserved 6 PROD 5 IO_LEVEL 4 VBUS_CON 3 SP 2:0 VBUSLIM Description Register Address: 05 0 R 0 R/W 1 0 Charger operates in Normal Mode. Battery current is controlled by IOCHARGE bits. Battery current control is set to 340 mA. R 1 Indicates that VBUS is above 4.4 V (rising) or 3.8 V (falling). When VBUS_CON changes from 0 to 1, a STAT pulse occurs. R VBUS control loop is not active (VBUS is able to stay above VBUSLIM) 1 Table 15 This bit always returns 0 Charger operates in Production Test Mode. R/W 1 0 Default Value=001X X100 VBUS control loop is active and VBUS is being regulated to VBUSLIM R/W SAFETY VBUS control voltage reference, see Table 15 Register Address: 06 Default Value=0100 0000 (40H) 7:4 ISAFE Table 16 R/W Sets the maximum IOCHARGE value used by the control circuit, see Table 16 3:0 VSAFE Table 17 R/W Sets the maximum VOREG used by the control circuit, see Table 17 POST_CHARGING Register Address: 07 Default Value=0000 0001 (01H) These bits determine whether a battery absent detection will be performed when the NTC reading indicates out-of-range when charging. [7:6] 7:6 BDET R/W 00 01 10 11 When NTC goes out-of-range Always do battery absent detection Disable detection in Normal Mode Disable detection when Reg FA = B5 (PWM running after charge done. NTC out-of-range in charge done does not cause battery absent detection. After charger termination, in the charge done state, these bits control VBUS loading to improve detection of AC power removal from the AC adapter. [5:4] 5:4 VBUS_LOAD 3 PC_EN 2:0 PC_IT 0 R/W 0 R/W 1 Table 6 00 01 10 11 VBUS loading in Charge Done State: None Load VBUS for 4 ms every two seconds Load VBUS for 131 ms every two seconds Load VBUS for 135 ms every two seconds Post charging or background charging feature is disabled Post charging or background charging feature is enabled R/W MONITOR0 Sets the termination current for post or underground charging, see Table 6 Register Address: 10H (16) Default Value=XXX0 XXXX (XXH) 7 ITERM_CMP R ITERM comparator output, 1 when ICHARGE > ITERM reference 6 VBAT_CMP R Output of VBAT comparator, 1 when VBAT < VBUS 5 LINCHG R 1 when 30 mA linear charger ON (VBAT < VSHORT) 4 T_120 R Thermal regulation comparator, 1 when the die temperature is greater than 120C. During this condition, charge current is limited to 340 mA. 3 ICHG R 0 indicates the ICHARGE loop is controlling the battery charge current. 2 IBUS R 0 indicates the IBUS (input current) loop is controlling the battery charge current. 1 VBUS_VALID R 1 indicates VBUS has passed validation and is capable of charging. 0 CV R 1 indicates the constant-voltage loop (OREG) is controlling the charger and all current limiting loops have released. (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 36 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Bit Name Value Type 0 R MONITOR1 7 GATE 6 VBAT 5 POK_B 4 DIS_LEVEL 3 NOBAT Description Register Address: 11H (17) 1 0 GATE pin is HIGH, Q5 is off. R 1 0 1 0 R/W R POK_B Pin is LOW. POK_B Pin is HIGH. Writing to this bit sets the POK_B pin. DIS pin is LOW. DIS pin is HIGH. R 0 1 VBAT < VBATMIN in PP charging, VBAT < VLOW in PWM charging VBAT > VBATMIN in PP charging, VBAT > VLOW in PWM charging 1 1 Default Value=XX1X XXXX GATE pin is LOW, Q5 is driven on. Battery absence Battery presence R Post charging (background charging) is under progress. 2 PC_ON 1:0 Reserved 0 R 7:6 Reserved 00 R 0 R/W 5 TEMP_DIS 4 NTC_OK R 0 if NTC is either shorted to GND, open, or shorted to REF. 3 NTC4 R 1 indicates that NTC is above the T4 threshold. 2 NTC3 R 1 indicates that NTC is above the T3 threshold. 1 NTC2 R 1 indicates that NTC is above the T2 threshold. 0 NTC1 R 1 indicates that NTC is above the T1 threshold. 0 Post charging (background charging) is not under progress. NTC These bits always return 0. Register Address: 12H (18) Default Value=000X XXXX These bits always return 0. NTC Temperature measurement results affect charge parameters. NTC Temperature measurement results do not affect charge. Temperature measurements continue to be updated every second in the NTC1-4 monitor bits. 1 WD_CONTROL Register Address: 13H (19) Default Value = 0110 1100 7 Reserved 0 R/W These bits do not change the function of the IC. 6:5 Reserved 11 R/W These bits do not change the function of the IC. 4 Reserved 0 R/W These bits do not change the function of the IC. 3 Reserved 1 R/W These bits do not change the function of the IC. 2 EN_VREG 1 WD_DIS 0 Reserved 0 1 0 1 0 R/W R/W R RESTART 7:0 RESTART (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 VREG is off VREG is on Watchdog timer (T32S) operation normal Watchdog timer (T32S) disabled. This bit always returns 0 Register Address: FAH (250) W See Table 10 - Table 13 Default Value = 1111 1111 Writing B5H restarts charging when the IC is in the charge done state. This register reads back FF. www.fairchildsemi.com 37 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support Bit Bypass capacitors should be placed as close to the IC as possible. In particular, the total loop length for CMID should be minimized to reduce overshoot and ringing on the SW, PMID, and VBUS pins. Power and ground pins should be routed directly to their bypass capacitors using the top copper layer. The copper area connecting to the IC should be maximized to improve thermal performance. See the layout recommendations in Figure 54. Figure 54. PCB Layout Recommendation Product-Specific Dimensions Product D E X Y FAN5404XUCX 2.40 0.030 2.00 0.030 0.180 0.380 (c) 2012 Fairchild Semiconductor Corporation FAN54040 - FAN54047 * Rev. 1.3 www.fairchildsemi.com 38 FAN54040 - FAN54047-- USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support PCB Layout Recommendation 0.03 C E 2X A F 1.60 B A1 BALL A1 INDEX AREA 1.60 D 0.40 0.40 (O0.200) Cu Pad (O0.300) Solder Mask 0.03 C RECOMMENDED LAND PATTERN (NSMD PAD TYPE) 2X TOP VIEW 0.06 C 0.625 0.547 0.05 C 0.3780.018 0.2080.021 E SIDE VIEWS C D SEATING PLANE NOTES: A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. 1.60 0.005 O0.2600.02 25X 0.40 1.60 E D C B 0.40 D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS 39 MICRONS (547-625 MICRONS). (Y) 0.018 A F 1 2 3 4 5 F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILENAME: MKT-UC025AArev3. (X) 0.018 BOTTOM VIEW C A B C. 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