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February 2015

FAN54040 – FAN54047 • Rev. 1.3

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

FAN54040 — FAN54047

USB-OTG, 1.55 A, Li-Ion Switching Charger with Power

Path and 2.3 A Production Test Support

Features

 Fully Integrated, High-Efficiency Charger for Single-Cell

Li-Ion and Li-Polymer Battery Packs

 Power Path Circuit Ensures Fast System Startup with a

Dead Battery when VBUS is Connected

 1.55 A Maximum Charge Current

 Float Voltage Accuracy:

- 0.5% at 25°C

- 1% from 0 to 125°C

 5% Input and Charge Current Regulation Accuracy

 Temperature-Sense Input Prevents Auto-Charging for

JEITA Compliance

 Thermal Regulation and Shutdown

 4.2 V at 2.3 A Production Test Mode

 5 V, 500 mA Boost Mode for USB OTG

 28 V Absolute Maximum Input Voltage

 6 V Maximum Input Operating Voltage

 Programmable through High-Speed I2C Interface

(3.4 Mb/s) with Fast Mode Plus Compatibility

- Input Current

- Fast-Charge / Termination Current

- Float Voltage

- Termination Enable

 3 MHz Synchronous Buck PWM Controller with

Wide Duty Cycle Range

 Small Footprint 1 H External Inductor

 Safety Timer with Reset Control

 Dynamic Input Voltage Control

 Very Low Battery Current when Charger Inactive

Applications

 Cell Phones, Smart Phones, PDAs

 Tablet, Portable Media Players

 Gaming Device, Digital Cameras

Description

The FAN5404X family includes I2C controlled 1.55 A USB-

compliant switch-mode chargers with power path operation

and USB OTG boost operation. Integrated with the charger,

the IC supports production test mode, which provides 4.2 V

at up to 2.3 A to the system.

To facilitate fast system startup, the IC includes a power

path circuit, which disconnects the battery from the system

rail, ensuring that the system can power up quickly following

a VBUS connection. The power path circuit ensures that the

system rail stays up when the charger is plugged in, even if

the battery is dead or shorted.

The charging parameters and operating modes are

programmable through an I2C Interface that operates up to

3.4 Mbps. The charger and boost regulator circuits switch at

3 MHz to minimize the size of external passive components.

The FAN5404X provides battery charging in three phases:

conditioning, constant current, and constant voltage. The

integrated circuit automatically restarts the charge cycle

when the battery falls below a voltage threshold. If the input

source is removed, the IC enters a high-impedance mode

blocking battery current from leaking to the input. Charge

status is reported back to the host through the I2C port.

Dynamic input voltage control prevents a weak adapter’s

voltage from collapsing, ensuring charging capability from

such adapters.

The FAN5404X is available in a 25-bump, 0.4 mm pitch,

WLCSP package.

SW

SYSTEM

LOAD

L1

Q5

SDA

SCL

VBUS

CBUS

VBAT

SYS

GATE

CSYS

External

PMOS

POK_B

ILIM

DIS

PGND

STAT

AGND

+

PMID

CMID

CBAT

NTC

REF RREF

CREF

T

BATTERY

FAN5404X

Figure 1. Typical Application

All trademarks are the property of their respective owners.

FAN54040 – FAN54047 • Rev. 1.3 2

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Ordering Information

Part Number

Temperature Range

Package

PN Bits: IC_INFO[5:3]

Packing Method

FAN54040UCX

-40 to 85°C

25-Bump, Wafer-Level

Chip-Scale Package

(WLCSP), 0.4 mm Pitch

000

Tape and Reel

FAN54041UCX

001

FAN54042UCX(1)

010

FAN54045UCX(1)

101

FAN54046UCX(1)

110

FAN54047UCX

110

Note:

1. Contact Fairchild Sales for availability.

Table 1. Feature Comparison Summary

Part Number

Slave Address

Automatic Charge

Battery Absent Behavior

E1 Pin

FAN54040

1101011

Yes

Off

POK_B

FAN54041

1101011

No

Off

POK_B

FAN54042

1101011

Yes

On

POK_B

FAN54045

1101011

No

Off

ILIM

FAN54046

1101011

No

On

ILIM

FAN54047

1101011

Yes

On

ILIM

FAN54040 – FAN54047 • Rev. 1.3 3

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Block Diagram

SW

SYSTEM

LOAD

Q2

L1

Q5

SDA

SCL

VBUS

CBUS

VBAT

SYS

GATE

CSYS

External

PMOS

Q3

POK_B

ILIM

CHARGE

PUMP

Q3

DIS

PGND

STAT

AGND

+

Q1B

Q1A

Q1

PMID

PWM

MODULATOR

CC and CV

Battery

Charger

CMID

CBAT

NTC

REF RREF

TEMP

SENSE

I2C INTERFACE

LOGIC AND CONTROL

CREF

IBUS &

VBUS

CONTROL

VBUS OVP

POWER OK

Q4B

Q4A

Q4

T

BATTERY

PMID

Q1A

Q1B

Greater than VBAT

ON

OFF

Less than VBAT

OFF

ON

SYS

Q4A

Q4B

Greater than VBAT

ON

OFF

Less than VBAT

OFF

ON

Figure 2. IC and System Block Diagram

Table 2. Recommended External Components

Component

Description

Vendor

Parameter

Typ.

Unit

L1

1 H, 20%, 2.2 A, 2016

Taiyo Yuden MAKK2016T1R0M

or Equivalent

L

1.0

H

DCR (Series R)

75

m

CBAT, CSYS

10 F, 20%, 6.3 V, X5R, 0603

Murata: GRM188R60J106M

TDK: C1608X5R0J106M

C

10

F

CMID

4.7 F, 10%, 6.3 V, X5R, 0603

Murata: GRM188R60J475K

TDK: C1608X5R0J475K

C(2)

4.7

F

CBUS,

1.0 F, 10%, 25 V, X5R, 0603

Murata GRM188R61E105K

TDK:C1608X5R1E105M

C

1.0

F

Q5

PMOS,12 V, 16 m, MLP2x2

Fairchild FDMA905P

RDS(ON)

16

m

CREF

1 F, 10%, 6.3 V, X5R, 0402

C

1.0

F

Note:

2. 6.3 V rating is sufficient for CMID since PMID is protected from over-voltage surges on VBUS by Q3.

FAN54040 – FAN54047 • Rev. 1.3 4

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Pin Configuration

Figure 3. Top View

Figure 4. Bottom View

Pin Definitions

Pin #

Name

Description

A1

SDA

I2C Interface Serial Data. This pin should not be left floating.

B1

SCL

I2C Interface Serial Clock. This pin should not be left floating.

C1

DIS

Disable. If this pin is held HIGH, Q1 and Q3 are turned off, creating a HIGH Z condition at VBUS and

the PWM converter is disabled.

D1

STAT

Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in

progress; can be used to signal the host processor when a fault condition occurs.

E1

POK_B

Power OK (FAN54040-2). Open-drain output that pulls LOW when VBUS is plugged in and the battery

has risen above VLOWV. This signal is used to signal the host processor that it can begin to draw

significant current.

E1

ILIM

Input Current Limit (FAN54045-7). Controls input current limit in Auto-Charge Mode. When LOW, input

current is limited to 100 mA maximum. When HIGH, input current is limited to 500 mA. In 32-Second

Mode, the input current limit is set by the IBUSLIM bits.

A2 – D2

PGND

Power Ground. Power return for gate drive and power transistors. The connection from this pin to the

bottom of CMID should be as short as possible.

E2

AGND

Analog Ground. All IC signals are referenced to this node.

A3 – C3

SW

Switching Node. Connect to output inductor.

D3 – E3

SYS

System Supply. Output voltage of the switching charger and input to the power path controller. Bypass

SYS to PGND with a 10 μF capacitor.

A4 – C4

PMID

Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense.

Bypass with a minimum of a 4.7 F, 6.3 V capacitor to PGND.

D4 – E4

VBAT

Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 10 F capacitor

to PGND. VBAT is a power path connection.

A5 – B5

VBUS

Charger Input Voltage and USB-OTG output voltage. Bypass with a 1 F capacitor to PGND.

C5

GATE

External MOSFET Gate. This pin controls the gate of an external P-channel MOSFET transistor used to

augment the internal ideal diode. The source of the P-channel MOSFET should be connected to SYS

and the drain should be connected to VBAT.

D5

NTC

Thermistor input. The IC compares this node with taps on a resistor divider from REF to inhibit auto-

charging when the battery temperature is outside of permitted fast-charge limits.

E5

REF

Reference Voltage. REF is a 1.8 V regulated output.

REF

NTC

PGND

GATEDIS

STAT

SCL

SDA

POK_B

SYS VBAT

SW PMID VBUS

AGND

A1 A2 A3 A4 A5

B1 B3B2 B4 B5

C1 C3C2 C4 C5

D1 D3D2 D4 D5

E1 E3E2 E4 E5

C1

B1

A1

C5

B5

A5 A4

C4

D1D5 D4

B4

E1E5 E4

C3

B3

A3 A2

C2

D3 D2

B2

E3 E2

FAN54040 – FAN54047 • Rev. 1.3 5

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable

above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,

extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute

maximum ratings are stress ratings only.

Symbol

Parameter

Min.

Max.

Unit

VBUS

Voltage on VBUS Pin

Continuous

-0.3

28.0

V

Pulsed, 100 ms Maximum Non-Repetitive

-1.0

VI

Voltage on PMID Voltage Pin

–0.3

7.0

V

Voltage on SW, SYS, VBAT, STAT, DIS Pins

–0.3

7.0

VO

Voltage on Other Pins

–0.3

6.5(3)

V

dt

dVBUS

Maximum VBUS Slope Above 5.5 V when Boost or Charger Active

4

V/s

ESD

Electrostatic Discharge

Protection Level

Human Body Model per JESD22-A114

2000

V

Charged Device Model per JESD22-C101

500

IEC 61000-4-2 System ESD(4)

USB Connector

Pins (VBUS to GND)

Air Gap

15

kV

Contact

8

TJ

Junction Temperature

–40

+150

°C

TSTG

Storage Temperature

–65

+150

°C

TL

Lead Soldering Temperature, 10 Seconds

+260

°C

Note:

3. Lesser of 6.5 V or VI + 0.3 V.

4. Guaranteed if CBUS ≥1 µF and CMID ≥ 4. 7µF.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend

exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min.

Max.

Unit

VBUS

Supply Voltage

4

6

V

VBAT(MAX)

Maximum Battery Voltage when Boost enabled

4.5

V

dt

dVBUS



Negative VBUS Slew Rate during VBUS Short Circuit,

CMID < 4.7 µF, see VBUS Short While Charging

TA < 60°C

4

V/s

TA > 60°C

2

TA

Ambient Temperature

–30

+85

°C

TJ

Junction Temperature (see Thermal Regulation and Protection section)

–30

+120

°C

Thermal Properties

Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer

2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature

TJ(max) at a given ambient temperature TA. For measured data, see Table 18.

Symbol

Parameter

Typical

Unit

JA

Junction-to-Ambient Thermal Resistance (see also Figure 18)

50

°C/W

JB

Junction-to-PCB Thermal Resistance

20

°C/W

FAN54040 – FAN54047 • Rev. 1.3 6

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Electrical Specifications

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;

VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for TJ=25°C.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

Power Supplies

IVBUS

VBUS Current

VBUS > VBUS(min), PWM Switching

10

mA

VBUS > VBUS(min); VBAT > VOREG

IBUSLIM=100 mA

2.5

mA

0°C < TJ < 85°C, HZ_MODE=1

VBAT < VLOWV, 32S Mode, IREG=0

280

µA

IBAT_HZ

Battery Discharge Current in High-

Impedance Mode

DIS=1, or HZ_MODE=1,

VBUS=0, 5 V or Floating, VBAT=4.2 V

<1

10

µA

IBUS_HZ

Battery Leakage Current to VBUS in

High-Impedance Mode

DIS=1, or HZ_MODE=1,

VBUS Shorted to Ground, VBAT=4.2 V

-5.0

-0.2

µA

Charger Voltage Regulation

VOREG

Charge Voltage Range

3.5

4.4

V

Charge Voltage Accuracy

TA=25°C

–0.5

+0.5

%

TJ=0 to 125°C

–1

+1

%

Charging Current Regulation

IOCHRG

Output Charge Current Range

VLOWV < VBAT < VOREG

IO_LEVEL=0

550

1550

mA

IO_LEVEL=1

290

340

390

mA

Charge Current Accuracy

IO_LEVEL=0

–5

+5

%

Weak Battery Detection

VLOWV

Weak Battery Threshold Range

3.4

3.7

V

Weak Battery Threshold Accuracy

–5

+5

%

Weak Battery Deglitch Time

Rising Voltage, 2 mV Overdrive

30

ms

Logic Levels : DIS, SDA, SCL

VIH

High-Level Input Voltage

1.05

V

VIL

Low-Level Input Voltage

0.4

V

IIN

Input Bias Current

Input Tied to GND or VBUS

0.01

1.00

µA

Charge Termination Detection

I(TERM)

Termination Current Range

VBAT > VOREG – VRCH, VBUS > VSLP

50

400

mA

Termination Current Accuracy

ITERM Setting < 100 mA

–15

+15

%

ITERM Setting > 200 mA

–5

+5

Termination Current Deglitch Time

30

ms

Power Path (Q4) Control

ILIN

Power Path Max. Charge Current

IO_LEVEL=1

290

340

390

mA

IBUSLIM > 01,

IOCHARGE < 02

IO_LEVEL=0

400

450

510

mA

IBUSLIM > 01,

IOCHARGE > 02

IO_LEVEL=0

650

725

800

mA

VTHSYS

VBAT to SYS Threshold for Q4 and

Gate Transition While Charging

(SYS-VBAT) Falling

–6

–5

–3

mV

(SYS-VBAT) Rising

-1

+1

2

mV

Production Test Mode

VBAT(PTM)

Production Test Output Voltage

1 mA < IBAT < 2 A, VBUS=5.5 V

4.116

4.200

4.284

V

IBAT(PTM)

Production Test Output Current

20% Duty with Max. Period 10 ms

2.3

A

Continued on the following page…

FAN54040 – FAN54047 • Rev. 1.3 7

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Electrical Specifications (Continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;

VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for TJ=25°C.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

Input Power Source Detection

T1

T1 (0°C) Temperature Threshold

71.9

73.9

75.9

% of

VREF

T2

T1 (10°C) Temperature Threshold

62.6

64.6

66.6

T3

T1 (45°C) Temperature Threshold

31.9

32.9

34.9

T4

T1 (60°C) Temperature Threshold

21.3

23.3

25.3

Input Power Source Detection

VIN(MIN)1

VBUS Input Voltage Rising

To Initiate and Pass VBUS Validation

4.29

4.42

V

VIN(MIN)2

Minimum VBUS during Charge

During Charging

3.71

3.94

V

tVBUS_VALID

VBUS Validation Time

30

ms

VBUS Control Loop

VBUSLIM

VBUS Loop Setpoint Accuracy

–3

+3

%

Input Current Limit

IBUSLIM

Charger Input Current Limit

Threshold

IBUSLIM Set to 100 mA

88

93

98

mA

IBUSLIM Set to 500 mA

450

475

500

VREF Bias Generator

VREF

Bias Regulator Voltage

VBUS > VIN(MIN)

1.8

V

Short-Circuit Current Limit

2.5

mA

Battery Recharge Threshold

VRCH

Recharge Threshold

Below V(OREG)

100

120

150

mV

Deglitch Time

VBAT Falling Below VRCH Threshold

130

ms

STAT, POK_B Output

VSTAT(OL)

STAT Output Low

ISTAT=10 mA

0.4

V

ISTAT(OH)

STAT High Leakage Current

VSTAT=5 V

1

A

Battery Detection

IDETECT

Battery Detection Current before

Charge Done (Sink Current)(5)

Begins after Termination Detected

and VBAT < VOREG –VRCH

–0.8

mA

tDETECT

Battery Detection Time

262

ms

Sleep Comparator

VSLP

Sleep-Mode Entry Threshold,

VBUS – VBAT

2.3 V < VBAT < VOREG, VBUS Falling

0

0.04

0.10

V

Power Switches (see Figure 2)

RDS(ON)

Q3 On Resistance (VBUS to PMID)

IIN(LIMIT)=500 mA

180

250

mΩ

Q1 On Resistance (PMID to SW)

130

225

Q2 On Resistance (SW to GND)

150

225

Q4 On Resistance (SYS to VBAT)

VBAT=4.2 V

70

100

mΩ

ISYNC

Synchronous to Non-Synchronous

Current Cut-Off Threshold(6)

Low-Side MOSFET (Q2) Cycle-by-

Cycle Current Limit

140

mA

Continued on the following page…

FAN54040 – FAN54047 • Rev. 1.3 8

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Electrical Specifications (Continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;

VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for TJ=25°C.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

Charger PWM Modulator

fSW

Oscillator Frequency

2.7

3.0

3.3

MHz

DMAX

Maximum Duty Cycle

100

%

DMIN

Minimum Duty Cycle

0

%

Boost Mode Operation (OPA_MODE=1, HZ_MODE=0)

VBOOST

Boost Output Voltage at VBUS

2.5 V < VBAT < 4.5 V, ILOAD from 0 to

200 mA

4.80

5.07

5.20

V

3.0 V < VBAT < 4.5 V, ILOAD from 0 to

500 mA

4.77

5.07

5.20

IBAT(BOOST)

Boost Mode Quiescent Current

PFM Mode, VBAT=3.6 V, ILOAD=0

250

350

A

ILIMPK(BST)

Q2 Peak Current Limit

1350

1550

1950

mA

UVLOBST

Minimum Battery Voltage for Boost

Operation

While Boost Active

2.32

V

To Start Boost Regulator

2.48

2.70

VBUS Load Resistance

RVBUS

VBUS to PGND Resistance

Normal Operation

500

k

VBUS Validation

100



Protection and Timers

VBUSOVP

VBUS Over-Voltage Shutdown

VBUS Rising

6.09

6.29

6.49

V

Hysteresis

VBUS Falling

100

mV

ILIMPK(CHG)

Q1 Cycle-by-Cycle Peak Current

Limit

Charge Mode

3

A

VSHORT

Battery Short-Circuit Threshold

VBAT Rising

1.95

2.00

2.05

V

Hysteresis

100

mV

ISHORT

Linear Charging Current

VBAT < VSHORT

Power Path

13

mA

Linear

30

TSHUTDWN

Thermal Shutdown Threshold(7)

TJ Rising

145

°C

Hysteresis(7)

TJ Falling

25

TCF

Thermal Regulation Threshold(7)

Charge Current Reduction Begins

120

°C

tINT

Detection Interval

2.1

s

t32S

32-Second Timer(8)

Charger Enabled

20.5

25.2

28.0

s

Charger Disabled

18.0

25.2

34.0

t15MIN

15-Minute Timer

15-Minute Mode (FAN54040,

FAN54042, FAN54046, FAN54047)

12.0

13.5

15.0

min

∆tLF

Low-Frequency Timer Accuracy

Charger Inactive

–25

25

%

Notes:

5. Negative current is current flowing from the battery to VBUS (discharging the battery).

6. Q2 always turns on for 60 ns, then turns off if current is below ISYNC.

7. Guaranteed by design; not tested in production.

8. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers.

FAN54040 – FAN54047 • Rev. 1.3 9

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

I2C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

fSCL

SCL Clock Frequency

Standard Mode

100

kHz

Fast Mode

400

Fast Mode Plus

1000

High-Speed Mode, CB < 100 pF

3400

High-Speed Mode, CB < 400 pF

1700

tBUF

BUS-free Time between STOP and

START Conditions

Standard Mode

4.7

s

Fast Mode

1.3

Fast Mode Plus

0.5

tHD;STA

START or Repeated START Hold

Time

Standard Mode

4

s

Fast Mode

600

ns

Fast Mode Plus

260

ns

High-Speed Mode

160

ns

tLOW

SCL LOW Period

Standard Mode

4.7

s

Fast Mode

1.3

s

Fast Mode Plus

0.5

s

High-Speed Mode, CB < 100 pF

160

ns

High-Speed Mode, CB < 400 pF

320

ns

tHIGH

SCL HIGH Period

Standard Mode

4

s

Fast Mode

600

ns

Fast Mode Plus

260

ns

High-Speed Mode, CB < 100 pF

60

ns

High-Speed Mode, CB < 400 pF

120

ns

tSU;STA

Repeated START Setup Time

Standard Mode

4.7

s

Fast Mode

600

ns

Fast Mode Plus

260

ns

High-Speed Mode

160

ns

tSU;DAT

Data Setup Time

Standard Mode

250

ns

Fast Mode

100

Fast Mode Plus

50

High-Speed Mode

10

tHD;DAT

Data Hold Time

Standard Mode

0

3.45

s

Fast Mode

0

900

ns

Fast Mode Plus

0

450

ns

High-Speed Mode, CB < 100 pF

0

70

ns

High-Speed Mode, CB < 400 pF

0

150

ns

tRCL

SCL Rise Time

Standard Mode

20+0.1CB

1000

ns

Fast Mode

20+0.1CB

300

Fast Mode Plus

20+0.1CB

120

High-Speed Mode, CB < 100 pF

10

80

High-Speed Mode, CB < 400 pF

20

160

Continued on the following page…

FAN54040 – FAN54047 • Rev. 1.3 10

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

I2C Timing Specifications (Continued)

Guaranteed by design.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

tFCL

SCL Fall Time

Standard Mode

20+0.1CB

300

ns

Fast Mode

20+0.1CB

300

Fast Mode Plus

20+0.1CB

120

High-Speed Mode, CB < 100 pF

10

40

High-Speed Mode, CB < 400 pF

20

80

tRCL1

Rise Time of SCL after a Repeated

START Condition and after ACK Bit

High-Speed Mode, CB < 100 pF

10

80

ns

High-Speed Mode, CB < 400 pF

20

160

tRDA

SDA Rise Time

Standard Mode

20+0.1CB

1000

ns

Fast Mode

20+0.1CB

300

Fast Mode Plus

20+0.1CB

120

High-Speed Mode, CB < 100 pF

10

80

High-Speed Mode, CB < 400 pF

20

160

tFDA

SDA Fall Time

Standard Mode

20+0.1CB

300

ns

Fast Mode

20+0.1CB

300

Fast Mode Plus

20+0.1CB

120

High-Speed Mode, CB < 100 pF

10

80

High-Speed Mode, CB < 400 pF

20

160

tSU;STO

Stop Condition Setup Time

Standard Mode

4

s

Fast Mode

600

ns

Fast Mode Plus

120

ns

High-Speed Mode

160

ns

CB

Capacitive Load for SDA and SCL

400

pF

FAN54040 – FAN54047 • Rev. 1.3 11

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Timing Diagrams

Figure 5. I2C Interface Timing for Fast and Slow Modes

Figure 6. I2C Interface Timing for High-Speed Mode

START

REPEATED

START

SCL

SDA

tF

tHD;STA

tLOW

tR

tHD;DAT

tHIGH

TSU;DAT

tSU;STA

tHD;STO

tBUF

START STOP

tHD;STA

REPEATED

START

SCLH

SDAH

tFDA

tLOW

tRCL1

tHD;DAT

tHIGH

tSU;STO

REPEATED

START

tRDA

tFCL

tSU;DAT

tRCL

STOP

= MCS Current Source Pull-up

= RP Resistor Pull-up

note A

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

tHD;STA

tSU;STA

FAN54040 – FAN54047 • Rev. 1.3 12

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25°C.

Figure 7. Battery Charge Current vs. VBUS with

IBUSLIM=100 mA

Figure 8. Battery Charge Current vs. VBUS with

IBUSLIM=500 mA

Figure 9. Efficiency vs. VBUS, IBUSLIM=500 mA, ISYS=0

Figure 10. Efficiency vs. Charging Current,

IBUSLIM=No Limit

80

90

100

110

120

130

140

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

Battery Charge Current (mA)

Battery Voltage VBAT (V)

4.5 VBUS

5.0 VBUS

5.5 VBUS

200

300

400

500

600

700

800

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

Battery Charge Current (mA)

Battery Voltage VBAT (V)

4.5 VBUS

5.0 VBUS

5.5 VBUS

65

70

75

80

85

90

95

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

Efficiency (%)

Battery Voltage VBAT (V)

4.5 VBUS

5.0 VBUS

5.5 VBUS

78

80

82

84

86

88

90

550 750 950 1150 1350 1550

Efficiency (%)

Battery Charge Current IBAT (mA)

4.5VBUS, 3.9VBAT

5.0VBUS, 3.54VBAT

5.0VBUS, 4.2VBAT

5.5VBUS, 3.9VBAT

FAN54040 – FAN54047 • Rev. 1.3 13

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25°C.

Figure 11. Charger Startup at VBUS Plug-In, 100 mA

IBUSLIM, 3.2 VBAT, 100 Ω SYS Load

Figure 12. Charger Startup at VBUS Plug-In, 500 mA

IINBUSLIM, 3.2 VBAT, 100 Ω SYS Load

Figure 13. Charger Startup at VBUS Plug-In Using

300 mA Current Limited Source, 500 mA IBUSLIM,

3.2 VBAT, 50  SYS Load

Figure 14. Charger Startup with HZ Bit Reset, 500 mA

IBUSLIM, 950 mA ICHARGE, 50 SYS Load

FAN54040 – FAN54047 • Rev. 1.3 14

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25°C.

Figure 15. Battery Removal / Insertion while Charging,

TE=0, 3.9 VBAT, ICHRG=950 mA, IBUSLIM=No Limit, 50 Ω

SYS Load

Figure 16. Battery Removal / Insertion when

Charging, TE=1, 3.9 VBAT, ICHRG=950 mA, IBUSLIM=No

Limit, 50 Ω SYS Load

Figure 17. No Battery at VBUS Power-Up, FAN54040, 100 Ω

SYS Load, 1 kΩ VBAT Load

Figure 18. No Battery at VBUS Power-Up, FAN54042,

100 Ω SYS Load, 1 kΩ VBAT Load

FAN54040 – FAN54047 • Rev. 1.3 15

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, VOREG=4.2 V, VBUS=5.0 V, and TA=25°C.

Figure 19. HZ Mode VBUS Current vs. Temperature,

3.7 VBAT

Figure 20. VREF vs. Load Current, Over-Temperature,

5.0 VBUS

Figure 21. Charging vs. Temperature (NTC), +30°C to -10°C

3.7 VBAT, ICHRG=950 mA, No IBUSLIM, 100 Ω SYS Load

Figure 22 Charging vs. Temperature (NTC), +30°C to +70°C

3.7 VBAT, ICHRG=950 mA, No IBUSLIM, 100 Ω SYS Load

0

200

400

600

800

1,000

4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

High-Z Mode Input Current (μA)

VBUS Input Voltage (V)

-30C

+25C

+85C

1.00

1.20

1.40

1.60

1.80

2.00

0 1 2 3 4 5

VREF Output Voltage (V)

VREF Load Current (mA)

-30C

+25C

+85C

FAN54040 – FAN54047 • Rev. 1.3 16

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

GSM Typical Characteristics

A 2.0 A GSM pulse applied at VBAT with 5 µs rise / fall time. Simultaneous to GSM pulse, 50 Ω additional load applied at SYS.

Figure 23. 2.0 A GSM Pulse Response, IBUSLIM=500 mA

Control, ICHRG=950 mA, 3.7 VBAT, OREG=4.2 V

Figure 24. 2.0 A GSM Pulse Response, IBUSLIM=500 mA,

ICHRG=950 mA, 3.7 VBAT, OREG=4.2 V, 200 mA Source

Current Limit

FAN54040 – FAN54047 • Rev. 1.3 17

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 1, VBAT=3.6 V, TA=25°C.

Figure 25. Efficiency vs. IBUS Over VBAT

Figure 26. Efficiency vs. IBUS Over-Temperature, 3.6 VBAT

Figure 27. Regulation vs. IBUS Over VBAT

Figure 28. Output Ripple vs. IBUS Over VBAT

Figure 29. Quiescent Current (IQ) vs. VBAT Over-

Temperature

Figure 30. Battery Discharge Current vs. VBAT, HZ /

Sleep Mode

75

80

85

90

95

100

0100 200 300 400 500

Efficiency (%)

VBUS Load Current (mA)

2.7VBAT

3.6VBAT

4.2VBAT

75

80

85

90

95

100

0100 200 300 400 500

Efficiency (%)

VBUS Load Current (mA)

-10C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

4.85

4.90

4.95

5.00

5.05

5.10

5.15

0100 200 300 400 500

Output Voltage VBUS (V)

VBUS Load Current (mA)

2.7VBAT

3.6VBAT

4.2VBAT

0

5

10

15

20

25

30

0100 200 300 400 500

VBUS Ripple (mVpp)

VBUS Load Current (mA)

2.7VBAT

3.6VBAT

4.2VBAT

100

150

200

250

300

350

2 2.5 3 3.5 4 4.5 5

OTG/Boost Quiescent Current (µA)

Battery Voltage, VBAT (V)

-30C

+25C

+85C

0

2

4

6

8

10

2 2.5 3 3.5 4 4.5 5

HZ Mode Battery Current (µA)

Battery Voltage, VBAT (V)

-30C

+25C

+85C

FAN54040 – FAN54047 • Rev. 1.3 18

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 1, VBAT=3.6 V, TA=25°C.

Figure 31. OTG Startup, 50 Ω Load, 3.6 VBAT

External / Additional 10 µf on VBUS

Figure 32. OTG VBUS Overload Response

Figure 33. Load Transient, 20-200-20 mA IBUS,

tRISE/FALL=100 ns

Figure 34. Line Transient, 50 Ω Load, 3.9-3.3-

3.9 VBAT, tRISE/FALL=10 µs

FAN54040 – FAN54047 • Rev. 1.3 19

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Circuit Description / Overview

When charging batteries with a current-limited input source,

such as USB, a switching charger’s high efficiency over a

wide range of output voltages minimizes charging time.

FAN5404X combines a highly integrated synchronous buck

regulator for charging with a synchronous boost regulator,

which can supply 5 V to USB On-The-Go (OTG) peripherals.

The FAN5404X employs synchronous rectification for both

the charger and boost regulators to maintain high efficiency

over a wide range of battery voltages and charge states.

The FAN5404X has four operating modes:

1. Charge Mode:

Charges a single-cell Li-ion or Li-polymer battery.

2. Boost Mode:

Provides 5 V power to USB-OTG with an integrated

synchronous rectification boost regulator, using the

battery as input.

3. High-Impedance Mode:

Both the boost and charging circuits are OFF in this

mode. Current flow from VBUS to the battery or from the

battery to VBUS is blocked in this mode. This mode

consumes very little current from VBUS or the battery.

4. Production Test Mode

This mode provides 4.2 V output on VBAT and supplies

a load current of up to 2.3 A.

Charge Mode

In Charge Mode, FAN5404X employs six regulation loops:

1. Input Current: Limits the amount of current drawn from

VBUS. This current is sensed internally and can be

programmed through the I2C interface.

2. Charging Current: Limits the maximum charging current.

This current is sensed using an internal sense

MOSFET.

3. VBUS Voltage: This loop is designed to prevent the

input supply from being dragged below VBUSLIM (typically

4.5 V) when the input power source is current limited.

An example of this would be a travel charger. This loop

cuts back the current when VBUS approaches VBUSLIM,

allowing the input source to run in current limit.

4. Charge Voltage: The regulator is restricted from

exceeding this voltage. As the internal battery voltage

rises, the battery’s internal impedance works in

conjunction with the charge voltage regulation to

decrease the amount of current flowing to the battery.

Battery charging is completed when the current through

Q4 drops below the ITERM threshold.

5. Power Path: When VBAT is below VBATMIN, Q4 operates

as a linear current source and modulates its current to

ensure that the voltage on SYS stays above 3.4 V.

6. Temperature: If the IC’s junction temperature reaches

120°C, charge current is reduced until the IC’s

temperature is below 120°C.

Battery Charging Curve

If the battery voltage is below VSHORT, a linear current source

pre-charges the battery until VBAT reaches VSHORT. The PWM

charging circuit is then started and the battery is charged

with a constant current if sufficient input power is available.

The current slew rate is limited to prevent overshoot.

The FAN5404X is designed to work with a current-limited

input source at VBUS. During the current regulation phase of

charging, IBUSLIM or the programmed charging current limits

the amount of current available to charge the battery and

power the system. The effect of IBUSLIM on ICHARGE can be

seen in Figure 36.

IBAT

ISHORT

CHARGE CONSTANT

CURRENT (CC) CONSTANT

VOLTAGE (CV)

PRE-

CHARGE RE-

CHARGE

BATTERY VOLTAGE DECAY

ICHARGE Current Charging

VFLOAT

ICHARGE

VSHORT

ISHORT

ITERM

VBAT

VBATMIN

IO_LEVEL

Figure 35. Charge Curve, ICHARGE Not Limited by IINLIM

IBAT

ISHORT

CHARGE CONSTANT

CURRENT (CC) CONSTANT

VOLTAGE (CV)

PRE-

CHARGE RE-

CHARGE

BATTERY VOLTAGE DECAY

Input Current Limited Charging

VBAT

VFLOAT

ICHARGE

IO_LEVEL

VBATMIN

VSHORT

ISHORT

ITERM

Figure 36. Charge Curve, IBUSLIM Limits ICHARGE

Assuming that VOREG is programmed to the cell’s fully

charged “float” voltage, the current that the battery accepts

with the PWM regulator limiting its output (sensed at VBAT)

to VOREG declines and the charger enters the voltage

regulation phase of charging. When the current declines to

the programmed ITERM value, the charge cycle is complete.

Charge current termination can be disabled by resetting the

TE bit (REG1[3]).

The charger output or “float” voltage can be programmed by

the OREG bits from 3.5 V to 4.44 V in 20 mV increments, as

shown in Table 4.

FAN54040 – FAN54047 • Rev. 1.3 20

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

The following charging parameters can be programmed by

the host through I2C:

Table 3. Programmable Charging Parameters

Parameter

Name

Register

Output Voltage Regulation

VOREG

REG2[7:2]

Battery Charging Current Limit

IOCHRG

REG4[6:3]

Input Current Limit

IINLIM

REG1[7:6]

Charge Termination Limit

ITERM

REG4[2:0]

Weak Battery Voltage

VLOWV

REG1[5:4]

Table 4. OREG Bits (OREG[7:2]) vs. Charger VOUT

(VOREG) Float Voltage

Decimal

Hex

VOREG

Decimal

Hex

VOREG

0

00

3.50

24

18

3.98

1

01

3.52

25

19

4.00

2

02

3.54

26

1A

4.02

3

03

3.56

27

1B

4.04

4

04

3.58

28

1C

4.06

5

05

3.60

29

1D

4.08

6

06

3.62

30

1E

4.10

7

07

3.64

31

1F

4.12

8

08

3.66

32

20

4.14

9

09

3.68

33

21

4.16

10

0A

3.70

34

22

4.18

11

0B

3.72

35

23

4.20

12

0C

3.74

36

24

4.22

13

0D

3.76

37

25

4.24

14

0E

3.78

38

26

4.26

15

0F

3.80

39

27

4.28

16

10

3.82

40

28

4.30

17

11

3.84

41

29

4.32

18

12

3.86

42

2A

4.34

19

13

3.88

43

2B

4.36

20

14

3.90

44

2C

4.38

21

15

3.92

45

2D

4.40

22

16

3.94

46

2E

4.42

23

17

3.96

47 - 63

2F-3F

4.44

Note:

9. Default settings are denoted by bold typeface.

Provided DIS, CE# and HZ_MODE are LOW, a new charge

cycle begins when one of the following occurs:

1. The battery voltage falls below VOREG - VRCH after

charge termination has occurred.

2. Any I2C write occurs causing the T32 s timer to run.

Products that include the auto-charge feature also begin

charging if:

3. VBUS Power-on-Reset (POR) occurs and the battery

voltage is below the weak battery threshold (VLOWV).

Charge Current Limit (IOCHARGE)

Table 5. IOCHARGE Current as Function of IOCHARGE

Bits (REG4 [6:3])

DEC

BIN

HEX

IOCHARGE (mA)

0

0000

0

550

1

0001

1

650

2

0010

2

750

3

0011

3

850

4

0100

4

950

5

0101

5

1,050

6

0110

6

1,150

7

0111

7

1,250

8

1000

8

1,350

9

1001

9

1,450

10-15

1010-1111

A-F

1,550

When the IO_LEVEL bit is set (default), the IOCHARGE bits are

ignored and charge current is set to 340 mA.

PWM Controller in Charge Mode

The IC uses a current-mode PWM controller to regulate the

output voltage and battery charge currents. The synchronous

rectifier (Q2) has a negative current limit that turns off Q2 at

140 mA to prevent current flow from the battery.

Termination Current Limit

Current charge termination is enabled when TE (REG1[3])=1.

Typical termination current values are given in Table 6.

Table 6. Termination Current as Function of ITERM

Bits (REG4[2:0]) or PC_IT Bits (REG7[2:0]

ITERM Bits or PC_IT Bits

Termination Current

(mA)

0

50

1

100

2

150

3

200

4

250

5

300

6

350

7

400

When the charge current falls below ITERM; PWM charging

stops, but the STAT pin remains LOW. The STAT pin then

goes HIGH and the STATUS bits change to CHARGE DONE

(10), provided the battery and charger are still connected.

A post-charging feature, “top-off” charging, is available to

continue the battery charging to a lower charge current to

maximize battery capacity. The PC_EN bit must be set to 1

before the battery charging current reaches the termination

current ITERM for normal charging. The post-charging

termination current is set by the PC_IT[2:0] bits, as shown in

Table 6. If PC_EN is set to 1; right after the normal charging

is ended as described above, post charging is started with

PC_ON monitor bit set to 1. Once the current reaches the

FAN54040 – FAN54047 • Rev. 1.3 21

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

threshold for post-charging completion, PWM charging stops

and PC_ON bit changes back to 0.

During post-charging, the STAT pin is HIGH, indicating that

the charge current is below the ITERM level. To exit post-

charging, one of the following must occur: a VBUS POR, the

POK_B cycled when VBAT <3.0 V, or the CE# or HZ_Mode

bit cycled.

Safety Timer

At the beginning of charging, the IC starts a 15-minute timer

(t15MIN ). When this timer times out, charging is terminated.

Writing to any register through I2C stops and resets the t15MIN

timer, which in turn starts a 32-second timer (t32S). Setting

the TMR_RST bit (REG0[7]) resets the t32S timer. If the t32S

timer times out; charging is terminated, the registers are set

to their default values, and charging resumes using the

default values with the t15MIN timer running.

Normal charging is controlled by the host with the t32S timer

running to ensure that the host is alive. Charging with the

t15MIN timer running is used for charging unattended by the

host. If the t15MIN timer expires, the IC turns off the charger

and indicates a timer fault (110) on the FAULT bits

(REG0[2:0]). This sequence prevents overcharge if the host

fails to reset the t32S timer.

VBUS POR / Non-Compliant Charger Rejection

256 ms after VBUS is connected, the IC pulses the STAT pin

and sets the VBUS_CON bit. Before starting to supply

current, the IC applies a 110  load from VBUS to GND.

VBUS must remain above VIN(MIN)1 and below VBUSOVP for

tVBUS_VALID (32 ms) before the IC initiates charging or

supplies power to SYS. The VBUS validation sequence

always occurs before significant current is drawn from VBUS

(for example, after a VBUS OVP fault or a VRCH recharge

initiation). tVBUS_VALID ensures that unfiltered 50/60 Hz

chargers and other non-compliant chargers are rejected.

USB-Friendly Boot Sequence

At VBUS POR, when the battery voltage is above the weak

battery threshold (VLOWV); the IC operates in accordance with

its I2C register settings. If VBAT < VLOWV and t32s is not

running, the IC sets all registers to their default values and

begins to deliver power to SYS.

FAN54040, FAN54042, and FAN54047 feature auto-charge,

which allow these parts to deliver charge to the battery prior

to receiving host commands.

FAN54041 does not automatically initiate charging at VBUS

POR. Instead, it waits in IDLE state for the host to initiate

charging through I2C commands. While in IDLE state, Q4

and Q5 are on. This allows the system to run through a

separate power path without requiring an additional

disconnection MOSFET.

Power Path Operation

As long as VBAT < VBATMIN, Q4 operates as a linear current

source, (Power Path Mode) with its current limited to

340 mA. The IC then regulates SYS to 3.54 V and attempts

to charge the battery with as much current as possible with

the available IBUSLIM input current, without allowing SYS to

drop below 3.4 V. This ensures that system power always

receives first priority from a limited input supply. During this

time, POK_B is HIGH. If VBAT < VSHORT, Q4’s current is

further reduced to about 13 mA (ISHORT) when IBUSLIM is set to

100 or 500 mA. For all other input current limits, ISHORT

current is approximately 30 mA.

The POK_B signal can be used to keep the system in a low-

power state, preventing excessive loading from the system

while attempting to charge a depleted battery.

Table 7. VBATMIN Thresholds to Exit Power Path

Mode

IBUSLIM (mA)

VBATMIN (V)

100

3.4

500

3.3

800

3.2

No Limit

3.2

After VBAT reaches VBATMIN, Q4 closes and is used as a

current-sense element to limit ICHARGE per the I2C register

settings by limiting the PWM modulator’s current (Full PWM

Mode). During PWM Mode, if SYS drops more than 5 mV

(VTHSYS) below VBAT, Q4 and Q5 are turned on (GATE is

pulled LOW). Once SYS voltage becomes higher than VBAT,

Q5 is turned off and Q4 again serves as the current-sense

element to limit IOCHARGE.

Q4 and Q5 are both turned on when the IC enters SLEEP

Mode (VBUS < VBAT).

POK_B pulls LOW once VBAT reaches VLOWV, and remains

LOW as long as the IC is in Full PWM Mode. The IC remains

in Full PWM Mode as long as VBAT > 3.0 V, at which point,

the IC enters Power Path Charging Mode.

Startup with a Dead Battery

At VBUS POR, a 2 k load is applied to VBAT for 256 ms to

discharge any residual system capacitance in case the

battery is absent or its discharge protection switch is open.

If VBAT < VLOWV, all registers are reset to default values and

the IC charges in T15Min Mode. If VBAT < VSHORT, the

SAFETY register is reset to its default value and the Battery

Detection test below is performed.

Battery Detection

If VBAT is below VSHORT when charging is enabled, the

DBAT_B bit is reset and the IC (except FAN54045 and

FAN54046) performs an addition battery detection test.

After VBAT rises above VSHORT, PWM charging begins (when

CE# = 0) with the float voltage (VOREG) temporarily set to 4 V.

If the battery voltage exceeds 3.7 V within 32 ms of the

beginning of PWM charging, the battery is absent. If battery

absence is detected:

1. STAT pulses, with FAULT bits set to 111, and the

NOBAT bit is set.

2. For FAN54040 only; the t15MIN timer is disabled until

VBUS is removed, IDLE state is entered, and POK_B

remains HIGH.

3. The IC bypasses the protection switch close test below,

since no battery is present.

The FAN54042 and FAN54047 continue to charge.

If VBAT remained below 3.7 V during the initial 32 ms period,

Power Path Mode charging continues to ensure that the

FAN54040 – FAN54047 • Rev. 1.3 22

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

battery’s discharge protection switch has closed before

exiting Power Path Mode:

1. If VBAT is less than 3.4 V, VSYS is set to 4 V, and Power

Path charging continues until VBAT has exceeded 3.4 V

for at least 128 ms. Charging continues until:

2. VBAT has dropped below 3.2 V for at least 32 ms. Once

this occurs, VSYS returns to the OREG register setting

(default 3.54 V).

3. VBAT has again risen above VBATMIN for at least 4 ms.

After these three events, PWM Mode is entered and the IC

sets the DBAT_B bit. If the host sets the DBAT_B bit

(Reg2[1]), events 1 and 2 above are skipped and PWM

Mode is entered once VBAT rises above VBATMIN.

In a typical application, as soon as the host processor has

cleared its UVLO threshold (typically 3.3 V), the host’s low

level software would set the IBUSLIM and IOCHARGE

registers to charge the battery more rapidly above VBATMIN as

soon as the host determines that more than 100 mA is

available through VBUS (see Figure 37).

Once the host processor begins writing to the IC, charge

parameters are set by the host, which must continually reset

the t32S timer to continue charging using the programmed

charging parameters.

If t32S times out; the register defaults are loaded, the FAULT

bits are set to 110, STAT is pulsed, and charging continues

with default charge parameters in T15MIN Mode for the

FAN54040, FAN54042, and FAN54047.

POK_B (see Table 8)

The POK_B pin and bit are intended to provide feedback to

the baseband processor that the battery is strong enough to

allow the device to fully function. Whenever the IC is

operating in Power Path Mode, POK_B is HIGH. On exiting

Power Path Mode, POK_B remains HIGH until VBAT > VLOWV.

Reg1[5:4] sets the VLOWV threshold.

The STAT pin pulses any time the POK_B pin changes.

Table 8. Q4, Q5, POK_B, and GATE Operation vs. Charging Mode

Q4 CC-CV Control

VBUS

VBAT

VSYS

Q4

Q5

GATE

POK_B

Power Path Mode: Maintain VSYS > 3.4 V

Valid

< VBATMIN

<3.4

Linear

OFF

HIGH

Power Path Mode: Limit ICHARGE < 340 mA

Valid

< VBATMIN

> 3.4

Linear

OFF

HIGH

PWM Mode. Q4 Senses Current for ICHARGE

Valid

> VBATMIN and < VLOWV

X

ON

OFF

HIGH

> VLOWV

LOW

OFF

<VBAT

X

ON

LOW

HIGH

Note:

10. POK_B remains LOW until Q4 returns to Power Path Mode. Q4 and Q5 are both ON if VSYS < VBAT and CE# = 0.

If CE# = 1 and VSYS < VBAT, Q5 is OFF and Q4 blocks current flow from VBAT to SYS.

Table 9. Q4, Q5 Operation as a Function of Relationship between VBUS and VBAT

PWM

Charger

CE#

VBUS

VBAT

Q4

Q5

GATE

ON

PWM Mode

0

Valid

< VSYS,

>VBATMIN

ON

OFF

HIGH

ON

PWM Mode

0

Valid

> VSYS,

>VBATMIN

ON

LOW

ON

Disabled

1

Valid

X

OFF

HIGH

ON

Power Path Charging

0

Valid

2 V < VBAT <

VBATMIN

Linear

OFF

HIGH

OFF

30 mA Linear Charging

X

Valid

< 2 VBAT

ON

LOW

OFF

X

ON

LOW

FAN54040 – FAN54047 • Rev. 1.3 23

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Figure 37. Recommended Host Software Sequence when Booting with Dead Battery

System Wake-up

HALT

Load Low-level

software

Determine USB

power available

Set IINLIM per USB

power available,

reset IO_LEVEL and

set IOCHARGE bits

Battery

Installed? NO

YES

NO

2 minutes

elapsed?

DEADBAT

bit SET?

YES

NO

SET

DEADBAT bit

YES

Set all charge

parameters

Set Safety

Register

Set TMR_RST bit

every 10 sec.

POK_B = 0?

YES

NO

YES

Load full

functionality

FAN54040 – FAN54047 • Rev. 1.3 24

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Battery Temperature (NTC) Monitor

The FAN5404X reduces the maximum charge current and

termination voltage if an NTC measuring battery temperature

(TBAT) indicates that it is outside the fast-charging limits (T2

to T3), as described in the JEITA specification1. There are

four temperature thresholds that change battery charger

operation: T1, T2, T3, and T4, shown in Table 10.

Table 10. Battery Temperature Thresholds

For use with 10 kΩ NTC,  = 3380, and RREF = 10 kΩ.

Threshold

Temperature

% of VREF

T1

0°C

73.9

T2

10°C

64.6

T3

45°C

32.9

T4

60°C

23.3

Table 11. Charge Parameters vs. TBAT

TBAT (°C)

ICHARGE

VFLOAT

Below T1

Charging to VBAT Disabled

Between T1 and T2

IOCHARGE / 2(11)

4.0 V

Between T2 and T3

IOCHARGE

VOREG

Between T3 and T4

IOCHARGE / 2(11)

4.0 V

Above T4

Charging to VBAT Disabled

Note:

11. If IOCHARGE is programmed to less than 650 mA, the

charge current is limited to 340 mA.

Thermistors with other  values can be used, with some shift

in the corresponding temperature threshold, as shown in

Table 12.

Table 12. Thermistor Temperature Thresholds

RREF = RTHRM at 25°C

Parameter

Various Thermistors

RTHRM(25°C)

10 kΩ

47 kΩ

100 kΩ



3380

3940

4050

4250

T1

0°C

3°C

6

8

T2

10°C

12°C

13

14

T3

45°C

42°C

41

40

T4

60°C

55°C

53

51

1 Japan Electronics and Information Technology Industries

Association (JEITA) and Battery Association of Japan. “A Guide to

the Safe Use of Secondary Lithium Ion Batteries in Notebook-type

Personal Computers,” April 28, 2007.

The host processor can disable temperature-driven control

of charging parameters by writing 1 to the TEMP_DIS bit.

Since TEMP_DIS is reset whenever the IC resets its

registers, the temperature controls are enforced whenever

the IC is auto-charging, since auto-charge is always

preceeded by a reset of registers.

To disable the thermistor circuit, tie the NTC pin to GND.

Before enabling the charger, the IC tests to see if NTC is

shorted to GND. If NTC is shorted to GND, no thermistor

readings occur and the NTC_OK and NTC1-NTC4 is reset.

The IC first measures the NTC immediately prior to entering

any PWM charging state, then measures the NTC once per

second, updating the result in NTC1-NTC4 bits (Reg

12H[3:0]).

Table 13. NTC1-NTC4 Decoding

TBAT (°C)

NTC4

NTC3

NTC2

NTC1

Above T4

1

Between T3 and T4

0

1

Between T2 and T3

0

1

Between T1 and T2

0

1

Below T1

0

FAN54040 – FAN54047 • Rev. 1.3 25

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Flow Charts

Figure 38. Charger VBUS POR Flow Chart

Figure 39. Ready State Flow Chart

VBUS POR

YES

Ready State

NO

Reset all registers

Start T32SEC

HZ State

Charge State

YES

NO

T32Sec

Armed?

NO

YES

HZ or

DISABLE Pin

set?

VBAT > VLOWV

YES

HZ, or

DISABLE Pin

set?

T32Sec

Armed?

NO

YES

HZ_STATE

VBAT > VLOWV?

YES

RUN

T32Sec

NO

HZ or

DISABLE Pin

set?

YES

Ready State PWM = OFF

Q4, Q5 = ON

NO

T32Sec

Armed? YES Charge State

FAN54040 – FAN54047 • Rev. 1.3 26

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

YES

CHARGE STATE

YES

NO

VBAT < VSHORT VBAT < VSHORT

YES

Linear Charging

Reset Safety reg

VBUS OK?

Indicate timer fault

Indicate Charge

Complete

Battery absent

behavior?

OFF

Protection

switch closed? NO

Enable PWM

VBAT < VBATMIN

Enable PowerPath

charging

CE# = 1

IDLE State

NO

Timer

Running?

YES

NO

YES

NO

Enable PWM

charging

IDLE State

T15MIN T.O. or

[T32S T.O. and

FAN54041] ?

IDLE State

YES

Indicate VBUS

Fault

NO

YES

Battery

Present? NO

Battery Removed

Reset charge

parameters &

Safety Regs

YES

VBAT <

VOREG–VRCH

?

CHARGE

STATE

NO

YES

NO

NO IOUT < ITERM

and TE = 1

YES

PWM ON

Q4 and Q5 OFF

Enable PWM

FIRST TIME?

YES

NO

Disable PWM for

2 seconds

EOC = 1

NO

YES

NO

Battery

Present?

Enunciate

battery absent

fault

NO

CE# = 1

NO

YES

ON

YES

Figure 40. Charge State Flow Chart

FAN54040 – FAN54047 • Rev. 1.3 27

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Figure 41. HZ State

Figure 42. IDLE State

Stop T32Sec

HZ State

NO

Start timer and GOTO

Charge State

VBAT > VLOWV?

YES YES

Run T32Sec

Reset T15min

if running

DIS

PIN HIGH

LOW

NO

HZ_MODE or

DIS pin set?

PWM = OFF

Q4, Q5 = ON

Timer

Armed?

YES

NO IDLE STATE

HZ STATE

YES

NO

HZ or

DISABLE Pin

set?

YES

IDLE State PWM = OFF

Q4, Q5 = ON

NO

T32Sec

Armed?

Charge State

FAN54040 – FAN54047 • Rev. 1.3 28

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Charge Start

Start T15MIN

T15MIN

Active?

Reset Registers

YES

NO

Start T32SEC

Stop T15MIN

I2C Write

Received?

YES

T15MIN

Expired?

NO Continue

Charging

T32SEC

Expired?

YES

NO

YES

Timer Fault

PWM = OFF

Figure 43. Timer Flow Chart for FAN54040, FAN54042, FAN54047

Charge Start

from Host control

Charge T32SEC

Expired? YES Timer Fault

Stop PWM and

Reset Registers

TMR_RST

Bit Set?

Reset

T32SEC

YES

NO

Figure 44. Timer Flow Chart for FAN54041

Input Current Limiting

To minimize charging time without overloading VBUS current

limitations, the IC’s input current limit can be programmed by

the IBUSLIM bits (REG1[7:6]).

Table 14. Input Current Limit

IBUSLIM REG1[7:6]

Input Current Limit

00

100 mA

01

500 mA

10

800 mA

11

No Limit

For the FAN54041, no charging occurs automatically at

VBUS POR, so the input current limit is established by the

IBUSLIM bits.

VBUS Control loop

The IC includes a control loop that limits input current in

case a current-limited source is supplying VBUS.

The control increases the charging current until either:

 IBUSLIM or IOCHARGE is reached OR

 VBUS=VBUSLIM.

If VBUS collapses to VBUSLIM, the VBUS loop reduces its

current to keep VBUS=VBUSLIM. When the VBUS control loop

is limiting the charge current, the VLIM bit (REG5[3]) is set.

FAN54040 – FAN54047 • Rev. 1.3 29

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Table 15. VBUS Limit as Function of VBUSLIM Bits

(REG5[2:0])

VBUSLIM (REG5[2:0])

DEC

BIN

HEX

VBUSLIM

0

000

0

4.213

1

001

1

4.293

2

010

2

4.373

3

011

3

4.453

4

100

4

4.533

5

101

5

4.613

6

110

6

4.693

7

111

7

4.773

Safety Settings

The IC contains a SAFETY register (REG6) that prevents

the values in OREG (REG2[7:2]) and IOCHARGE

(REG4[7:4]) from exceeding the values of the VSAFE and

ISAFE values.

After VBAT rises above VSHORT, the SAFETY register is

loaded with its default value and may be written to only

before writing to any other register. The same 8-bit value

should be written to the Safety register twice to set the

register value. After writing to any other register, the

SAFETY register is locked until VBAT falls below VSHORT.

The ISAFE (REG6[7:4]) and VSAFE (REG6[3:0]) registers

establish values that limit the maximum values of IOCHARGE

and VOREG used by the control logic. If the host attempts to

write a value higher than VSAFE or ISAFE to OREG or

IOCHARGE, respectively; the VSAFE, ISAFE value appears

as the OREG, IOCHARGE register value, respectively.

Table 16. Maximum IOCHARGE as Function of ISAFE

Bits (REG6[7:4])

DEC

BIN

HEX

IOCHARGE(MAX) (mA)

0

0000

0

550

1

0001

1

650

2

0010

2

750

3

0011

3

850

4

0100

4

950

5

0101

5

1,050

6

0110

6

1,150

7

0111

7

1,250

8

1000

8

1,350

9

1001

9

1,450

10-15

1010-1111

A-F

1,550

Table 17. VSAFE (VOREG Limit) as Function of VSAFE

Bits (REG6[3:0])

VSAFE (REG6[3:0])

DEC

BIN

HEX

OREG Max.

(REG2[7:2])

VOREG

Max.

0

0000

0

100011

4.20

1

0001

1

100100

4.22

2

0010

2

100101

4.24

3

0011

3

100110

4.26

4

0100

4

100111

4.28

5

0101

5

101000

4.30

6

0110

6

101001

4.32

7

0111

7

101010

4.34

8

1000

8

101011

4.36

9

1001

9

101100

4.38

10

1010

A

101101

4.40

11

1011

B

101110

4.42

12-15

1100-1111

C-F

101111-110010

4.44

Thermal Regulation and Protection

When the IC’s junction temperature reaches TCF (about 120°C),

the charger reduces its output current to 550 mA to prevent

overheating. If the temperature increases beyond TSHUTDOWN;

charging is suspended, the FAULT bits are set to 101, and

STAT is pulsed HIGH. In Suspend Mode, all timers stop and the

state of the IC’s logic is preserved. Charging resumes at

programmed current after the die cools to about 120°C.

Additional JA data points, measured using the FAN54040

evaluation board, are given in Table 18 (measured with

TA=25°C). Note that as power dissipation increases, the

effective JA decreases due to the larger difference between

the die temperature and ambient.

Table 18. Evaluation Board Measured JA

Power (W)

JA

0.504

54°C/W

0.844

50°C/W

1.506

46°C/W

FAN54040 – FAN54047 • Rev. 1.3 30

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Charge Mode Input Supply Protection

Sleep Mode

When VBUS falls below VBAT + VSLP and VBUS is above VIN(MIN),

the IC enters Sleep Mode to prevent the battery from

draining into VBUS. During Sleep Mode, reverse current is

disabled by body switching Q1.

Input Supply Low-Voltage Detection

The IC continuously monitors VBUS during charging. If VBUS

falls below VIN(MIN), the IC:

1. Terminates charging

2. Pulses the STAT pin, sets the STATUS bits to 11, and

sets the FAULT bits to 011.

If VBUS recovers above the VIN(MIN) rising threshold after time

tINT (about two seconds), the charging process is repeated.

This function prevents the USB power bus from collapsing or

oscillating when the IC is connected to a suspended USB

port or a low-current-capable OTG device.

Input Over-Voltage Detection

When the VBUS exceeds VBUSOVP, the IC:

1. Turns off Q3

2. Suspends charging

3. Sets the FAULT bits to 001, sets the STATUS bits to

11, and pulses the STAT pin.

When VBUS falls about 100 mV below VBUSOVP, the fault is

cleared and charging resumes after VBUS is revalidated

(see VBUS POR / Non-Compliant Charger Rejection).

VBUS Short While Charging

If VBUS is shorted with a very low impedance while the IC is

charging with IBUSLIMIT=100 mA, the IC may not meet

datasheet specifications until power is removed. To trigger

this condition, VBUS must be driven from 5 V to GND with a

high slew rate. Achieving this slew rate requires a 0  short

to the USB cable less than 10 cm from the connector.

SYS Short During Discharge / Supplemental Mode

Caution should be taken to ensure the SYS pin is not

shorted when connected to a battery. This condition can

induce high current flow through the BATFET (Q4) until the

battery’s own safety circuit trips. The resulting high current

can damage the IC.

Charge Mode Battery Detection & Protection

VBAT Over-Voltage Protection

The OREG voltage regulation loop prevents VBAT from

overshooting VOREG by more than 50 mV when the battery is

removed. When the PWM charger runs with no battery, the

TE bit is not set and a battery is inserted that is charged to a

voltage higher than VOREG; PWM pulses stop. If no further

pulses occur for 30 ms, the IC sets the FAULT bits to 100,

sets the STATUS bits to 11, and pulses the STAT pin.

Battery Detection During Charging

The IC can detect the presence, absence, or removal of a

battery if the termination bit (TE) is set and CE# = 0. During

normal charging, once VBAT is close to VOREG and the charge

current falls below ITERM; the PWM charger continues to

provide power to SYS and Q4 is turned off. It then turns on a

discharge current, IDETECT, for tDETECT. If VBAT is still above

VOREG – VRCH, the battery is present and the IC sets the

STATUS bits to 10 (Charge Done). If VBAT is below VOREG –

VRCH, the battery is absent and the IC:

1. Sets the charging parameters to their default values.

2. Sets the FAULT bits to 111 (Battery Absent) and sets

the NOBAT bit.

3. If EOC=0, the IC turns off the PWM for tINT, then

resumes charging. If the battery is still absent, the

battery absent fault is then re-enunciated every tINT.

4. If EOC = 1, the PWM remains on to provide power to

SYS, but charge termination and the battery absent test

are performed every tINT.

Linear Charging

If the battery voltage is below the short-circuit threshold

(VSHORT); a linear current source, ISHORT, charges VBAT until

VBAT > VSHORT.

For IBUSLIM settings of 100 mA or 500 mA, the linear charging

current is typically 13 mA. For higher IBUSLIM settings, the

linear charging current is increased to 30 mA.

Charger Status / Fault Status

The STAT pin indicates the operating condition of the IC and

provides a fault indicator for interrupt driven systems.

Table 19. STAT Pin Function

EN_STAT

Charge State

STAT Pin

0

X

OPEN

X

Normal Conditions

OPEN

1

Charging

LOW

X

Fault (Charging or Boost)

128 s Pulse,

then OPEN

The FAULT bits (R0[2:0]) indicate the type of fault in Charge

Mode (see Table 28).

Production Test Mode (PTM)

PTM provides 4.2 V at up to 2.3 A to VBAT when VBUS =

5.5 V ±5%.

The IC enters PTM when the PROD bit is set and the

NOBAT bit is HIGH, indicating that the IC has detected

battery absence. A battery absence detection test after

VBUS POR is performed automatically for FAN54040,

FAN54042, and FAN54047 only.

A battery-absent detection test can be performed at any time

by setting the TE bit, setting VOREG to at least 4.0 V, then

resetting the CE# bit. If no battery is present; charge

termination occurs, followed by a battery absent test, which

sets the NOBAT bit. Battery-absence detection is completed

within 500 ms from the time that CE# is set.

FAN54040 – FAN54047 • Rev. 1.3 31

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

In PTM, GATE is LOW, Q4 and Q5 are on, and all auxiliary

control loops are disabled. Only the OREG loop is active,

which controls VBAT to 4.2 V, regardless of the OREG

register setting. Thermal shutdown remains active.

During PTM, high current pulses (load currents greater than

1.5 A) must be limited to 20% duty cycle with a minimum

period of 10 ms.

Charge Mode Control Bits

Setting either HZ_MODE through I2C or DIS pin to HIGH

disables the charger, puts the IC into High-Impedance Mode,

and stops t32S. If VBAT < VLOWV while in High-Impedance

Mode, t32S begins running and, when it overflows, all

registers (except SAFETY) reset, which enables t15MIN

charging on versions with the 15-minute timer if DIS=0.

When t15MIN overflows, the IC enters High-Impedance Mode

(IDLE). A new charge cycle can only be initiated through I2C

or VBUS POR.

Setting the RESET bit clears all registers. If HZ_MODE bit

was set when the RESET bit is set, this bit is also cleared,

but the t32S timer is not started and the IC remains in High-

Impedance Mode.

Table 20. DIS Pin and HZ_MODE Bit Functionality

Charging

DIS Pin

HZ_MODE

ENABLE

0

DISABLE

X

1

DISABLE

1

X

Raising the DIS pin stops t32S from advancing, but does not

reset it. If the DIS pin is raised during t15MIN charging, the

t15MIN timer is reset. CE# determines whether charging to

VBAT is enabled or not.

Boost Mode

Boost Mode can be enabled if the IC is in 32-Second Mode

by setting the OPA_MODE bit HIGH and clearing the

HZ_MODE bit.

Table 21. Enabling Boost

HZ_MODE

OPA_MODE

BOOST

0

1

Enabled

1

X

Disabled

X

0

Disabled

To remain in Boost Mode, the TMR_RST must be set by the

host before the t32S timer times out. If t32S times out in Boost

Mode; the IC resets all registers, pulses the STAT pin, sets

the FAULT bits to 110, and resets the BOOST bit. VBUS

POR or reading R0 clears the fault condition.

Boost PWM Control

The IC uses a minimum on-time and computed minimum off-

time to regulate VBUS. The regulator achieves excellent

transient response by employing current-mode modulation.

This technique causes the regulator to exhibit a load line.

During PWM Mode, the output voltage drops slightly as the

input current rises. With a constant VBAT, this appears as a

constant output resistance.

The “droop” caused by the output resistance when a load is

applied allows the regulator to respond smoothly to load

transients with no undershoot from the load line. This can be

seen in Figure 33 and Figure 45.

Figure 45. Output Resistance (ROUT)

VBUS as a function of ILOAD can be computed when the

regulator is in PWM Mode (continuous conduction) as:

LOADOUTOUT IRV  07.5

EQ. 1

At VBAT=3.0 V and ILOAD=300 mA, VBUS drops to:

VVOUT 98.43.030.007.5 

EQ. 2

At VBAT=3.6 V and ILOAD=500 mA, VBUS drops to:

VVOUT 95.45.024.007.5 

EQ. 3

PFM Mode

If VBUS > VREFBOOST (nominally 5.07 V) when the minimum

off-time ends, the regulator enters PFM Mode. Boost pulses

are inhibited until VBUS < VREFBOOST. The minimum on-time

is increased to enable the output to pump up sufficiently with

each PFM boost pulse. Therefore, the regulator behaves like

a constant on-time regulator, with the bottom of its output

voltage ripple at 5.07 V in PFM Mode.

Table 22. Boost PWM Operating States

Mode

Description

Invoked When

LIN

Linear Startup

VBAT > VBUS

SS

Boost Soft-Start

VBUS < VBST

BST

Boost Operating Mode

VBAT > UVLOBST and

SS Completed

Startup

When the boost regulator is shut down, current flow is

prevented from VBAT to VBUS, as well as reverse flow from

VBUS to VBAT.

200

240

280

320

360

400

2.0 2.5 3.0 3.5 4.0 4.5

VBUS Output Resistance (m)

Battery Voltage, VBAT (V)

FAN54040 – FAN54047 • Rev. 1.3 32

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

LIN State

When EN rises, if VBAT > UVLOBST; the regulator first

attempts to bring PMID within 400 mV of VBAT using an

internal 450 mA current source from VBAT (LIN State). If

PMID has not achieved VBAT – 400 mV after 560 s, a

FAULT state is initiated.

SS State

When PMID > VBAT – 400 mV, the boost regulator begins

switching with a reduced peak current limit of about 50% of

its normal current limit. The output slews up until VBUS is

within 5% of its setpoint; at which time, the regulation loop is

closed and the current limit is set to 100%.

If the output fails to achieve 95% of its setpoint (VBST) within

128 s, the current limit is increased to 100%. If the output

fails to achieve 95% of its setpoint after this second 384 s

period, a fault state is initiated.

BST State

This is the normal operating mode of the regulator. The

regulator uses a minimum tOFF-minimum tON modulation

scheme. The minimum tOFF is proportional to , which

keeps the regulator’s switching frequency reasonably

constant in CCM. tON(MIN) is proportional to VBAT and is a

higher value if the inductor current reached 0 before tOFF(MIN)

in the prior cycle.

To ensure VBUS does not overshoot the regulation point, the

boost switch remains off as long as VFB > VREF(BST).

Boost Faults

If a BOOST fault occurs:

1. The STAT pin pulses.

2. OPA_MODE bit is reset.

3. The power stage is in High-Impedance Mode.

4. The FAULT bits (REG0[2:0]) are set per Table 23.

Restart After Boost Faults

OPA_MODE is reset on boost faults. Boost Mode can only

be re-enabled by setting the OPA_MODE bit.

Table 23. Fault Bits During Boost Mode

Fault Bit

Fault Description

B2

B1

B0

0

Normal (no fault)

0

1

VBUS > VBUSOVP

0

1

0

VBUS fails to achieve the voltage required to

advance to the next state during soft-start

or sustained (>50 s) current limit during the

BST state.

0

1

VBAT < UVLOBST

1

0

NA: This code does not appear.

1

0

1

Thermal shutdown

1

0

Timer fault; all registers reset.

1

NA: This code does not appear.

Monitor Registers (Reg10H, Reg11H)

Additional status monitoring bits enable the host processor

to have more visibility into the status of the IC. The monitor

bits are real-time status indicators and are not internally

debounced or otherwise time qualified.

The state of the MONITOR register bits listed in High-

Impedance Mode is valid only when VBUS is valid.

I2C Interface

The FAN5404X’s serial interface is compatible with

Standard, Fast, Fast Plus, and High-Speed Mode I2C bus

specifications. The FAN5404X SCL line is an input and the

SDA line is a bi-directional open-drain output; it can only pull

down the bus when active. The SDA line only pulls LOW

during data reads and when signaling ACK. All data is

shifted in MSB (bit 7) first.

Slave Address

Table 24. I2C Slave Address Byte

7

6

5

4

3

2

1

0

1

0

1

0

1

In hex notation, the slave address assumes a 0 LSB. The

hex slave address is D6H for all parts in the family. Other

slave addresses can be accommodated upon request.

Contact a Fairchild Semiconductor representative.

Bus Timing

As shown in Figure 46, data is normally transferred when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

SCL tSU

tH

SDA

Data change allowed

Figure 46. Data Transfer Timing

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which is

defined as SDA transitioning from 1 to 0 with SCL HIGH, as

shown in Figure 47

SCL

tHD;STA

SDA Slave Address

MS Bit

Figure 47. Start Bit

OUT

IN

VV

WR/

FAN54040 – FAN54047 • Rev. 1.3 33

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Transactions end with a STOP condition, which is SDA

transitioning from 0 to 1 with SCL HIGH, as shown in Figure 48.

SCL

SDA

Slave Releases Master Drives

ACK(0) or

NACK(1)

tHD;STO

Figure 48. Stop Bit

During a read from the FAN5404X (Figure 51), the master

issues a Repeated Start after sending the register address

and before resending the slave address. The Repeated Start

is a 1-to-0 transition on SDA while SCL is HIGH, as shown in

Figure 49.

High-Speed (HS) Mode

The protocols for High-Speed (HS), Low-Speed (LS), and

Fast-Speed (FS) Modes are identical except the bus speed

for HS Mode is 3.4 MHz. HS Mode is entered when the bus

master sends the HS master code 00001XXX after a start

condition. The master code is sent in Fast or Fast Plus Mode

(less than 1 MHz clock); slaves do not ACK the

transmission.

The master then generates a repeated start condition

(Figure 49) that causes all slaves on the bus to switch to HS

Mode. The master then sends I2C packets, as described

above, using the HS Mode clock rate and timing.

The bus remains in HS Mode until a stop bit (Figure 48) is

sent by the master. While in HS Mode, packets are

separated by repeated start conditions (Figure 49).

SCL

SDA ACK(0) or

NACK(1)

Slave Releases

SLADDR

MS Bit

tHD;STA

tSU;STA

Figure 49. Repeated Start Timing

Read and Write Transactions

The figures below outline the sequences for data read and

write. Bus control is signified by the shading of the packet,

defined as and .

All addresses and data are MSB first.

Table 25. Bit Definitions for Figure 50 - Figure 53

Symbol

Definition

S

START, see Figure 47

A

ACK. The slave drives SDA to 0 to acknowledge

the preceding packet.

NACK. The slave sends a 1 to NACK the

preceding packet.

R

Repeated START, see Figure 49

P

STOP, see Figure 48

Multi-Byte (Sequential) Read and Write

Transactions

Sequential Write (Figure 52)

The Slave Address, Reg Addr address, and the first data

byte are transmitted to the FAN5404x in the same way as in

a byte write (Figure 50). However, instead of generating a

Stop condition, the master transmits additional bytes that are

written to consecutive sequential registers after the falling

edge of the eighth bit. After the last byte written and its ACK

bit received, the master issues a STOP bit. The IC contains

an 8-bit counter that increments the address pointer after

each byte is written.

Sequential Read (Figure 53)

Sequential reads are initiated in the same way as a single-

byte read (Figure 51), except that once the slave transmits

the first data byte, the master issues an acknowledge

instead of a STOP condition. This directs the slave’s I2C

logic to transmit the next sequentially addressed 8-bit word.

The FAN5404x contains an 8-bit counter that increments the

address pointer after each byte is read, which allows the entire

memory contents to be read during one I2C transaction.

Figure 50. Single-Byte Write Transaction

Figure 51. Single-Byte Read Transaction

Figure 52. Multi-Byte (Sequential) Write Transaction

Figure 53. Multi-Byte (Sequential) Read Transaction

Master Drives Bus

Slave Drives Bus

A

FAN54040 – FAN54047 • Rev. 1.3 34

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Register Descriptions

The eight user-accessible IC registers are defined in Table 26.

Table 26. I2C Register Address

Register

Address Bits

Name

REG#

7

6

5

4

3

2

1

0

CONTROL0

0H

0

CONTROL1

1H

0

1

OREG

2H

0

1

0

IC_INFO

3H

0

1

IBAT

4H

0

1

0

VBUS_CONTROL

5H

0

1

0

1

SAFETY

6H

0

1

0

POST_CHARGING

7H

0

1

MONITOR0

10H

0

1

0

MONITOR1

11H

0

1

0

1

NTC

12H

0

1

0

1

0

WD_CONTROL

13H

0

1

0

1

0

Table 27. Register Bit Definitions

This table defines the operation of each register bit for all IC versions. Default values are in bold text.

Bit

Name

Value

Type

Description

CONTROL0

Register Address: 00

Default Value=0100 0000

7

TMR_RST

0

W

Writing a 1 resets the t32S timer; writing a 0 has no effect.

Reading this bit always returns 0

6

EN_STAT

0

R/W

Prevents STAT pin from going LOW during charging; STAT pin still pulses to

enunciate faults

1

Enables STAT pin to be LOW when IC is charging

5:4

STAT

00

R

Ready

01

PWM Enabled. Charging is occurring if CE# = 0.

10

Charge done

11

Fault

3

BOOST

0

R

IC is not in Boost Mode

1

IC is in Boost Mode

2:0

FAULT

R

Table 28. Charger Mode Faults

Fault Bit

Fault Description

2

1

0

Normal (No Fault)

0

1

VBUS OVP

0

1

0

Sleep Mode

0

1

Poor Input Source

1

0

Battery OVP

1

0

1

Thermal Shutdown

1

0

Timer Fault

1

No Battery

For Boost Mode faults, see Table 23

FAN54040 – FAN54047 • Rev. 1.3 35

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Bit

Name

Value

Type

Description

CONTROL1

Register Address: 01

Default Value=0011 0X00

7:6

IBUSLIM

R/W

Input current limit; defaults to 00 (100 mA), see Table 14

5:4

VLOWV

00

R/W

3.4 V

Weak battery voltage threshold

01

3.5 V

10

3.6 V

11

3.7 V

3

TE

0

R/W

Disable charge current termination

1

Enable charge current termination

2

CE#

0

R/W

Charging enabled. Default for FAN54040, FAN54042, FAN54047.

1

Charging disabled. Default for FAN54041, FAN54045 , FAN54046.

1

HZ_MODE

0

R/W

Not High-Impedance Mode

See Table 21

1

High-Impedance Mode

0

OPA_MODE

0

R/W

Charge Mode

1

Boost Mode

OREG

Register Address: 02

Default Value=0000 1000 (08H)

7:2

OREG

R/W

Charger output “float” voltage; programmable from 3.5 to 4.44 V in 20 mV

increments; defaults to 000010 (3.54 V), see Table 4.

1

DBAT_B

0

R/W

Indicates that the IC detected a dead battery after VBUS_POR and that the charger

has not yet completed the three steps to ensure that the battery’s protection switch

is closed if a battery is present, as described in the Dead Battery section on page

21. Writing a 0 to this bit is ignored.

1

The IC sets this bit to 1 if any of the following are true:

1. Dead Battery (VBAT < VSHORT) was not detected at VBUS_POR.

2. The IC has completed the three steps to ensure that if the battery is

present, the battery’s protection switch has closed, as described in the

Dead Battery section on page 21.

If the host sets this bit while the IC is charging the battery and DBAT_B is LOW,

the three steps are aborted and normal Power Path or PWM charging proceeds.

0

EOC

0

R/W

If no battery is detected when a full battery (end of charge) is reached, PWM stops,

Q4 and Q5 remain on, and the charger automatically restarts after two seconds with

TE and CE# bits unchanged.

1

If no battery is detected when a full battery (end of charge) is reached, the PWM

charger stays on, allowing the host processor to continue to run with no battery.

IC_INFO

Register Address: 03

Default Value=100X XXXX

7:6

Vendor Code

10

R

Identifies Fairchild Semiconductor as the IC supplier

5:3

PN

R

Part number bits, see the Ordering Info on page 2

2:0

REV

R

IC Revision, revision 1.X, where X is the decimal of these three bits

IBAT

Register Address: 04

Default Value=1000 0001 (81H)

7

RESET

1

W

Writing a 1 resets all registers, except the Safety register (Reg6), to their defaults:

writing a 0 has no effect; read returns 1

6:3

IOCHARGE

Table 5

R/W

Programs the maximum charge current, see Table 5

2:0

ITERM

Table 6

R/W

Sets the current used for charging termination, see Table 6

FAN54040 – FAN54047 • Rev. 1.3 36

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Bit

Name

Value

Type

Description

VBUS_CONTROL

Register Address: 05

Default Value=001X X100

7

Reserved

0

R

This bit always returns 0

6

PROD

0

R/W

Charger operates in Normal Mode.

1

Charger operates in Production Test Mode.

5

IO_LEVEL

0

R/W

Battery current is controlled by IOCHARGE bits.

1

Battery current control is set to 340 mA.

4

VBUS_CON

R

1 Indicates that VBUS is above 4.4 V (rising) or 3.8 V (falling). When VBUS_CON

changes from 0 to 1, a STAT pulse occurs.

3

SP

0

R

VBUS control loop is not active (VBUS is able to stay above VBUSLIM)

1

VBUS control loop is active and VBUS is being regulated to VBUSLIM

2:0

VBUSLIM

Table 15

R/W

VBUS control voltage reference, see Table 15

SAFETY

Register Address: 06

Default Value=0100 0000 (40H)

7:4

ISAFE

Table 16

R/W

Sets the maximum IOCHARGE value used by the control circuit, see Table 16

3:0

VSAFE

Table 17

R/W

Sets the maximum VOREG used by the control circuit, see Table 17

POST_CHARGING

Register Address: 07

Default Value=0000 0001 (01H)

7:6

BDET

R/W

These bits determine whether a battery absent detection will be performed when

the NTC reading indicates out-of-range when charging.

[7:6]

When NTC goes out-of-range

00

Always do battery absent detection

01

Disable detection in Normal Mode

10

Disable detection when Reg FA = B5 (PWM running after charge

done.

11

NTC out-of-range in charge done does not cause battery absent

detection.

5:4

VBUS_LOAD

0

R/W

After charger termination, in the charge done state, these bits control VBUS loading

to improve detection of AC power removal from the AC adapter.

[5:4]

VBUS loading in Charge Done State:

00

None

01

Load VBUS for 4 ms every two seconds

10

Load VBUS for 131 ms every two seconds

11

Load VBUS for 135 ms every two seconds

3

PC_EN

0

R/W

Post charging or background charging feature is disabled

1

Post charging or background charging feature is enabled

2:0

PC_IT

Table 6

R/W

Sets the termination current for post or underground charging, see Table 6

MONITOR0

Register Address: 10H (16)

Default Value=XXX0 XXXX (XXH)

7

ITERM_CMP

R

ITERM comparator output, 1 when ICHARGE > ITERM reference

6

VBAT_CMP

R

Output of VBAT comparator, 1 when VBAT < VBUS

5

LINCHG

R

1 when 30 mA linear charger ON (VBAT < VSHORT)

4

T_120

R

Thermal regulation comparator, 1 when the die temperature is greater than 120°C.

During this condition, charge current is limited to 340 mA.

3

ICHG

R

0 indicates the ICHARGE loop is controlling the battery charge current.

2

IBUS

R

0 indicates the IBUS (input current) loop is controlling the battery charge current.

1

VBUS_VALID

R

1 indicates VBUS has passed validation and is capable of charging.

0

CV

R

1 indicates the constant-voltage loop (OREG) is controlling the charger and all

current limiting loops have released.

FAN54040 – FAN54047 • Rev. 1.3 37

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

Bit

Name

Value

Type

Description

MONITOR1

Register Address: 11H (17)

Default Value=XX1X XXXX

7

GATE

0

R

GATE pin is LOW, Q5 is driven on.

1

GATE pin is HIGH, Q5 is off.

6

VBAT

0

R

VBAT < VBATMIN in PP charging, VBAT < VLOW in PWM charging

1

VBAT > VBATMIN in PP charging, VBAT > VLOW in PWM charging

5

POK_B

0

R/W

POK_B Pin is LOW.

1

POK_B Pin is HIGH. Writing to this bit sets the POK_B pin.

4

DIS_LEVEL

0

R

DIS pin is LOW.

1

DIS pin is HIGH.

3

NOBAT

1

R

Battery absence

0

Battery presence

2

PC_ON

1

R

Post charging (background charging) is under progress.

0

Post charging (background charging) is not under progress.

1:0

Reserved

0

R

These bits always return 0.

NTC

Register Address: 12H (18)

Default Value=000X XXXX

7:6

Reserved

00

R

These bits always return 0.

5

TEMP_DIS

0

R/W

NTC Temperature measurement results affect charge parameters.

1

NTC Temperature measurement results do not affect charge. Temperature

measurements continue to be updated every second in the NTC1-4 monitor bits.

4

NTC_OK

R

0 if NTC is either shorted to GND, open, or shorted to REF.

3

NTC4

R

1 indicates that NTC is above the T4 threshold.

See Table 10 – Table 13

2

NTC3

R

1 indicates that NTC is above the T3 threshold.

1

NTC2

R

1 indicates that NTC is above the T2 threshold.

0

NTC1

R

1 indicates that NTC is above the T1 threshold.

WD_CONTROL

Register Address: 13H (19)

Default Value = 0110 1100

7

Reserved

0

R/W

These bits do not change the function of the IC.

6:5

Reserved

11

R/W

These bits do not change the function of the IC.

4

Reserved

0

R/W

These bits do not change the function of the IC.

3

Reserved

1

R/W

These bits do not change the function of the IC.

2

EN_VREG

0

R/W

VREG is off

1

VREG is on

1

WD_DIS

0

R/W

Watchdog timer (T32S) operation normal

1

Watchdog timer (T32S) disabled.

0

Reserved

0

R

This bit always returns 0

RESTART

Register Address: FAH (250)

Default Value = 1111 1111

7:0

RESTART

W

Writing B5H restarts charging when the IC is in the charge done state. This register

reads back FF.

FAN54040 – FAN54047 • Rev. 1.3 38

FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support

PCB Layout Recommendation

Bypass capacitors should be placed as close to the IC as

possible. In particular, the total loop length for CMID should

be minimized to reduce overshoot and ringing on the SW,

PMID, and VBUS pins. Power and ground pins should be

routed directly to their bypass capacitors using the top

copper layer. The copper area connecting to the IC should

be maximized to improve thermal performance. See the

layout recommendations in Figure 54.

Figure 54. PCB Layout Recommendation

Product-Specific Dimensions

Product

D

E

X

Y

FAN5404XUCX

2.40 ±0.030

2.00 ±0.030

0.180

0.380

BALL A1

INDEX ARE

A

12345

A

B

C

D

E

SEATING PLANE

25X

A1

0.005 C A B

F

Ø0.260±0.02

0.40

1.60

0.40

1.60

(X) ±0.018

(Y) ±0.018

E

D

0.06 C

0.05 CE

D

F

0.378±0.018

0.208±0.021

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

D. DATUM C IS DEF IN ED BY TH E SP HE RICAL

CROWNS OF THE BALLS.

E. PACKAGE NOMIN AL HEIGHT IS 586 MICRONS

±39 MICRONS (547-625 MICRONS).

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

G. DRAWING FILENAME: MKT-UC025AArev3.

0.03 C

2X

0.03 C

2X

C

B

A

0.625

0.547

0.40

1.60

0.40

1.60 (Ø0.200)

Cu Pad

(Ø0.300)

Solder Mask

RECOMMEN DE D LA ND PATTERN

(NSMD PAD TYPE)

TOP VIEW

BOTTOM VIEW

SIDE VIEWS

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