HIGH SPEED IDT7132SA/LA 2K x 8 DUAL PORT IDT7142SA/LA STATIC RAM Features * TTL-compatible, single 5V +10% power supply * High-speed access * Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC - Military: 25/35/55/100ns (max.) - Commercial: 20/25/35/55/100ns (max.) * Low-power operation - 1DT7132/42SA Active: 325mW (typ.) Standby: 5mW (typ.) ~ 1DT7132/42LA Active: 325mW (typ.) Standby: ImW (typ.) * MASTER IDT7132 easily expands data bus width to 16-or- more bits using SLAVE IDT7142 * On-chip port arbitration logic (1DT7132 only) * BUSY output flag on 1DT7132; BUSY input on 1DT7142 * Battery backup operation 2V data retention packages * Military product compliant to MIL-PRF-38535 QML * Industrial temperature range (-40 T to +85 C) is available for selected speeds Description The 1DT71324DT7/142 are high-speed 2K x 8 Dual-Port Static RAMs. The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7142 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or- more-bit memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Functional Block Diagram | m 7 3 fal VOov- VO7L VO Control Busy. AOL AoL MEMORY ARRAY ARBITRATION LOGIC NOTES: 1. 1077132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Q. IDT7142 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 27022. ;Oor-1/O7R /O Control BUSYr" A1oR AoR 2692 drw 01 MARCH 1999 1999 integrated Device Technology, tnc DSC-2692/12IDT7132SA/LA and IDT 7142S A/LA High Speed 2K x & Dual Port Stauc RAM Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (LA) versions offer battery backup data retention capability, with each Dual- Pin Configurations" 2>) ) Tec eon HerOLCEaCArcEMec AT eMe Soe 1SR LS CcaMRT =| 012015 TELCO Le oMe SE aES [ott Port typically consuming 200yW from a 2V battery. The 1DT7132/7142 devices are packaged in a 48-pin sidebraze or plastic DiPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks. Military grade product is manufactured in compliance with the fatest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. CE. C1 4g] Vec R/WL Ge 47 CER BUSYL 4]3 46 R pig iL 4 45] BUSYR L 44 10R AoL Ae aA OER Aif7 1 42] Aor Ait O17 IDI 7132! Aol] Aor Aas 4iC Air Az Ls 41[] Air As oC] Ae As.Clg Por gold Aor 9 4 A Aa. C10 39L] A3R AaLt 10 1DT7132/42L48 or F i Aan As 11 pyg.4(a) 381) Ask As. [111 L48-1(4) sal] Asr ASL 5 ays nn As_[_] 12 ea (4) 370 ASR 6R - au C]1a 482 380) ara Ar. 13 48-Pin LCC/ Flatpack 36L Aer AoLCJ15 48-pin 34 Asr As. [1 14 Top View(5) 35(-] Avr VOot H 16 DIP 33 ASR Ao. [115 34] Asr WOeLEN18 Viens) Sit Von Oo. 51 16 gal] Aer VOst FS 19 30) eR VO. 17 32] /O7R VOat L120 29 4A VO2{-] 18 31} vOsr VOst (21 28] /O3R 19 20 21 22 23 24 25 26 27 28 29 30 vOs. 22 97\1 VOe2R adatalatatatatalatatata VO7. L}23 26) /O1R todo dt od SO oe Oo ee 2692dwOs GND C24 25}1 Vor SSSSSZSOSSSS 2692 drw 02 See eeVes estes NOTES: 1. 2. 3. All Vcc pins must be connected to the power supply. All GND pins must be connected to the ground supply. P48-1 package body is approximately .55 in x .61 in x .19 in. C48-2 package body is approximately .62 in 2.43 in x .15 in. L48-1 package body is approximately .57 in x .57 in x .68 in. F48-1 package body is approximately .75 in x .75 in x .17 in. This package code is used to reference the package diagram. This text does not indicate orientation of the actual part-marking. Capacitance") (Ta = +25C,f = 1.0MHz) Symbol Parameter Conditions | Max | Unit Cin Input Capacitance Vin = 3dV "1 pF Court Output Capacitance Vout = 3dV "i pF 2682 1 00 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 3V to OV.IDT7132SA/LA and IBDT 7142SA/LA High Speea 2K x 6 Dual Port Static RAN Mideary, INdustial ana Commercial lemperature Ranges Pin Configurations 2*) (con't.) seoBew epee s aw e205 uw 2 Y 2 INDEX ZB 2SRS6 8b SBS 2 Yy WUE POUR 765432 52 51 50 49 48 47 __ Ai p18 1 46[-] OEr Ac. 19 45[71 Aor Ast F110 44(Jj air Aa (111 43(7] aor IDT7132/4. As. (12 Wess 42-1 Ase 313 ait Ae. 52-Pin PLCC MA An 114 Top View) 40] Asa ASL 415 397 A6R As. FJ 16 38] Aza vOo. [17 377] Asr vor F118 364} Agr vOe. F119 36] wc VOa FJ] 20 34 oz 21 22 23 24 25 26 27 28 29 3031 3233) CY 2692 drw 04 ge@epePONOCTtcreece SS8S8S2Z66688686 1. All Vcc pins must be connected to the power supply. 2. Al GND pins must be connected to the ground supply. 3. Package body is approximately .75 in x .75 in x .17 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Absolute Maximum Ratings Recommended Operating Commercial _ _| Temperature and Supply Voltage) Symbol Rating & Industrial Military Unit Ambient VeRM? | Terminal Voltage | -05t0+7.0 | 05t+7.0} V Grade Temperature | GND Vee we Military 55C 125C | Ov | 50V+ 10% 0, Tas _| Temperature $510 +125 | 65104135 | oc | [Commercial OPC to +70C OV | 5.0V + 10% Under Bias Industrial 40C to +85C ov 5.0V + 10% TSTG Storage -55 to +125 65 to +150 C 2692 th! 02 Temperature NOTES: 1. This is the parameter Ta. lout DC Output w 50 mA 2. Industrial temperature: for specific speeds, packages and powers contact your Current sales office. 2692 thi Ot NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional Recommended DC Operating operation of the device at these or any other conditions above those indicated in Conditions the operational sections of the specification is not implied. Exposure to absolute : : maximum rating conditions for extended periods may affect reliability. Symbol Parameter Min. | Typ. | Max | Unit 2. VTeRM Must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns vec | Supply Voltage 45 50 55 Vv maximum, and is limited to < 20mA for the period of Vrerm > Vcc + 10%. GND = | Ground 0 0 0 Vv VIK_ | Input High Voltage 2.2 | 60%) v Vi. | Input Low Voltage O50 | 0.8 v 2692 ti 03 NOTES: 1. Vit (min.) = -1.5V for pulse width less than 10ns. 2. VreRM must not exceed Vcc + 10%.IDT7132SA/LA and IDT 71425AN& High Speed 2K x & Dual Part Static RAL ee eal eLeeot Gers mes bP MmOLeLi SED DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range"5) (vcc = 5.0v + 10%) aiure Ranges 7432x202 7132x258 7132X35 7142X20?) 7142x25") 7142X35 Com't Only Com't & Com'l & Military Military Symbol Parameter Test Condition Version Typ. Max. Typ. Max Typ. Max. Unit Iec Dynamic Operating Current = | CEL = CER = Vit, COM'L SA 10 250 110 220 80 165 mA (Both Ports Active) Pupus 6 Open LA 110 200 110 170 80 120 f= fMAX MIL & SA 110 280 80 230 IND LA 0 220 80 170 isa Standby Current CEL = CER = Vin, COM'L SA} 30 65 20 65 25 65 mA (Both Ports - TT. f= iMate) LA 30 45 Kt] 45 25 45 Level Inputs} MIL. & SA 30 80 25 80 IND LA 30 60 5 60 IsB2 Standby Current CEa" = Vi and CE*B" = Vin COM'L SA] 65 165 65 150 50 125 mA (One Port - TIL Active Port Outputs Open LA 65 125 65 115 50 90 Level Inputs) fefMax) MIL & SA 65 160 50 150 IND LA 65 125 50 "5 1SB3 Full Standby Current (Both | GE and CER 2 Voc -0.2V COM'L SA] 10 5 1.0 15 1.9 18 mA Ports - All Vin 2 Voc -0.2V or VIN s 0.2V, f= 04 iA 02 5 0.2 5 0.2 4 CMOS Level Inputs) MiL & SA 1.0 30 1.0 30 IND LA 0.2 10 0.2 10 ISB4 Full Standby Current CEA" < 0.2V andCE'e" > Voc 0.2v COM'L SA 60 155 60 145 5 110 mA (One Port - All VIN > VCC - 0.2V or VIN < 0.2V LA 60 115 60 405 45 85 CMOS Level Inputs} Active Port Outputs Open f= MAX?) MIL & SA 60 155 45 145 IND LA 60 115 45 105 2692 thi O4a 7132X55 7132X100 7142X55 7142X100 Com'l & Com't & Military Military Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit icc Dynamic Operating CE = CER = Ve, COM'L SA 65 155 65 155 mA Curent Outputs Open LA 65 110 65 110 (Both Ports Active) f= IMA) MIL & SA 65 190 65 190 IND LA 65 140 65 140 IsBt Standby Current CEL = CER = Vin, COM'L SA 20 65 20 55 mA (Both Ports - TL = ) LA 20 35 2 38 Level Inputs) MIL & SA 20 65 20 65 IND LA 20 45 20 45 IsB2 Standby Current CEra" = Vi. and CEs" = Vinf) COM'L SA 40 110 40 110 mA (One Port - TTL Active Port Outputs Open LA 40 75 40 75 Level inputs) feiMax) MIL & SA 40 125 40 125 IND LA 40 90 40 90 isB3 Full Standby Current CEL and CER > Veo 0.2V / COM'L SA 1.0 15 1.0 1 mA (Both Ports - All VIN 2 VCC -0.2V or VIN < 0.2V, f= 0% LA 0.2 4 02 4 CMOS Level inputs) ML & SA 1.0 % 1.0 x IND LA 0.2 40 0.2 10 IsB4 Full Standby Current CE*a" < 0.2V and CEB" > vec -0.2V9 COM'L SA 40 100 40 95 mA (One Port - Al VIN > VOC - 0.2V or VIN < 0.2V LA 40 70 40 70 CMOS Level Inputs) Active Port Outputs Open f= Mae? MIL & SA| 40 110 40 110 : IND LA 40 85 4 80 2692 bi 04 NOTES: 1. 'Xin part numbers indicates power rating (SA or LA). 2. PLCC Package only 3. Atf=fhax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of T/tac, and using "AC TEST CONDITIONS of input levels of GND to 3V. 4. f=0means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Vec = 5V, Ta=+25 C for Typ and is not praduction tested. Vcc pc = 100mA (Typ) 6. Port "A" may be either left or right port. Port "B is opposite from port "A". 7. 8 Not available in DIP packages. Industrial temperature: for specific speeds, packages and powers contact your sales office.IDT7132SA/LA and IDT 7142S5A/L A High Speed 2K x & Dual Port Stabc RAM Mibiaty, industal and Coniunerciai temperature Ranges DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (Vcc = 5.0V + 10%) 71328A 7132LA 71425A 7142LA Symbol Parameter Test Conditions Min. Max. Min. Max, Unit {lay input Leakage Current Vee = 5.5V, 10 - 5 pA Vin = OV to Vec jiLo| Output Leakage Current Vec = 5.5V, _ 10 -- 5 CE = Vin, Vout = OV to Voc yA VoL Output Low Voltage fo. = 4mA ~~ 0.4 - 0.4 Vv Vow Open Drain Output. lo. = 16mA ~ 05 - 0.5 Low Voltage (BUSY, INT) v VoH Output High Voltage lo = -4mA 24 ~ 24 ~ Vv 2692 fbi 05 NOTE: 1. At Vcc < 2.0V leakages are undefined. Data Retention Characteristics (LA Version Only) Symbol Parameter Test Condition Min. Typ. Max. Unit VbR Vcc for Data Retention Vec = 2.0V 2.0 - ~ V Iccor Data Retention Current CE = Vee 0.2V Mil. & Ind. - 100 4000 uA Vin > Veco -0.2V or Com'l. _ 100 1500 HA tcor) Chip Deselect to Data Retention Time Vin < 0.2V 0 - ns Ro) Operation Recovery Time tac) ~ ns NOTES: 22 be 1. Vec = 2V, Ta = +25 C, and is not production tested. 2. Inc = Read Cycle Time 3. This parameter is quaranteed but not production tested. Data Retention Waveform DATA RETENTION MODE Vcc VDR>2.0V 4.5V MtCDR ttR _ VDR CE / / : VIH VIH 2692 drw 05leh Payer eee sie ee ect Lae High Speed 2K x 8 Dual Port Static RAM Miidary, iidustral and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels GND to 3.0V input Rise/Fail Times Sns Max. Input Timing Reference Levels 4.5V Output Reference Levels 1.5V Output Load Figures 1, 2, and 3 2692 bl 07 5V, 12502 DATAOUT 775Q == 30pF 100pF for 55 and 100ns versions Figure 1. AC Output Test Load SV. 1250Q BUSY or INT 30pF 100pF for 55 and 100ns versions Figure 3. BUSY and INT AC Output Test Load 5V, 12502 DATAouT 775Q 5pF* Figure 2, Output Test Load (for tz, tz, deparahiows * Including scope and jigIDT7132SA/LA and JDT 7142SA/LA High Speed 2K x 8 Dual Port Static HAN Miluarg, industial and Commercial femperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range) 7132x20 713225) 7432X35 7142X202) 7142X25? 74142X35 Com! Only Comt & Com'l & Military Military Symbol Parameter Min. | Max. Min. Max. | Min. | Max | Unit READ CYCLE iRC Read Cycle Time 20 - 25 35 ns (AA Address Access Time 2 _ 25 35 ns tacE | Chip Enable Access Time oo 20 25 _ 35 ns tace =| Output Enable Access Time oe 11 _ 12 _ 20 ns ton Output Hold from Address Change 3 _ 3 aa 3 ns tz | Output LowZ Time! 0 ~ 0 0 _ ns tz | Output High-Z Time# ~ 10 oa 40 15 ns pu | Chip Enable to Power Up Time! 0 - ) - 0 ns tp _ | Chip Disable to Power Down Time me 20 - 25 von 35 ns 2692 tb! 08a 7132X55 7132X100 7142X55 7442X100 Com't & Com'l & Military Military Symbol Parameter Min. Max. Min. Max | Unit READ CYCLE {RC Read Cycle Time 55 ~ 100 _ ns faa Address Access Time _ 55 _ 100 ns tacE | Chip Enable Access Time oe 55 fo 100 ns face | Output Enable Access Time 25 40 ns toH -| Output Hold from Address Change 3 = 10 ns tz | Output Low-Z Time) 5 oe 5 ~ ns tz | Output High-Z Time"? 25 40 ns tpu | Chip Enable to Power Up Time 0 -- 0 ~ ns po | Chip Disable to Power Down Time ~ 50 - 50 ns 2692 tbl O8b NOTES: 1. Transition is measured +500mV from Low or High-Impedance Voltage Output Test Load (Figure 2). 2. PLCC package only. 3. X' in part numbers indicates power rating (SA or LA). 4. This parameter is guaranteed by device characterization, but is not production tested. 5. Industrial temperature: for specific speeds, packages and powers contact your sales office.IDT7 132SA/LA and IDT 7142S A/.4 High Speed 2K x 8 Dual Part Static z @unary. industeai and Gammercial leniperature Ranges Timing Waveform of Read Cycle No. 1, Either Side j~ tRc ADDRESS [+ taa tOH + tou DATAouT PREVIOUS DATA VALID DATA VALID BUSYouT WARAY I. teopH29) 2692 drw 07 Timing Waveform of Read Cycle No. 2, Either Side tACE tHz) DATAouT loc tpu-* CURRENT , 50% 50% Iss VALID DATA tep) tuz 2692 drw 08 NOTES: 1. RAW = Vin, CE = Vin, and is OE = Vi. Address is valid prior to the coincidental with CE transition LOW, 2. tBop delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tao, tAce, tA, and tBDD. 4. Timing depends on which signal is asserted tast, OE or CE. 5, Timing depends on which signal is de-assented first, OE or CE.IDT7132SA/LA and IDT 71d2SA/LA High Speed 2K x 8 Dual Port Static RAN Mituary, industeal and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range 7132x208 7132X25) 7132X38 742X202) 7142x254 7142X35 Com'! Only Com'l & Com'l & Military Military Symbol Parameter min. | Max | min. | Max | min. | Max | unit WRITE CYCLE twe Write Cycle Time! 20 25 35 ns tew Chip Enable to End-of Write 14 _ 20 30 - ns taw Address Valid to End-of Write 15 _ 20 ~ 30 ns tas Address Setup Time 6 0 ~ 0 - ns twe Write Pulse Width 15 - 15 25 - ns tr White Recovery Time C _ 0 - 0 ns pw Data Valid to End-of-Write 10 12 - 15 - ns tHz Output High-Z Time") 0 | 10 15 ns IDH Data Hold Time 0 0 - 0 - ns twz Write Enable to Output in High-2Z 10 ~~ 10 15 ns tow Output Active from End-of Write G 0 0 ns 2692 tbl 09 7132X55 7132X100 7142X55 7142X100 Com't & Com! & Military Military Symbol Parameter Min. Max. Min. | Max Unit WRITE CYCLE twe Write Cycle Time) 55 100 - ns. Ew Chip Enable to End-of-Write 40 90 ns taw Address Valid to End-of Write 40 - SO) - ns tas Address Set-up Time 0 0 ~ ns {we Write Pulse Width 30 - 55 ns wR Write Recovery Time 0 oO | ns tow Data Valid to End-of-Write 20 -- 40 ~ ns tz Output High-Z Time" - 25 ~ 40 ns {DH Data Hold Time 0 - 0 ns wz Write Enable to Output in High-2" 30 _ 40 ns tow Output Active from End-of-Write" 0 0 - ns NOTES: 2692 bl 70 1. Transition is measured +500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is Not production tested. 2. PLCC package only. For Master/Slave combination, twc = teaa + twp, Since R/W = Vit must occur afler tBaa. 4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of twr or (twz + tow) to allow the 1/O drivers to turn off data to be placed on the bus for the required tow. if OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twr. 5. "X' in part numbers indicates power rating (SA or LA). 6. Industrial temperature: for specific speeds, packages and powers contact your sales office. wIDT7132SA/L4 and IDT 71425A/L 4 High Speed 2K x & Dual Port Stalic RAM UEC Ee ameter Oe-S Cater: Ie Meee ds start aeent-t mee -tta) 0) 20:1 Ceca ct lee 1) Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing) > t- two aa ADDRESS x xX tH2" _] OE J Mt tAaw CE \ \ nw e tas twe? wal? taz!?? AN . YY R/AW N /) et yy7l) >| tow>} DATAouT x (43 (4) omen TOW _$- to # | DATAIN 2692 drw 09 Timing Waveform of Write Cycle No. 2, (CE Controlled Timing) - two > ADDRESS x ye < taw > CE ff XK re tag) tew) et twROe aN / how + 1 NZ DATAIN \ NOTES: 2692 drw 10 RAW or CE must be HIGH during all address transitions. A write occurs during the overlap (tew or twe) of CE = Vit and RAW = VIL. tweis measured from the earlier of CE or R/W going HIGH to the end of the write cycie. During this period, the /O pins are in the output state and input signals must not be applied. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. Timing depends on which enable signal (CE or RAW) is asserted last. This parameter is determined be device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load (Figure 2). If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of twe or (twz + tow) to allow the /O drivers to turn off data to be placed on the bus for the required tow. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twe. OO Pwn > 2IDT7132SA/LA and IDT 71425A/L & High Speed canoe O ier: ME sere aett AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range) iary. Industial and Commercial lernperature Ranges 7132x20' 7132X25 7132X35 7142x20 7142X252) 7142X35 Com Only Com & Com! & Military Military Symbol Parameter Min. | Max. Min. | Max. Min. i Max. Unit BUSY Timing (For Master IDT7132 Onty) {BAA BUSY Access Time from Address 20 20 20 ns taDa BUSY Disable Time from Address 20 20 20 ns {BAC BUSY Access Time from Chip Enable 20 20 20 ns tBoc BUSY Disable Time fram Chip Enable 20 20 20 ns woo Write Pulse to Data Delay?) 50 50 60 ns tH Write Hold After BUSY 12 15 20 ns tod Write Data Valid to Read Data Delay?) 35 35 35 ns tars Arbitration Priority Setup Time" 5 5 5 ns tBO0 BUSY Disable to Valid Data 25 35 35 ns BUSY Timing (For Slave 1DT7142 Only) we Write to BUSY Input*) 0 0 0 ns twH Write Hold After SUSY 12 16 20 ns woo Write Pulse to Data Delay? 40 50 60 ns peo Write Data Valid to Read Data Delay 30 : 35 35 ns 2692 thi a 7132K55 7132X100 7142X55 7142X100 Com & Com'l & Military Military Symbol Parameter Min. Max Min. } Max Unit BUSY Timing (For Master IDT7132 Only) {BAA BUSY Access Time from Address 30 50 ns {BDA BUSY Disable Time from Address 30 50 ns tpac BUSY Access Time from Chip Enable 30 50 ns tBoc BUSY Disable Time from Chip Enable 30 50 ns twoo Write Pulse to Data Delay?! 80 120 ns twH Write Hold After BUSY 20 20 ns tpop Write Data Valid to Read Data Delay?) 55 100 ns laps Arbitration Priority Setup Time 5 5 ns (Boo BUSY Disable to Valid Data) 50 65 ns BUSY Timing (For Slave i0T7142 Only) wa Write to BUSY Input) 9 0 ns WH Write Hold After BUSY 20 20 ns woo Write Pulse to Data Delay! 80 120 ns tpop Write Oata Valid to Read Data Delay? - 55 100 ns NOTES: 2692 bi 1b 1. PLCC package only. 2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to Timing Waveform of Write with Port -to-Port Read and BUSY. 3. To ensure that the earlier of the two ports wins. 4. spo is a calculated parameter and is the greater of 0, woo twP (actual) or too - tow (actual). 5. To ensure that a write cycle is inhibited on port "B" during contention on port A, 6. To ensure that a write cycle is completed on port "B" after contention on port "A". 7. Xin part numbers indicates power rating (SA or LA). 8. industrial temperature: for specific speeds, packages and powers contact your sales office.IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Stare RAN Milvary. industrial ang Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY? < {Wc > ADDR'a" *K MATCH XK twe R/W'a * NX + tow {DH DATAIN"A" *K VALID Se pt taps) ADDR's" a MATCH } {BAA tapa7* tBDD> BUS Yok k rt woo > DATAouT's * VALID tooo > NOTES: 2692 dew 1 1. To ensure that the earlier of the two ports wins. taps is ignored for Slave (IDT7142). 2. CEL =CEr= Vi 3. OE = Vir for the reading port. 4. Alltiming is the same for the left and right ports. Port "A" may be either the feft or right port. Port "B" is opposite from port "A". Timing Waveform of Write with BUSY) < twp R/Wa" \ Ok Vv twp) BUSY's 74 R/Wss: . \ N \ (2) NOTES: 2692 drw 12 1. tw must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master). 2. BUSY is asserted on port "8" blocking R/W's", until BUSY-B- goes HIGH. 3. twe applies only to the slave version (1017142). 4. All timing is the same for the left and right ports. Port A may be either the left or right port. Port "B" is opposite from port "A".IDT7 1325S A/1.4 and IDT 7142S A/LA High Speed 2K x 8 Dual Port Slaiic SAN Winary, industual and Commercial lemperature Ranges Timing Waveform of BUSY Arbitration Controlled by CE Timing" ADDR ADDRESSES MATCH weand-e = > X Feo YY CE's' 7 CEs: tBac h+ tec BUSY": Timing Waveform of BUSY Arbitration Controlled by Address Match Timing" {RC or two 2692 drw 13 ADDR a" ADDRESSES MATCH KK ADDRESSES DO NOT MATCH x taps) ADDR! * xX + BAA +- BDA BUSY'"8" 2692 drw 14 NOTES: 1. All timing is the same for left and right ports. Port A may be either left or right port. Port "B" is the opposite from port "A". 2. {f taps is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only). Truth Tables Table I. Non-Contention Read/Write Control Left or Right Port RW | CE OE Do-7 Function x H X zZ Port Disabled and in Power-Down Mode, 1882 or isB4 X H X Zz CER = CEL = Vin, Power-Down Mode, [81 or 1883 L L X DATAIN | Data on Port Written into Memory! H L L DATAOUT | Data in Memory Output on Port? x L H Zz High impedance Outputs NOTES: 2692 thi 12 J. Aot - Aro # Aor - Ator 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see twoo and topo timing. 4. 'H= Vin, 'L'= Vi, 'X' = DON'T CARE, 'Z = HIGH IMPEDANCEIDT7132SA/L A and IDT 7142SA/LA High Speed 2K x & Dual Port Static ea Table ll Address BUSY Arbitration Inputs Outputs CE | CER Aot-Ato. Busy." | BUSYa Aor-Ator Function X xX NO MATCH H H Norma! H xX MATCH H H Normat X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit) NOTES: mee 1. Pins BUSY. and BUSY. are both outputs for 1DT7132 (master). Both are inputs for 1017142 (slave). BUSYx outputs on the 1DT7132 are open drain, not push-pull outputs. On slaves the BUSYx input internally inhibits writes. 2. 'L'ifthe inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If wes is not met, either BUSYL or BUSY = LOW will result. BUSYi and BUSY. outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSY outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSY outputs are driving LOW regardless of actual logic level on the pin. Functional Description The IDT7132/1DT7142 provides two ports with separate controi, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7132/IDT7142 has an automatic power down feature controlled by CE. The CE controls on- chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = Vin). When a portis enabled, access to the entire memory array is permitted. Busy Logic Busy Logic provides a hardware indication that both ports of the SRAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the SRAM is busy. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applica- tions. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by piacing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended BY nec a4 industrial ang Commercial femperalure Ranges write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 7132 SRAM (Master) are open drain type outputs and require open drain resistors to operate. If these SRAMS are being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate. Width Expansion with Busy Logic Master/Slave Arrays When expanding an SRAM array in width while using BUSY logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the 1DT7132/ 1DT7142 SRAM the BUSY pin is an output if the part is used as a master (M/S pin = Vin), and the BUSY pin is an input if the part used as a slave (M/S pin = Vit) as shown in Figure 4. {_ c lis 5V, MASTER CE Q Dual Port Oo SRAM i SRAM ee ona a 2702 BUSY. __-BUSYa ; 2702 r t MASTER GE SLAVE GE Dual Port Dual Port SRAM SRAM BUSYL BUSYaA BUSY. BUSYR BUSYA sey tp 2692 orw $5 Figure 4. Busy and chip enable routing for both width and depth expansion with IDT7132 (Master) and (Slave) 1IDT7142 SRAMs. if two or more master parts were used when expanding in width, a split decision coutd resuit with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration on a master is based on the chip enable and address signals only. It ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.IDT7132SA/LA andIDT 7142S ALA High Speed 2K x 8 Dual Port Static RAM Miliary, iadustiai anc Cammercial lemperature Ranges Ordering Information IDT XXXX A _999 _A _ A Device Type Power Speed Package Process/ Temperature Range | BLANK Commercial (0C to +70C) I industrial (-40C to +85C) Military (-55C to +125C) Compliant to MIL-PRF-38535 QML 48-pin Plastic DIP (ee). 48-pin Sidebraze DIP (C-48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) 20 Commercial PLCC Only 25 Commercial & Military 35 Commercial & Military Speed in nanoseconds 55 Commercial & Military 400 Commercial & Military | LA Low Power | SA Standard Power | 7132 16K ie x eB MASTER Dual-Port RAM | 7142 2K x 8-Bit) SLAVE Dual-Port RAM NOTE: 2692 drw 16 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. Datasheet Document History 3/24/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations CORPORATE HEADQUARTERS | for SALES: for Tech Support: &> IiDT 2975 Stender Way 800-345-7015 or 408-727-5166 | 831-754-4613 Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com www.idt.com The IDT logo is a registered trademark of integrated Device Technology, Inc.