PTB48600AAS - Texas Instruments - Datasheet.Directory

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Pin Configuration

Pin Function

1+V

2 Sync In

3 Enable *

4–V

5+V

6 COM

O Adjust

8–V

Shaded functions indicate signals

that are referenced to –Vin.

* Denotes negative logic:

Open = Outputs Off

–Vin = Normal operation

Stand-Alone Application

PTB48600 —48-V Input

85 W Dual Complementary-Output

DC/DC Converter for DSL

Features

•Dual Complementary Outputs

(±5 V)

•Input Voltage Range:

36 V to 75 V

•On/Off Enable for Sequencing

•1500 VDC Isolation

•Over-Current Protection

•Over-Temperature Shutdown

•Under-Voltage Lockout

•Temp Range: –40 to +85°C

•Fixed Frequency Operation

•Synchronizes with PTB4850x

•Powers line driver ICs for AC-7

and other xDSL chipsets

•Safety Approvals: (Pending)

EN60950

UL/cUL60950

Description

The PTB48600A is one of a series

of isolated DC/DC converter modules

that provide a pair of complementary

supply voltages for powering line-driver

ICs in xDSL telecom applications. These

modules operate from a standard telecom

(-48 V) central office supply and can

provide up to a 85 W of power in a bal-

anced load configuration.

The A-suffix module (±5 V) is designed

to power the line driver ICs for the AC-7

ADSL chipset. It will also power any

other applications that require a comple-

mentary supply with relatively balanced

loads. The two compliementary outputs

can also be configured as a single output

of twice the voltage magnitude. As an

example, the outputs of a PTB48600A

can be adjusted up to ±6 V, and config-

ured as a single 12-V output.

The PTB48600 includes an output

“on/off” enable control, output current

limit, over-temperature protection, and

input under-voltage lockout (UVLO).

The control inputs, “Enable” and

“Sync In,” are compatible with the “EN

Out” and “Sync Out” signals of the

PTB4850x DC/DC converter. This

allows the power-up and switching fre-

quency of a PTB48600 module to be

directly controlled from a PTB48500.

Together the PTB48500 and PTB48600

converters meet all the system power

and sequencing requirements of the AC-7

ADSL chipset.

The PTB48600 employs double-sided

surface mount construction. The pack-

age options include both through-hole

and surface mount pin configurations.

–VO

+VI

–VI

COM

+VO

PTB48600

+VI

Enable

–VI

–VO

COM 6

Sync In

±VO Adj 7

+VO5

Complementary

Output & Load

Single-Ended

Output & Load

SLTS239 JANUARY 2005

Not Recommended for New Designs

For technical support and further information visit http://power.ti.com

Ordering Information

Package Options (PT48600A❒❒)

Code Description Pkg Ref. (1)

AH Horiz. T/H (ERT)

AS SMD, Standard (2) (ERU)

Output Voltage (PTB48600❒xx)

Code Voltage

A ±5 V

Notes: (1) Reference the applicable package reference drawing for the dimensions and PC board layout

(2) “Standard” option specifies 63/37, Sn/Pb pin solder material.

Pin Descriptions

+VI: The positive input supply for the module with respect

to –VI. When powering the module from a –48 V telecom

central office supply, this input is connected to the primary

system ground.

–VI: The negative input supply for the module, and the

0 VDC reference for the ‘Enable*’, and ‘Sync In’ signals.

When the module is powered from a +48-V supply, this

input is connected to the 48-V Return.

+VO: The positive output supply voltage, which is refer-

enced to the ‘COM’ node. The voltage at ‘+VO’ has the

same magnitude, but is the complement to that at ‘-VO’.

–VO: The negative output supply voltage, which is refer-

enced to the ‘COM’ node. The voltage at ‘-VO’ has the

same magnitude, but is the complement to that at ‘+VO’.

COM: The secondary return reference for the module’s

regulated output voltages. This node is dc isolated from

the input supply pins.

±VO Adjust: Using a single resistor, this pin allows the

magnitude of both ‘+VO’ and ‘–VO’ to be adjusted to-

gether, either higher or lower than their preset value. If

not used, this pin should be left open circuit.

Enable*: This is an open-collector (open-drain) negative

logic input that enables the module output. This pin is

referenced to -VI. A logic ‘0’ at this pin enables the

module’s outputs, and a high impedance disables the

outputs. If this feature is not used the pin should be con-

nected to –VI. Note: Connecting this input directly to the

“EN Out” pin of the PTB4850x enables the output voltages

from both converters (PTB4850x and PTB48600) to power

up in sequence.

Sync In: This pin is used when the PTB48600 and PTB4850x

DC/DC converter modules are used together. Connect-

ing this pin to the ‘Sync Out’ of the PTB4850x module

allows the PTB48600 to be synchronized to the same

switch conversion frequency as the PTB4850x.

Environmental and General Specifications (Unless otherwise stated, all voltages are with respect to –VI)

Characteristics Symbols Conditions Min Typ Max Units

Input Voltage Range VIOver output load range 36 48 75 VDC

Isolation Voltage Input–output/input–case 1500 — — V

Capacitance Input to output — 1500 — pF

Resistance Input to output 10 — — MΩ

Operating Temperature Range TAOver Vin Range –40 — +85 °C

Over-Temperature Protection OTP Shutdown threshold — 115 (i) —°C

Hysterisis — 10 —

Solder Reflow Temperature TREFLOW Surface temperature of module body or pins 235 (ii) °C

Storage Temperature TS— –40 — 125 °C

Mechanical Vibration Mil-STD-883D, Method 2007.2 T/H — 20 — G’s

20-2000 Hz SMD — 2.5 —

Mechanical Shock Per Mil-STD-883D, Method 2002.3 T/H — 500 — G’s

1 msec, ½ Sine, mounted SMD — 250 —

Weight — — 35 — grams

Flammability — Meets UL 94V-O

Notes: (i) This parameter is defined by design

(ii) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum.

Base Pt. No. (PTB4860❒xxx)

Order Prefix Description

PTB48600xxx Basic Model

85 W Dual Complementary-Output

DC/DC Converter for DSL

SLTS239 JANUARY 2005

PTB48600 —48-V Input

Not Recommended for New Designs

For technical support and further information visit http://power.ti.com

85 W Dual Complementary-Output

DC/DC Converter for DSL

Specifications (Unless otherwise stated, TA =25°C, VI =48 V, CI =0 µF, ±CO =0 µF, |+IO | = |–IO |, and |±IO | =0.5 |±IO |max)

PTB48600A

Characteristic Symbol Conditions Min Typ Max Units

Output Power POTotal output power from ±VO0—85

(1) W

Output Current |±IO |Over VI range, |+IO | – |–IO | ≤ 0.1 A 0 — 8.5 (2) A

Output Load Imbalance |+IO | – |–IO ||+IO | ≥0.1 A, |–IO | ≥ 0.1 A 0 — 1 (3) A

Output Voltage |±VO |Inlcudes set-point, line, |+IO | – |–IO | ≤ 0.1 A 4.75 (2) 5 5.25 (2) V

–40 ≤TA ≤+85°C

Temperature Variation ∆RegTEMP –40 ≤TA ≤ +85°C, |±IO| =0.1 A +VO—±1—%V

–VO—±1—

Line Regulation ∆RegLINE Over VI range, balanced load ±VO— ±0.1 ±0.4 %Vo

Load Regulation ∆RegLOAD Over ±IO range, balanced load ±VO— ±0.2 ±0.4 %Vo

Efficiency η—85—%

Vo Ripple (pk-pk) ±VR20 MHz bandwidth, — 20 30 (4) mVpp

CO =10 µF tantalum capacitor

Transient Response tTR 0.1 A/µs load step, 50% to 75% ±IOmax — 30 — µs

∆VTR |±VO | over/undershoot — ±1 — %Vo

Over Current Threshold |±IO| trip VI =36 V, |+IO| = |–IO|,9 1012A

reset followed by auto-recovery

Short Circuit Current Continuous over-current trip, |±IO |PK —16—A

|+IO | = |–IO |Duty — 10 — %

Output Voltage Adjust Range |±VO | adj |+VO | and |–VO | adjust simulataneously 3.31 — 6 V

Switching Frequency ƒSOver VI and IO ranges 440 470 (5) 500 kHz

Under-Voltage Lockout VI on VI increasing — 33 — V

VI off VI decreasing — 32 —

On/Off Enable (pin 3) Referenced to –VI (pin 4)

Input High Voltage VIH +3.6 — +75 (6) V

Input Low Voltage VIL –0.2 — +0.8

Input Low Current IIL ——–1mA

Standby Input Current II standby pin 3 open circuit — 2 — mA

Start-up Time tON |±IO | =1 A, |±VO | rising 0 to 0.95 |±VO | typ 6 1022ms

Internal Input Capacitance CI—3 —µF

External Output Capacitance ±COCapacitance from either output to COM 0 — 5,000 (7) µF

Reliability MTBF Per Telcordia SR-332 2.8 — — 106 Hrs

50% stress, TA =40°C, gnd benign

Notes: (1) See Safe Operating Area curves or contact the factory for the appropriate derating.

(2) Under balanced load conditions, load current flowing out of +VO is balanced to within ±0.1 A of that flowing into –VO.

(3) A load imbalance is the difference in current flowing from +VO to –VO. The module can operate with a higher imbalance but with reduced specifications.

(4) Output voltage ripple is measured with a 10 µF tantalum capacitor connected from +VO (pin 5) or –VO (pin 8), to COM (pin 6).

(5) This is the free-running frequency. The module can be made to synchronize with the PTB48500 when both modules are used together in a system.

(6) The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is diode protected

and may be connected to +VI. The open-circuit voltage is 5 V max. If it is left open circuit the converter will operate when input power is applied.

(7) Electrolytic capacitors with very low equivalent series resistance (ESR) may induce instability when used on the output. Consult the factory before using

capacitors with organic, or polymer-aluminum type electrolytes.

SLTS239 JANUARY 2005

PTB48600 —48-V Input

Not Recommended for New Designs

For technical support and further information visit http://power.ti.com

Note A: Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the converter.

Note B: Under a balanced load, current flowing out of +Vo is equal to that flowing into –Vo.

Note C: SOA curves represent the conditions at which internal components are at or below the manufacturer’s maximum operating temperatures. Derating limits apply to

modules soldered directly to a 4 in.

4 in. double-sided PCB with 1 oz. copper.

Typical Characteristics

PTB48600A Characteristic Data @VIN =48 V (See Notes A)

Efficiency vs Load Current (See Note B)

Power Dissipation vs Load Current (See Note B)

Safe Operating Area PTB48600A (See Note C)

Balanced Load, VI =48 VDC (See Note B)

Cross Regulation, ∆|+VO| vs |–IO|, with |+IO| = 1 A

Cross Regulation, ∆|–VO| vs |+IO|, with |–IO| = 1 A

85 W Dual Complementary-Output

DC/DC Converter for DSL

01.534.567.5

|±IO| – Output Current – A

Ambient Temperature – °C

400LFM

200LFM

100LFM

Nat conv

Airflow

-400

-200

200

400

01.534.567.5

|-IO| – Output Current – A

±|+VO| – Output Voltage – mV

-400

-200

200

400

01.534.567.5

|+IO| – Output Current – A

±|-VO| – Output Voltage – mV

02468

|±IO| – Balanced Output Current – A

Efficiency - %

36 V

48 V

60 V

72 V

0 1.5 3 4.5 6 7.5

|±IO| – Balanced Output Current – A

PD – Power Dissipation – W

72 V

60 V

48 V

36 V

SLTS239 JANUARY 2005

PTB48600 —48-V Input

Not Recommended for New Designs

Application Notes

For technical support and further information visit http://power.ti.com

Adjusting the Output Voltages of the

PTB48600 Series of DC/DC Converters

The PTB48600 DC/DC converter produces a balanced

pair of complementary output voltages. They are identi-

fied +VO and -VO, respectively. The magnitude of both

output voltages can be adjusted together as a pair, higher

or lower. The adjustment method uses a single external

resistor. 1 The value of the resistor determines the adjust-

ment magnitude, and its placement determines whether

the magnitude is increased or decreased. The resistor

values can be calculated using the appropriate formula

(see below). The formula constants are given in Table 1-1.

The placement of each resistor is as follows.

Adjust Up: To increase the magnitude of both output

voltages, place a resistor R1 between ±VO Adj (pin 7) and

the -VO (pin 8) voltage rail; see Figure 1-1(a).

Figure 1-1b

PTB48600

Calculation of Resistor Adjust Values

The value of the adjust resistor is calculated using one of

the following equations. Use the equation for R1 to adjust

up, or (R2) to adjust down.

R1 [Adjust Up] = VR RO– RSkΩ

2 (VA – VO )

(R2) [Adjust Down] = Ro (2 VA – VR ) – R

SkΩ

2 (VO – VA )

Where: VO= Magitude of the original ±VO

VA= Magnitude of the adjusted voltage

VR= The reference voltage from Table 1-1

RO= The resistance value in Table 1-1

RS= The series resistance from Table 1-1

Figure 1-1a

Adjust Down: To decrease the magnitude of both output

voltages, add a resistor (R2), between ±VO Adj (pin 7)

and the +VO (pin 5) voltage rail; see Figure 1-1(b).

Notes:

1. A 0.05-W rated resistor may be used. The tolerance

should be 1%, with a temperature stability of 100 ppm/°C or

better. Place the resistor in either the R1 or (R2)

location, as close to the converter as possible.

2. Never connect capacitors to the ±V

Adj pin. Capacitance

added to this pin can affect the stability of the regulated

output.

Adjust Up

+VO

±VO Adj

+VO

PTB48600

–VO

COM

(R2)

Adj Down

+VO

±VO Adj

+VO

PTB48600

–VO

COM

Table 1-1

ADJUSTMENT RANGE AND FORMULA PARAMETERS

Series Pt. No. PTB48600A

VO (nom) 5 V

VA (min) 3.31 V

VA (max) 6 V

VR2.495 V

RO (kΩ)7.5

RS (kΩΩ

ΩΩ

Ω)9.09

Not Recommended for New Designs

Application Notes

For technical support and further information visit http://power.ti.com

Configuring the PTB48600 & PTB4850x DC/DC

Converters for DSL Applications

When operated as a pair, the PTB48600 and PTB4850x

converters are specifically designed to provide all the

required supply voltages for powering xDSL chipsets.

The PTB4850x produces two logic voltages. They include

a 3.3-V source for logic and I/O, and a low-voltage for

powering a digital signal processor core. The PTB48600

produces a balanced pair of complementary supply voltages

that is required for the xDSL transceiver ICs. When used

together in these types of applications, the PTB4850x and

PTB48600 may be configured for power-up sequencing,

and also synchronized to a common switch conversion

frequency. Figure 2-1 shows the required cross-connects

between the two converters to enable these two features.

Switching Frequency Synchronization

Unsynchronized, the difference in switch frequency

introduces a beat frequency into the input and output

AC ripple components from the converters. The beat

frequency can vary considerably with any slight variation

in either converter’s switch frequency. This results in a

variable and undefined frequency spectrum for the ripple

waveforms, which would normally require separate filters

at the input of each converter. When the switch frequency

of the converters are synchronized, the ripple components

are constrained to the fundamental and higher. This

simplifies the design of the output filters, and allows a

common filter to be specified for the treatment of input

ripple.

Figure 2-1; Example of PTB4850x & PTB48600 Modules Configured for DSL Applications

–VTCVR

PTB4850xA

+VI

Enable

–VI

VO1

VO2

COM

Sync OutEN Out

VO2 Adj

PTB48600A

+VI

Enable

–VI

+VO

–VO

COM

Sync In ±VO Adj

VCCIO

VCORE

+VTCVR

–48 V RTN

–48 V

Input

Filter

–

Power-Up Sequencing

The desired power-up sequence for the AC7 supply volt-

ages requires that the two logic-level voltages from the

PTB4850x converter rise to regulation prior to the two

complementary voltages that power the transceiver ICs.

This sequence cannot be guaranteed if the PTB4850x

and PTB48600 are allowed to power up independently,

especially if the 48-V input voltage rises relatively slowly.

To ensure the desired power-up sequence, the “EN Out”

pin of the PTB4850x is directly connected to the active-

low “Enable” input of the PTB48600 (see Figure 2-1).

This allows the PTB4850x to momentarily hold off the

outputs from the PTB48600 until the logic-level voltages

have risen first. Figure 2-2 shows the power-up wave-

forms of all four supply voltages from the schematic of

Figure 2-1.

Figure 2-2; Power-Up Sequencing Waveforms

PTB48600 & PTB4850x

V (1 V/Div)

CORE

CCIO

+V (5 V/Div)

–V (5 V/Div)

TCVR

HORIZ SCALE: 10 ms/Div

Not Recommended for New Designs

PACKAGE OPTION ADDENDUM

www.ti.com 1-Sep-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

PTB48600AAH NRND Through-

Hole Module ERT 8 9 Pb-Free (RoHS) SN N / A for Pkg Type

PTB48600AAS OBSOLETE Surface

Mount Module ERU 8 TBD Call TI Call TI

PTB48600AAZ NRND Surface

Mount Module ERU 8 9 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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