_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
19-5707; Rev 0; 12/10
General Description
The MAX14886 high-speed, low-skew, active redriver
multiplexer is ideal for switching between outputs of
dual-graphics systems and signal conditioning to meet
HDMIK v.1.4 compliance up to 2.25Gbps at an external
HDMI connector. It is used for switching between inte-
grated (e.g., Intel or AMD) and discrete graphics (e.g.,
NVIDIA or ATI GPU). The device is VESA DisplayPortK
Interoperability Guideline v.1.1a-compliant (requires
external DDC logic) and integrates seamlessly with an
external HDMI connector on the motherboard.
The device accommodates differential inputs as low
as 200mV and drives transition minimized differential
signaling (TMDS®) outputs to 1000mV (typ). A precision
resistor on the output level adjust pin (ADJ) allows differ-
entiated output back-termination resistors of 400I (typ)
to better meet HDMI mask jitter compliance, while main-
taining full TMDS swing requirements. The device sup-
ports AC-(DisplayPort) or DC-(HDMI) coupling directly
to the graphics IC and must be DC-coupled to the HDMI
connector. In addition, the device features current back-
flow protection at the HDMI connector and a low-power,
active-high or active-low shutdown mode.
The device operates with a single +3.3V supply, is
specified over the 0NC to +70NC commercial temperature
range, and is available in a 5mm x 5mm, 40-pin TQFN
package.
Applications
Dual Graphics Notebook Computers
Dual Mode DisplayPort to HDMI External
Switches or Adapters
Features
S Single +3.3V Supply
S Meets HDMI v.1.4 Eye Mask Up to 2.25Gbps
S Meets VESA DisplayPort Interoperability Guideline
v.1.1a (Requires External DDC Logic)
S Low-Power Shutdown Mode
Active High or Active Low
S Output Level Adjust (ADJ) for Output Back-
Termination Without Amplitude Loss
S Seamless Integration into Dual-Graphics Systems
with External HDMI Connector
DC-Coupled HDMI Outputs Mate Directly to
HDMI Connector
AC- or DC-Coupled TMDS-Formatted Inputs
Ordering Information
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
HDMI is a trademark of HDMI Licensing, LLC.
DisplayPort is a trademark of Video Electronics Standards
Association (VESA).
TMDS is a registered trademark of Silicon Image, Inc.
EVALUATION KIT
AVAILABLE
MAX14886
D0AP
D0AN
CKAP
CKAN
D0CP
D0CN
CKCP
CKCN
SEL
EN1
EN2
ADJ
GND
VCC
100nF
3.3kΩ
50Ω
3.3V
DisplayPort
A
HDMI CONNECTORMCU
HDMI SINK
D0BP
D0BN
CKBP
CKBN
100nF
DisplayPort
B
VAVCC = 3.3V
PART TEMP RANGE PIN-PACKAGE
MAX14886CTL+ 0NC to +70NC40 TQFN-EP*
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
2
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to GND.)
VCC .......................................................................-0.3V to +4.0V
EN1, EN2, SEL, ADJ ................................ -0.3V to (VCC + 0.3V)
D_CP, D_CN, CKCP, CKCN Short-Circuit
Output Current ............................................................. Q30mA
All Other Pins Short-Circuit Current .................................. Q5mA
Continuous Power Dissipation (TA = +70NC)
TQFN (derate 35.7mW/NC above +70NC) ..................2857mW
Operating Temperature Range ............................. 0NC to +70NC
Storage Temperature Range ............................ -65NC to +150NC
Maximum Junction Temperature .....................................+150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(VCC = +3.3V, TA = 0NC to +70NC, RADJ = 3.3kI, CCL = 100nF, typical values are at TA = +25NC.) (Note 2)
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (qJA) ..........45°C/W
Junction-to-Case Thermal Resistance (qJC) .................2°C/W
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC PERFORMANCE
Supply Voltage VCC 3 3.6 V
Supply Current ICC EN1 = high, EN2 = low 52.5 mA
Total Supply Current IGND 50I termination to AVCC, VAVCC = +3.3V
(Note 3) 105 mA
Shutdown Supply Current ISHUT EN1 = low or EN2 = high 100 FA
Single-Ended Input Termination
Resistance RIN DC 40 60 I
Single-Ended Output Voltage
High VOH DC, VAVCC = +3.3V (Notes 3, 4) VAVCC
- 0.01
VAVCC
+ 0.01 V
Single-Ended Output Voltage
Low VOL DC, VAVCC = +3.3V (Notes 3, 4) VAVCC
- 0.6
VAVCC
- 0.45 V
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.3V, TA = 0NC to +70NC, RADJ = 3.3kI, CCL = 100nF, typical values are at TA = +25NC.) (Note 2)
Note 2: All units are production tested at TA = +70NC. Specifications over temperature are guaranteed by design.
Note 3: AVCC is an external supply.
Note 4: Guaranteed by design; not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AC PERFORMANCE
Differential Input Return Loss SDD11 150MHz P f P 1.25GHz -8 dB
Input Frequency Range fIN Clock 25 225 MHz
Data 225 1125
Differential Input Range VIDIFF 200 1600 mV
Differential Output Voltage VODIFF 50I single termination 900 1250 mV
Output Rise/Fall Time tR/F 20% to 80%, 2.25Gbps 80 ps
Deterministic Jitter tDJ K28.5 pattern, up to 2.25Gbps (Note 4) 0.04 UI
Random Jitter tRJ D10.2 pattern, 2.25Gbps (Note 4) 1.1 psRMS
Lane-to-Lane Skew tSK 50 ps
Propagation Delay tPD 250 ps
CONTROL LOGIC (EN1, EN2, SEL)
Input Logic-Low Voltage VIL 0.6 V
Input Logic-High Voltage VIH 1.4 V
Input Logic Hysteresis VHYST 50 mV
Input Pulldown/Pullup Resistor RIPULL 400 kI
Shutdown Recovery Time tSHUT 20 Fs
TMDS Mux Switching Time tMUX 50 ns
ESD PROTECTION
All Pins Human Body Model ±8 kV
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
4
Typical Operating Characteristics
(VCC = +3.3V, TA = +25NC, RADJ = 3.3kI, unless otherwise noted.)
DIFFERENTIAL INPUT RETURN LOSS
vs. FREQUENCY
MAX14886 toc08
FREQUENCY (GHz)
MAGNITUDE (dB)
21
-40
-35
-30
-25
-20
-15
-10
-5
0
5
-45
0 3
EYE DIAGRAM, V
IN
= 200mV
P-P
, 2.25Gbps,
400Ω BACK TERMINATION, RSET = 3kΩ, FIGURE 1
MAX14886 toc07
(ps)
VOLTAGE (mV)
300 4002000 100-200 -100-300-400
-800
-600
-400
-200
0
200
400
600
800
EYE DIAGRAM, VIN = 200mVP-P,
2.25Gbps, NO BACK TERMINATION,
225MHz CLOCK, 1080p, 12-BIT COLOR, 60Hz
MAX14886 toc06
(ps)
VOLTAGE (mV)
300 4002000 100-200 -100-300-400
-800
-600
-400
-200
0
200
400
600
800
EYE DIAGRAM, VIN = 1600mVP-P,
2.25Gbps, NO BACK TERMINATION
MAX14886 toc05
(ps)
VOLTAGE (mV)
300 4002000 100-200 -100-300-400
-800
-600
-400
-200
0
200
400
600
800
EYE DIAGRAM, VIN = 200mVP-P,
1.5Gbps, NO BACK TERMINATION,
1080p, 8-BIT COLOR, 60Hz
MAX14886 toc04
(ps)
VOLTAGE (mV)
400 6002000-200-400-600
-800
-600
-400
-200
0
200
400
600
800
EYE DIAGRAM, VIN = 1600mVP-P,
1.5Gbps, NO BACK TERMINATION, 150MHz CLOCK
MAX14886 toc03
(ps)
VOLTAGE (mV)
400 6002000-200-400-600
-800
-600
-400
-200
0
200
400
600
800
EYE DIAGRAM, VIN = 200mVP-P,
250Mbps, NO BACK TERMINATION,
25MHz CLOCK, 640 x 480, 8-BIT COLOR, 60Hz
MAX14886 toc02
VOLTAGE (mV)
431 2-3 -2 -1 0-4
-800
-600
-400
-200
0
200
400
600
800
-5
(ns)
EYE DIAGRAM, VIN = 1600mVP-P,
250Mbps, NO BACK TERMINATION,
25MHz CLOCK, 640 x 480, 8-BIT COLOR, 60Hz
MAX14886 toc01
VOLTAGE (mV)
431 2-3 -2 -1 0-4
-800
-600
-400
-200
0
200
400
600
800
-5
(ns)
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
5
Pin Configuration
Pin Description
TQFN
(5mm × 5mm × 0.75mm)
TOP VIEW
35
36
34
33
12
11
13
D0AN
D0BN
GND
CKAP
CKAN
14
D0AP
D1BP
D2AN
D2AP
D1BN
D1AP
D1AN
D2BN
D2BP
1 2
SEL
+
4 5 6 7
27282930 26 24 23 22
GND
VCC
D1CP
D1CN
VCC
D0CP
D0BP
GND
3
25
37
EN2 D0CN
38
39
40
EN1
GND
VCC
CKCP
CKCN
GND
ADJ
32
15
D2CN
GND
31
16
17
18
19
20 D2CP
CKBP
CKBN
GND GND
8 9 10
21
VCC
*EP
*CONNECT EP TO GND.
MAX14886
PIN NAME FUNCTION
1 D0AP Noninverting Input D0 for Channel A
2 D0AN Inverting Input D0 for Channel A
3 D0BP Noninverting Input D0 for Channel B
4 D0BN Inverting Input D0 for Channel B
5, 10,
11, 21,
26, 32,
35, 39
GND Ground
6 CKAP Noninverting Input Clock for Channel A
7 CKAN Inverting Input Clock for Channel A
8 CKBP Noninverting Input Clock for Channel B
9 CKBN Inverting Input Clock for Channel B
12 CKCN Inverting Output Clock
13 CKCP Noninverting Output Clock
14 D0CN Inverting Output D0
15 D0CP Noninverting Output D0
16, 31,
36, 40 VCC
Power-Supply Voltage. Bypass VCC
to GND with low-ESR 10nF and
4.7FF ceramic capacitors in parallel
as close as possible to the device.
Recommended on each VCC pin.
17 D1CN Inverting Output D1
PIN NAME FUNCTION
18 D1CP Noninverting Output D1
19 D2CN Inverting Output D2
20 D2CP Noninverting Output D2
22 D2BP Noninverting Input D2 for Channel B
23 D2BN Inverting Input D2 for Channel B
24 D2AP Noninverting Input D2 for Channel A
25 D2AN Inverting Input D2 for Channel A
27 D1BP Noninverting Input D1 for Channel B
28 D1BN Inverting Input D1 for Channel B
29 D1AP Noninverting Input D1 for Channel A
30 D1AN Inverting Input D1 for Channel A
33 ADJ Output Level Adjust
34 SEL Mux Select Input. SEL is internally
pulled down by a 400kI (typ) resistor.
37 EN2
Active-Low Enable Input. EN2 is inter-
nally pulled up by a 400kI (typ)
resistor.
38 EN1
Active-High Enable Input. EN1 is
internally pulled down by a 400kI (typ)
resistor.
— EP Exposed Pad. Connect EP to GND.
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
6
Functional Diagram/Truth Tables
X = Don’t care.
X = Don’t care.
MAX14886
50Ω
D2AP
D2AN
50Ω
VCC
VCC
50Ω
D2BP
D2BN
50Ω
VCC
50Ω
D1AP
D1AN
50Ω
VCC
50Ω
D1BP
D1BN
50Ω
VCC
50Ω
D0AP
D0AN
50Ω
VCC
50Ω
D0BP
D0BN
D2CP
D2CN
D1CP
D1CN
D0CP
D0CN
CKCP
CKCN
50Ω
VCC
50Ω
CKAP
CKAN
50Ω
VCC
50Ω
CKBP
CKBN
50Ω
EN1 EN2 SEL ADJGND
VCC
MULTIPLEXER/
LIMITING
AMPLIFIER
CONTROL
EN1 EN2 FUNCTION
0/Unconnected X Shutdown
X 1/Unconnected Shutdown
1 0 Active
SEL D_A_, CKA_ D_B_, CKB_
0/Unconnected On Off
1 Off On
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
7
Detailed Description
The MAX14886 is a high-speed, low-skew, active
redriver multiplexer designed to switch and amplify
TMDS-formatted signals. Input buffers have 50I HDMI-
compliant terminations to VCC (see the Functional
Diagram/Truth Tables), allowing either DC-coupling to
an HDMI source or AC-coupling to a DisplayPort source.
Signals from the input buffers are multiplexed and
redriven by the limiting amplifier and an open-collector
output buffer. The HDMI monitor sink is DC-coupled to
the outputs and provides DC bias.
Both TMDS clock and data are multiplexed and redriven
to full HDMI v.1.4 levels with low skew and jitter to
guarantee mask compliance at an external HDMI con-
nector. The device is VESA DisplayPort Interoperability
Guideline v.1.1a-compliant and integrates seamlessly
with an external HDMI connector on the motherboard.
The low-frequency signals (DDC, CEC, and HPD) can be
handled by external low-cost logic.
The device accommodates differential inputs as low as
200mV and drives differential TMDS outputs to 1000mV
(typ). A precision resistor on the output level adjust pin
(ADJ) allows differential output back-termination resis-
tors of 400I (typ) to better meet HDMI mask jitter compli-
ance, while maintaining full TMDS swing requirements.
This device also features both active-high and active-
low enable inputs. One of the enable inputs can be
connected to either VCC or GND, while the other can be
used to control the device (see the Functional Diagram/
Truth Tables and Enable Inputs (EN1, EN2) section). This
eliminates any issues with logic sense and the need for
an inverter.
Level Translation
The device accepts two sets of four differential
DisplayPort-level TMDS-formatted inputs, each with
magnitudes as low as 200mV. The selected channel is
translated to full HDMI TMDS levels that are HDMI v.1.4
port mask-compliant up to 2.25Gbps.
Enable Inputs (EN1, EN2)
The device features both an active-high enable input
(EN1) and an active-low enable input (EN2) that can be
controlled by LVCMOS or LVTTL. EN1 has an internal
400kI (typ) pulldown resistor, and EN2 has an internal
400kI (typ) pullup resistor. When EN1 is driven low or
left unconnected, or EN2 is driven high or left uncon-
nected, the device enters low-power shutdown mode.
For normal operation drive both EN1 high and EN2 low.
See the Functional Diagram/Truth Tables.
Only one input is necessary to control the device. If
active-high enable is desired, connect EN2 to GND and
use EN1 to control the device. Similarly, for active-low
enable, connect EN1 to VCC and use EN2 to control the
device.
Note: The monitor sink termination must be present and
powered before enabling the device (see the Control
Sequence section and Figure 2).
Digital Control Input (SEL)
The device provides two sets of 4 channels for all the dif-
ferential signals required by HDMI connections. The SEL
input controls which channel is translated to the output
channel (see the Functional Diagram/Truth Tables). An
internal 400kI pulldown resistor guarantees that channel
A is translated to the output if the SEL pin is not externally
driven.
Output Level Adjust (ADJ)
The level-shifter’s output current and output signal swing
are set with an external ±1% precision 3.3kI (typ) resis-
tor. If a double output termination (400I typ) is desired
for signal integrity reasons, the ADJ resistor value can be
decreased to maintain a desired output swing (Figure 1).
Applications Information
HDMI Driver
The device’s high-speed, low-skew, active redriver
multiplexer is ideal for switching between outputs of
dual-graphics systems and signal conditioning to meet
HDMI v.1.4 compliance at an external HDMI connector
(Figure 1). It is well suited for switching between inte-
grated (e.g., Intel or AMD) and discrete graphics (e.g.,
NVIDIA or ATI GPU). The device is VESA DisplayPort
Interoperability Guideline v.1.1a-compliant (requires
external DDC logic) and integrates seamlessly with an
external HDMI connector on the motherboard.
Output Termination
Outputs are terminated in normal use by the HDMI moni-
tor. For 50I test equipment purposes, terminate each
output with a high-frequency bias-T that has an inductor
in series with a 50I resistor to VCC.
Control Sequence
The monitor sink termination must be present and pow-
ered before enabling the device. A simple circuit can
be added to protect the device by forcing hot-plug
detection (HPD) to be present before the part is enabled
(Figure 2).
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
8
Figure 1. HDMI Driver Application with Output Back Termination
Figure 2. Control Sequence Protection Circuit
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to maxi-
mize performance and noise immunity. Bypass each
VCC pin to GND with high-frequency, low-ESR, X7R/X5R
10nF and 4.7FF surface-mount ceramic capacitors as
close as possible to the device.
Printed Circuit Board (PCB) Traces
Input and output trace characteristics affect the perfor-
mance of the device. Connect each of the inputs and
outputs to a 50I characteristic impedance trace in to
minimize reflections. Avoid discontinuities in differential
impedance and maximize common-mode noise immuni-
ty by maintaining the distance between differential traces
and avoiding sharp corners. Minimize the number of vias
to prevent impedance discontinuities. Reduce reflec-
tions by maintaining the 50I characteristic impedance
through connectors and across cables. Minimize skew
by matching the electrical length of the traces.
MAX14886
D0AP
D0AN
CKAP
CKAN
D0CP
D0CN
CKCP
CKCN
SEL
EN1
EN2
ADJ
GND
VCC
3kΩ
50Ω
3.3V
SOURCE A
HDMI CONNECTOR
MCU
HDMI SINK
D0BP
D0BN
CKBP
CKBN
FOR DisplayPort SOURCE, ADD AC-COUPLING CAPACITORS.
SOURCE B
VAVCC = 3.3V
400Ω
400Ω
MAX14886
EN
N
CONTROL CPU
GPIO
HPD
EN1
10kΩ
10kΩ
HPD
+3.3V
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
9
Exposed-Pad Package
The exposed-pad, 40-pin TQFN package incorporates
features that provide a very low thermal resistance
path for heat removal from the IC. The exposed pad
on the device must be soldered to the circuit board
ground plane for proper electrical and thermal perfor-
mance. For more informa tion on exposed-pad pack-
ages, refer to Application Note 862: HFAN-08.1: Thermal
Considerations of QFN and Other Exposed-Paddle
Packages.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
40 TQFN-EP T4055+2 21-0140 90-0002
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX14886
Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 12/10 Initial release —
