Freescale Semiconductor, Inc. Order this document by MCM63P736/D SEMICONDUCTOR TECHNICAL DATA Freescale Semiconductor, Inc... 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM MCM63P736 MCM63P818 The MCM63P736 and MCM63P818 are 4M-bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each, and the MCM63P818 is organized as 256K words of 18 bits each. These devices integrate input registers, an output R, O register, a 2-bit address counter, and high speed SRAM onto a single monolithic CT circuit for reduced parts count in cache data RAM applications. Synchronous U design allows precise cycle control with the use of an external clock (K). ND Addresses (SA), data inputs (DQx), and all control signals except outputO IC enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled M through positive-edge-triggered noninverting registers. SE burst Bursts can be initiated with either ADSP or ADSC input pins. Subsequent E L MCM63P818 addresses can be generated internally by the MCM63P736A and C (burst sequence operates in linear or interleaved mode dependent upon the state S (ADV) input pin. of LBO) and controlled by the burst address advance E E Write cycles are internally self-timed and are initiated R by the rising edge of the Foff-chip clock (K) input. This feature eliminates complex write pulse generation Y Bincoming and provides increased timing flexibility for signals. global write (SGW), and synchroSynchronous byte write (SBx), synchronous ED V I to allow writes to either individual bytes or nous write enable (SW) are provided to all bytes. The bytes are designated as "a", "b", etc. SBa controls DQa, SBb CH R controls DQb, etc. Individual A bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge-triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM63P736 and MCM63P818 operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. C IN . TQ PACKAGE TQFP CASE 983A-01 ZP PACKAGE PBGA CASE 999-02 * MCM63P736/MCM63P818-133 = 4 ns Access/7.5 ns Cycle (133 MHz) MCM63P736/MCM63P818-100 = 5 ns Access/10 ns Cycle (100 MHz) MCM63P736/MCM63P818-66 = 7 ns Access/15 ns Cycle (66 MHz) * 3.3 V + 10%, - 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply * ADSP, ADSC, and ADV Burst Control Pins * Selectable Burst Sequencing Order (Linear/Interleaved) * Two-Cycle Deselect Timing * Internally Self-Timed Write Cycle * Byte Write and Global Write Control * Sleep Mode (ZZ) * JEDEC Standard 100-Pin TQFP and 119-Pin PBGA Packages The PowerPC name is a trademark of IBM Corp., used under license therefrom. REV 3 3/12/99 Motorola, Inc. 1999 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P736*MCM63P818 1 Freescale Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM LBO ADV K ADSC BURST COUNTER K2 2 17/18 128K x 36 / 256K x 18 ARRAY CLR ADSP 2 SA SA1 SA0 17/18 ADDRESS REGISTER 15/16 SGW Freescale Semiconductor, Inc... SW WRITE REGISTER a SBa SBb SBc* CH R A SBd* ED V I BY EE R F LE A SC WRITE REGISTER b S O IC EM R, O CT U ND . 36/18 36/18 4/2 DATA-IN REGISTER WRITE REGISTER c* DATA-OUT REGISTER K WRITE REGISTER d* K K2 SE1 SE2 SE3 C IN ENABLE REGISTER K WRITE REGISTER ENABLE REGISTER G DQa - DQd / DQa - DQb ZZ * Valid only for MCM63P736. MCM63P736*MCM63P818 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CH R A ED V I BY EE R F DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa LE A SC S A B C D 1 2 3 4 5 6 VDDQ SA SA ADSP SA SA VDDQ NC SE2 SA ADSC SA SE3 NC NC SA SA VDD SA SA NC DQc DQc VSS NC VSS DQb DQb DQc DQc VSS . NCG VSS DQb DQb VSS DQb VDDQ ADV SBb DQb DQb SGW VSS DQb DQb VDD NC VDD VDDQ K VSS DQa DQa DQa E F ,I R DQc DQc SBc TO H C DQc U DQc VSS J D N VDDQ VDD NC O K IC DQd DQd VSS M E L VDDQ DQc G SE1 VSS 7 DQd SBd NC SBa DQa VDDQ DQd VSS SW VSS DQa VDDQ DQd M N P R DQd DQd VSS SA1 VSS DQa DQa DQd DQd VSS SA0 VSS DQa DQa NC SA LBO VDD NC SA NC NC NC SA SA SA NC ZZ VDDQ NC NC NC NC NC VDDQ T U LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA Freescale Semiconductor, Inc... SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA MCM63P736 PIN ASSIGNMENTS 100-PIN TQFP TOP VIEW 119-BUMP PBGA TOP VIEW Not to Scale MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P736*MCM63P818 3 Freescale Semiconductor, Inc. MCM63P736 TQFP PIN DESCRIPTIONS Pin Locations Symbol Type 85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). 83 ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 Freescale Semiconductor, Inc... 86 89 31 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 36, 37 CH R A ED V I Description . Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d). C IN R, O T G Input Asynchronous Output Enable Input: C(DQx Low -- enables output buffers pins). U D impedance. High -- DQx pins are high N K Input Clock: This signal registers the address, data in, and all control signals CO I except G, LBO, and ZZ. M E LBO Input Linear S Burst Order Input: This pin must remain in steady state (this E signal L not registered or latched). It must be tied high or low. ALow -- linear burst counter (68K/PowerPC). C S High -- interleaved burst counter (486/i960/Pentium). E E SA R Input Synchronous Address Inputs: These inputs are registered and must F meet setup and hold times. Y B SA1, SA0 Input Synchronous Address Inputs: these pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b, c, d). SGW overrides SBx. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 87 SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 15, 41, 65, 91 VDD Supply Core Power Supply. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Supply Ground. 14, 16, 38, 39, 42, 43, 66 NC -- MCM63P736*MCM63P818 4 No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM63P736 PBGA PIN DESCRIPTIONS Pin Locations Symbol Type 4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). 4G ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P DQx I/O Freescale Semiconductor, Inc... 4F 4K 3R 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T 4N, 4P CH R A ED V I Description . Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d). C IN R, O T G Input Asynchronous Output Enable Input: C(DQx Low -- enables output buffers pins). U D impedance. High -- DQx pins are high N K Input Clock: This signal registers the address, data in, and all control signals CO I except G, LBO, and ZZ. M E LBO Input Linear S Burst Order Input: This pin must remain in steady state (this E signal L not registered or latched). It must be tied high or low. ALow -- linear burst counter (68K/PowerPC). C S High -- interleaved burst counter (486/i960/Pentium). E E SA R Input Synchronous Address Inputs: These inputs are registered and must F meet setup and hold times. Y B SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 5L, 5G, 3G, 3L (a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b, c, d). SGW overrides SBx. 4E SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. 2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 6B SE3 Input Synchronous Chip Enable: Active low for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 4M SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 7T ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 4C, 2J, 4J, 6J, 4R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply I/O Power Supply. 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P VSS Supply Ground. 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U NC -- MOTOROLA FAST SRAM No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MCM63P736*MCM63P818 5 Freescale Semiconductor, Inc. NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CH R A ED V I BY EE R F SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC LE A SC S A B C D 1 2 3 4 5 6 VDDQ SA SA ADSP SA SA VDDQ NC SE2 SA ADSC SA SE3 NC NC SA SA VDD SA SA NC DQb NC VSS NC VSS DQa NC NC DQb VSS . NCG VSS NC DQa VSS DQa VDDQ ADV VSS NC DQa SGW VSS DQa NC VDD NC VDD VDDQ K VSS NC DQa E F ,I R NC DQb SBb O T H C DQb U NC VSS J D N VDDQ VDD NC O K IC NC DQb VSS M E L VDDQ NC G SE1 VSS 7 NC VSS NC SBa DQa NC VDDQ DQb VSS SW VSS NC VDDQ DQb M N P R DQb NC VSS SA1 VSS DQa NC NC DQb VSS SA0 VSS NC DQa NC SA LBO VDD NC SA NC NC SA SA NC SA SA ZZ VDDQ NC NC NC NC NC VDDQ T U LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA Freescale Semiconductor, Inc... SA SA SE1 SE2 NC NC SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA MCM63P818 PIN ASSIGNMENTS 100-PIN TQFP TOP VIEW 119-BUMP PBGA TOP VIEW Not to Scale MCM63P736*MCM63P818 6 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM63P818 TQFP PIN DESCRIPTIONS Pin Locations Symbol Type 85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). 83 ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 DQx I/O Freescale Semiconductor, Inc... 86 Description . Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b). C IN R, O CT U K Input Clock: This signal registers D the address, data in, and all control signals N except G, LBO, and ZZ. O IC Input: This pin must remain in steady state (this LBO Input Linear Burst Order M signal notEregistered or latched). It must be tied high or low. S Low -- linear burst counter (68K/PowerPC). High LE-- interleaved burst counter (486/i960/Pentium). A SA Input SC Synchronous Address Inputs: These inputs are registered and must E meet setup and hold times. E R F Input Synchronous Address Inputs: These pins must be wired to the two SA1, SA0 LSBs of the address bus for proper burst operation. These inputs are BY registered and must meet setup and hold times. G Input Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. SBx Input Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b). SGW overrides SBx. SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 87 SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 15, 41, 65, 91 VDD Supply Core Power Supply. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Supply Ground. 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 NC -- 89 31 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 36, 37 93, 94 (a) (b) 98 CH R A MOTOROLA FAST SRAM ED V I No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MCM63P736*MCM63P818 7 Freescale Semiconductor, Inc. MCM63P818 PBGA PIN DESCRIPTIONS Pin Locations Symbol Type 4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). 4G ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P DQx I/O Freescale Semiconductor, Inc... 4F Description . Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b). C IN R, O CT U K Input Clock: This signal registers D the address, data in, and all control signals N except G, LBO, and ZZ. O IC Input: This pin must remain in steady state (this LBO Input Linear Burst Order M signal notEregistered or latched). It must be tied high or low. S Low -- linear burst counter (68K/PowerPC). High LE-- interleaved burst counter (486/i960/Pentium). A SA Input SC Synchronous Address Inputs: These inputs are registered and must E meet setup and hold times. E R F Input Synchronous Address Inputs: These pins must be wired to the two SA1, SA0 LSBs of the address bus for proper burst operation. These inputs are BY registered and must meet setup and hold times. G Input Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. SBx Input Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b). SGW overrides SBx. SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. 2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 6B SE3 Input Synchronous Chip Enable: Active low for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 4M SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 7T ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 4C, 2J, 4J, 6J, 4R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply I/O Power Supply. 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P VSS Supply Ground. 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U NC -- 4K 3R 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 4N, 4P 5L, 3G (a) (b) 4E CH R A MCM63P736*MCM63P818 8 ED V I No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. TRUTH TABLE (See Notes 1 Through 5) Address Used SE1 SE2 SE3 ADSP ADSC ADV G3 DQx Write 2, 4 Deselect None 1 X X X 0 X X High-Z X Deselect None 0 X 1 0 X X X High-Z X Deselect None 0 0 X 0 X X X High-Z X Deselect None X X 1 1 0 X X High-Z X Deselect None X 0 X 1 0 X X High-Z X Begin Read External 0 1 0 0 X X X High-Z X Begin Read READ Freescale Semiconductor, Inc... Next Cycle External 0 1 0 1 0 X X High-Z Continue Read Next X X X 1 1 0 1 High-Z READ Continue Read Next X X X 1 1 READ Continue Read Next 1 X X X 1 Continue Read Next 1 X X X 1 Suspend Read Current X X X 1 1 Suspend Read Current X X X 1 1 Suspend Read Current 1 X X X N 0 1 , I High-Z 0 DQ O0R T 1 C 1 High-Z U D 1 0 DQ N Suspend Read Current 1 X X X Begin Write External 0 1 Continue Write Next X X Continue Write Next 1 Suspend Write Current X Suspend Write Current 1 O IC 1 EM 1 1 0 1 C. DQ READ READ READ READ High-Z READ 1 0 DQ READ 0 X X High-Z WRITE X 1 0 X High-Z WRITE EE X R FX X 1 0 X High-Z WRITE 1 1 1 X High-Z WRITE X 1 1 X High-Z WRITE X X BY 0 LE1 A X SXC 0 1 S NOTES: 1. X = Don't Care. 1 = logic high. 0 = logic low. 2. Write is defined as either 1) any SBx and SW low or 2) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. CH R A ED V I ASYNCHRONOUS TRUTH TABLE Operation ZZ G I/O Status Read L L Data Out (DQx) Read L H High-Z Write L X High-Z Deselected L X High-Z Sleep H X High-Z 4th Address (Internal) LINEAR BURST ADDRESS TABLE (LBO = VSS) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 4th Address (Internal) INTERLEAVED BURST ADDRESS TABLE (LBO = VDD) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P736*MCM63P818 9 Freescale Semiconductor, Inc. WRITE TRUTH TABLE SGW SW SBa SBb SBc (See Note 1) SBd (See Note 1) Read H H X X X X Read H L H H H H Write Byte a H L L H H H Write Byte b H L H L H H Write Byte c (See Note 1) H L H H L H Write Byte d (See Note 1) H L H H H L Write All Bytes H L L L L L Write All Bytes L X X X X X Cycle Type C IN NOTE: 1. Valid only for MCM63P736. Freescale Semiconductor, Inc... ABSOLUTE MAXIMUM RATINGS (See Note 1) Symbol Rating Power Supply Voltage I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD VDD VSS - 0.5 to 4.6 V VSS - 0.5 to VDD V Vin, Vout VSS - 0.5 to VDD + 0.5 VIT Output Current (per I/O) Iout Package Power Dissipation PD Storage Temperature CH R A Unit VDDQ Input Voltage (Three-State I/O) Temperature Under Bias Value D TE bias V I T BY stg VS E L VSS - 0.5 toCA V S VDDQ + 0.5 E E mA FR 20 1.6 W - 10 to 85 C - 55 to 125 C Notes O IC EM . R, O T C This device contains circuitry to protect the U inputs against damage due to high static voltND 2 2 ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 2 3 NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady-state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics. PACKAGE THERMAL CHARACTERISTICS -- TQFP Rating Symbol Max Unit Notes RJA 40 25 C/W 1, 2 Junction to Board (Bottom) RJB 17 C/W 3 Junction to Case (Top) RJC 9 C/W 4 Junction to Ambient (@ 200 lfm) Single-Layer Board Four-Layer Board NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1). MCM63P736*MCM63P818 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. PACKAGE THERMAL CHARACTERISTICS -- PBGA Rating Symbol Max Unit Notes RJA 38 22 C/W 1, 2 Junction to Board (Bottom) RJB 14 C/W 3 Junction to Case (Top) RJC 5 C/W 4 Junction to Ambient (@ 200 lfm) Single-Layer Board Four-Layer Board NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1). , DC OPERATING CONDITIONS AND CHARACTERISTICS OR C IN . Freescale Semiconductor, Inc... (VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise CTNoted) DU N RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS: 2.5 V I/O SUPPLY O (Voltages Referenced to VSS = 0 V) IC Parameter Symbol EM Min Typ S Supply Voltage 3.135 3.3 E LVDD A I/O Supply Voltage V 2.375 2.5 SC DDQ E Input Low Voltage VIL - 0.3 -- E R Input High Voltage VIH 1.7 -- F Y Input High Voltage I/O Pins VIH2 1.7 -- B D Output Low Voltage (IOL = 2 mA) VOL -- -- VE I Output High Voltage (IOL = - 2 mA) VOH 1.7 -- CH R A Max Unit 3.6 V 2.9 V 0.7 V VDD + 0.3 V VDDQ + 0.3 V 0.7 V -- V RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS: 3.3 V I/O SUPPLY (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Typ Max Unit VDD 3.135 3.3 3.6 V I/O Supply Voltage VDDQ 3.135 3.3 VDD V Input Low Voltage VIL - 0.5 -- 0.8 V Input High Voltage VIH 2 -- VDD + 0.5 V Input High Voltage I/O Pins VIH2 2 -- VDDQ + 0.5 V Supply Voltage Output Low Voltage (IOL = 8 mA) VOL -- -- 0.4 V Output High Voltage (IOL = - 4 mA) VOH 2.4 -- -- V VIH VSS VSS - 1.0 V 20% tKHKH (MIN) Figure 1. Undershoot Voltage MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P736*MCM63P818 11 Freescale Semiconductor, Inc. SUPPLY CURRENTS Parameter Symbol Min Typ Max Unit Notes Input Leakage Current (0 V Vin VDD) Ilkg(I) -- -- 1 A 1 Output Leakage Current (0 V Vin VDDQ) Ilkg(O) -- -- 1 A IDDA -- -- 450/380 410/345 350/285 mA 2, 3, 4 CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels) ISB2 -- -- 15 mA 5, 6 Sleep Mode Standby Current (Device Deselected, Freq = Max, VDD = Max, All Other Inputs Static at CMOS Levels, ZZ VDD - 0.2 V) IZZ -- -- 5 mA 1, 5, 6 AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes VDD Only MCM63P736 / 818-133 MCM63P736 / 818-100 MCM63P736 / 818-66 mA 5, 7 , R T--O Clock Running (Device Deselected, MCM63P736 / 818-133 ISB4 -- 160/145 mA 5, 6 C Freq = Max, VDD = Max, All Inputs MCM63P736 / 818-100 135/120 U Toggling at CMOS Levels) MCM63P736 / 818-66 110/95 ND O Static Clock Running (Device Deselected, MCM63P736 / 818-133 ISB5 -- 65/55 mA 5, 6 IC -- Freq = Max,VDD = Max, All Inputs MCM63P736 / 818-100 50/40 M Static at TTL Levels) MCM63P736 / 818-66 35/30 SE E NOTES: AL and will exhibit leakage currents of 5 A. 1. LBO and ZZ pins have an internal pull-up and pull-down, respectively; C 2. Reference AC Operating Conditions and Characteristics S for input and timing. Ehigh 3. All addresses transition simultaneously low (LSB) then (MSB). E R 4. Data states are all zero. F 5. Device is deselected as defined by the Truth YTable. B 6. CMOS levels for I/Os are VIT VSS + 0.2 V or VDDQ - 0.2 V. CMOS levels for other inputs are Vin VSS + 0.2 V or VDD - 0.2 V. 7. TTL levels for I/Os are VIT VIL orED V . TTL levels for other inputs are Vin VIL or VIH. V IH2 I CH R A TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at TTL Levels) Freescale Semiconductor, Inc... C. N I 35 MCM63P736*MCM63P818 12 ISB3 -- For More Information On This Product, Go to: www.freescale.com -- MOTOROLA FAST SRAM Freescale Semiconductor, Inc. AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20% to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1 and 2) MCM63P736-133 MCM63P818-133 Freescale Semiconductor, Inc... Parameter P MCM63P736-100 MCM63P818-100 MCM63P737-66 MCM63P819-66 Symbol S b l Min Max Min Max Min Cycle Time tKHKH 7.5 -- 10 -- 15 Clock High Pulse Width tKHKL 3 Clock Low Pulse Width tKLKH 3 Clock Access Time tKHQV -- Output Enable to Output Valid tGLQV -- Clock High to Output Active tKHQX1 0 Clock High to Output Change tKHQX2 1.5 Output Enable to Output Active tGLQX Output Disable to Q High-Z tGHQZ Clock High to Q High-Z Setup Times: Hold Times: EE Address tADKH R F ADSP, ADSC, ADV tADSKH Data In Y tDVKH B tWVKH Write ED tEVKH Chip Enable V I Address tKHAX CH ADSP, tKHADSX ADSC, ADV R A tKHDX Data In tKHQZ Write Chip Enable Max Unit U i -- ns Notes N -- 4 -- 6 C.-- ns 3 -- 4 -- 6 -- ns 3 7 ns 6 ns -- ns 4, 5 -- ns 4 0 IN , R 4 -- 5 TO -- 3.8 -- -- U4C D N -- 0 -- 0 O C I -- -- 1.5 M 1.5 E 0 -- 0 S-- -- ns 4, 5 -- 3.8 -- 4 -- 6 ns 4, 5 7.5 1.5 10 1.5 15 ns 4, 5 2 -- 2 -- 2 -- ns 0.5 -- 0.5 -- 0.5 -- ns LE A SC1.5 tKHWX tKHEX NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. This parameter is sampled and not 100% tested. 5. Measured at 200 mV from steady state. MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P736*MCM63P818 13 Freescale Semiconductor, Inc. OUTPUT Z0 = 50 RL = 50 1.5 V Figure 2. AC Test Load 2400 C IN CLOCK ACCESS TIME DELAY (ps) Freescale Semiconductor, Inc... 2200 OUTPUT CL ED V I BY EE R F 2000 1800 1600 1400 1200 1000 L600E A SC 400 800 S O IC EM R, O CT U ND . 200 0 0 20 40 60 80 100 LUMPED CAPACITANCE, CL (pF) H 3. Lumped Capacitive Load and Typical Derating Curve CFigure R A OUTPUT LOAD OUTPUT BUFFER TEST POINT UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM OUTPUT WAVEFORM 2.4 2.4 0.6 0.6 2.4 2.4 0.6 0.6 tr tf NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.6 to 2.4 V unloaded. 3. Fall time is measured from 2.4 to 0.6 V unloaded. Figure 4. Unloaded Rise and Fall Time Characterization MCM63P736*MCM63P818 14 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. 2.9 2.5 PULL-UP I (mA) MIN I (mA) MAX - 0.5 - 38 - 105 0 - 38 - 105 0.8 - 38 - 105 1.25 - 26 - 83 1.5 - 20 - 70 2.3 0 - 30 2.7 0 - 10 2.9 0 0 2.3 2.1 VOLTAGE (V) VOLTAGE (V) 1.25 0.8 R, O CT (a) Pull-Up for 2.5 V I/O Supply U ND O 3.6 IC M SE E L 3.135 A C PULL-UP 2.8 S E I (mA) MIN I (mA) MAX RE - 50 - 150 F Y B - 50 - 150 D 1.5 - 50 VE - 150 I - 46 - 130 H 1.4 C - 101 AR - 35 0 - 0.5 0 1.4 1.65 2.0 3.135 . - 38 CURRENT (mA) - 105 - 50 - 100 CURRENT (mA) - 150 VOLTAGE (V) VOLTAGE (V) 3.6 0 - 25 0 0 0 0 (b) Pull-Up for 3.3 V I/O Supply VDD PULL-DOWN VOLTAGE (V) I (mA) MIN I (mA) MAX - 0.5 0 0 0 0 0 0.4 10 20 0.8 20 40 1.25 31 63 1.6 40 80 2.8 40 80 3.2 40 80 3.4 40 80 1.6 VOLTAGE (V) Freescale Semiconductor, Inc... 0 C IN 1.25 0.3 0 0 40 CURRENT (mA) 80 (c) Pull-Down Figure 5. Typical Output Buffer Characteristics MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63P736*MCM63P818 15 MCM63P736*MCM63P818 16 For More Information On This Product, Go to: www.freescale.com DESELECTED tKHQZ Q(n) SINGLE READ tKHQX1 Q(A) tKHQX2 Q(B) Q(B+2) BURST READ Q(B+1) tGHQZ Q(B+3) Q(B) ADSP, SA SE2, SE3 IGNORED D(C) D(C+2) BURST WRITE D(C+1) R, O CT U ND D(C+3) C IN NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low. DQx BURST WRAPS AROUND O IC EM G t KHQV S W C LE A SC E BY EE R F SE1 B tKLKH ED V I ADV ADSC A tKHKL CH R A ADSP SA K tKHKH READ/WRITE CYCLES Freescale Semiconductor, Inc... D SINGLE READ t GLQX Q(D) t GLQV Freescale Semiconductor, Inc. . MOTOROLA FAST SRAM . tZZREC NO READS OR WRITES ALLOWED R, O CT U ND C IN EEEEEEEEEEEEEEEEEEEEEEEEEEE S EEEEEEEEEEEEEEEEEEEEEEEEEEE E L EEEEEEEEEEEEEEEEEEEEEEEEEEE CA S EEEEEEEEEEEEEEEEEEEEEEEEEEE EE EEEEEEEEEEEEEEEEEEEEEEEEEEE R F EEEEEEEEEEEEEEEEEEEEEEEEEEE BY EEEEEEEEEEEEEEEEEEEEEEEEEEE ED V EEEEEEEEEEEEEEEEEEEEEEEEEEE HI C EEEEEEEEEEEEEEEEEEEEEEEEEEE AR EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE I ZZ IN SLEEP MODE O IC EM NO NEW READS OR WRITES ALLOWED For More Information On This Product, Go to: www.freescale.com IDD ZZ DQ G W E ADV ADDR ADS K NORMAL OPERATION MOTOROLA FAST SRAM NOTE: ADS low = ADSC low or ADSP low. ADS high = both ADSC, ADSP high. E low = SE1 low, SE2 high, SE3 low. IZZ (max) specifications will not be met if inputs toggle. tZZQZ EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE tZZS SLEEP MODE TIMING Freescale Semiconductor, Inc... NORMAL OPERATION Freescale Semiconductor, Inc. MCM63P736*MCM63P818 17 Freescale Semiconductor, Inc. APPLICATION INFORMATION Freescale Semiconductor, Inc... SLEEP MODE current (IZZ). All inputs are allowed to toggle -- the RAM will not be selected and perform any reads or writes. However, if inputs toggle, the IZZ (max) specification will not be met. Note: It is invalid to go from stop clock mode directly into sleep mode. A sleep mode feature, the ZZ pin, has been implemented on the MCM63P736 and MCM63P818. It allows the system designer to place the RAM in the lowest possible power condition by asserting ZZ. The sleep mode timing diagram shows the different modes of operation: Normal Operation, NON-BURST SYNCHRONOUS OPERATION No READ/WRITE Allowed, and Sleep Mode. Each mode has Although this BurstRAM has been designed for PowerPC- its own set of constraints and conditions that are allowed. and other high end MPU-based systems, these SRAMs can Normal Operation: All inputs must meet setup and hold be used in other high speed L2 cache or memory applicatimes prior to sleep and t ZZREC nanoseconds after retions that do not require the burst address covering from sleep. Clock (K) must also meet cycle, high, . feature. Most L2 C caches designed with a synchronous interface can make use and low times during these periods. Two cycles prior to IN of the MCM63P736 and MCM63P818. The burst counter sleep, initiation of either a read or write operation is not , R feature of the BurstRAMs can be disabled, and the SRAMs allowed. TOupon a continuous stream of adcan be configured to act No READ/WRITE: During the period of time just prior to C dresses. See Figure sleep and during recovery from sleep, the assertion of either DU 6. ADSC, ADSP, or any write signal is not allowed. If a write N O operation occurs during these periods, the memory array CONTROL IC PIN TIE VALUES EXAMPLE (H VIH, L VIL) may be corrupted. Validity of data out from the RAM can not M ADSP ADSC ADV SE1 SE2 LBO ENon-Burst be guaranteed immediately after ZZ is asserted (prior to S Non-Burst, H L H L H X being in sleep). E Sync L Pipelined SRAM Sleep Mode: The RAM automatically deselects itself. TheA RAM disconnects its internal clock buffer. The external clock NOTE: Although X is specified in the table as a don't care, the pin SC E may continue to run without impacting the RAMs must be tied either high or low. E sleep CH R A K ADDR A B ED V I C BY FR D E F G H SE3 W G DQ Q(A) Q(B) Q(C) Q(D) D(E) D(F) READS D(G) D(H) WRITES Figure 6. Example Configuration as Non-Burst Synchronous SRAM MCM63P736*MCM63P818 18 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. ORDERING INFORMATION (Order by Full Part Number) MCM 63P736 63P818 XX X X Motorola Memory Prefix Blank = Trays, R = Tape and Reel Part Number Speed (133 = 133 MHz, 100 = 100 MHz, 66 = 66 MHz) Freescale Semiconductor, Inc... Package (TQ = TQFP, ZP = PBGA) Full Part Numbers -- MCM63P736TQ133 MCM63P736TQ133R MCM63P736ZP133 MCM63P736ZP133R MCM63P736TQ100 MCM63P736TQ100R MCM63P736ZP100 MCM63P736ZP100R MCM63P736TQ66 MCM63P736TQ66R MCM63P736ZP66 MCM63P736ZP66R MCM63P818TQ133 MCM63P818TQ133R MCM63P818ZP133 MCM63P818ZP133R MCM63P818TQ100 MCM63P818TQ100R MCM63P818ZP100 MCM63P818ZP100R MCM63P818TQ66 MCM63P818TQ66R MCM63P818ZP66 MCM63P818ZP66R CH R A MOTOROLA FAST SRAM ED V I BY EE R F LE A SC S O IC EM R, O CT U ND For More Information On This Product, Go to: www.freescale.com C IN . MCM63P736*MCM63P818 19 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS TQ PACKAGE TQFP CASE 983A-01 e 4X 0.20 (0.008) H A-B D 2X 30 TIPS e/2 0.20 (0.008) C A-B D -D- 80 51 B 50 81 -A- -B- Freescale Semiconductor, Inc... E1 E E1/2 31 100 1 30 D1/2 D/2 D1 D 2X 20 TIPS BY 0.20 (0.008) C A-B D A -H- -C- CH R A ED V I EE R F LE A SC 2 S O IC EM 0.10 (0.004) C S S c A1 R1 L2 L L1 M C A-B S D S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). GAGE PLANE VIEW AB MCM63P736*MCM63P818 20 c1 b 0.25 (0.010) R2 PLATING EEEE CCCC CCCC EEEE CCCC 1 A2 -X- X=A, B, OR D SECTION B-B VIEW AB 0.05 (0.002) . , Y RVIEW O CT U b1 ND BASE METAL 0.13 (0.005) 3 SEATING PLANE C IN B E/2 For More Information On This Product, Go to: www.freescale.com DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 1 2 3 MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 --- 0.08 --- 0.08 0.20 0 7 0 --- 11 13 11 13 INCHES MIN MAX --- 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 --- 0.003 --- 0.003 0.008 0 7 0 --- 11 13 11 13 MOTOROLA FAST SRAM Freescale Semiconductor, Inc. ZP PACKAGE 7 x 17 BUMP PBGA CASE 999-02 0.20 4X 119X B E C D Freescale Semiconductor, Inc... e 6X E2 BOTTOM VIEW LE A A SC 0.25 A A3 0.35 A A2 BY SIDE VIEW A1 CH R A ED V I A B C A e E1 TOP VIEW M A B C D E F G H J K L M N P R T U D1 16X M 0.15 7 6 5 4 3 2 1 D2 b 0.3 EE R F SEATING PLANE S O IC EM NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. ALL DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. DIM A A1 A2 A3 D D1 D2 E E1 E2 b e MILLIMETERS MIN MAX --- 2.40 0.50 0.70 1.30 1.70 0.80 1.00 22.00 BSC 20.32 BSC 19.40 19.60 14.00 BSC 7.62 BSC 11.90 12.10 0.60 0.90 1.27 BSC R, O CT U ND C IN . 0.20 A A Motorola reserves the right to make changes without further notice to any products herein. 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Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488 Mfax : RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. - http://sps.motorola.com /mfax / 852-26629298 HOME PAGE : http://motorola.com/sps / MOTOROLA FAST SRAM CUSTOMER FOCUS CENTER: 1-800-521-6274 For More Information On This Product, Go to: www.freescale.com MCM63P736/D MCM63P736*MCM63P818 21